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KVM: arm64: GICv3: mandate page-aligned GICV region
[mirror_ubuntu-artful-kernel.git] / arch / arm64 / kvm / sys_regs.c
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7c8c5e6a
MZ		 1/*
2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * Derived from arch/arm/kvm/coproc.c:
6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
7 * Authors: Rusty Russell <rusty@rustcorp.com.au>
8 * Christoffer Dall <c.dall@virtualopensystems.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License, version 2, as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#include <linux/mm.h>
24#include <linux/kvm_host.h>
25#include <linux/uaccess.h>
26#include <asm/kvm_arm.h>
27#include <asm/kvm_host.h>
28#include <asm/kvm_emulate.h>
29#include <asm/kvm_coproc.h>
9d218a1f 30#include <asm/kvm_mmu.h>
7c8c5e6a
MZ		 31#include <asm/cacheflush.h>
32#include <asm/cputype.h>
0c557ed4 33#include <asm/debug-monitors.h>
7c8c5e6a
MZ		 34#include <trace/events/kvm.h>
35
36#include "sys_regs.h"
37
38/*
39 * All of this file is extremly similar to the ARM coproc.c, but the
40 * types are different. My gut feeling is that it should be pretty
41 * easy to merge, but that would be an ABI breakage -- again. VFP
42 * would also need to be abstracted.
62a89c44
MZ		 43 *
44 * For AArch32, we only take care of what is being trapped. Anything
45 * that has to do with init and userspace access has to go via the
46 * 64bit interface.
7c8c5e6a
MZ		 47 */
48
49/* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
50static u32 cache_levels;
51
52/* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
53#define CSSELR_MAX 12
54
55/* Which cache CCSIDR represents depends on CSSELR value. */
56static u32 get_ccsidr(u32 csselr)
57{
58 u32 ccsidr;
59
60 /* Make sure noone else changes CSSELR during this! */
61 local_irq_disable();
62 /* Put value into CSSELR */
63 asm volatile("msr csselr_el1, %x0" : : "r" (csselr));
64 isb();
65 /* Read result out of CCSIDR */
66 asm volatile("mrs %0, ccsidr_el1" : "=r" (ccsidr));
67 local_irq_enable();
68
69 return ccsidr;
70}
71
72static void do_dc_cisw(u32 val)
73{
74 asm volatile("dc cisw, %x0" : : "r" (val));
98f7685e 75 dsb(ish);
7c8c5e6a
MZ		 76}
77
78static void do_dc_csw(u32 val)
79{
80 asm volatile("dc csw, %x0" : : "r" (val));
98f7685e 81 dsb(ish);
7c8c5e6a
MZ		 82}
83
84/* See note at ARM ARM B1.14.4 */
85static bool access_dcsw(struct kvm_vcpu *vcpu,
86 const struct sys_reg_params *p,
87 const struct sys_reg_desc *r)
88{
89 unsigned long val;
90 int cpu;
91
92 if (!p->is_write)
93 return read_from_write_only(vcpu, p);
94
95 cpu = get_cpu();
96
97 cpumask_setall(&vcpu->arch.require_dcache_flush);
98 cpumask_clear_cpu(cpu, &vcpu->arch.require_dcache_flush);
99
100 /* If we were already preempted, take the long way around */
101 if (cpu != vcpu->arch.last_pcpu) {
102 flush_cache_all();
103 goto done;
104 }
105
106 val = *vcpu_reg(vcpu, p->Rt);
107
108 switch (p->CRm) {
109 case 6: /* Upgrade DCISW to DCCISW, as per HCR.SWIO */
110 case 14: /* DCCISW */
111 do_dc_cisw(val);
112 break;
113
114 case 10: /* DCCSW */
115 do_dc_csw(val);
116 break;
117 }
118
119done:
120 put_cpu();
121
122 return true;
123}
124
4d44923b
MZ		 125/*
126 * Generic accessor for VM registers. Only called as long as HCR_TVM
127 * is set.
128 */
129static bool access_vm_reg(struct kvm_vcpu *vcpu,
130 const struct sys_reg_params *p,
131 const struct sys_reg_desc *r)
132{
133 unsigned long val;
134
135 BUG_ON(!p->is_write);
136
137 val = *vcpu_reg(vcpu, p->Rt);
f0a3eaff 138 if (!p->is_aarch32 || !p->is_32bit)
4d44923b 139 vcpu_sys_reg(vcpu, r->reg) = val;
f0a3eaff
VK		 140 else
141 vcpu_cp15_64_low(vcpu, r->reg) = val & 0xffffffffUL;
142
4d44923b
MZ		 143 return true;
144}
145
146/*
147 * SCTLR_EL1 accessor. Only called as long as HCR_TVM is set. If the
148 * guest enables the MMU, we stop trapping the VM sys_regs and leave
149 * it in complete control of the caches.
150 */
151static bool access_sctlr(struct kvm_vcpu *vcpu,
152 const struct sys_reg_params *p,
153 const struct sys_reg_desc *r)
154{
155 access_vm_reg(vcpu, p, r);
156
9d218a1f 157 if (vcpu_has_cache_enabled(vcpu)) { /* MMU+Caches enabled? */
4d44923b 158 vcpu->arch.hcr_el2 &= ~HCR_TVM;
9d218a1f
MZ		 159 stage2_flush_vm(vcpu->kvm);
160 }
4d44923b
MZ		 161
162 return true;
163}
164
7609c125
MZ		 165static bool trap_raz_wi(struct kvm_vcpu *vcpu,
166 const struct sys_reg_params *p,
167 const struct sys_reg_desc *r)
7c8c5e6a
MZ		 168{
169 if (p->is_write)
170 return ignore_write(vcpu, p);
171 else
172 return read_zero(vcpu, p);
173}
174
0c557ed4
MZ		 175static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
176 const struct sys_reg_params *p,
177 const struct sys_reg_desc *r)
178{
179 if (p->is_write) {
180 return ignore_write(vcpu, p);
181 } else {
182 *vcpu_reg(vcpu, p->Rt) = (1 << 3);
183 return true;
184 }
185}
186
187static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
188 const struct sys_reg_params *p,
189 const struct sys_reg_desc *r)
190{
191 if (p->is_write) {
192 return ignore_write(vcpu, p);
193 } else {
194 u32 val;
195 asm volatile("mrs %0, dbgauthstatus_el1" : "=r" (val));
196 *vcpu_reg(vcpu, p->Rt) = val;
197 return true;
198 }
199}
200
201/*
202 * We want to avoid world-switching all the DBG registers all the
203 * time:
204 *
205 * - If we've touched any debug register, it is likely that we're
206 * going to touch more of them. It then makes sense to disable the
207 * traps and start doing the save/restore dance
208 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
209 * then mandatory to save/restore the registers, as the guest
210 * depends on them.
211 *
212 * For this, we use a DIRTY bit, indicating the guest has modified the
213 * debug registers, used as follow:
214 *
215 * On guest entry:
216 * - If the dirty bit is set (because we're coming back from trapping),
217 * disable the traps, save host registers, restore guest registers.
218 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
219 * set the dirty bit, disable the traps, save host registers,
220 * restore guest registers.
221 * - Otherwise, enable the traps
222 *
223 * On guest exit:
224 * - If the dirty bit is set, save guest registers, restore host
225 * registers and clear the dirty bit. This ensure that the host can
226 * now use the debug registers.
227 */
228static bool trap_debug_regs(struct kvm_vcpu *vcpu,
229 const struct sys_reg_params *p,
230 const struct sys_reg_desc *r)
231{
232 if (p->is_write) {
233 vcpu_sys_reg(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt);
234 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
235 } else {
236 *vcpu_reg(vcpu, p->Rt) = vcpu_sys_reg(vcpu, r->reg);
237 }
238
239 return true;
240}
241
7c8c5e6a
MZ		 242static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
243{
244 u64 amair;
245
246 asm volatile("mrs %0, amair_el1\n" : "=r" (amair));
247 vcpu_sys_reg(vcpu, AMAIR_EL1) = amair;
248}
249
250static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
251{
252 /*
253 * Simply map the vcpu_id into the Aff0 field of the MPIDR.
254 */
255 vcpu_sys_reg(vcpu, MPIDR_EL1) = (1UL << 31) | (vcpu->vcpu_id & 0xff);
256}
257
0c557ed4
MZ		 258/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
259#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
260 /* DBGBVRn_EL1 */ \
261 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b100), \
262 trap_debug_regs, reset_val, (DBGBVR0_EL1 + (n)), 0 }, \
263 /* DBGBCRn_EL1 */ \
264 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b101), \
265 trap_debug_regs, reset_val, (DBGBCR0_EL1 + (n)), 0 }, \
266 /* DBGWVRn_EL1 */ \
267 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b110), \
268 trap_debug_regs, reset_val, (DBGWVR0_EL1 + (n)), 0 }, \
269 /* DBGWCRn_EL1 */ \
270 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b111), \
271 trap_debug_regs, reset_val, (DBGWCR0_EL1 + (n)), 0 }
272
7c8c5e6a
MZ		 273/*
274 * Architected system registers.
275 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
7609c125
MZ		 276 *
277 * We could trap ID_DFR0 and tell the guest we don't support performance
278 * monitoring. Unfortunately the patch to make the kernel check ID_DFR0 was
279 * NAKed, so it will read the PMCR anyway.
280 *
281 * Therefore we tell the guest we have 0 counters. Unfortunately, we
282 * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
283 * all PM registers, which doesn't crash the guest kernel at least.
284 *
0c557ed4
MZ		 285 * Debug handling: We do trap most, if not all debug related system
286 * registers. The implementation is good enough to ensure that a guest
287 * can use these with minimal performance degradation. The drawback is
288 * that we don't implement any of the external debug, none of the
289 * OSlock protocol. This should be revisited if we ever encounter a
290 * more demanding guest...
7c8c5e6a
MZ		 291 */
292static const struct sys_reg_desc sys_reg_descs[] = {
293 /* DC ISW */
294 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010),
295 access_dcsw },
296 /* DC CSW */
297 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010),
298 access_dcsw },
299 /* DC CISW */
300 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
301 access_dcsw },
302
0c557ed4
MZ		 303 DBG_BCR_BVR_WCR_WVR_EL1(0),
304 DBG_BCR_BVR_WCR_WVR_EL1(1),
305 /* MDCCINT_EL1 */
306 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
307 trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
308 /* MDSCR_EL1 */
309 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
310 trap_debug_regs, reset_val, MDSCR_EL1, 0 },
311 DBG_BCR_BVR_WCR_WVR_EL1(2),
312 DBG_BCR_BVR_WCR_WVR_EL1(3),
313 DBG_BCR_BVR_WCR_WVR_EL1(4),
314 DBG_BCR_BVR_WCR_WVR_EL1(5),
315 DBG_BCR_BVR_WCR_WVR_EL1(6),
316 DBG_BCR_BVR_WCR_WVR_EL1(7),
317 DBG_BCR_BVR_WCR_WVR_EL1(8),
318 DBG_BCR_BVR_WCR_WVR_EL1(9),
319 DBG_BCR_BVR_WCR_WVR_EL1(10),
320 DBG_BCR_BVR_WCR_WVR_EL1(11),
321 DBG_BCR_BVR_WCR_WVR_EL1(12),
322 DBG_BCR_BVR_WCR_WVR_EL1(13),
323 DBG_BCR_BVR_WCR_WVR_EL1(14),
324 DBG_BCR_BVR_WCR_WVR_EL1(15),
325
326 /* MDRAR_EL1 */
327 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
328 trap_raz_wi },
329 /* OSLAR_EL1 */
330 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b100),
331 trap_raz_wi },
332 /* OSLSR_EL1 */
333 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0001), Op2(0b100),
334 trap_oslsr_el1 },
335 /* OSDLR_EL1 */
336 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0011), Op2(0b100),
337 trap_raz_wi },
338 /* DBGPRCR_EL1 */
339 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0100), Op2(0b100),
340 trap_raz_wi },
341 /* DBGCLAIMSET_EL1 */
342 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1000), Op2(0b110),
343 trap_raz_wi },
344 /* DBGCLAIMCLR_EL1 */
345 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1001), Op2(0b110),
346 trap_raz_wi },
347 /* DBGAUTHSTATUS_EL1 */
348 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b110),
349 trap_dbgauthstatus_el1 },
350
62a89c44
MZ		 351 /* TEECR32_EL1 */
352 { Op0(0b10), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
353 NULL, reset_val, TEECR32_EL1, 0 },
354 /* TEEHBR32_EL1 */
355 { Op0(0b10), Op1(0b010), CRn(0b0001), CRm(0b0000), Op2(0b000),
356 NULL, reset_val, TEEHBR32_EL1, 0 },
0c557ed4
MZ		 357
358 /* MDCCSR_EL1 */
359 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0001), Op2(0b000),
360 trap_raz_wi },
361 /* DBGDTR_EL0 */
362 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0100), Op2(0b000),
363 trap_raz_wi },
364 /* DBGDTR[TR]X_EL0 */
365 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0101), Op2(0b000),
366 trap_raz_wi },
367
62a89c44
MZ		 368 /* DBGVCR32_EL2 */
369 { Op0(0b10), Op1(0b100), CRn(0b0000), CRm(0b0111), Op2(0b000),
370 NULL, reset_val, DBGVCR32_EL2, 0 },
371
7c8c5e6a
MZ		 372 /* MPIDR_EL1 */
373 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101),
374 NULL, reset_mpidr, MPIDR_EL1 },
375 /* SCTLR_EL1 */
376 { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
4d44923b 377 access_sctlr, reset_val, SCTLR_EL1, 0x00C50078 },
7c8c5e6a
MZ		 378 /* CPACR_EL1 */
379 { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),
380 NULL, reset_val, CPACR_EL1, 0 },
381 /* TTBR0_EL1 */
382 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000),
4d44923b 383 access_vm_reg, reset_unknown, TTBR0_EL1 },
7c8c5e6a
MZ		 384 /* TTBR1_EL1 */
385 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001),
4d44923b 386 access_vm_reg, reset_unknown, TTBR1_EL1 },
7c8c5e6a
MZ		 387 /* TCR_EL1 */
388 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010),
4d44923b 389 access_vm_reg, reset_val, TCR_EL1, 0 },
7c8c5e6a
MZ		 390
391 /* AFSR0_EL1 */
392 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000),
4d44923b 393 access_vm_reg, reset_unknown, AFSR0_EL1 },
7c8c5e6a
MZ		 394 /* AFSR1_EL1 */
395 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001),
4d44923b 396 access_vm_reg, reset_unknown, AFSR1_EL1 },
7c8c5e6a
MZ		 397 /* ESR_EL1 */
398 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000),
4d44923b 399 access_vm_reg, reset_unknown, ESR_EL1 },
7c8c5e6a
MZ		 400 /* FAR_EL1 */
401 { Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
4d44923b 402 access_vm_reg, reset_unknown, FAR_EL1 },
1bbd8054
MZ		 403 /* PAR_EL1 */
404 { Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000),
405 NULL, reset_unknown, PAR_EL1 },
7c8c5e6a
MZ		 406
407 /* PMINTENSET_EL1 */
408 { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
7609c125 409 trap_raz_wi },
7c8c5e6a
MZ		 410 /* PMINTENCLR_EL1 */
411 { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
7609c125 412 trap_raz_wi },
7c8c5e6a
MZ		 413
414 /* MAIR_EL1 */
415 { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
4d44923b 416 access_vm_reg, reset_unknown, MAIR_EL1 },
7c8c5e6a
MZ		 417 /* AMAIR_EL1 */
418 { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000),
4d44923b 419 access_vm_reg, reset_amair_el1, AMAIR_EL1 },
7c8c5e6a
MZ		 420
421 /* VBAR_EL1 */
422 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
423 NULL, reset_val, VBAR_EL1, 0 },
424 /* CONTEXTIDR_EL1 */
425 { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
4d44923b 426 access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
7c8c5e6a
MZ		 427 /* TPIDR_EL1 */
428 { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100),
429 NULL, reset_unknown, TPIDR_EL1 },
430
431 /* CNTKCTL_EL1 */
432 { Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000),
433 NULL, reset_val, CNTKCTL_EL1, 0},
434
435 /* CSSELR_EL1 */
436 { Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
437 NULL, reset_unknown, CSSELR_EL1 },
438
439 /* PMCR_EL0 */
440 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
7609c125 441 trap_raz_wi },
7c8c5e6a
MZ		 442 /* PMCNTENSET_EL0 */
443 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
7609c125 444 trap_raz_wi },
7c8c5e6a
MZ		 445 /* PMCNTENCLR_EL0 */
446 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
7609c125 447 trap_raz_wi },
7c8c5e6a
MZ		 448 /* PMOVSCLR_EL0 */
449 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
7609c125 450 trap_raz_wi },
7c8c5e6a
MZ		 451 /* PMSWINC_EL0 */
452 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
7609c125 453 trap_raz_wi },
7c8c5e6a
MZ		 454 /* PMSELR_EL0 */
455 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
7609c125 456 trap_raz_wi },
7c8c5e6a
MZ		 457 /* PMCEID0_EL0 */
458 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
7609c125 459 trap_raz_wi },
7c8c5e6a
MZ		 460 /* PMCEID1_EL0 */
461 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
7609c125 462 trap_raz_wi },
7c8c5e6a
MZ		 463 /* PMCCNTR_EL0 */
464 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
7609c125 465 trap_raz_wi },
7c8c5e6a
MZ		 466 /* PMXEVTYPER_EL0 */
467 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
7609c125 468 trap_raz_wi },
7c8c5e6a
MZ		 469 /* PMXEVCNTR_EL0 */
470 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
7609c125 471 trap_raz_wi },
7c8c5e6a
MZ		 472 /* PMUSERENR_EL0 */
473 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
7609c125 474 trap_raz_wi },
7c8c5e6a
MZ		 475 /* PMOVSSET_EL0 */
476 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
7609c125 477 trap_raz_wi },
7c8c5e6a
MZ		 478
479 /* TPIDR_EL0 */
480 { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010),
481 NULL, reset_unknown, TPIDR_EL0 },
482 /* TPIDRRO_EL0 */
483 { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
484 NULL, reset_unknown, TPIDRRO_EL0 },
62a89c44
MZ		 485
486 /* DACR32_EL2 */
487 { Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
488 NULL, reset_unknown, DACR32_EL2 },
489 /* IFSR32_EL2 */
490 { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001),
491 NULL, reset_unknown, IFSR32_EL2 },
492 /* FPEXC32_EL2 */
493 { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000),
494 NULL, reset_val, FPEXC32_EL2, 0x70 },
495};
496
bdfb4b38
MZ		 497static bool trap_dbgidr(struct kvm_vcpu *vcpu,
498 const struct sys_reg_params *p,
499 const struct sys_reg_desc *r)
500{
501 if (p->is_write) {
502 return ignore_write(vcpu, p);
503 } else {
504 u64 dfr = read_cpuid(ID_AA64DFR0_EL1);
505 u64 pfr = read_cpuid(ID_AA64PFR0_EL1);
506 u32 el3 = !!((pfr >> 12) & 0xf);
507
508 *vcpu_reg(vcpu, p->Rt) = ((((dfr >> 20) & 0xf) << 28) |
509 (((dfr >> 12) & 0xf) << 24) |
510 (((dfr >> 28) & 0xf) << 20) |
511 (6 << 16) | (el3 << 14) | (el3 << 12));
512 return true;
513 }
514}
515
516static bool trap_debug32(struct kvm_vcpu *vcpu,
517 const struct sys_reg_params *p,
518 const struct sys_reg_desc *r)
519{
520 if (p->is_write) {
521 vcpu_cp14(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt);
522 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
523 } else {
524 *vcpu_reg(vcpu, p->Rt) = vcpu_cp14(vcpu, r->reg);
525 }
526
527 return true;
528}
529
530#define DBG_BCR_BVR_WCR_WVR(n) \
531 /* DBGBVRn */ \
532 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_debug32, \
533 NULL, (cp14_DBGBVR0 + (n) * 2) }, \
534 /* DBGBCRn */ \
535 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_debug32, \
536 NULL, (cp14_DBGBCR0 + (n) * 2) }, \
537 /* DBGWVRn */ \
538 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_debug32, \
539 NULL, (cp14_DBGWVR0 + (n) * 2) }, \
540 /* DBGWCRn */ \
541 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_debug32, \
542 NULL, (cp14_DBGWCR0 + (n) * 2) }
543
544#define DBGBXVR(n) \
545 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_debug32, \
546 NULL, cp14_DBGBXVR0 + n * 2 }
547
548/*
549 * Trapped cp14 registers. We generally ignore most of the external
550 * debug, on the principle that they don't really make sense to a
551 * guest. Revisit this one day, whould this principle change.
552 */
72564016 553static const struct sys_reg_desc cp14_regs[] = {
bdfb4b38
MZ		 554 /* DBGIDR */
555 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
556 /* DBGDTRRXext */
557 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
558
559 DBG_BCR_BVR_WCR_WVR(0),
560 /* DBGDSCRint */
561 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
562 DBG_BCR_BVR_WCR_WVR(1),
563 /* DBGDCCINT */
564 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
565 /* DBGDSCRext */
566 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
567 DBG_BCR_BVR_WCR_WVR(2),
568 /* DBGDTR[RT]Xint */
569 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
570 /* DBGDTR[RT]Xext */
571 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
572 DBG_BCR_BVR_WCR_WVR(3),
573 DBG_BCR_BVR_WCR_WVR(4),
574 DBG_BCR_BVR_WCR_WVR(5),
575 /* DBGWFAR */
576 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
577 /* DBGOSECCR */
578 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
579 DBG_BCR_BVR_WCR_WVR(6),
580 /* DBGVCR */
581 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
582 DBG_BCR_BVR_WCR_WVR(7),
583 DBG_BCR_BVR_WCR_WVR(8),
584 DBG_BCR_BVR_WCR_WVR(9),
585 DBG_BCR_BVR_WCR_WVR(10),
586 DBG_BCR_BVR_WCR_WVR(11),
587 DBG_BCR_BVR_WCR_WVR(12),
588 DBG_BCR_BVR_WCR_WVR(13),
589 DBG_BCR_BVR_WCR_WVR(14),
590 DBG_BCR_BVR_WCR_WVR(15),
591
592 /* DBGDRAR (32bit) */
593 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
594
595 DBGBXVR(0),
596 /* DBGOSLAR */
597 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
598 DBGBXVR(1),
599 /* DBGOSLSR */
600 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
601 DBGBXVR(2),
602 DBGBXVR(3),
603 /* DBGOSDLR */
604 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
605 DBGBXVR(4),
606 /* DBGPRCR */
607 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
608 DBGBXVR(5),
609 DBGBXVR(6),
610 DBGBXVR(7),
611 DBGBXVR(8),
612 DBGBXVR(9),
613 DBGBXVR(10),
614 DBGBXVR(11),
615 DBGBXVR(12),
616 DBGBXVR(13),
617 DBGBXVR(14),
618 DBGBXVR(15),
619
620 /* DBGDSAR (32bit) */
621 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
622
623 /* DBGDEVID2 */
624 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
625 /* DBGDEVID1 */
626 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
627 /* DBGDEVID */
628 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
629 /* DBGCLAIMSET */
630 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
631 /* DBGCLAIMCLR */
632 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
633 /* DBGAUTHSTATUS */
634 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
72564016
MZ		 635};
636
a9866ba0
MZ		 637/* Trapped cp14 64bit registers */
638static const struct sys_reg_desc cp14_64_regs[] = {
bdfb4b38
MZ		 639 /* DBGDRAR (64bit) */
640 { Op1( 0), CRm( 1), .access = trap_raz_wi },
641
642 /* DBGDSAR (64bit) */
643 { Op1( 0), CRm( 2), .access = trap_raz_wi },
a9866ba0
MZ		 644};
645
4d44923b
MZ		 646/*
647 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
648 * depending on the way they are accessed (as a 32bit or a 64bit
649 * register).
650 */
62a89c44 651static const struct sys_reg_desc cp15_regs[] = {
4d44923b
MZ		 652 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_sctlr, NULL, c1_SCTLR },
653 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
654 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
655 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
656 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
657 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
658 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
659 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
660 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
661 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
662 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
663
62a89c44
MZ		 664 /*
665 * DC{C,I,CI}SW operations:
666 */
667 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
668 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
669 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
4d44923b 670
7609c125
MZ		 671 /* PMU */
672 { Op1( 0), CRn( 9), CRm(12), Op2( 0), trap_raz_wi },
673 { Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
674 { Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
675 { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
676 { Op1( 0), CRn( 9), CRm(12), Op2( 5), trap_raz_wi },
677 { Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
678 { Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
679 { Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
680 { Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi },
681 { Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
682 { Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
683 { Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },
684 { Op1( 0), CRn( 9), CRm(14), Op2( 2), trap_raz_wi },
4d44923b
MZ		 685
686 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
687 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
688 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
689 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
690 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
a9866ba0
MZ		 691};
692
693static const struct sys_reg_desc cp15_64_regs[] = {
694 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
4d44923b 695 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
7c8c5e6a
MZ		 696};
697
698/* Target specific emulation tables */
699static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
700
701void kvm_register_target_sys_reg_table(unsigned int target,
702 struct kvm_sys_reg_target_table *table)
703{
704 target_tables[target] = table;
705}
706
707/* Get specific register table for this target. */
62a89c44
MZ		 708static const struct sys_reg_desc *get_target_table(unsigned target,
709 bool mode_is_64,
710 size_t *num)
7c8c5e6a
MZ		 711{
712 struct kvm_sys_reg_target_table *table;
713
714 table = target_tables[target];
62a89c44
MZ		 715 if (mode_is_64) {
716 *num = table->table64.num;
717 return table->table64.table;
718 } else {
719 *num = table->table32.num;
720 return table->table32.table;
721 }
7c8c5e6a
MZ		 722}
723
724static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
725 const struct sys_reg_desc table[],
726 unsigned int num)
727{
728 unsigned int i;
729
730 for (i = 0; i < num; i++) {
731 const struct sys_reg_desc *r = &table[i];
732
733 if (params->Op0 != r->Op0)
734 continue;
735 if (params->Op1 != r->Op1)
736 continue;
737 if (params->CRn != r->CRn)
738 continue;
739 if (params->CRm != r->CRm)
740 continue;
741 if (params->Op2 != r->Op2)
742 continue;
743
744 return r;
745 }
746 return NULL;
747}
748
62a89c44
MZ		 749int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
750{
751 kvm_inject_undefined(vcpu);
752 return 1;
753}
754
72564016
MZ		 755/*
756 * emulate_cp -- tries to match a sys_reg access in a handling table, and
757 * call the corresponding trap handler.
758 *
759 * @params: pointer to the descriptor of the access
760 * @table: array of trap descriptors
761 * @num: size of the trap descriptor array
762 *
763 * Return 0 if the access has been handled, and -1 if not.
764 */
765static int emulate_cp(struct kvm_vcpu *vcpu,
766 const struct sys_reg_params *params,
767 const struct sys_reg_desc *table,
768 size_t num)
62a89c44 769{
72564016 770 const struct sys_reg_desc *r;
62a89c44 771
72564016
MZ		 772 if (!table)
773 return -1; /* Not handled */
62a89c44 774
62a89c44 775 r = find_reg(params, table, num);
62a89c44 776
72564016 777 if (r) {
62a89c44
MZ		 778 /*
779 * Not having an accessor means that we have
780 * configured a trap that we don't know how to
781 * handle. This certainly qualifies as a gross bug
782 * that should be fixed right away.
783 */
784 BUG_ON(!r->access);
785
786 if (likely(r->access(vcpu, params, r))) {
787 /* Skip instruction, since it was emulated */
788 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
62a89c44 789 }
72564016
MZ		 790
791 /* Handled */
792 return 0;
793 }
794
795 /* Not handled */
796 return -1;
797}
798
799static void unhandled_cp_access(struct kvm_vcpu *vcpu,
800 struct sys_reg_params *params)
801{
802 u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
803 int cp;
804
805 switch(hsr_ec) {
806 case ESR_EL2_EC_CP15_32:
807 case ESR_EL2_EC_CP15_64:
808 cp = 15;
809 break;
810 case ESR_EL2_EC_CP14_MR:
811 case ESR_EL2_EC_CP14_64:
812 cp = 14;
813 break;
814 default:
815 WARN_ON((cp = -1));
62a89c44
MZ		 816 }
817
72564016
MZ		 818 kvm_err("Unsupported guest CP%d access at: %08lx\n",
819 cp, *vcpu_pc(vcpu));
62a89c44
MZ		 820 print_sys_reg_instr(params);
821 kvm_inject_undefined(vcpu);
822}
823
824/**
72564016 825 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP15 access
62a89c44
MZ		 826 * @vcpu: The VCPU pointer
827 * @run: The kvm_run struct
828 */
72564016
MZ		 829static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
830 const struct sys_reg_desc *global,
831 size_t nr_global,
832 const struct sys_reg_desc *target_specific,
833 size_t nr_specific)
62a89c44
MZ		 834{
835 struct sys_reg_params params;
836 u32 hsr = kvm_vcpu_get_hsr(vcpu);
837 int Rt2 = (hsr >> 10) & 0xf;
838
2072d29c
MZ		 839 params.is_aarch32 = true;
840 params.is_32bit = false;
62a89c44
MZ		 841 params.CRm = (hsr >> 1) & 0xf;
842 params.Rt = (hsr >> 5) & 0xf;
843 params.is_write = ((hsr & 1) == 0);
844
845 params.Op0 = 0;
846 params.Op1 = (hsr >> 16) & 0xf;
847 params.Op2 = 0;
848 params.CRn = 0;
849
850 /*
851 * Massive hack here. Store Rt2 in the top 32bits so we only
852 * have one register to deal with. As we use the same trap
853 * backends between AArch32 and AArch64, we get away with it.
854 */
855 if (params.is_write) {
856 u64 val = *vcpu_reg(vcpu, params.Rt);
857 val &= 0xffffffff;
858 val |= *vcpu_reg(vcpu, Rt2) << 32;
859 *vcpu_reg(vcpu, params.Rt) = val;
860 }
861
72564016
MZ		 862 if (!emulate_cp(vcpu, &params, target_specific, nr_specific))
863 goto out;
864 if (!emulate_cp(vcpu, &params, global, nr_global))
865 goto out;
866
867 unhandled_cp_access(vcpu, &params);
62a89c44 868
72564016 869out:
62a89c44
MZ		 870 /* Do the opposite hack for the read side */
871 if (!params.is_write) {
872 u64 val = *vcpu_reg(vcpu, params.Rt);
873 val >>= 32;
874 *vcpu_reg(vcpu, Rt2) = val;
875 }
876
877 return 1;
878}
879
880/**
881 * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
882 * @vcpu: The VCPU pointer
883 * @run: The kvm_run struct
884 */
72564016
MZ		 885static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
886 const struct sys_reg_desc *global,
887 size_t nr_global,
888 const struct sys_reg_desc *target_specific,
889 size_t nr_specific)
62a89c44
MZ		 890{
891 struct sys_reg_params params;
892 u32 hsr = kvm_vcpu_get_hsr(vcpu);
893
2072d29c
MZ		 894 params.is_aarch32 = true;
895 params.is_32bit = true;
62a89c44
MZ		 896 params.CRm = (hsr >> 1) & 0xf;
897 params.Rt = (hsr >> 5) & 0xf;
898 params.is_write = ((hsr & 1) == 0);
899 params.CRn = (hsr >> 10) & 0xf;
900 params.Op0 = 0;
901 params.Op1 = (hsr >> 14) & 0x7;
902 params.Op2 = (hsr >> 17) & 0x7;
903
72564016
MZ		 904 if (!emulate_cp(vcpu, &params, target_specific, nr_specific))
905 return 1;
906 if (!emulate_cp(vcpu, &params, global, nr_global))
907 return 1;
908
909 unhandled_cp_access(vcpu, &params);
62a89c44
MZ		 910 return 1;
911}
912
72564016
MZ		 913int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
914{
915 const struct sys_reg_desc *target_specific;
916 size_t num;
917
918 target_specific = get_target_table(vcpu->arch.target, false, &num);
919 return kvm_handle_cp_64(vcpu,
a9866ba0 920 cp15_64_regs, ARRAY_SIZE(cp15_64_regs),
72564016
MZ		 921 target_specific, num);
922}
923
924int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
925{
926 const struct sys_reg_desc *target_specific;
927 size_t num;
928
929 target_specific = get_target_table(vcpu->arch.target, false, &num);
930 return kvm_handle_cp_32(vcpu,
931 cp15_regs, ARRAY_SIZE(cp15_regs),
932 target_specific, num);
933}
934
935int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
936{
937 return kvm_handle_cp_64(vcpu,
a9866ba0 938 cp14_64_regs, ARRAY_SIZE(cp14_64_regs),
72564016
MZ		 939 NULL, 0);
940}
941
942int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
943{
944 return kvm_handle_cp_32(vcpu,
945 cp14_regs, ARRAY_SIZE(cp14_regs),
946 NULL, 0);
947}
948
7c8c5e6a
MZ		 949static int emulate_sys_reg(struct kvm_vcpu *vcpu,
950 const struct sys_reg_params *params)
951{
952 size_t num;
953 const struct sys_reg_desc *table, *r;
954
62a89c44 955 table = get_target_table(vcpu->arch.target, true, &num);
7c8c5e6a
MZ		 956
957 /* Search target-specific then generic table. */
958 r = find_reg(params, table, num);
959 if (!r)
960 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
961
962 if (likely(r)) {
963 /*
964 * Not having an accessor means that we have
965 * configured a trap that we don't know how to
966 * handle. This certainly qualifies as a gross bug
967 * that should be fixed right away.
968 */
969 BUG_ON(!r->access);
970
971 if (likely(r->access(vcpu, params, r))) {
972 /* Skip instruction, since it was emulated */
973 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
974 return 1;
975 }
976 /* If access function fails, it should complain. */
977 } else {
978 kvm_err("Unsupported guest sys_reg access at: %lx\n",
979 *vcpu_pc(vcpu));
980 print_sys_reg_instr(params);
981 }
982 kvm_inject_undefined(vcpu);
983 return 1;
984}
985
986static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
987 const struct sys_reg_desc *table, size_t num)
988{
989 unsigned long i;
990
991 for (i = 0; i < num; i++)
992 if (table[i].reset)
993 table[i].reset(vcpu, &table[i]);
994}
995
996/**
997 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
998 * @vcpu: The VCPU pointer
999 * @run: The kvm_run struct
1000 */
1001int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
1002{
1003 struct sys_reg_params params;
1004 unsigned long esr = kvm_vcpu_get_hsr(vcpu);
1005
2072d29c
MZ		 1006 params.is_aarch32 = false;
1007 params.is_32bit = false;
7c8c5e6a
MZ		 1008 params.Op0 = (esr >> 20) & 3;
1009 params.Op1 = (esr >> 14) & 0x7;
1010 params.CRn = (esr >> 10) & 0xf;
1011 params.CRm = (esr >> 1) & 0xf;
1012 params.Op2 = (esr >> 17) & 0x7;
1013 params.Rt = (esr >> 5) & 0x1f;
1014 params.is_write = !(esr & 1);
1015
1016 return emulate_sys_reg(vcpu, &params);
1017}
1018
1019/******************************************************************************
1020 * Userspace API
1021 *****************************************************************************/
1022
1023static bool index_to_params(u64 id, struct sys_reg_params *params)
1024{
1025 switch (id & KVM_REG_SIZE_MASK) {
1026 case KVM_REG_SIZE_U64:
1027 /* Any unused index bits means it's not valid. */
1028 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
1029 | KVM_REG_ARM_COPROC_MASK
1030 | KVM_REG_ARM64_SYSREG_OP0_MASK
1031 | KVM_REG_ARM64_SYSREG_OP1_MASK
1032 | KVM_REG_ARM64_SYSREG_CRN_MASK
1033 | KVM_REG_ARM64_SYSREG_CRM_MASK
1034 | KVM_REG_ARM64_SYSREG_OP2_MASK))
1035 return false;
1036 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
1037 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
1038 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
1039 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
1040 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
1041 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
1042 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
1043 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
1044 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
1045 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
1046 return true;
1047 default:
1048 return false;
1049 }
1050}
1051
1052/* Decode an index value, and find the sys_reg_desc entry. */
1053static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
1054 u64 id)
1055{
1056 size_t num;
1057 const struct sys_reg_desc *table, *r;
1058 struct sys_reg_params params;
1059
1060 /* We only do sys_reg for now. */
1061 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
1062 return NULL;
1063
1064 if (!index_to_params(id, &params))
1065 return NULL;
1066
62a89c44 1067 table = get_target_table(vcpu->arch.target, true, &num);
7c8c5e6a
MZ		 1068 r = find_reg(&params, table, num);
1069 if (!r)
1070 r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1071
1072 /* Not saved in the sys_reg array? */
1073 if (r && !r->reg)
1074 r = NULL;
1075
1076 return r;
1077}
1078
1079/*
1080 * These are the invariant sys_reg registers: we let the guest see the
1081 * host versions of these, so they're part of the guest state.
1082 *
1083 * A future CPU may provide a mechanism to present different values to
1084 * the guest, or a future kvm may trap them.
1085 */
1086
1087#define FUNCTION_INVARIANT(reg) \
1088 static void get_##reg(struct kvm_vcpu *v, \
1089 const struct sys_reg_desc *r) \
1090 { \
1091 u64 val; \
1092 \
1093 asm volatile("mrs %0, " __stringify(reg) "\n" \
1094 : "=r" (val)); \
1095 ((struct sys_reg_desc *)r)->val = val; \
1096 }
1097
1098FUNCTION_INVARIANT(midr_el1)
1099FUNCTION_INVARIANT(ctr_el0)
1100FUNCTION_INVARIANT(revidr_el1)
1101FUNCTION_INVARIANT(id_pfr0_el1)
1102FUNCTION_INVARIANT(id_pfr1_el1)
1103FUNCTION_INVARIANT(id_dfr0_el1)
1104FUNCTION_INVARIANT(id_afr0_el1)
1105FUNCTION_INVARIANT(id_mmfr0_el1)
1106FUNCTION_INVARIANT(id_mmfr1_el1)
1107FUNCTION_INVARIANT(id_mmfr2_el1)
1108FUNCTION_INVARIANT(id_mmfr3_el1)
1109FUNCTION_INVARIANT(id_isar0_el1)
1110FUNCTION_INVARIANT(id_isar1_el1)
1111FUNCTION_INVARIANT(id_isar2_el1)
1112FUNCTION_INVARIANT(id_isar3_el1)
1113FUNCTION_INVARIANT(id_isar4_el1)
1114FUNCTION_INVARIANT(id_isar5_el1)
1115FUNCTION_INVARIANT(clidr_el1)
1116FUNCTION_INVARIANT(aidr_el1)
1117
1118/* ->val is filled in by kvm_sys_reg_table_init() */
1119static struct sys_reg_desc invariant_sys_regs[] = {
1120 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000),
1121 NULL, get_midr_el1 },
1122 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110),
1123 NULL, get_revidr_el1 },
1124 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000),
1125 NULL, get_id_pfr0_el1 },
1126 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b001),
1127 NULL, get_id_pfr1_el1 },
1128 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b010),
1129 NULL, get_id_dfr0_el1 },
1130 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b011),
1131 NULL, get_id_afr0_el1 },
1132 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b100),
1133 NULL, get_id_mmfr0_el1 },
1134 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b101),
1135 NULL, get_id_mmfr1_el1 },
1136 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b110),
1137 NULL, get_id_mmfr2_el1 },
1138 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b111),
1139 NULL, get_id_mmfr3_el1 },
1140 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
1141 NULL, get_id_isar0_el1 },
1142 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b001),
1143 NULL, get_id_isar1_el1 },
1144 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
1145 NULL, get_id_isar2_el1 },
1146 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b011),
1147 NULL, get_id_isar3_el1 },
1148 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b100),
1149 NULL, get_id_isar4_el1 },
1150 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b101),
1151 NULL, get_id_isar5_el1 },
1152 { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b001),
1153 NULL, get_clidr_el1 },
1154 { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b111),
1155 NULL, get_aidr_el1 },
1156 { Op0(0b11), Op1(0b011), CRn(0b0000), CRm(0b0000), Op2(0b001),
1157 NULL, get_ctr_el0 },
1158};
1159
26c99af1 1160static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
7c8c5e6a 1161{
7c8c5e6a
MZ		 1162 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
1163 return -EFAULT;
1164 return 0;
1165}
1166
26c99af1 1167static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
7c8c5e6a 1168{
7c8c5e6a
MZ		 1169 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
1170 return -EFAULT;
1171 return 0;
1172}
1173
1174static int get_invariant_sys_reg(u64 id, void __user *uaddr)
1175{
1176 struct sys_reg_params params;
1177 const struct sys_reg_desc *r;
1178
1179 if (!index_to_params(id, &params))
1180 return -ENOENT;
1181
1182 r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1183 if (!r)
1184 return -ENOENT;
1185
1186 return reg_to_user(uaddr, &r->val, id);
1187}
1188
1189static int set_invariant_sys_reg(u64 id, void __user *uaddr)
1190{
1191 struct sys_reg_params params;
1192 const struct sys_reg_desc *r;
1193 int err;
1194 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
1195
1196 if (!index_to_params(id, &params))
1197 return -ENOENT;
1198 r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1199 if (!r)
1200 return -ENOENT;
1201
1202 err = reg_from_user(&val, uaddr, id);
1203 if (err)
1204 return err;
1205
1206 /* This is what we mean by invariant: you can't change it. */
1207 if (r->val != val)
1208 return -EINVAL;
1209
1210 return 0;
1211}
1212
1213static bool is_valid_cache(u32 val)
1214{
1215 u32 level, ctype;
1216
1217 if (val >= CSSELR_MAX)
1218 return -ENOENT;
1219
1220 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
1221 level = (val >> 1);
1222 ctype = (cache_levels >> (level * 3)) & 7;
1223
1224 switch (ctype) {
1225 case 0: /* No cache */
1226 return false;
1227 case 1: /* Instruction cache only */
1228 return (val & 1);
1229 case 2: /* Data cache only */
1230 case 4: /* Unified cache */
1231 return !(val & 1);
1232 case 3: /* Separate instruction and data caches */
1233 return true;
1234 default: /* Reserved: we can't know instruction or data. */
1235 return false;
1236 }
1237}
1238
1239static int demux_c15_get(u64 id, void __user *uaddr)
1240{
1241 u32 val;
1242 u32 __user *uval = uaddr;
1243
1244 /* Fail if we have unknown bits set. */
1245 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1246 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1247 return -ENOENT;
1248
1249 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
1250 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
1251 if (KVM_REG_SIZE(id) != 4)
1252 return -ENOENT;
1253 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
1254 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
1255 if (!is_valid_cache(val))
1256 return -ENOENT;
1257
1258 return put_user(get_ccsidr(val), uval);
1259 default:
1260 return -ENOENT;
1261 }
1262}
1263
1264static int demux_c15_set(u64 id, void __user *uaddr)
1265{
1266 u32 val, newval;
1267 u32 __user *uval = uaddr;
1268
1269 /* Fail if we have unknown bits set. */
1270 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1271 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1272 return -ENOENT;
1273
1274 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
1275 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
1276 if (KVM_REG_SIZE(id) != 4)
1277 return -ENOENT;
1278 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
1279 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
1280 if (!is_valid_cache(val))
1281 return -ENOENT;
1282
1283 if (get_user(newval, uval))
1284 return -EFAULT;
1285
1286 /* This is also invariant: you can't change it. */
1287 if (newval != get_ccsidr(val))
1288 return -EINVAL;
1289 return 0;
1290 default:
1291 return -ENOENT;
1292 }
1293}
1294
1295int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
1296{
1297 const struct sys_reg_desc *r;
1298 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
1299
1300 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
1301 return demux_c15_get(reg->id, uaddr);
1302
1303 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
1304 return -ENOENT;
1305
1306 r = index_to_sys_reg_desc(vcpu, reg->id);
1307 if (!r)
1308 return get_invariant_sys_reg(reg->id, uaddr);
1309
1310 return reg_to_user(uaddr, &vcpu_sys_reg(vcpu, r->reg), reg->id);
1311}
1312
1313int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
1314{
1315 const struct sys_reg_desc *r;
1316 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
1317
1318 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
1319 return demux_c15_set(reg->id, uaddr);
1320
1321 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
1322 return -ENOENT;
1323
1324 r = index_to_sys_reg_desc(vcpu, reg->id);
1325 if (!r)
1326 return set_invariant_sys_reg(reg->id, uaddr);
1327
1328 return reg_from_user(&vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
1329}
1330
1331static unsigned int num_demux_regs(void)
1332{
1333 unsigned int i, count = 0;
1334
1335 for (i = 0; i < CSSELR_MAX; i++)
1336 if (is_valid_cache(i))
1337 count++;
1338
1339 return count;
1340}
1341
1342static int write_demux_regids(u64 __user *uindices)
1343{
efd48cea 1344 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
7c8c5e6a
MZ		 1345 unsigned int i;
1346
1347 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
1348 for (i = 0; i < CSSELR_MAX; i++) {
1349 if (!is_valid_cache(i))
1350 continue;
1351 if (put_user(val | i, uindices))
1352 return -EFAULT;
1353 uindices++;
1354 }
1355 return 0;
1356}
1357
1358static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
1359{
1360 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
1361 KVM_REG_ARM64_SYSREG |
1362 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
1363 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
1364 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
1365 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
1366 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
1367}
1368
1369static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
1370{
1371 if (!*uind)
1372 return true;
1373
1374 if (put_user(sys_reg_to_index(reg), *uind))
1375 return false;
1376
1377 (*uind)++;
1378 return true;
1379}
1380
1381/* Assumed ordered tables, see kvm_sys_reg_table_init. */
1382static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
1383{
1384 const struct sys_reg_desc *i1, *i2, *end1, *end2;
1385 unsigned int total = 0;
1386 size_t num;
1387
1388 /* We check for duplicates here, to allow arch-specific overrides. */
62a89c44 1389 i1 = get_target_table(vcpu->arch.target, true, &num);
7c8c5e6a
MZ		 1390 end1 = i1 + num;
1391 i2 = sys_reg_descs;
1392 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
1393
1394 BUG_ON(i1 == end1 || i2 == end2);
1395
1396 /* Walk carefully, as both tables may refer to the same register. */
1397 while (i1 || i2) {
1398 int cmp = cmp_sys_reg(i1, i2);
1399 /* target-specific overrides generic entry. */
1400 if (cmp <= 0) {
1401 /* Ignore registers we trap but don't save. */
1402 if (i1->reg) {
1403 if (!copy_reg_to_user(i1, &uind))
1404 return -EFAULT;
1405 total++;
1406 }
1407 } else {
1408 /* Ignore registers we trap but don't save. */
1409 if (i2->reg) {
1410 if (!copy_reg_to_user(i2, &uind))
1411 return -EFAULT;
1412 total++;
1413 }
1414 }
1415
1416 if (cmp <= 0 && ++i1 == end1)
1417 i1 = NULL;
1418 if (cmp >= 0 && ++i2 == end2)
1419 i2 = NULL;
1420 }
1421 return total;
1422}
1423
1424unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
1425{
1426 return ARRAY_SIZE(invariant_sys_regs)
1427 + num_demux_regs()
1428 + walk_sys_regs(vcpu, (u64 __user *)NULL);
1429}
1430
1431int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
1432{
1433 unsigned int i;
1434 int err;
1435
1436 /* Then give them all the invariant registers' indices. */
1437 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
1438 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
1439 return -EFAULT;
1440 uindices++;
1441 }
1442
1443 err = walk_sys_regs(vcpu, uindices);
1444 if (err < 0)
1445 return err;
1446 uindices += err;
1447
1448 return write_demux_regids(uindices);
1449}
1450
e6a95517
MZ		 1451static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n)
1452{
1453 unsigned int i;
1454
1455 for (i = 1; i < n; i++) {
1456 if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
1457 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
1458 return 1;
1459 }
1460 }
1461
1462 return 0;
1463}
1464
7c8c5e6a
MZ		 1465void kvm_sys_reg_table_init(void)
1466{
1467 unsigned int i;
1468 struct sys_reg_desc clidr;
1469
1470 /* Make sure tables are unique and in order. */
e6a95517
MZ		 1471 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs)));
1472 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs)));
1473 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs)));
1474 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
1475 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs)));
1476 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)));
7c8c5e6a
MZ		 1477
1478 /* We abuse the reset function to overwrite the table itself. */
1479 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
1480 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
1481
1482 /*
1483 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
1484 *
1485 * If software reads the Cache Type fields from Ctype1
1486 * upwards, once it has seen a value of 0b000, no caches
1487 * exist at further-out levels of the hierarchy. So, for
1488 * example, if Ctype3 is the first Cache Type field with a
1489 * value of 0b000, the values of Ctype4 to Ctype7 must be
1490 * ignored.
1491 */
1492 get_clidr_el1(NULL, &clidr); /* Ugly... */
1493 cache_levels = clidr.val;
1494 for (i = 0; i < 7; i++)
1495 if (((cache_levels >> (i*3)) & 7) == 0)
1496 break;
1497 /* Clear all higher bits. */
1498 cache_levels &= (1 << (i*3))-1;
1499}
1500
1501/**
1502 * kvm_reset_sys_regs - sets system registers to reset value
1503 * @vcpu: The VCPU pointer
1504 *
1505 * This function finds the right table above and sets the registers on the
1506 * virtual CPU struct to their architecturally defined reset values.
1507 */
1508void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
1509{
1510 size_t num;
1511 const struct sys_reg_desc *table;
1512
1513 /* Catch someone adding a register without putting in reset entry. */
1514 memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs));
1515
1516 /* Generic chip reset first (so target could override). */
1517 reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1518
62a89c44 1519 table = get_target_table(vcpu->arch.target, true, &num);
7c8c5e6a
MZ		 1520 reset_sys_reg_descs(vcpu, table, num);
1521
1522 for (num = 1; num < NR_SYS_REGS; num++)
1523 if (vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
1524 panic("Didn't reset vcpu_sys_reg(%zi)", num);
1525}
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