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Commit | Line | Data |
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f1a0c4aa CM |
1 | /* |
2 | * Cache maintenance | |
3 | * | |
4 | * Copyright (C) 2001 Deep Blue Solutions Ltd. | |
5 | * Copyright (C) 2012 ARM Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
a2d25a53 | 20 | #include <linux/errno.h> |
f1a0c4aa CM |
21 | #include <linux/linkage.h> |
22 | #include <linux/init.h> | |
23 | #include <asm/assembler.h> | |
301bcfac | 24 | #include <asm/cpufeature.h> |
8d883b23 | 25 | #include <asm/alternative.h> |
b4b8664d | 26 | #include <asm/asm-uaccess.h> |
f1a0c4aa | 27 | |
f1a0c4aa CM |
28 | /* |
29 | * flush_icache_range(start,end) | |
30 | * | |
31 | * Ensure that the I and D caches are coherent within specified region. | |
32 | * This is typically used when code has been written to a memory region, | |
33 | * and will be executed. | |
34 | * | |
35 | * - start - virtual start address of region | |
36 | * - end - virtual end address of region | |
37 | */ | |
38 | ENTRY(flush_icache_range) | |
39 | /* FALLTHROUGH */ | |
40 | ||
41 | /* | |
42 | * __flush_cache_user_range(start,end) | |
43 | * | |
44 | * Ensure that the I and D caches are coherent within specified region. | |
45 | * This is typically used when code has been written to a memory region, | |
46 | * and will be executed. | |
47 | * | |
48 | * - start - virtual start address of region | |
49 | * - end - virtual end address of region | |
50 | */ | |
51 | ENTRY(__flush_cache_user_range) | |
448fadc8 | 52 | uaccess_ttbr0_enable x2, x3, x4 |
f1a0c4aa CM |
53 | dcache_line_size x2, x3 |
54 | sub x3, x2, #1 | |
55 | bic x4, x0, x3 | |
56 | 1: | |
290622ef | 57 | user_alt 9f, "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE |
f1a0c4aa CM |
58 | add x4, x4, x2 |
59 | cmp x4, x1 | |
60 | b.lo 1b | |
dc60b777 | 61 | dsb ish |
f1a0c4aa | 62 | |
4fee9473 | 63 | invalidate_icache_by_line x0, x1, x2, x3, 9f |
a2d25a53 | 64 | mov x0, #0 |
39bc88e5 | 65 | 1: |
0482b505 | 66 | uaccess_ttbr0_disable x1, x2 |
a2d25a53 VM |
67 | ret |
68 | 9: | |
69 | mov x0, #-EFAULT | |
39bc88e5 | 70 | b 1b |
f1a0c4aa CM |
71 | ENDPROC(flush_icache_range) |
72 | ENDPROC(__flush_cache_user_range) | |
73 | ||
4fee9473 MZ |
74 | /* |
75 | * invalidate_icache_range(start,end) | |
76 | * | |
77 | * Ensure that the I cache is invalid within specified region. | |
78 | * | |
79 | * - start - virtual start address of region | |
80 | * - end - virtual end address of region | |
81 | */ | |
82 | ENTRY(invalidate_icache_range) | |
448fadc8 | 83 | uaccess_ttbr0_enable x2, x3, x4 |
4fee9473 MZ |
84 | |
85 | invalidate_icache_by_line x0, x1, x2, x3, 2f | |
86 | mov x0, xzr | |
87 | 1: | |
0482b505 | 88 | uaccess_ttbr0_disable x1, x2 |
4fee9473 MZ |
89 | ret |
90 | 2: | |
91 | mov x0, #-EFAULT | |
92 | b 1b | |
93 | ENDPROC(invalidate_icache_range) | |
94 | ||
f1a0c4aa | 95 | /* |
03324e6e | 96 | * __flush_dcache_area(kaddr, size) |
f1a0c4aa | 97 | * |
0a28714c AK |
98 | * Ensure that any D-cache lines for the interval [kaddr, kaddr+size) |
99 | * are cleaned and invalidated to the PoC. | |
f1a0c4aa CM |
100 | * |
101 | * - kaddr - kernel address | |
102 | * - size - size in question | |
103 | */ | |
104 | ENTRY(__flush_dcache_area) | |
0a28714c | 105 | dcache_by_line_op civac, sy, x0, x1, x2, x3 |
f1a0c4aa | 106 | ret |
20791846 | 107 | ENDPIPROC(__flush_dcache_area) |
7363590d | 108 | |
0a28714c AK |
109 | /* |
110 | * __clean_dcache_area_pou(kaddr, size) | |
111 | * | |
112 | * Ensure that any D-cache lines for the interval [kaddr, kaddr+size) | |
113 | * are cleaned to the PoU. | |
114 | * | |
115 | * - kaddr - kernel address | |
116 | * - size - size in question | |
117 | */ | |
118 | ENTRY(__clean_dcache_area_pou) | |
119 | dcache_by_line_op cvau, ish, x0, x1, x2, x3 | |
120 | ret | |
121 | ENDPROC(__clean_dcache_area_pou) | |
122 | ||
c218bca7 | 123 | /* |
d46befef RM |
124 | * __inval_dcache_area(kaddr, size) |
125 | * | |
126 | * Ensure that any D-cache lines for the interval [kaddr, kaddr+size) | |
127 | * are invalidated. Any partial lines at the ends of the interval are | |
128 | * also cleaned to PoC to prevent data loss. | |
129 | * | |
130 | * - kaddr - kernel address | |
d34fdb70 | 131 | * - size - size in question |
c218bca7 | 132 | */ |
d46befef | 133 | ENTRY(__inval_dcache_area) |
c218bca7 CM |
134 | /* FALLTHROUGH */ |
135 | ||
7363590d | 136 | /* |
d46befef RM |
137 | * __dma_inv_area(start, size) |
138 | * - start - virtual start address of region | |
139 | * - size - size in question | |
7363590d | 140 | */ |
d46befef RM |
141 | __dma_inv_area: |
142 | add x1, x1, x0 | |
7363590d CM |
143 | dcache_line_size x2, x3 |
144 | sub x3, x2, #1 | |
ebf81a93 | 145 | tst x1, x3 // end cache line aligned? |
7363590d | 146 | bic x1, x1, x3 |
ebf81a93 CM |
147 | b.eq 1f |
148 | dc civac, x1 // clean & invalidate D / U line | |
149 | 1: tst x0, x3 // start cache line aligned? | |
150 | bic x0, x0, x3 | |
151 | b.eq 2f | |
152 | dc civac, x0 // clean & invalidate D / U line | |
153 | b 3f | |
154 | 2: dc ivac, x0 // invalidate D / U line | |
155 | 3: add x0, x0, x2 | |
7363590d | 156 | cmp x0, x1 |
ebf81a93 | 157 | b.lo 2b |
7363590d CM |
158 | dsb sy |
159 | ret | |
d46befef | 160 | ENDPIPROC(__inval_dcache_area) |
d34fdb70 KL |
161 | ENDPROC(__dma_inv_area) |
162 | ||
163 | /* | |
164 | * __clean_dcache_area_poc(kaddr, size) | |
165 | * | |
166 | * Ensure that any D-cache lines for the interval [kaddr, kaddr+size) | |
167 | * are cleaned to the PoC. | |
168 | * | |
169 | * - kaddr - kernel address | |
170 | * - size - size in question | |
171 | */ | |
172 | ENTRY(__clean_dcache_area_poc) | |
173 | /* FALLTHROUGH */ | |
7363590d CM |
174 | |
175 | /* | |
d34fdb70 | 176 | * __dma_clean_area(start, size) |
7363590d | 177 | * - start - virtual start address of region |
d34fdb70 | 178 | * - size - size in question |
7363590d | 179 | */ |
d34fdb70 KL |
180 | __dma_clean_area: |
181 | dcache_by_line_op cvac, sy, x0, x1, x2, x3 | |
7363590d | 182 | ret |
d34fdb70 KL |
183 | ENDPIPROC(__clean_dcache_area_poc) |
184 | ENDPROC(__dma_clean_area) | |
7363590d | 185 | |
d50e071f RM |
186 | /* |
187 | * __clean_dcache_area_pop(kaddr, size) | |
188 | * | |
189 | * Ensure that any D-cache lines for the interval [kaddr, kaddr+size) | |
190 | * are cleaned to the PoP. | |
191 | * | |
192 | * - kaddr - kernel address | |
193 | * - size - size in question | |
194 | */ | |
195 | ENTRY(__clean_dcache_area_pop) | |
196 | dcache_by_line_op cvap, sy, x0, x1, x2, x3 | |
197 | ret | |
198 | ENDPIPROC(__clean_dcache_area_pop) | |
199 | ||
7363590d | 200 | /* |
d34fdb70 KL |
201 | * __dma_flush_area(start, size) |
202 | * | |
203 | * clean & invalidate D / U line | |
204 | * | |
7363590d | 205 | * - start - virtual start address of region |
d34fdb70 | 206 | * - size - size in question |
7363590d | 207 | */ |
d34fdb70 KL |
208 | ENTRY(__dma_flush_area) |
209 | dcache_by_line_op civac, sy, x0, x1, x2, x3 | |
7363590d | 210 | ret |
d34fdb70 | 211 | ENDPIPROC(__dma_flush_area) |
7363590d CM |
212 | |
213 | /* | |
214 | * __dma_map_area(start, size, dir) | |
215 | * - start - kernel virtual start address | |
216 | * - size - size of region | |
217 | * - dir - DMA direction | |
218 | */ | |
219 | ENTRY(__dma_map_area) | |
7363590d | 220 | cmp w2, #DMA_FROM_DEVICE |
d34fdb70 KL |
221 | b.eq __dma_inv_area |
222 | b __dma_clean_area | |
20791846 | 223 | ENDPIPROC(__dma_map_area) |
7363590d CM |
224 | |
225 | /* | |
226 | * __dma_unmap_area(start, size, dir) | |
227 | * - start - kernel virtual start address | |
228 | * - size - size of region | |
229 | * - dir - DMA direction | |
230 | */ | |
231 | ENTRY(__dma_unmap_area) | |
7363590d | 232 | cmp w2, #DMA_TO_DEVICE |
d34fdb70 | 233 | b.ne __dma_inv_area |
7363590d | 234 | ret |
20791846 | 235 | ENDPIPROC(__dma_unmap_area) |