[mirror_ubuntu-zesty-kernel.git] / arch / arm64 / mm / context.c

/*
 * Based on arch/arm/mm/context.c
 *
 * Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved.
 * Copyright (C) 2012 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/bitops.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/mm.h>

#include <asm/cpufeature.h>
#include <asm/mmu_context.h>
#include <asm/tlbflush.h>

static u32 asid_bits;
static DEFINE_RAW_SPINLOCK(cpu_asid_lock);

static atomic64_t asid_generation;
static unsigned long *asid_map;

static DEFINE_PER_CPU(atomic64_t, active_asids);
static DEFINE_PER_CPU(u64, reserved_asids);
static cpumask_t tlb_flush_pending;

#define ASID_MASK		(~GENMASK(asid_bits - 1, 0))
#define ASID_FIRST_VERSION	(1UL << asid_bits)
#define NUM_USER_ASIDS		ASID_FIRST_VERSION

static void flush_context(unsigned int cpu)
{
	int i;
	u64 asid;

	/* Update the list of reserved ASIDs and the ASID bitmap. */
	bitmap_clear(asid_map, 0, NUM_USER_ASIDS);

	/*
	 * Ensure the generation bump is observed before we xchg the
	 * active_asids.
	 */
	smp_wmb();

	for_each_possible_cpu(i) {
		asid = atomic64_xchg_relaxed(&per_cpu(active_asids, i), 0);
		/*
		 * If this CPU has already been through a
		 * rollover, but hasn't run another task in
		 * the meantime, we must preserve its reserved
		 * ASID, as this is the only trace we have of
		 * the process it is still running.
		 */
		if (asid == 0)
			asid = per_cpu(reserved_asids, i);
		__set_bit(asid & ~ASID_MASK, asid_map);
		per_cpu(reserved_asids, i) = asid;
	}

	/* Queue a TLB invalidate and flush the I-cache if necessary. */
	cpumask_setall(&tlb_flush_pending);

	if (icache_is_aivivt())
		__flush_icache_all();
}

static bool check_update_reserved_asid(u64 asid, u64 newasid)
{
	int cpu;
	bool hit = false;

	/*
	 * Iterate over the set of reserved ASIDs looking for a match.
	 * If we find one, then we can update our mm to use newasid
	 * (i.e. the same ASID in the current generation) but we can't
	 * exit the loop early, since we need to ensure that all copies
	 * of the old ASID are updated to reflect the mm. Failure to do
	 * so could result in us missing the reserved ASID in a future
	 * generation.
	 */
	for_each_possible_cpu(cpu) {
		if (per_cpu(reserved_asids, cpu) == asid) {
			hit = true;
			per_cpu(reserved_asids, cpu) = newasid;
		}
	}

	return hit;
}

static u64 new_context(struct mm_struct *mm, unsigned int cpu)
{
	static u32 cur_idx = 1;
	u64 asid = atomic64_read(&mm->context.id);
	u64 generation = atomic64_read(&asid_generation);

	if (asid != 0) {
		u64 newasid = generation | (asid & ~ASID_MASK);

		/*
		 * If our current ASID was active during a rollover, we
		 * can continue to use it and this was just a false alarm.
		 */
		if (check_update_reserved_asid(asid, newasid))
			return newasid;

		/*
		 * We had a valid ASID in a previous life, so try to re-use
		 * it if possible.
		 */
		asid &= ~ASID_MASK;
		if (!__test_and_set_bit(asid, asid_map))
			return newasid;
	}

	/*
	 * Allocate a free ASID. If we can't find one, take a note of the
	 * currently active ASIDs and mark the TLBs as requiring flushes.
	 * We always count from ASID #1, as we use ASID #0 when setting a
	 * reserved TTBR0 for the init_mm.
	 */
	asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, cur_idx);
	if (asid != NUM_USER_ASIDS)
		goto set_asid;

	/* We're out of ASIDs, so increment the global generation count */
	generation = atomic64_add_return_relaxed(ASID_FIRST_VERSION,
						 &asid_generation);
	flush_context(cpu);

	/* We have at least 1 ASID per CPU, so this will always succeed */
	asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1);

set_asid:
	__set_bit(asid, asid_map);
	cur_idx = asid;
	return asid | generation;
}

void check_and_switch_context(struct mm_struct *mm, unsigned int cpu)
{
	unsigned long flags;
	u64 asid;

	asid = atomic64_read(&mm->context.id);

	/*
	 * The memory ordering here is subtle. We rely on the control
	 * dependency between the generation read and the update of
	 * active_asids to ensure that we are synchronised with a
	 * parallel rollover (i.e. this pairs with the smp_wmb() in
	 * flush_context).
	 */
	if (!((asid ^ atomic64_read(&asid_generation)) >> asid_bits)
	    && atomic64_xchg_relaxed(&per_cpu(active_asids, cpu), asid))
		goto switch_mm_fastpath;

	raw_spin_lock_irqsave(&cpu_asid_lock, flags);
	/* Check that our ASID belongs to the current generation. */
	asid = atomic64_read(&mm->context.id);
	if ((asid ^ atomic64_read(&asid_generation)) >> asid_bits) {
		asid = new_context(mm, cpu);
		atomic64_set(&mm->context.id, asid);
	}

	if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending))
		local_flush_tlb_all();

	atomic64_set(&per_cpu(active_asids, cpu), asid);
	raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);

switch_mm_fastpath:
	cpu_switch_mm(mm->pgd, mm);
}

static int asids_init(void)
{
	int fld = cpuid_feature_extract_field(read_cpuid(SYS_ID_AA64MMFR0_EL1), 4);

	switch (fld) {
	default:
		pr_warn("Unknown ASID size (%d); assuming 8-bit\n", fld);
		/* Fallthrough */
	case 0:
		asid_bits = 8;
		break;
	case 2:
		asid_bits = 16;
	}

	/* If we end up with more CPUs than ASIDs, expect things to crash */
	WARN_ON(NUM_USER_ASIDS < num_possible_cpus());
	atomic64_set(&asid_generation, ASID_FIRST_VERSION);
	asid_map = kzalloc(BITS_TO_LONGS(NUM_USER_ASIDS) * sizeof(*asid_map),
			   GFP_KERNEL);
	if (!asid_map)
		panic("Failed to allocate bitmap for %lu ASIDs\n",
		      NUM_USER_ASIDS);

	pr_info("ASID allocator initialised with %lu entries\n", NUM_USER_ASIDS);
	return 0;
}
early_initcall(asids_init);
Commit	Line	Data
b3901d54 CM	1	/*
	2	* Based on arch/arm/mm/context.c
	3	*
	4	* Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved.
	5	* Copyright (C) 2012 ARM Ltd.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
5aec715d	20	#include <linux/bitops.h>
b3901d54	21	#include <linux/sched.h>
5aec715d	22	#include <linux/slab.h>
b3901d54	23	#include <linux/mm.h>
b3901d54	24
5aec715d	25	#include <asm/cpufeature.h>
b3901d54 CM	26	#include <asm/mmu_context.h>
b3901d54 CM	27	#include <asm/tlbflush.h>
b3901d54	28
5aec715d WD	29	static u32 asid_bits;
5aec715d WD	30	static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
b3901d54	31
5aec715d WD	32	static atomic64_t asid_generation;
5aec715d WD	33	static unsigned long *asid_map;
b3901d54	34
5aec715d WD	35	static DEFINE_PER_CPU(atomic64_t, active_asids);
	36	static DEFINE_PER_CPU(u64, reserved_asids);
	37	static cpumask_t tlb_flush_pending;
b3901d54	38
5aec715d WD	39	#define ASID_MASK (~GENMASK(asid_bits - 1, 0))
	40	#define ASID_FIRST_VERSION (1UL << asid_bits)
	41	#define NUM_USER_ASIDS ASID_FIRST_VERSION
	42
	43	static void flush_context(unsigned int cpu)
b3901d54	44	{
5aec715d WD	45	int i;
	46	u64 asid;
	47
	48	/* Update the list of reserved ASIDs and the ASID bitmap. */
	49	bitmap_clear(asid_map, 0, NUM_USER_ASIDS);
	50
	51	/*
	52	* Ensure the generation bump is observed before we xchg the
	53	* active_asids.
	54	*/
	55	smp_wmb();
	56
	57	for_each_possible_cpu(i) {
	58	asid = atomic64_xchg_relaxed(&per_cpu(active_asids, i), 0);
	59	/*
	60	* If this CPU has already been through a
	61	* rollover, but hasn't run another task in
	62	* the meantime, we must preserve its reserved
	63	* ASID, as this is the only trace we have of
	64	* the process it is still running.
	65	*/
	66	if (asid == 0)
	67	asid = per_cpu(reserved_asids, i);
	68	__set_bit(asid & ~ASID_MASK, asid_map);
	69	per_cpu(reserved_asids, i) = asid;
	70	}
	71
	72	/* Queue a TLB invalidate and flush the I-cache if necessary. */
	73	cpumask_setall(&tlb_flush_pending);
	74
	75	if (icache_is_aivivt())
	76	__flush_icache_all();
b3901d54 CM	77	}
b3901d54 CM	78
0ebea808	79	static bool check_update_reserved_asid(u64 asid, u64 newasid)
b3901d54	80	{
5aec715d	81	int cpu;
0ebea808 WD	82	bool hit = false;
	83
	84	/*
	85	* Iterate over the set of reserved ASIDs looking for a match.
	86	* If we find one, then we can update our mm to use newasid
	87	* (i.e. the same ASID in the current generation) but we can't
	88	* exit the loop early, since we need to ensure that all copies
	89	* of the old ASID are updated to reflect the mm. Failure to do
	90	* so could result in us missing the reserved ASID in a future
	91	* generation.
	92	*/
	93	for_each_possible_cpu(cpu) {
	94	if (per_cpu(reserved_asids, cpu) == asid) {
	95	hit = true;
	96	per_cpu(reserved_asids, cpu) = newasid;
	97	}
	98	}
	99
	100	return hit;
b3901d54 CM	101	}
b3901d54 CM	102
5aec715d	103	static u64 new_context(struct mm_struct *mm, unsigned int cpu)
b3901d54	104	{
5aec715d WD	105	static u32 cur_idx = 1;
	106	u64 asid = atomic64_read(&mm->context.id);
	107	u64 generation = atomic64_read(&asid_generation);
b3901d54	108
5aec715d	109	if (asid != 0) {
0ebea808 WD	110	u64 newasid = generation \| (asid & ~ASID_MASK);
0ebea808 WD	111
b3901d54	112	/*
5aec715d WD	113	* If our current ASID was active during a rollover, we
5aec715d WD	114	* can continue to use it and this was just a false alarm.
b3901d54	115	*/
0ebea808 WD	116	if (check_update_reserved_asid(asid, newasid))
0ebea808 WD	117	return newasid;
5aec715d WD	118
	119	/*
	120	* We had a valid ASID in a previous life, so try to re-use
	121	* it if possible.
	122	*/
	123	asid &= ~ASID_MASK;
	124	if (!__test_and_set_bit(asid, asid_map))
0ebea808	125	return newasid;
b3901d54	126	}
b3901d54 CM	127
b3901d54 CM	128	/*
5aec715d WD	129	* Allocate a free ASID. If we can't find one, take a note of the
	130	* currently active ASIDs and mark the TLBs as requiring flushes.
	131	* We always count from ASID #1, as we use ASID #0 when setting a
	132	* reserved TTBR0 for the init_mm.
b3901d54	133	*/
5aec715d WD	134	asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, cur_idx);
	135	if (asid != NUM_USER_ASIDS)
	136	goto set_asid;
	137
	138	/* We're out of ASIDs, so increment the global generation count */
	139	generation = atomic64_add_return_relaxed(ASID_FIRST_VERSION,
	140	&asid_generation);
	141	flush_context(cpu);
	142
	143	/* We have at least 1 ASID per CPU, so this will always succeed */
	144	asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1);
	145
	146	set_asid:
	147	__set_bit(asid, asid_map);
	148	cur_idx = asid;
0ebea808	149	return asid \| generation;
b3901d54 CM	150	}
b3901d54 CM	151
5aec715d	152	void check_and_switch_context(struct mm_struct *mm, unsigned int cpu)
b3901d54	153	{
5aec715d WD	154	unsigned long flags;
	155	u64 asid;
	156
	157	asid = atomic64_read(&mm->context.id);
b3901d54	158
565630d5	159	/*
5aec715d WD	160	* The memory ordering here is subtle. We rely on the control
	161	* dependency between the generation read and the update of
	162	* active_asids to ensure that we are synchronised with a
	163	* parallel rollover (i.e. this pairs with the smp_wmb() in
	164	* flush_context).
565630d5	165	*/
5aec715d WD	166	if (!((asid ^ atomic64_read(&asid_generation)) >> asid_bits)
	167	&& atomic64_xchg_relaxed(&per_cpu(active_asids, cpu), asid))
	168	goto switch_mm_fastpath;
	169
	170	raw_spin_lock_irqsave(&cpu_asid_lock, flags);
	171	/* Check that our ASID belongs to the current generation. */
	172	asid = atomic64_read(&mm->context.id);
	173	if ((asid ^ atomic64_read(&asid_generation)) >> asid_bits) {
	174	asid = new_context(mm, cpu);
	175	atomic64_set(&mm->context.id, asid);
	176	}
565630d5	177
5aec715d WD	178	if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending))
5aec715d WD	179	local_flush_tlb_all();
b3901d54	180
5aec715d	181	atomic64_set(&per_cpu(active_asids, cpu), asid);
5aec715d	182	raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
b3901d54	183
5aec715d	184	switch_mm_fastpath:
b3901d54 CM	185	cpu_switch_mm(mm->pgd, mm);
	186	}
	187
5aec715d	188	static int asids_init(void)
b3901d54	189	{
0f54b14e	190	int fld = cpuid_feature_extract_field(read_cpuid(SYS_ID_AA64MMFR0_EL1), 4);
5aec715d WD	191
	192	switch (fld) {
	193	default:
	194	pr_warn("Unknown ASID size (%d); assuming 8-bit\n", fld);
	195	/* Fallthrough */
	196	case 0:
	197	asid_bits = 8;
	198	break;
	199	case 2:
	200	asid_bits = 16;
b3901d54 CM	201	}
b3901d54 CM	202
5aec715d WD	203	/* If we end up with more CPUs than ASIDs, expect things to crash */
	204	WARN_ON(NUM_USER_ASIDS < num_possible_cpus());
	205	atomic64_set(&asid_generation, ASID_FIRST_VERSION);
	206	asid_map = kzalloc(BITS_TO_LONGS(NUM_USER_ASIDS) * sizeof(*asid_map),
	207	GFP_KERNEL);
	208	if (!asid_map)
	209	panic("Failed to allocate bitmap for %lu ASIDs\n",
	210	NUM_USER_ASIDS);
	211
	212	pr_info("ASID allocator initialised with %lu entries\n", NUM_USER_ASIDS);
	213	return 0;
b3901d54	214	}
5aec715d	215	early_initcall(asids_init);