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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1d18c47c CM |
2 | /* |
3 | * Based on arch/arm/mm/fault.c | |
4 | * | |
5 | * Copyright (C) 1995 Linus Torvalds | |
6 | * Copyright (C) 1995-2004 Russell King | |
7 | * Copyright (C) 2012 ARM Ltd. | |
1d18c47c CM |
8 | */ |
9 | ||
d44f1b8d | 10 | #include <linux/acpi.h> |
0edfa839 | 11 | #include <linux/extable.h> |
1d18c47c CM |
12 | #include <linux/signal.h> |
13 | #include <linux/mm.h> | |
14 | #include <linux/hardirq.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/kprobes.h> | |
17 | #include <linux/uaccess.h> | |
18 | #include <linux/page-flags.h> | |
3f07c014 | 19 | #include <linux/sched/signal.h> |
b17b0153 | 20 | #include <linux/sched/debug.h> |
1d18c47c CM |
21 | #include <linux/highmem.h> |
22 | #include <linux/perf_event.h> | |
7209c868 | 23 | #include <linux/preempt.h> |
e7c600f1 | 24 | #include <linux/hugetlb.h> |
1d18c47c | 25 | |
d44f1b8d | 26 | #include <asm/acpi.h> |
7209c868 | 27 | #include <asm/bug.h> |
3bbf7157 | 28 | #include <asm/cmpxchg.h> |
338d4f49 | 29 | #include <asm/cpufeature.h> |
1d18c47c | 30 | #include <asm/exception.h> |
9a0c0328 | 31 | #include <asm/daifflags.h> |
1d18c47c | 32 | #include <asm/debug-monitors.h> |
9141300a | 33 | #include <asm/esr.h> |
356607f2 | 34 | #include <asm/kasan.h> |
338d4f49 | 35 | #include <asm/sysreg.h> |
1d18c47c CM |
36 | #include <asm/system_misc.h> |
37 | #include <asm/pgtable.h> | |
38 | #include <asm/tlbflush.h> | |
92ff0674 | 39 | #include <asm/traps.h> |
1d18c47c | 40 | |
09a6adf5 VK |
41 | struct fault_info { |
42 | int (*fn)(unsigned long addr, unsigned int esr, | |
43 | struct pt_regs *regs); | |
44 | int sig; | |
45 | int code; | |
46 | const char *name; | |
47 | }; | |
48 | ||
49 | static const struct fault_info fault_info[]; | |
359048f9 | 50 | static struct fault_info debug_fault_info[]; |
09a6adf5 VK |
51 | |
52 | static inline const struct fault_info *esr_to_fault_info(unsigned int esr) | |
53 | { | |
00bbd5d9 | 54 | return fault_info + (esr & ESR_ELx_FSC); |
09a6adf5 | 55 | } |
3495386b | 56 | |
359048f9 AK |
57 | static inline const struct fault_info *esr_to_debug_fault_info(unsigned int esr) |
58 | { | |
59 | return debug_fault_info + DBG_ESR_EVT(esr); | |
60 | } | |
61 | ||
2dd0e8d2 SP |
62 | #ifdef CONFIG_KPROBES |
63 | static inline int notify_page_fault(struct pt_regs *regs, unsigned int esr) | |
64 | { | |
65 | int ret = 0; | |
66 | ||
67 | /* kprobe_running() needs smp_processor_id() */ | |
68 | if (!user_mode(regs)) { | |
69 | preempt_disable(); | |
70 | if (kprobe_running() && kprobe_fault_handler(regs, esr)) | |
71 | ret = 1; | |
72 | preempt_enable(); | |
73 | } | |
74 | ||
75 | return ret; | |
76 | } | |
77 | #else | |
78 | static inline int notify_page_fault(struct pt_regs *regs, unsigned int esr) | |
79 | { | |
80 | return 0; | |
81 | } | |
82 | #endif | |
83 | ||
1f9b8936 JT |
84 | static void data_abort_decode(unsigned int esr) |
85 | { | |
86 | pr_alert("Data abort info:\n"); | |
87 | ||
88 | if (esr & ESR_ELx_ISV) { | |
89 | pr_alert(" Access size = %u byte(s)\n", | |
90 | 1U << ((esr & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT)); | |
91 | pr_alert(" SSE = %lu, SRT = %lu\n", | |
92 | (esr & ESR_ELx_SSE) >> ESR_ELx_SSE_SHIFT, | |
93 | (esr & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT); | |
94 | pr_alert(" SF = %lu, AR = %lu\n", | |
95 | (esr & ESR_ELx_SF) >> ESR_ELx_SF_SHIFT, | |
96 | (esr & ESR_ELx_AR) >> ESR_ELx_AR_SHIFT); | |
97 | } else { | |
0a6de8b8 | 98 | pr_alert(" ISV = 0, ISS = 0x%08lx\n", esr & ESR_ELx_ISS_MASK); |
1f9b8936 JT |
99 | } |
100 | ||
101 | pr_alert(" CM = %lu, WnR = %lu\n", | |
102 | (esr & ESR_ELx_CM) >> ESR_ELx_CM_SHIFT, | |
103 | (esr & ESR_ELx_WNR) >> ESR_ELx_WNR_SHIFT); | |
104 | } | |
105 | ||
1f9b8936 JT |
106 | static void mem_abort_decode(unsigned int esr) |
107 | { | |
108 | pr_alert("Mem abort info:\n"); | |
109 | ||
42dbf54e | 110 | pr_alert(" ESR = 0x%08x\n", esr); |
1f9b8936 JT |
111 | pr_alert(" Exception class = %s, IL = %u bits\n", |
112 | esr_get_class_string(esr), | |
113 | (esr & ESR_ELx_IL) ? 32 : 16); | |
114 | pr_alert(" SET = %lu, FnV = %lu\n", | |
115 | (esr & ESR_ELx_SET_MASK) >> ESR_ELx_SET_SHIFT, | |
116 | (esr & ESR_ELx_FnV) >> ESR_ELx_FnV_SHIFT); | |
117 | pr_alert(" EA = %lu, S1PTW = %lu\n", | |
118 | (esr & ESR_ELx_EA) >> ESR_ELx_EA_SHIFT, | |
119 | (esr & ESR_ELx_S1PTW) >> ESR_ELx_S1PTW_SHIFT); | |
120 | ||
121 | if (esr_is_data_abort(esr)) | |
122 | data_abort_decode(esr); | |
123 | } | |
124 | ||
356607f2 AK |
125 | static inline bool is_ttbr0_addr(unsigned long addr) |
126 | { | |
127 | /* entry assembly clears tags for TTBR0 addrs */ | |
128 | return addr < TASK_SIZE; | |
129 | } | |
130 | ||
131 | static inline bool is_ttbr1_addr(unsigned long addr) | |
132 | { | |
133 | /* TTBR1 addresses may have a tag if KASAN_SW_TAGS is in use */ | |
134 | return arch_kasan_reset_tag(addr) >= VA_START; | |
135 | } | |
136 | ||
1d18c47c | 137 | /* |
67ce16ec | 138 | * Dump out the page tables associated with 'addr' in the currently active mm. |
1d18c47c | 139 | */ |
7048a597 | 140 | static void show_pte(unsigned long addr) |
1d18c47c | 141 | { |
67ce16ec | 142 | struct mm_struct *mm; |
20a004e7 WD |
143 | pgd_t *pgdp; |
144 | pgd_t pgd; | |
1d18c47c | 145 | |
356607f2 | 146 | if (is_ttbr0_addr(addr)) { |
67ce16ec KM |
147 | /* TTBR0 */ |
148 | mm = current->active_mm; | |
149 | if (mm == &init_mm) { | |
150 | pr_alert("[%016lx] user address but active_mm is swapper\n", | |
151 | addr); | |
152 | return; | |
153 | } | |
356607f2 | 154 | } else if (is_ttbr1_addr(addr)) { |
67ce16ec | 155 | /* TTBR1 */ |
1d18c47c | 156 | mm = &init_mm; |
67ce16ec KM |
157 | } else { |
158 | pr_alert("[%016lx] address between user and kernel address ranges\n", | |
159 | addr); | |
160 | return; | |
161 | } | |
1d18c47c | 162 | |
48caebf7 | 163 | pr_alert("%s pgtable: %luk pages, %u-bit VAs, pgdp=%016lx\n", |
1eb34b6e | 164 | mm == &init_mm ? "swapper" : "user", PAGE_SIZE / SZ_1K, |
48caebf7 WD |
165 | mm == &init_mm ? VA_BITS : (int)vabits_user, |
166 | (unsigned long)virt_to_phys(mm->pgd)); | |
20a004e7 WD |
167 | pgdp = pgd_offset(mm, addr); |
168 | pgd = READ_ONCE(*pgdp); | |
169 | pr_alert("[%016lx] pgd=%016llx", addr, pgd_val(pgd)); | |
1d18c47c CM |
170 | |
171 | do { | |
20a004e7 WD |
172 | pud_t *pudp, pud; |
173 | pmd_t *pmdp, pmd; | |
174 | pte_t *ptep, pte; | |
1d18c47c | 175 | |
20a004e7 | 176 | if (pgd_none(pgd) || pgd_bad(pgd)) |
1d18c47c CM |
177 | break; |
178 | ||
20a004e7 WD |
179 | pudp = pud_offset(pgdp, addr); |
180 | pud = READ_ONCE(*pudp); | |
181 | pr_cont(", pud=%016llx", pud_val(pud)); | |
182 | if (pud_none(pud) || pud_bad(pud)) | |
1d18c47c CM |
183 | break; |
184 | ||
20a004e7 WD |
185 | pmdp = pmd_offset(pudp, addr); |
186 | pmd = READ_ONCE(*pmdp); | |
187 | pr_cont(", pmd=%016llx", pmd_val(pmd)); | |
188 | if (pmd_none(pmd) || pmd_bad(pmd)) | |
1d18c47c CM |
189 | break; |
190 | ||
20a004e7 WD |
191 | ptep = pte_offset_map(pmdp, addr); |
192 | pte = READ_ONCE(*ptep); | |
193 | pr_cont(", pte=%016llx", pte_val(pte)); | |
194 | pte_unmap(ptep); | |
1d18c47c CM |
195 | } while(0); |
196 | ||
6ef4fb38 | 197 | pr_cont("\n"); |
1d18c47c CM |
198 | } |
199 | ||
66dbd6e6 CM |
200 | /* |
201 | * This function sets the access flags (dirty, accessed), as well as write | |
202 | * permission, and only to a more permissive setting. | |
203 | * | |
204 | * It needs to cope with hardware update of the accessed/dirty state by other | |
205 | * agents in the system and can safely skip the __sync_icache_dcache() call as, | |
206 | * like set_pte_at(), the PTE is never changed from no-exec to exec here. | |
207 | * | |
208 | * Returns whether or not the PTE actually changed. | |
209 | */ | |
210 | int ptep_set_access_flags(struct vm_area_struct *vma, | |
211 | unsigned long address, pte_t *ptep, | |
212 | pte_t entry, int dirty) | |
213 | { | |
3bbf7157 | 214 | pteval_t old_pteval, pteval; |
20a004e7 | 215 | pte_t pte = READ_ONCE(*ptep); |
66dbd6e6 | 216 | |
20a004e7 | 217 | if (pte_same(pte, entry)) |
66dbd6e6 CM |
218 | return 0; |
219 | ||
220 | /* only preserve the access flags and write permission */ | |
73e86cb0 | 221 | pte_val(entry) &= PTE_RDONLY | PTE_AF | PTE_WRITE | PTE_DIRTY; |
66dbd6e6 CM |
222 | |
223 | /* | |
224 | * Setting the flags must be done atomically to avoid racing with the | |
6d332747 CM |
225 | * hardware update of the access/dirty state. The PTE_RDONLY bit must |
226 | * be set to the most permissive (lowest value) of *ptep and entry | |
227 | * (calculated as: a & b == ~(~a | ~b)). | |
66dbd6e6 | 228 | */ |
6d332747 | 229 | pte_val(entry) ^= PTE_RDONLY; |
20a004e7 | 230 | pteval = pte_val(pte); |
3bbf7157 CM |
231 | do { |
232 | old_pteval = pteval; | |
233 | pteval ^= PTE_RDONLY; | |
234 | pteval |= pte_val(entry); | |
235 | pteval ^= PTE_RDONLY; | |
236 | pteval = cmpxchg_relaxed(&pte_val(*ptep), old_pteval, pteval); | |
237 | } while (pteval != old_pteval); | |
66dbd6e6 CM |
238 | |
239 | flush_tlb_fix_spurious_fault(vma, address); | |
240 | return 1; | |
241 | } | |
66dbd6e6 | 242 | |
9adeb8e7 LA |
243 | static bool is_el1_instruction_abort(unsigned int esr) |
244 | { | |
245 | return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_CUR; | |
246 | } | |
247 | ||
dbfe3828 AK |
248 | static inline bool is_el1_permission_fault(unsigned long addr, unsigned int esr, |
249 | struct pt_regs *regs) | |
b824b930 SB |
250 | { |
251 | unsigned int ec = ESR_ELx_EC(esr); | |
252 | unsigned int fsc_type = esr & ESR_ELx_FSC_TYPE; | |
253 | ||
254 | if (ec != ESR_ELx_EC_DABT_CUR && ec != ESR_ELx_EC_IABT_CUR) | |
255 | return false; | |
256 | ||
257 | if (fsc_type == ESR_ELx_FSC_PERM) | |
258 | return true; | |
259 | ||
356607f2 | 260 | if (is_ttbr0_addr(addr) && system_uses_ttbr0_pan()) |
b824b930 SB |
261 | return fsc_type == ESR_ELx_FSC_FAULT && |
262 | (regs->pstate & PSR_PAN_BIT); | |
263 | ||
264 | return false; | |
265 | } | |
266 | ||
c870f14e MR |
267 | static void die_kernel_fault(const char *msg, unsigned long addr, |
268 | unsigned int esr, struct pt_regs *regs) | |
269 | { | |
270 | bust_spinlocks(1); | |
271 | ||
272 | pr_alert("Unable to handle kernel %s at virtual address %016lx\n", msg, | |
273 | addr); | |
274 | ||
275 | mem_abort_decode(esr); | |
276 | ||
277 | show_pte(addr); | |
278 | die("Oops", regs, esr); | |
279 | bust_spinlocks(0); | |
280 | do_exit(SIGKILL); | |
281 | } | |
282 | ||
67ce16ec KM |
283 | static void __do_kernel_fault(unsigned long addr, unsigned int esr, |
284 | struct pt_regs *regs) | |
1d18c47c | 285 | { |
b824b930 SB |
286 | const char *msg; |
287 | ||
1d18c47c CM |
288 | /* |
289 | * Are we prepared to handle this kernel fault? | |
9adeb8e7 | 290 | * We are almost certainly not prepared to handle instruction faults. |
1d18c47c | 291 | */ |
9adeb8e7 | 292 | if (!is_el1_instruction_abort(esr) && fixup_exception(regs)) |
1d18c47c CM |
293 | return; |
294 | ||
dbfe3828 | 295 | if (is_el1_permission_fault(addr, esr, regs)) { |
b824b930 SB |
296 | if (esr & ESR_ELx_WNR) |
297 | msg = "write to read-only memory"; | |
298 | else | |
299 | msg = "read from unreadable memory"; | |
300 | } else if (addr < PAGE_SIZE) { | |
301 | msg = "NULL pointer dereference"; | |
302 | } else { | |
303 | msg = "paging request"; | |
304 | } | |
305 | ||
c870f14e | 306 | die_kernel_fault(msg, addr, esr, regs); |
1d18c47c CM |
307 | } |
308 | ||
f29ad209 | 309 | static void set_thread_esr(unsigned long address, unsigned int esr) |
1d18c47c | 310 | { |
f29ad209 | 311 | current->thread.fault_address = address; |
cc198460 PM |
312 | |
313 | /* | |
314 | * If the faulting address is in the kernel, we must sanitize the ESR. | |
315 | * From userspace's point of view, kernel-only mappings don't exist | |
316 | * at all, so we report them as level 0 translation faults. | |
317 | * (This is not quite the way that "no mapping there at all" behaves: | |
318 | * an alignment fault not caused by the memory type would take | |
319 | * precedence over translation fault for a real access to empty | |
320 | * space. Unfortunately we can't easily distinguish "alignment fault | |
321 | * not caused by memory type" from "alignment fault caused by memory | |
322 | * type", so we ignore this wrinkle and just return the translation | |
323 | * fault.) | |
324 | */ | |
356607f2 | 325 | if (!is_ttbr0_addr(current->thread.fault_address)) { |
cc198460 PM |
326 | switch (ESR_ELx_EC(esr)) { |
327 | case ESR_ELx_EC_DABT_LOW: | |
328 | /* | |
329 | * These bits provide only information about the | |
330 | * faulting instruction, which userspace knows already. | |
331 | * We explicitly clear bits which are architecturally | |
332 | * RES0 in case they are given meanings in future. | |
333 | * We always report the ESR as if the fault was taken | |
334 | * to EL1 and so ISV and the bits in ISS[23:14] are | |
335 | * clear. (In fact it always will be a fault to EL1.) | |
336 | */ | |
337 | esr &= ESR_ELx_EC_MASK | ESR_ELx_IL | | |
338 | ESR_ELx_CM | ESR_ELx_WNR; | |
339 | esr |= ESR_ELx_FSC_FAULT; | |
340 | break; | |
341 | case ESR_ELx_EC_IABT_LOW: | |
342 | /* | |
343 | * Claim a level 0 translation fault. | |
344 | * All other bits are architecturally RES0 for faults | |
345 | * reported with that DFSC value, so we clear them. | |
346 | */ | |
347 | esr &= ESR_ELx_EC_MASK | ESR_ELx_IL; | |
348 | esr |= ESR_ELx_FSC_FAULT; | |
349 | break; | |
350 | default: | |
351 | /* | |
352 | * This should never happen (entry.S only brings us | |
353 | * into this code for insn and data aborts from a lower | |
354 | * exception level). Fail safe by not providing an ESR | |
355 | * context record at all. | |
356 | */ | |
357 | WARN(1, "ESR 0x%x is not DABT or IABT from EL0\n", esr); | |
358 | esr = 0; | |
359 | break; | |
360 | } | |
361 | } | |
362 | ||
92ff0674 | 363 | current->thread.fault_code = esr; |
1d18c47c CM |
364 | } |
365 | ||
59f67e16 | 366 | static void do_bad_area(unsigned long addr, unsigned int esr, struct pt_regs *regs) |
1d18c47c | 367 | { |
1d18c47c CM |
368 | /* |
369 | * If we are in kernel mode at this point, we have no context to | |
370 | * handle this fault with. | |
371 | */ | |
09a6adf5 | 372 | if (user_mode(regs)) { |
92ff0674 | 373 | const struct fault_info *inf = esr_to_fault_info(esr); |
3eb0f519 | 374 | |
effb093a | 375 | set_thread_esr(addr, esr); |
feca355b EB |
376 | arm64_force_sig_fault(inf->sig, inf->code, (void __user *)addr, |
377 | inf->name); | |
92ff0674 | 378 | } else { |
67ce16ec | 379 | __do_kernel_fault(addr, esr, regs); |
92ff0674 | 380 | } |
1d18c47c CM |
381 | } |
382 | ||
383 | #define VM_FAULT_BADMAP 0x010000 | |
384 | #define VM_FAULT_BADACCESS 0x020000 | |
385 | ||
50a7ca3c | 386 | static vm_fault_t __do_page_fault(struct mm_struct *mm, unsigned long addr, |
db6f4106 | 387 | unsigned int mm_flags, unsigned long vm_flags, |
1d18c47c CM |
388 | struct task_struct *tsk) |
389 | { | |
390 | struct vm_area_struct *vma; | |
50a7ca3c | 391 | vm_fault_t fault; |
1d18c47c CM |
392 | |
393 | vma = find_vma(mm, addr); | |
394 | fault = VM_FAULT_BADMAP; | |
395 | if (unlikely(!vma)) | |
396 | goto out; | |
397 | if (unlikely(vma->vm_start > addr)) | |
398 | goto check_stack; | |
399 | ||
400 | /* | |
401 | * Ok, we have a good vm_area for this memory access, so we can handle | |
402 | * it. | |
403 | */ | |
404 | good_area: | |
db6f4106 WD |
405 | /* |
406 | * Check that the permissions on the VMA allow for the fault which | |
cab15ce6 | 407 | * occurred. |
db6f4106 WD |
408 | */ |
409 | if (!(vma->vm_flags & vm_flags)) { | |
1d18c47c CM |
410 | fault = VM_FAULT_BADACCESS; |
411 | goto out; | |
412 | } | |
413 | ||
dcddffd4 | 414 | return handle_mm_fault(vma, addr & PAGE_MASK, mm_flags); |
1d18c47c CM |
415 | |
416 | check_stack: | |
417 | if (vma->vm_flags & VM_GROWSDOWN && !expand_stack(vma, addr)) | |
418 | goto good_area; | |
419 | out: | |
420 | return fault; | |
421 | } | |
422 | ||
541ec870 MR |
423 | static bool is_el0_instruction_abort(unsigned int esr) |
424 | { | |
425 | return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_LOW; | |
426 | } | |
427 | ||
1d18c47c CM |
428 | static int __kprobes do_page_fault(unsigned long addr, unsigned int esr, |
429 | struct pt_regs *regs) | |
430 | { | |
2d2837fa | 431 | const struct fault_info *inf; |
1d18c47c CM |
432 | struct task_struct *tsk; |
433 | struct mm_struct *mm; | |
50a7ca3c | 434 | vm_fault_t fault, major = 0; |
cab15ce6 | 435 | unsigned long vm_flags = VM_READ | VM_WRITE; |
db6f4106 WD |
436 | unsigned int mm_flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE; |
437 | ||
2dd0e8d2 SP |
438 | if (notify_page_fault(regs, esr)) |
439 | return 0; | |
440 | ||
1d18c47c CM |
441 | tsk = current; |
442 | mm = tsk->mm; | |
443 | ||
1d18c47c CM |
444 | /* |
445 | * If we're in an interrupt or have no user context, we must not take | |
446 | * the fault. | |
447 | */ | |
70ffdb93 | 448 | if (faulthandler_disabled() || !mm) |
1d18c47c CM |
449 | goto no_context; |
450 | ||
759496ba JW |
451 | if (user_mode(regs)) |
452 | mm_flags |= FAULT_FLAG_USER; | |
453 | ||
541ec870 | 454 | if (is_el0_instruction_abort(esr)) { |
759496ba | 455 | vm_flags = VM_EXEC; |
aed40e01 | 456 | } else if ((esr & ESR_ELx_WNR) && !(esr & ESR_ELx_CM)) { |
759496ba JW |
457 | vm_flags = VM_WRITE; |
458 | mm_flags |= FAULT_FLAG_WRITE; | |
459 | } | |
460 | ||
356607f2 | 461 | if (is_ttbr0_addr(addr) && is_el1_permission_fault(addr, esr, regs)) { |
e19a6ee2 JM |
462 | /* regs->orig_addr_limit may be 0 if we entered from EL0 */ |
463 | if (regs->orig_addr_limit == KERNEL_DS) | |
c870f14e MR |
464 | die_kernel_fault("access to user memory with fs=KERNEL_DS", |
465 | addr, esr, regs); | |
70544196 | 466 | |
9adeb8e7 | 467 | if (is_el1_instruction_abort(esr)) |
c870f14e MR |
468 | die_kernel_fault("execution of user memory", |
469 | addr, esr, regs); | |
9adeb8e7 | 470 | |
57f4959b | 471 | if (!search_exception_tables(regs->pc)) |
c870f14e MR |
472 | die_kernel_fault("access to user memory outside uaccess routines", |
473 | addr, esr, regs); | |
57f4959b | 474 | } |
338d4f49 | 475 | |
0e3a9026 PA |
476 | perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr); |
477 | ||
1d18c47c CM |
478 | /* |
479 | * As per x86, we may deadlock here. However, since the kernel only | |
480 | * validly references user space from well defined areas of the code, | |
481 | * we can bug out early if this is from code which shouldn't. | |
482 | */ | |
483 | if (!down_read_trylock(&mm->mmap_sem)) { | |
484 | if (!user_mode(regs) && !search_exception_tables(regs->pc)) | |
485 | goto no_context; | |
486 | retry: | |
487 | down_read(&mm->mmap_sem); | |
488 | } else { | |
489 | /* | |
490 | * The above down_read_trylock() might have succeeded in which | |
491 | * case, we'll have missed the might_sleep() from down_read(). | |
492 | */ | |
493 | might_sleep(); | |
494 | #ifdef CONFIG_DEBUG_VM | |
495 | if (!user_mode(regs) && !search_exception_tables(regs->pc)) | |
496 | goto no_context; | |
497 | #endif | |
498 | } | |
499 | ||
db6f4106 | 500 | fault = __do_page_fault(mm, addr, mm_flags, vm_flags, tsk); |
0e3a9026 | 501 | major |= fault & VM_FAULT_MAJOR; |
1d18c47c | 502 | |
0e3a9026 PA |
503 | if (fault & VM_FAULT_RETRY) { |
504 | /* | |
505 | * If we need to retry but a fatal signal is pending, | |
506 | * handle the signal first. We do not need to release | |
507 | * the mmap_sem because it would already be released | |
508 | * in __lock_page_or_retry in mm/filemap.c. | |
509 | */ | |
289d07a2 MR |
510 | if (fatal_signal_pending(current)) { |
511 | if (!user_mode(regs)) | |
512 | goto no_context; | |
0e3a9026 | 513 | return 0; |
289d07a2 | 514 | } |
0e3a9026 PA |
515 | |
516 | /* | |
517 | * Clear FAULT_FLAG_ALLOW_RETRY to avoid any risk of | |
518 | * starvation. | |
519 | */ | |
520 | if (mm_flags & FAULT_FLAG_ALLOW_RETRY) { | |
521 | mm_flags &= ~FAULT_FLAG_ALLOW_RETRY; | |
522 | mm_flags |= FAULT_FLAG_TRIED; | |
523 | goto retry; | |
524 | } | |
525 | } | |
526 | up_read(&mm->mmap_sem); | |
1d18c47c CM |
527 | |
528 | /* | |
0e3a9026 | 529 | * Handle the "normal" (no error) case first. |
1d18c47c | 530 | */ |
0e3a9026 PA |
531 | if (likely(!(fault & (VM_FAULT_ERROR | VM_FAULT_BADMAP | |
532 | VM_FAULT_BADACCESS)))) { | |
533 | /* | |
534 | * Major/minor page fault accounting is only done | |
535 | * once. If we go through a retry, it is extremely | |
536 | * likely that the page will be found in page cache at | |
537 | * that point. | |
538 | */ | |
539 | if (major) { | |
1d18c47c CM |
540 | tsk->maj_flt++; |
541 | perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, regs, | |
542 | addr); | |
543 | } else { | |
544 | tsk->min_flt++; | |
545 | perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, regs, | |
546 | addr); | |
547 | } | |
1d18c47c | 548 | |
1d18c47c | 549 | return 0; |
0e3a9026 | 550 | } |
1d18c47c | 551 | |
87134102 JW |
552 | /* |
553 | * If we are in kernel mode at this point, we have no context to | |
554 | * handle this fault with. | |
555 | */ | |
556 | if (!user_mode(regs)) | |
557 | goto no_context; | |
558 | ||
1d18c47c CM |
559 | if (fault & VM_FAULT_OOM) { |
560 | /* | |
561 | * We ran out of memory, call the OOM killer, and return to | |
562 | * userspace (which will retry the fault, or kill us if we got | |
563 | * oom-killed). | |
564 | */ | |
565 | pagefault_out_of_memory(); | |
566 | return 0; | |
567 | } | |
568 | ||
2d2837fa | 569 | inf = esr_to_fault_info(esr); |
559d8d91 | 570 | set_thread_esr(addr, esr); |
1d18c47c CM |
571 | if (fault & VM_FAULT_SIGBUS) { |
572 | /* | |
573 | * We had some memory, but were unable to successfully fix up | |
574 | * this page fault. | |
575 | */ | |
feca355b EB |
576 | arm64_force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)addr, |
577 | inf->name); | |
9ea3a974 EB |
578 | } else if (fault & (VM_FAULT_HWPOISON_LARGE | VM_FAULT_HWPOISON)) { |
579 | unsigned int lsb; | |
580 | ||
581 | lsb = PAGE_SHIFT; | |
582 | if (fault & VM_FAULT_HWPOISON_LARGE) | |
583 | lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault)); | |
92ff0674 | 584 | |
b4d5557c EB |
585 | arm64_force_sig_mceerr(BUS_MCEERR_AR, (void __user *)addr, lsb, |
586 | inf->name); | |
1d18c47c CM |
587 | } else { |
588 | /* | |
589 | * Something tried to access memory that isn't in our memory | |
590 | * map. | |
591 | */ | |
feca355b EB |
592 | arm64_force_sig_fault(SIGSEGV, |
593 | fault == VM_FAULT_BADACCESS ? SEGV_ACCERR : SEGV_MAPERR, | |
594 | (void __user *)addr, | |
595 | inf->name); | |
1d18c47c CM |
596 | } |
597 | ||
1d18c47c CM |
598 | return 0; |
599 | ||
600 | no_context: | |
67ce16ec | 601 | __do_kernel_fault(addr, esr, regs); |
1d18c47c CM |
602 | return 0; |
603 | } | |
604 | ||
1d18c47c CM |
605 | static int __kprobes do_translation_fault(unsigned long addr, |
606 | unsigned int esr, | |
607 | struct pt_regs *regs) | |
608 | { | |
356607f2 | 609 | if (is_ttbr0_addr(addr)) |
1d18c47c CM |
610 | return do_page_fault(addr, esr, regs); |
611 | ||
612 | do_bad_area(addr, esr, regs); | |
613 | return 0; | |
614 | } | |
615 | ||
52d7523d EL |
616 | static int do_alignment_fault(unsigned long addr, unsigned int esr, |
617 | struct pt_regs *regs) | |
618 | { | |
619 | do_bad_area(addr, esr, regs); | |
620 | return 0; | |
621 | } | |
622 | ||
1d18c47c CM |
623 | static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs) |
624 | { | |
f67d5c4f | 625 | return 1; /* "fault" */ |
1d18c47c CM |
626 | } |
627 | ||
32015c23 TB |
628 | static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs) |
629 | { | |
32015c23 | 630 | const struct fault_info *inf; |
6fa998e8 | 631 | void __user *siaddr; |
32015c23 TB |
632 | |
633 | inf = esr_to_fault_info(esr); | |
32015c23 | 634 | |
7edda088 | 635 | /* |
d44f1b8d JM |
636 | * Return value ignored as we rely on signal merging. |
637 | * Future patches will make this more robust. | |
7edda088 | 638 | */ |
d44f1b8d | 639 | apei_claim_sea(regs); |
7edda088 | 640 | |
32015c23 | 641 | if (esr & ESR_ELx_FnV) |
6fa998e8 | 642 | siaddr = NULL; |
32015c23 | 643 | else |
6fa998e8 EB |
644 | siaddr = (void __user *)addr; |
645 | arm64_notify_die(inf->name, regs, inf->sig, inf->code, siaddr, esr); | |
32015c23 | 646 | |
faa75e14 | 647 | return 0; |
32015c23 TB |
648 | } |
649 | ||
09a6adf5 | 650 | static const struct fault_info fault_info[] = { |
af40ff68 DM |
651 | { do_bad, SIGKILL, SI_KERNEL, "ttbr address size fault" }, |
652 | { do_bad, SIGKILL, SI_KERNEL, "level 1 address size fault" }, | |
653 | { do_bad, SIGKILL, SI_KERNEL, "level 2 address size fault" }, | |
654 | { do_bad, SIGKILL, SI_KERNEL, "level 3 address size fault" }, | |
7f73f7ae | 655 | { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 0 translation fault" }, |
1d18c47c CM |
656 | { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" }, |
657 | { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" }, | |
760bfb47 | 658 | { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" }, |
af40ff68 | 659 | { do_bad, SIGKILL, SI_KERNEL, "unknown 8" }, |
084bd298 SC |
660 | { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 access flag fault" }, |
661 | { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 access flag fault" }, | |
1d18c47c | 662 | { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 access flag fault" }, |
af40ff68 | 663 | { do_bad, SIGKILL, SI_KERNEL, "unknown 12" }, |
084bd298 SC |
664 | { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 permission fault" }, |
665 | { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 permission fault" }, | |
1d18c47c | 666 | { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 permission fault" }, |
af40ff68 DM |
667 | { do_sea, SIGBUS, BUS_OBJERR, "synchronous external abort" }, |
668 | { do_bad, SIGKILL, SI_KERNEL, "unknown 17" }, | |
669 | { do_bad, SIGKILL, SI_KERNEL, "unknown 18" }, | |
670 | { do_bad, SIGKILL, SI_KERNEL, "unknown 19" }, | |
671 | { do_sea, SIGKILL, SI_KERNEL, "level 0 (translation table walk)" }, | |
672 | { do_sea, SIGKILL, SI_KERNEL, "level 1 (translation table walk)" }, | |
673 | { do_sea, SIGKILL, SI_KERNEL, "level 2 (translation table walk)" }, | |
674 | { do_sea, SIGKILL, SI_KERNEL, "level 3 (translation table walk)" }, | |
675 | { do_sea, SIGBUS, BUS_OBJERR, "synchronous parity or ECC error" }, // Reserved when RAS is implemented | |
676 | { do_bad, SIGKILL, SI_KERNEL, "unknown 25" }, | |
677 | { do_bad, SIGKILL, SI_KERNEL, "unknown 26" }, | |
678 | { do_bad, SIGKILL, SI_KERNEL, "unknown 27" }, | |
679 | { do_sea, SIGKILL, SI_KERNEL, "level 0 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented | |
680 | { do_sea, SIGKILL, SI_KERNEL, "level 1 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented | |
681 | { do_sea, SIGKILL, SI_KERNEL, "level 2 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented | |
682 | { do_sea, SIGKILL, SI_KERNEL, "level 3 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented | |
683 | { do_bad, SIGKILL, SI_KERNEL, "unknown 32" }, | |
52d7523d | 684 | { do_alignment_fault, SIGBUS, BUS_ADRALN, "alignment fault" }, |
af40ff68 DM |
685 | { do_bad, SIGKILL, SI_KERNEL, "unknown 34" }, |
686 | { do_bad, SIGKILL, SI_KERNEL, "unknown 35" }, | |
687 | { do_bad, SIGKILL, SI_KERNEL, "unknown 36" }, | |
688 | { do_bad, SIGKILL, SI_KERNEL, "unknown 37" }, | |
689 | { do_bad, SIGKILL, SI_KERNEL, "unknown 38" }, | |
690 | { do_bad, SIGKILL, SI_KERNEL, "unknown 39" }, | |
691 | { do_bad, SIGKILL, SI_KERNEL, "unknown 40" }, | |
692 | { do_bad, SIGKILL, SI_KERNEL, "unknown 41" }, | |
693 | { do_bad, SIGKILL, SI_KERNEL, "unknown 42" }, | |
694 | { do_bad, SIGKILL, SI_KERNEL, "unknown 43" }, | |
695 | { do_bad, SIGKILL, SI_KERNEL, "unknown 44" }, | |
696 | { do_bad, SIGKILL, SI_KERNEL, "unknown 45" }, | |
697 | { do_bad, SIGKILL, SI_KERNEL, "unknown 46" }, | |
698 | { do_bad, SIGKILL, SI_KERNEL, "unknown 47" }, | |
699 | { do_bad, SIGKILL, SI_KERNEL, "TLB conflict abort" }, | |
700 | { do_bad, SIGKILL, SI_KERNEL, "Unsupported atomic hardware update fault" }, | |
701 | { do_bad, SIGKILL, SI_KERNEL, "unknown 50" }, | |
702 | { do_bad, SIGKILL, SI_KERNEL, "unknown 51" }, | |
703 | { do_bad, SIGKILL, SI_KERNEL, "implementation fault (lockdown abort)" }, | |
704 | { do_bad, SIGBUS, BUS_OBJERR, "implementation fault (unsupported exclusive)" }, | |
705 | { do_bad, SIGKILL, SI_KERNEL, "unknown 54" }, | |
706 | { do_bad, SIGKILL, SI_KERNEL, "unknown 55" }, | |
707 | { do_bad, SIGKILL, SI_KERNEL, "unknown 56" }, | |
708 | { do_bad, SIGKILL, SI_KERNEL, "unknown 57" }, | |
709 | { do_bad, SIGKILL, SI_KERNEL, "unknown 58" }, | |
710 | { do_bad, SIGKILL, SI_KERNEL, "unknown 59" }, | |
711 | { do_bad, SIGKILL, SI_KERNEL, "unknown 60" }, | |
712 | { do_bad, SIGKILL, SI_KERNEL, "section domain fault" }, | |
713 | { do_bad, SIGKILL, SI_KERNEL, "page domain fault" }, | |
714 | { do_bad, SIGKILL, SI_KERNEL, "unknown 63" }, | |
1d18c47c CM |
715 | }; |
716 | ||
1d18c47c CM |
717 | asmlinkage void __exception do_mem_abort(unsigned long addr, unsigned int esr, |
718 | struct pt_regs *regs) | |
719 | { | |
09a6adf5 | 720 | const struct fault_info *inf = esr_to_fault_info(esr); |
1d18c47c CM |
721 | |
722 | if (!inf->fn(addr, esr, regs)) | |
723 | return; | |
724 | ||
1049c308 WD |
725 | if (!user_mode(regs)) { |
726 | pr_alert("Unhandled fault at 0x%016lx\n", addr); | |
727 | mem_abort_decode(esr); | |
80b6eb04 | 728 | show_pte(addr); |
1049c308 | 729 | } |
42dbf54e | 730 | |
6fa998e8 EB |
731 | arm64_notify_die(inf->name, regs, |
732 | inf->sig, inf->code, (void __user *)addr, esr); | |
1d18c47c CM |
733 | } |
734 | ||
30d88c0e WD |
735 | asmlinkage void __exception do_el0_irq_bp_hardening(void) |
736 | { | |
737 | /* PC has already been checked in entry.S */ | |
738 | arm64_apply_bp_hardening(); | |
739 | } | |
740 | ||
0f15adbb WD |
741 | asmlinkage void __exception do_el0_ia_bp_hardening(unsigned long addr, |
742 | unsigned int esr, | |
743 | struct pt_regs *regs) | |
744 | { | |
745 | /* | |
746 | * We've taken an instruction abort from userspace and not yet | |
747 | * re-enabled IRQs. If the address is a kernel address, apply | |
748 | * BP hardening prior to enabling IRQs and pre-emption. | |
749 | */ | |
356607f2 | 750 | if (!is_ttbr0_addr(addr)) |
0f15adbb WD |
751 | arm64_apply_bp_hardening(); |
752 | ||
9a0c0328 | 753 | local_daif_restore(DAIF_PROCCTX); |
0f15adbb WD |
754 | do_mem_abort(addr, esr, regs); |
755 | } | |
756 | ||
757 | ||
1d18c47c CM |
758 | asmlinkage void __exception do_sp_pc_abort(unsigned long addr, |
759 | unsigned int esr, | |
760 | struct pt_regs *regs) | |
761 | { | |
5dfc6ed2 | 762 | if (user_mode(regs)) { |
356607f2 | 763 | if (!is_ttbr0_addr(instruction_pointer(regs))) |
5dfc6ed2 | 764 | arm64_apply_bp_hardening(); |
9a0c0328 | 765 | local_daif_restore(DAIF_PROCCTX); |
5dfc6ed2 WD |
766 | } |
767 | ||
6fa998e8 EB |
768 | arm64_notify_die("SP/PC alignment exception", regs, |
769 | SIGBUS, BUS_ADRALN, (void __user *)addr, esr); | |
1d18c47c CM |
770 | } |
771 | ||
9fb7410f DM |
772 | int __init early_brk64(unsigned long addr, unsigned int esr, |
773 | struct pt_regs *regs); | |
774 | ||
775 | /* | |
776 | * __refdata because early_brk64 is __init, but the reference to it is | |
777 | * clobbered at arch_initcall time. | |
778 | * See traps.c and debug-monitors.c:debug_traps_init(). | |
779 | */ | |
780 | static struct fault_info __refdata debug_fault_info[] = { | |
1d18c47c CM |
781 | { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware breakpoint" }, |
782 | { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware single-step" }, | |
783 | { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware watchpoint" }, | |
af40ff68 | 784 | { do_bad, SIGKILL, SI_KERNEL, "unknown 3" }, |
1d18c47c | 785 | { do_bad, SIGTRAP, TRAP_BRKPT, "aarch32 BKPT" }, |
af40ff68 | 786 | { do_bad, SIGKILL, SI_KERNEL, "aarch32 vector catch" }, |
9fb7410f | 787 | { early_brk64, SIGTRAP, TRAP_BRKPT, "aarch64 BRK" }, |
af40ff68 | 788 | { do_bad, SIGKILL, SI_KERNEL, "unknown 7" }, |
1d18c47c CM |
789 | }; |
790 | ||
791 | void __init hook_debug_fault_code(int nr, | |
792 | int (*fn)(unsigned long, unsigned int, struct pt_regs *), | |
793 | int sig, int code, const char *name) | |
794 | { | |
795 | BUG_ON(nr < 0 || nr >= ARRAY_SIZE(debug_fault_info)); | |
796 | ||
797 | debug_fault_info[nr].fn = fn; | |
798 | debug_fault_info[nr].sig = sig; | |
799 | debug_fault_info[nr].code = code; | |
800 | debug_fault_info[nr].name = name; | |
801 | } | |
802 | ||
969f5ea6 WD |
803 | #ifdef CONFIG_ARM64_ERRATUM_1463225 |
804 | DECLARE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa); | |
805 | ||
806 | static int __exception | |
807 | cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs) | |
808 | { | |
809 | if (user_mode(regs)) | |
810 | return 0; | |
811 | ||
812 | if (!__this_cpu_read(__in_cortex_a76_erratum_1463225_wa)) | |
813 | return 0; | |
814 | ||
815 | /* | |
816 | * We've taken a dummy step exception from the kernel to ensure | |
817 | * that interrupts are re-enabled on the syscall path. Return back | |
818 | * to cortex_a76_erratum_1463225_svc_handler() with debug exceptions | |
819 | * masked so that we can safely restore the mdscr and get on with | |
820 | * handling the syscall. | |
821 | */ | |
822 | regs->pstate |= PSR_D_BIT; | |
823 | return 1; | |
824 | } | |
825 | #else | |
826 | static int __exception | |
827 | cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs) | |
828 | { | |
829 | return 0; | |
830 | } | |
831 | #endif /* CONFIG_ARM64_ERRATUM_1463225 */ | |
832 | ||
52c6d145 WD |
833 | asmlinkage void __exception do_debug_exception(unsigned long addr_if_watchpoint, |
834 | unsigned int esr, | |
835 | struct pt_regs *regs) | |
1d18c47c | 836 | { |
359048f9 | 837 | const struct fault_info *inf = esr_to_debug_fault_info(esr); |
b9a4b9d0 | 838 | unsigned long pc = instruction_pointer(regs); |
1d18c47c | 839 | |
969f5ea6 WD |
840 | if (cortex_a76_erratum_1463225_debug_handler(regs)) |
841 | return; | |
842 | ||
6afedcd2 JM |
843 | /* |
844 | * Tell lockdep we disabled irqs in entry.S. Do nothing if they were | |
845 | * already disabled to preserve the last enabled/disabled addresses. | |
846 | */ | |
847 | if (interrupts_enabled(regs)) | |
848 | trace_hardirqs_off(); | |
1d18c47c | 849 | |
b9a4b9d0 | 850 | if (user_mode(regs) && !is_ttbr0_addr(pc)) |
5dfc6ed2 WD |
851 | arm64_apply_bp_hardening(); |
852 | ||
52c6d145 | 853 | if (inf->fn(addr_if_watchpoint, esr, regs)) { |
6fa998e8 | 854 | arm64_notify_die(inf->name, regs, |
b9a4b9d0 | 855 | inf->sig, inf->code, (void __user *)pc, esr); |
6afedcd2 | 856 | } |
1d18c47c | 857 | |
6afedcd2 JM |
858 | if (interrupts_enabled(regs)) |
859 | trace_hardirqs_on(); | |
1d18c47c | 860 | } |
2dd0e8d2 | 861 | NOKPROBE_SYMBOL(do_debug_exception); |