[mirror_ubuntu-jammy-kernel.git] / arch / arm64 / mm / proc.S

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Based on arch/arm/mm/proc.S
 *
 * Copyright (C) 2001 Deep Blue Solutions Ltd.
 * Copyright (C) 2012 ARM Ltd.
 * Author: Catalin Marinas <catalin.marinas@arm.com>
 */

#include <linux/init.h>
#include <linux/linkage.h>
#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/asm_pointer_auth.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/cpufeature.h>
#include <asm/alternative.h>
#include <asm/smp.h>
#include <asm/sysreg.h>

#ifdef CONFIG_ARM64_64K_PAGES
#define TCR_TG_FLAGS	TCR_TG0_64K | TCR_TG1_64K
#elif defined(CONFIG_ARM64_16K_PAGES)
#define TCR_TG_FLAGS	TCR_TG0_16K | TCR_TG1_16K
#else /* CONFIG_ARM64_4K_PAGES */
#define TCR_TG_FLAGS	TCR_TG0_4K | TCR_TG1_4K
#endif

#ifdef CONFIG_RANDOMIZE_BASE
#define TCR_KASLR_FLAGS	TCR_NFD1
#else
#define TCR_KASLR_FLAGS	0
#endif

#define TCR_SMP_FLAGS	TCR_SHARED

/* PTWs cacheable, inner/outer WBWA */
#define TCR_CACHE_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA

#ifdef CONFIG_KASAN_SW_TAGS
#define TCR_KASAN_SW_FLAGS TCR_TBI1 | TCR_TBID1
#else
#define TCR_KASAN_SW_FLAGS 0
#endif

#ifdef CONFIG_KASAN_HW_TAGS
#define TCR_KASAN_HW_FLAGS SYS_TCR_EL1_TCMA1 | TCR_TBI1 | TCR_TBID1
#else
#define TCR_KASAN_HW_FLAGS 0
#endif

/*
 * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and
 * changed during __cpu_setup to Normal Tagged if the system supports MTE.
 */
#define MAIR_EL1_SET							\
	(MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) |	\
	 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) |	\
	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) |		\
	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) |			\
	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED))

#ifdef CONFIG_CPU_PM
/**
 * cpu_do_suspend - save CPU registers context
 *
 * x0: virtual address of context pointer
 *
 * This must be kept in sync with struct cpu_suspend_ctx in <asm/suspend.h>.
 */
SYM_FUNC_START(cpu_do_suspend)
	mrs	x2, tpidr_el0
	mrs	x3, tpidrro_el0
	mrs	x4, contextidr_el1
	mrs	x5, osdlr_el1
	mrs	x6, cpacr_el1
	mrs	x7, tcr_el1
	mrs	x8, vbar_el1
	mrs	x9, mdscr_el1
	mrs	x10, oslsr_el1
	mrs	x11, sctlr_el1
alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
	mrs	x12, tpidr_el1
alternative_else
	mrs	x12, tpidr_el2
alternative_endif
	mrs	x13, sp_el0
	stp	x2, x3, [x0]
	stp	x4, x5, [x0, #16]
	stp	x6, x7, [x0, #32]
	stp	x8, x9, [x0, #48]
	stp	x10, x11, [x0, #64]
	stp	x12, x13, [x0, #80]
	/*
	 * Save x18 as it may be used as a platform register, e.g. by shadow
	 * call stack.
	 */
	str	x18, [x0, #96]
	ret
SYM_FUNC_END(cpu_do_suspend)

/**
 * cpu_do_resume - restore CPU register context
 *
 * x0: Address of context pointer
 */
	.pushsection ".idmap.text", "awx"
SYM_FUNC_START(cpu_do_resume)
	ldp	x2, x3, [x0]
	ldp	x4, x5, [x0, #16]
	ldp	x6, x8, [x0, #32]
	ldp	x9, x10, [x0, #48]
	ldp	x11, x12, [x0, #64]
	ldp	x13, x14, [x0, #80]
	/*
	 * Restore x18, as it may be used as a platform register, and clear
	 * the buffer to minimize the risk of exposure when used for shadow
	 * call stack.
	 */
	ldr	x18, [x0, #96]
	str	xzr, [x0, #96]
	msr	tpidr_el0, x2
	msr	tpidrro_el0, x3
	msr	contextidr_el1, x4
	msr	cpacr_el1, x6

	/* Don't change t0sz here, mask those bits when restoring */
	mrs	x7, tcr_el1
	bfi	x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH

	msr	tcr_el1, x8
	msr	vbar_el1, x9

	/*
	 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
	 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
	 * exception. Mask them until local_daif_restore() in cpu_suspend()
	 * resets them.
	 */
	disable_daif
	msr	mdscr_el1, x10

	msr	sctlr_el1, x12
alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
	msr	tpidr_el1, x13
alternative_else
	msr	tpidr_el2, x13
alternative_endif
	msr	sp_el0, x14
	/*
	 * Restore oslsr_el1 by writing oslar_el1
	 */
	msr	osdlr_el1, x5
	ubfx	x11, x11, #1, #1
	msr	oslar_el1, x11
	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
	reset_amuserenr_el0 x0			// Disable AMU access from EL0

alternative_if ARM64_HAS_RAS_EXTN
	msr_s	SYS_DISR_EL1, xzr
alternative_else_nop_endif

	ptrauth_keys_install_kernel_nosync x14, x1, x2, x3
	isb
	ret
SYM_FUNC_END(cpu_do_resume)
	.popsection
#endif

	.pushsection ".idmap.text", "awx"

.macro	__idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
	adrp	\tmp1, reserved_pg_dir
	phys_to_ttbr \tmp2, \tmp1
	offset_ttbr1 \tmp2, \tmp1
	msr	ttbr1_el1, \tmp2
	isb
	tlbi	vmalle1
	dsb	nsh
	isb
.endm

/*
 * void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1)
 *
 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
 * called by anything else. It can only be executed from a TTBR0 mapping.
 */
SYM_FUNC_START(idmap_cpu_replace_ttbr1)
	save_and_disable_daif flags=x2

	__idmap_cpu_set_reserved_ttbr1 x1, x3

	offset_ttbr1 x0, x3
	msr	ttbr1_el1, x0
	isb

	restore_daif x2

	ret
SYM_FUNC_END(idmap_cpu_replace_ttbr1)
	.popsection

#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
	.pushsection ".idmap.text", "awx"

	.macro	__idmap_kpti_get_pgtable_ent, type
	dc	cvac, cur_\()\type\()p		// Ensure any existing dirty
	dmb	sy				// lines are written back before
	ldr	\type, [cur_\()\type\()p]	// loading the entry
	tbz	\type, #0, skip_\()\type	// Skip invalid and
	tbnz	\type, #11, skip_\()\type	// non-global entries
	.endm

	.macro __idmap_kpti_put_pgtable_ent_ng, type
	orr	\type, \type, #PTE_NG		// Same bit for blocks and pages
	str	\type, [cur_\()\type\()p]	// Update the entry and ensure
	dmb	sy				// that it is visible to all
	dc	civac, cur_\()\type\()p		// CPUs.
	.endm

/*
 * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
 *
 * Called exactly once from stop_machine context by each CPU found during boot.
 */
__idmap_kpti_flag:
	.long	1
SYM_FUNC_START(idmap_kpti_install_ng_mappings)
	cpu		.req	w0
	num_cpus	.req	w1
	swapper_pa	.req	x2
	swapper_ttb	.req	x3
	flag_ptr	.req	x4
	cur_pgdp	.req	x5
	end_pgdp	.req	x6
	pgd		.req	x7
	cur_pudp	.req	x8
	end_pudp	.req	x9
	pud		.req	x10
	cur_pmdp	.req	x11
	end_pmdp	.req	x12
	pmd		.req	x13
	cur_ptep	.req	x14
	end_ptep	.req	x15
	pte		.req	x16

	mrs	swapper_ttb, ttbr1_el1
	restore_ttbr1	swapper_ttb
	adr	flag_ptr, __idmap_kpti_flag

	cbnz	cpu, __idmap_kpti_secondary

	/* We're the boot CPU. Wait for the others to catch up */
	sevl
1:	wfe
	ldaxr	w17, [flag_ptr]
	eor	w17, w17, num_cpus
	cbnz	w17, 1b

	/* We need to walk swapper, so turn off the MMU. */
	pre_disable_mmu_workaround
	mrs	x17, sctlr_el1
	bic	x17, x17, #SCTLR_ELx_M
	msr	sctlr_el1, x17
	isb

	/* Everybody is enjoying the idmap, so we can rewrite swapper. */
	/* PGD */
	mov	cur_pgdp, swapper_pa
	add	end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
do_pgd:	__idmap_kpti_get_pgtable_ent	pgd
	tbnz	pgd, #1, walk_puds
next_pgd:
	__idmap_kpti_put_pgtable_ent_ng	pgd
skip_pgd:
	add	cur_pgdp, cur_pgdp, #8
	cmp	cur_pgdp, end_pgdp
	b.ne	do_pgd

	/* Publish the updated tables and nuke all the TLBs */
	dsb	sy
	tlbi	vmalle1is
	dsb	ish
	isb

	/* We're done: fire up the MMU again */
	mrs	x17, sctlr_el1
	orr	x17, x17, #SCTLR_ELx_M
	set_sctlr_el1	x17

	/* Set the flag to zero to indicate that we're all done */
	str	wzr, [flag_ptr]
	ret

	/* PUD */
walk_puds:
	.if CONFIG_PGTABLE_LEVELS > 3
	pte_to_phys	cur_pudp, pgd
	add	end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
do_pud:	__idmap_kpti_get_pgtable_ent	pud
	tbnz	pud, #1, walk_pmds
next_pud:
	__idmap_kpti_put_pgtable_ent_ng	pud
skip_pud:
	add	cur_pudp, cur_pudp, 8
	cmp	cur_pudp, end_pudp
	b.ne	do_pud
	b	next_pgd
	.else /* CONFIG_PGTABLE_LEVELS <= 3 */
	mov	pud, pgd
	b	walk_pmds
next_pud:
	b	next_pgd
	.endif

	/* PMD */
walk_pmds:
	.if CONFIG_PGTABLE_LEVELS > 2
	pte_to_phys	cur_pmdp, pud
	add	end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
do_pmd:	__idmap_kpti_get_pgtable_ent	pmd
	tbnz	pmd, #1, walk_ptes
next_pmd:
	__idmap_kpti_put_pgtable_ent_ng	pmd
skip_pmd:
	add	cur_pmdp, cur_pmdp, #8
	cmp	cur_pmdp, end_pmdp
	b.ne	do_pmd
	b	next_pud
	.else /* CONFIG_PGTABLE_LEVELS <= 2 */
	mov	pmd, pud
	b	walk_ptes
next_pmd:
	b	next_pud
	.endif

	/* PTE */
walk_ptes:
	pte_to_phys	cur_ptep, pmd
	add	end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
do_pte:	__idmap_kpti_get_pgtable_ent	pte
	__idmap_kpti_put_pgtable_ent_ng	pte
skip_pte:
	add	cur_ptep, cur_ptep, #8
	cmp	cur_ptep, end_ptep
	b.ne	do_pte
	b	next_pmd

	.unreq	cpu
	.unreq	num_cpus
	.unreq	swapper_pa
	.unreq	cur_pgdp
	.unreq	end_pgdp
	.unreq	pgd
	.unreq	cur_pudp
	.unreq	end_pudp
	.unreq	pud
	.unreq	cur_pmdp
	.unreq	end_pmdp
	.unreq	pmd
	.unreq	cur_ptep
	.unreq	end_ptep
	.unreq	pte

	/* Secondary CPUs end up here */
__idmap_kpti_secondary:
	/* Uninstall swapper before surgery begins */
	__idmap_cpu_set_reserved_ttbr1 x16, x17

	/* Increment the flag to let the boot CPU we're ready */
1:	ldxr	w16, [flag_ptr]
	add	w16, w16, #1
	stxr	w17, w16, [flag_ptr]
	cbnz	w17, 1b

	/* Wait for the boot CPU to finish messing around with swapper */
	sevl
1:	wfe
	ldxr	w16, [flag_ptr]
	cbnz	w16, 1b

	/* All done, act like nothing happened */
	offset_ttbr1 swapper_ttb, x16
	msr	ttbr1_el1, swapper_ttb
	isb
	ret

	.unreq	swapper_ttb
	.unreq	flag_ptr
SYM_FUNC_END(idmap_kpti_install_ng_mappings)
	.popsection
#endif

/*
 *	__cpu_setup
 *
 *	Initialise the processor for turning the MMU on.
 *
 * Output:
 *	Return in x0 the value of the SCTLR_EL1 register.
 */
	.pushsection ".idmap.text", "awx"
SYM_FUNC_START(__cpu_setup)
	tlbi	vmalle1				// Invalidate local TLB
	dsb	nsh

	mov	x1, #3 << 20
	msr	cpacr_el1, x1			// Enable FP/ASIMD
	mov	x1, #1 << 12			// Reset mdscr_el1 and disable
	msr	mdscr_el1, x1			// access to the DCC from EL0
	isb					// Unmask debug exceptions now,
	enable_dbg				// since this is per-cpu
	reset_pmuserenr_el0 x1			// Disable PMU access from EL0
	reset_amuserenr_el0 x1			// Disable AMU access from EL0

	/*
	 * Default values for VMSA control registers. These will be adjusted
	 * below depending on detected CPU features.
	 */
	mair	.req	x17
	tcr	.req	x16
	mov_q	mair, MAIR_EL1_SET
	mov_q	tcr, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
			TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
			TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS

#ifdef CONFIG_ARM64_MTE
	/*
	 * Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported
	 * (ID_AA64PFR1_EL1[11:8] > 1).
	 */
	mrs	x10, ID_AA64PFR1_EL1
	ubfx	x10, x10, #ID_AA64PFR1_MTE_SHIFT, #4
	cmp	x10, #ID_AA64PFR1_MTE
	b.lt	1f

	/* Normal Tagged memory type at the corresponding MAIR index */
	mov	x10, #MAIR_ATTR_NORMAL_TAGGED
	bfi	mair, x10, #(8 *  MT_NORMAL_TAGGED), #8

	/* initialize GCR_EL1: all non-zero tags excluded by default */
	mov	x10, #(SYS_GCR_EL1_RRND | SYS_GCR_EL1_EXCL_MASK)
	msr_s	SYS_GCR_EL1, x10

	/*
	 * If GCR_EL1.RRND=1 is implemented the same way as RRND=0, then
	 * RGSR_EL1.SEED must be non-zero for IRG to produce
	 * pseudorandom numbers. As RGSR_EL1 is UNKNOWN out of reset, we
	 * must initialize it.
	 */
	mrs	x10, CNTVCT_EL0
	ands	x10, x10, #SYS_RGSR_EL1_SEED_MASK
	csinc	x10, x10, xzr, ne
	lsl	x10, x10, #SYS_RGSR_EL1_SEED_SHIFT
	msr_s	SYS_RGSR_EL1, x10

	/* clear any pending tag check faults in TFSR*_EL1 */
	msr_s	SYS_TFSR_EL1, xzr
	msr_s	SYS_TFSRE0_EL1, xzr

	/* set the TCR_EL1 bits */
	mov_q	x10, TCR_KASAN_HW_FLAGS
	orr	tcr, tcr, x10
1:
#endif
	tcr_clear_errata_bits tcr, x9, x5

#ifdef CONFIG_ARM64_VA_BITS_52
	ldr_l		x9, vabits_actual
	sub		x9, xzr, x9
	add		x9, x9, #64
	tcr_set_t1sz	tcr, x9
#else
	ldr_l		x9, idmap_t0sz
#endif
	tcr_set_t0sz	tcr, x9

	/*
	 * Set the IPS bits in TCR_EL1.
	 */
	tcr_compute_pa_size tcr, #TCR_IPS_SHIFT, x5, x6
#ifdef CONFIG_ARM64_HW_AFDBM
	/*
	 * Enable hardware update of the Access Flags bit.
	 * Hardware dirty bit management is enabled later,
	 * via capabilities.
	 */
	mrs	x9, ID_AA64MMFR1_EL1
	and	x9, x9, #0xf
	cbz	x9, 1f
	orr	tcr, tcr, #TCR_HA		// hardware Access flag update
1:
#endif	/* CONFIG_ARM64_HW_AFDBM */
	msr	mair_el1, mair
	msr	tcr_el1, tcr
	/*
	 * Prepare SCTLR
	 */
	mov_q	x0, INIT_SCTLR_EL1_MMU_ON
	ret					// return to head.S

	.unreq	mair
	.unreq	tcr
SYM_FUNC_END(__cpu_setup)
Commit	Line	Data
caab277b	1	/* SPDX-License-Identifier: GPL-2.0-only */
9cce7a43 CM	2	/*
	3	* Based on arch/arm/mm/proc.S
	4	*
	5	* Copyright (C) 2001 Deep Blue Solutions Ltd.
	6	* Copyright (C) 2012 ARM Ltd.
	7	* Author: Catalin Marinas <catalin.marinas@arm.com>
9cce7a43 CM	8	*/
	9
	10	#include <linux/init.h>
	11	#include <linux/linkage.h>
65fddcfc	12	#include <linux/pgtable.h>
9cce7a43 CM	13	#include <asm/assembler.h>
9cce7a43 CM	14	#include <asm/asm-offsets.h>
e51f5f56	15	#include <asm/asm_pointer_auth.h>
9cce7a43	16	#include <asm/hwcap.h>
cabe1c81	17	#include <asm/pgtable-hwdef.h>
104a0c02 AP	18	#include <asm/cpufeature.h>
104a0c02 AP	19	#include <asm/alternative.h>
6982934e	20	#include <asm/smp.h>
3b714d24	21	#include <asm/sysreg.h>
9cce7a43	22
35a86976 CM	23	#ifdef CONFIG_ARM64_64K_PAGES
35a86976 CM	24	#define TCR_TG_FLAGS TCR_TG0_64K \| TCR_TG1_64K
44eaacf1 SP	25	#elif defined(CONFIG_ARM64_16K_PAGES)
	26	#define TCR_TG_FLAGS TCR_TG0_16K \| TCR_TG1_16K
	27	#else /* CONFIG_ARM64_4K_PAGES */
35a86976 CM	28	#define TCR_TG_FLAGS TCR_TG0_4K \| TCR_TG1_4K
	29	#endif
	30
e03e61c3 WD	31	#ifdef CONFIG_RANDOMIZE_BASE
	32	#define TCR_KASLR_FLAGS TCR_NFD1
	33	#else
	34	#define TCR_KASLR_FLAGS 0
	35	#endif
	36
35a86976	37	#define TCR_SMP_FLAGS TCR_SHARED
9cce7a43	38
35a86976 CM	39	/* PTWs cacheable, inner/outer WBWA */
	40	#define TCR_CACHE_FLAGS TCR_IRGN_WBWA \| TCR_ORGN_WBWA
	41
21696c16	42	#ifdef CONFIG_KASAN_SW_TAGS
bfc62c59	43	#define TCR_KASAN_SW_FLAGS TCR_TBI1 \| TCR_TBID1
21696c16	44	#else
bfc62c59 VF	45	#define TCR_KASAN_SW_FLAGS 0
	46	#endif
	47
	48	#ifdef CONFIG_KASAN_HW_TAGS
f34d93f3	49	#define TCR_KASAN_HW_FLAGS SYS_TCR_EL1_TCMA1 \| TCR_TBI1 \| TCR_TBID1
bfc62c59 VF	50	#else
bfc62c59 VF	51	#define TCR_KASAN_HW_FLAGS 0
21696c16 AK	52	#endif
21696c16 AK	53
0178dc76 CM	54	/*
	55	* Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and
	56	* changed during __cpu_setup to Normal Tagged if the system supports MTE.
	57	*/
95b3f74b CM	58	#define MAIR_EL1_SET \
	59	(MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) \| \
	60	MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) \| \
95b3f74b CM	61	MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) \| \
95b3f74b CM	62	MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) \| \
0178dc76	63	MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED))
9cce7a43	64
af3cfdbf	65	#ifdef CONFIG_CPU_PM
6732bc65 LP	66	/**
	67	* cpu_do_suspend - save CPU registers context
	68	*
	69	* x0: virtual address of context pointer
6d37d81f ST	70	*
6d37d81f ST	71	* This must be kept in sync with struct cpu_suspend_ctx in <asm/suspend.h>.
6732bc65	72	*/
f4659254	73	SYM_FUNC_START(cpu_do_suspend)
6732bc65 LP	74	mrs x2, tpidr_el0
	75	mrs x3, tpidrro_el0
	76	mrs x4, contextidr_el1
827a108e JPB	77	mrs x5, osdlr_el1
	78	mrs x6, cpacr_el1
	79	mrs x7, tcr_el1
	80	mrs x8, vbar_el1
	81	mrs x9, mdscr_el1
	82	mrs x10, oslsr_el1
	83	mrs x11, sctlr_el1
6d99b689	84	alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
827a108e	85	mrs x12, tpidr_el1
6d99b689	86	alternative_else
827a108e	87	mrs x12, tpidr_el2
6d99b689	88	alternative_endif
827a108e	89	mrs x13, sp_el0
6732bc65	90	stp x2, x3, [x0]
827a108e JPB	91	stp x4, x5, [x0, #16]
	92	stp x6, x7, [x0, #32]
	93	stp x8, x9, [x0, #48]
	94	stp x10, x11, [x0, #64]
	95	stp x12, x13, [x0, #80]
6d37d81f ST	96	/*
	97	* Save x18 as it may be used as a platform register, e.g. by shadow
	98	* call stack.
	99	*/
	100	str x18, [x0, #96]
6732bc65	101	ret
f4659254	102	SYM_FUNC_END(cpu_do_suspend)
6732bc65 LP	103
	104	/**
	105	* cpu_do_resume - restore CPU register context
	106	*
cabe1c81	107	* x0: Address of context pointer
6732bc65	108	*/
439e70e2	109	.pushsection ".idmap.text", "awx"
f4659254	110	SYM_FUNC_START(cpu_do_resume)
6732bc65 LP	111	ldp x2, x3, [x0]
6732bc65 LP	112	ldp x4, x5, [x0, #16]
cabe1c81 JM	113	ldp x6, x8, [x0, #32]
	114	ldp x9, x10, [x0, #48]
	115	ldp x11, x12, [x0, #64]
623b476f	116	ldp x13, x14, [x0, #80]
6d37d81f ST	117	/*
	118	* Restore x18, as it may be used as a platform register, and clear
	119	* the buffer to minimize the risk of exposure when used for shadow
	120	* call stack.
	121	*/
	122	ldr x18, [x0, #96]
	123	str xzr, [x0, #96]
6732bc65 LP	124	msr tpidr_el0, x2
	125	msr tpidrro_el0, x3
	126	msr contextidr_el1, x4
6732bc65	127	msr cpacr_el1, x6
cabe1c81 JM	128
cabe1c81 JM	129	/* Don't change t0sz here, mask those bits when restoring */
827a108e JPB	130	mrs x7, tcr_el1
827a108e JPB	131	bfi x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
cabe1c81	132
6732bc65 LP	133	msr tcr_el1, x8
6732bc65 LP	134	msr vbar_el1, x9
744c6c37 JM	135
	136	/*
	137	* __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
	138	* debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
0fbeb318	139	* exception. Mask them until local_daif_restore() in cpu_suspend()
744c6c37 JM	140	* resets them.
744c6c37 JM	141	*/
0fbeb318	142	disable_daif
6732bc65	143	msr mdscr_el1, x10
744c6c37	144
cabe1c81	145	msr sctlr_el1, x12
6d99b689	146	alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
623b476f	147	msr tpidr_el1, x13
6d99b689 JM	148	alternative_else
	149	msr tpidr_el2, x13
	150	alternative_endif
623b476f	151	msr sp_el0, x14
6732bc65 LP	152	/*
	153	* Restore oslsr_el1 by writing oslar_el1
	154	*/
827a108e	155	msr osdlr_el1, x5
6732bc65 LP	156	ubfx x11, x11, #1, #1
6732bc65 LP	157	msr oslar_el1, x11
f436b2ac	158	reset_pmuserenr_el0 x0 // Disable PMU access from EL0
87a1f063	159	reset_amuserenr_el0 x0 // Disable AMU access from EL0
68ddbf09 JM	160
	161	alternative_if ARM64_HAS_RAS_EXTN
	162	msr_s SYS_DISR_EL1, xzr
	163	alternative_else_nop_endif
	164
d0055da5	165	ptrauth_keys_install_kernel_nosync x14, x1, x2, x3
6732bc65 LP	166	isb
6732bc65 LP	167	ret
f4659254	168	SYM_FUNC_END(cpu_do_resume)
b6113038	169	.popsection
6732bc65 LP	170	#endif
6732bc65 LP	171
439e70e2	172	.pushsection ".idmap.text", "awx"
f992b4df WD	173
f992b4df WD	174	.macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
833be850	175	adrp \tmp1, reserved_pg_dir
fa0465fc	176	phys_to_ttbr \tmp2, \tmp1
c812026c	177	offset_ttbr1 \tmp2, \tmp1
f992b4df WD	178	msr ttbr1_el1, \tmp2
	179	isb
	180	tlbi vmalle1
	181	dsb nsh
	182	isb
	183	.endm
	184
50e1881d	185	/*
5ffdfaed	186	* void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1)
50e1881d MR	187	*
	188	* This is the low-level counterpart to cpu_replace_ttbr1, and should not be
	189	* called by anything else. It can only be executed from a TTBR0 mapping.
	190	*/
f4659254	191	SYM_FUNC_START(idmap_cpu_replace_ttbr1)
0fbeb318	192	save_and_disable_daif flags=x2
50e1881d	193
f992b4df	194	__idmap_cpu_set_reserved_ttbr1 x1, x3
50e1881d	195
c812026c	196	offset_ttbr1 x0, x3
5ffdfaed	197	msr ttbr1_el1, x0
50e1881d MR	198	isb
50e1881d MR	199
0fbeb318	200	restore_daif x2
50e1881d MR	201
50e1881d MR	202	ret
f4659254	203	SYM_FUNC_END(idmap_cpu_replace_ttbr1)
50e1881d MR	204	.popsection
50e1881d MR	205
f992b4df	206	#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
439e70e2	207	.pushsection ".idmap.text", "awx"
f992b4df WD	208
	209	.macro __idmap_kpti_get_pgtable_ent, type
	210	dc cvac, cur_\()\type\()p // Ensure any existing dirty
	211	dmb sy // lines are written back before
	212	ldr \type, [cur_\()\type\()p] // loading the entry
2ce77f6d WD	213	tbz \type, #0, skip_\()\type // Skip invalid and
2ce77f6d WD	214	tbnz \type, #11, skip_\()\type // non-global entries
f992b4df WD	215	.endm
	216
	217	.macro __idmap_kpti_put_pgtable_ent_ng, type
	218	orr \type, \type, #PTE_NG // Same bit for blocks and pages
71c8fc0c WD	219	str \type, [cur_\()\type\()p] // Update the entry and ensure
	220	dmb sy // that it is visible to all
	221	dc civac, cur_\()\type\()p // CPUs.
f992b4df WD	222	.endm
	223
	224	/*
	225	* void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
	226	*
	227	* Called exactly once from stop_machine context by each CPU found during boot.
	228	*/
	229	__idmap_kpti_flag:
	230	.long 1
f4659254	231	SYM_FUNC_START(idmap_kpti_install_ng_mappings)
f992b4df WD	232	cpu .req w0
	233	num_cpus .req w1
	234	swapper_pa .req x2
	235	swapper_ttb .req x3
	236	flag_ptr .req x4
	237	cur_pgdp .req x5
	238	end_pgdp .req x6
	239	pgd .req x7
	240	cur_pudp .req x8
	241	end_pudp .req x9
	242	pud .req x10
	243	cur_pmdp .req x11
	244	end_pmdp .req x12
	245	pmd .req x13
	246	cur_ptep .req x14
	247	end_ptep .req x15
	248	pte .req x16
	249
	250	mrs swapper_ttb, ttbr1_el1
e842dfb5	251	restore_ttbr1 swapper_ttb
f992b4df WD	252	adr flag_ptr, __idmap_kpti_flag
	253
	254	cbnz cpu, __idmap_kpti_secondary
	255
	256	/* We're the boot CPU. Wait for the others to catch up */
	257	sevl
	258	1: wfe
e3ec6582 ST	259	ldaxr w17, [flag_ptr]
	260	eor w17, w17, num_cpus
	261	cbnz w17, 1b
f992b4df WD	262
	263	/* We need to walk swapper, so turn off the MMU. */
	264	pre_disable_mmu_workaround
e3ec6582 ST	265	mrs x17, sctlr_el1
	266	bic x17, x17, #SCTLR_ELx_M
	267	msr sctlr_el1, x17
f992b4df WD	268	isb
	269
	270	/* Everybody is enjoying the idmap, so we can rewrite swapper. */
	271	/* PGD */
	272	mov cur_pgdp, swapper_pa
	273	add end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
	274	do_pgd: __idmap_kpti_get_pgtable_ent pgd
	275	tbnz pgd, #1, walk_puds
f992b4df	276	next_pgd:
2ce77f6d WD	277	__idmap_kpti_put_pgtable_ent_ng pgd
2ce77f6d WD	278	skip_pgd:
f992b4df WD	279	add cur_pgdp, cur_pgdp, #8
	280	cmp cur_pgdp, end_pgdp
	281	b.ne do_pgd
	282
	283	/* Publish the updated tables and nuke all the TLBs */
	284	dsb sy
	285	tlbi vmalle1is
	286	dsb ish
	287	isb
	288
	289	/* We're done: fire up the MMU again */
e3ec6582 ST	290	mrs x17, sctlr_el1
e3ec6582 ST	291	orr x17, x17, #SCTLR_ELx_M
8cc8a324	292	set_sctlr_el1 x17
f32c7a8e	293
f992b4df WD	294	/* Set the flag to zero to indicate that we're all done */
	295	str wzr, [flag_ptr]
	296	ret
	297
	298	/* PUD */
	299	walk_puds:
	300	.if CONFIG_PGTABLE_LEVELS > 3
	301	pte_to_phys cur_pudp, pgd
	302	add end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
	303	do_pud: __idmap_kpti_get_pgtable_ent pud
	304	tbnz pud, #1, walk_pmds
f992b4df	305	next_pud:
2ce77f6d WD	306	__idmap_kpti_put_pgtable_ent_ng pud
2ce77f6d WD	307	skip_pud:
f992b4df WD	308	add cur_pudp, cur_pudp, 8
	309	cmp cur_pudp, end_pudp
	310	b.ne do_pud
	311	b next_pgd
	312	.else /* CONFIG_PGTABLE_LEVELS <= 3 */
	313	mov pud, pgd
	314	b walk_pmds
	315	next_pud:
	316	b next_pgd
	317	.endif
	318
	319	/* PMD */
	320	walk_pmds:
	321	.if CONFIG_PGTABLE_LEVELS > 2
	322	pte_to_phys cur_pmdp, pud
	323	add end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
	324	do_pmd: __idmap_kpti_get_pgtable_ent pmd
	325	tbnz pmd, #1, walk_ptes
f992b4df	326	next_pmd:
2ce77f6d WD	327	__idmap_kpti_put_pgtable_ent_ng pmd
2ce77f6d WD	328	skip_pmd:
f992b4df WD	329	add cur_pmdp, cur_pmdp, #8
	330	cmp cur_pmdp, end_pmdp
	331	b.ne do_pmd
	332	b next_pud
	333	.else /* CONFIG_PGTABLE_LEVELS <= 2 */
	334	mov pmd, pud
	335	b walk_ptes
	336	next_pmd:
	337	b next_pud
	338	.endif
	339
	340	/* PTE */
	341	walk_ptes:
	342	pte_to_phys cur_ptep, pmd
	343	add end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
	344	do_pte: __idmap_kpti_get_pgtable_ent pte
	345	__idmap_kpti_put_pgtable_ent_ng pte
2ce77f6d	346	skip_pte:
f992b4df WD	347	add cur_ptep, cur_ptep, #8
	348	cmp cur_ptep, end_ptep
	349	b.ne do_pte
	350	b next_pmd
	351
e3ec6582 ST	352	.unreq cpu
	353	.unreq num_cpus
	354	.unreq swapper_pa
	355	.unreq cur_pgdp
	356	.unreq end_pgdp
	357	.unreq pgd
	358	.unreq cur_pudp
	359	.unreq end_pudp
	360	.unreq pud
	361	.unreq cur_pmdp
	362	.unreq end_pmdp
	363	.unreq pmd
	364	.unreq cur_ptep
	365	.unreq end_ptep
	366	.unreq pte
	367
f992b4df WD	368	/* Secondary CPUs end up here */
	369	__idmap_kpti_secondary:
	370	/* Uninstall swapper before surgery begins */
e3ec6582	371	__idmap_cpu_set_reserved_ttbr1 x16, x17
f992b4df WD	372
f992b4df WD	373	/* Increment the flag to let the boot CPU we're ready */
e3ec6582 ST	374	1: ldxr w16, [flag_ptr]
	375	add w16, w16, #1
	376	stxr w17, w16, [flag_ptr]
f992b4df WD	377	cbnz w17, 1b
	378
	379	/* Wait for the boot CPU to finish messing around with swapper */
	380	sevl
	381	1: wfe
e3ec6582 ST	382	ldxr w16, [flag_ptr]
e3ec6582 ST	383	cbnz w16, 1b
f992b4df WD	384
f992b4df WD	385	/* All done, act like nothing happened */
e3ec6582	386	offset_ttbr1 swapper_ttb, x16
f992b4df WD	387	msr ttbr1_el1, swapper_ttb
	388	isb
	389	ret
	390
f992b4df WD	391	.unreq swapper_ttb
f992b4df WD	392	.unreq flag_ptr
f4659254	393	SYM_FUNC_END(idmap_kpti_install_ng_mappings)
f992b4df WD	394	.popsection
	395	#endif
	396
9cce7a43 CM	397	/*
	398	* __cpu_setup
	399	*
df355101 ADK	400	* Initialise the processor for turning the MMU on.
df355101 ADK	401	*
df355101 ADK	402	* Output:
df355101 ADK	403	* Return in x0 the value of the SCTLR_EL1 register.
9cce7a43	404	*/
439e70e2	405	.pushsection ".idmap.text", "awx"
f4659254	406	SYM_FUNC_START(__cpu_setup)
fa7aae8a WD	407	tlbi vmalle1 // Invalidate local TLB
fa7aae8a WD	408	dsb nsh
9cce7a43	409
df355101 ADK	410	mov x1, #3 << 20
	411	msr cpacr_el1, x1 // Enable FP/ASIMD
	412	mov x1, #1 << 12 // Reset mdscr_el1 and disable
	413	msr mdscr_el1, x1 // access to the DCC from EL0
2ce39ad1 WD	414	isb // Unmask debug exceptions now,
2ce39ad1 WD	415	enable_dbg // since this is per-cpu
df355101	416	reset_pmuserenr_el0 x1 // Disable PMU access from EL0
44ca0e00	417	reset_amuserenr_el0 x1 // Disable AMU access from EL0
87a1f063	418
9cce7a43	419	/*
5cd6fa6d MR	420	* Default values for VMSA control registers. These will be adjusted
5cd6fa6d MR	421	* below depending on detected CPU features.
9cce7a43	422	*/
776e49af	423	mair .req x17
5cd6fa6d	424	tcr .req x16
776e49af	425	mov_q mair, MAIR_EL1_SET
5cd6fa6d MR	426	mov_q tcr, TCR_TxSZ(VA_BITS) \| TCR_CACHE_FLAGS \| TCR_SMP_FLAGS \| \
	427	TCR_TG_FLAGS \| TCR_KASLR_FLAGS \| TCR_ASID16 \| \
	428	TCR_TBI0 \| TCR_A1 \| TCR_KASAN_SW_FLAGS
bfc62c59	429
5cd6fa6d	430	#ifdef CONFIG_ARM64_MTE
3b714d24 VF	431	/*
	432	* Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported
	433	* (ID_AA64PFR1_EL1[11:8] > 1).
	434	*/
	435	mrs x10, ID_AA64PFR1_EL1
	436	ubfx x10, x10, #ID_AA64PFR1_MTE_SHIFT, #4
	437	cmp x10, #ID_AA64PFR1_MTE
	438	b.lt 1f
	439
	440	/* Normal Tagged memory type at the corresponding MAIR index */
	441	mov x10, #MAIR_ATTR_NORMAL_TAGGED
776e49af	442	bfi mair, x10, #(8 * MT_NORMAL_TAGGED), #8
3b714d24 VF	443
	444	/* initialize GCR_EL1: all non-zero tags excluded by default */
	445	mov x10, #(SYS_GCR_EL1_RRND \| SYS_GCR_EL1_EXCL_MASK)
	446	msr_s SYS_GCR_EL1, x10
	447
37a8024d PC	448	/*
	449	* If GCR_EL1.RRND=1 is implemented the same way as RRND=0, then
	450	* RGSR_EL1.SEED must be non-zero for IRG to produce
	451	* pseudorandom numbers. As RGSR_EL1 is UNKNOWN out of reset, we
	452	* must initialize it.
	453	*/
	454	mrs x10, CNTVCT_EL0
	455	ands x10, x10, #SYS_RGSR_EL1_SEED_MASK
	456	csinc x10, x10, xzr, ne
	457	lsl x10, x10, #SYS_RGSR_EL1_SEED_SHIFT
	458	msr_s SYS_RGSR_EL1, x10
	459
3b714d24 VF	460	/* clear any pending tag check faults in TFSR_EL1 /
	461	msr_s SYS_TFSR_EL1, xzr
	462	msr_s SYS_TFSRE0_EL1, xzr
bfc62c59 VF	463
bfc62c59 VF	464	/* set the TCR_EL1 bits */
5cd6fa6d MR	465	mov_q x10, TCR_KASAN_HW_FLAGS
5cd6fa6d MR	466	orr tcr, tcr, x10
3b714d24 VF	467	1:
3b714d24 VF	468	#endif
5cd6fa6d	469	tcr_clear_errata_bits tcr, x9, x5
67e7fdfc	470
b6d00d47	471	#ifdef CONFIG_ARM64_VA_BITS_52
2c624fe6	472	ldr_l x9, vabits_actual
67e7fdfc SC	473	sub x9, xzr, x9
67e7fdfc SC	474	add x9, x9, #64
5cd6fa6d	475	tcr_set_t1sz tcr, x9
67e7fdfc SC	476	#else
	477	ldr_l x9, idmap_t0sz
	478	#endif
5cd6fa6d	479	tcr_set_t0sz tcr, x9
dd006da2	480
87366d8c	481	/*
787fd1d0	482	* Set the IPS bits in TCR_EL1.
87366d8c	483	*/
5cd6fa6d	484	tcr_compute_pa_size tcr, #TCR_IPS_SHIFT, x5, x6
2f4b829c CM	485	#ifdef CONFIG_ARM64_HW_AFDBM
2f4b829c CM	486	/*
05abb595 SP	487	* Enable hardware update of the Access Flags bit.
	488	* Hardware dirty bit management is enabled later,
	489	* via capabilities.
2f4b829c CM	490	*/
	491	mrs x9, ID_AA64MMFR1_EL1
	492	and x9, x9, #0xf
05abb595	493	cbz x9, 1f
5cd6fa6d	494	orr tcr, tcr, #TCR_HA // hardware Access flag update
05abb595	495	1:
2f4b829c	496	#endif /* CONFIG_ARM64_HW_AFDBM */
776e49af	497	msr mair_el1, mair
5cd6fa6d	498	msr tcr_el1, tcr
df355101 ADK	499	/*
	500	* Prepare SCTLR
	501	*/
2ffac9e3	502	mov_q x0, INIT_SCTLR_EL1_MMU_ON
9cce7a43	503	ret // return to head.S
776e49af MR	504
776e49af MR	505	.unreq mair
5cd6fa6d	506	.unreq tcr
f4659254	507	SYM_FUNC_END(__cpu_setup)