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9cce7a43 CM |
1 | /* |
2 | * Based on arch/arm/mm/proc.S | |
3 | * | |
4 | * Copyright (C) 2001 Deep Blue Solutions Ltd. | |
5 | * Copyright (C) 2012 ARM Ltd. | |
6 | * Author: Catalin Marinas <catalin.marinas@arm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include <linux/init.h> | |
22 | #include <linux/linkage.h> | |
23 | #include <asm/assembler.h> | |
24 | #include <asm/asm-offsets.h> | |
25 | #include <asm/hwcap.h> | |
26 | #include <asm/pgtable-hwdef.h> | |
27 | #include <asm/pgtable.h> | |
28 | ||
29 | #include "proc-macros.S" | |
30 | ||
31 | #ifndef CONFIG_SMP | |
32 | /* PTWs cacheable, inner/outer WBWA not shareable */ | |
33 | #define TCR_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA | |
34 | #else | |
35 | /* PTWs cacheable, inner/outer WBWA shareable */ | |
36 | #define TCR_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA | TCR_SHARED | |
37 | #endif | |
38 | ||
39 | #define MAIR(attr, mt) ((attr) << ((mt) * 8)) | |
40 | ||
41 | /* | |
42 | * cpu_cache_off() | |
43 | * | |
44 | * Turn the CPU D-cache off. | |
45 | */ | |
46 | ENTRY(cpu_cache_off) | |
47 | mrs x0, sctlr_el1 | |
48 | bic x0, x0, #1 << 2 // clear SCTLR.C | |
49 | msr sctlr_el1, x0 | |
50 | isb | |
51 | ret | |
52 | ENDPROC(cpu_cache_off) | |
53 | ||
54 | /* | |
55 | * cpu_reset(loc) | |
56 | * | |
57 | * Perform a soft reset of the system. Put the CPU into the same state | |
58 | * as it would be if it had been reset, and branch to what would be the | |
59 | * reset vector. It must be executed with the flat identity mapping. | |
60 | * | |
61 | * - loc - location to jump to for soft reset | |
62 | */ | |
63 | .align 5 | |
64 | ENTRY(cpu_reset) | |
65 | mrs x1, sctlr_el1 | |
66 | bic x1, x1, #1 | |
67 | msr sctlr_el1, x1 // disable the MMU | |
68 | isb | |
69 | ret x0 | |
70 | ENDPROC(cpu_reset) | |
71 | ||
72 | /* | |
73 | * cpu_do_idle() | |
74 | * | |
75 | * Idle the processor (wait for interrupt). | |
76 | */ | |
77 | ENTRY(cpu_do_idle) | |
78 | dsb sy // WFI may enter a low-power mode | |
79 | wfi | |
80 | ret | |
81 | ENDPROC(cpu_do_idle) | |
82 | ||
83 | /* | |
84 | * cpu_switch_mm(pgd_phys, tsk) | |
85 | * | |
86 | * Set the translation table base pointer to be pgd_phys. | |
87 | * | |
88 | * - pgd_phys - physical address of new TTB | |
89 | */ | |
90 | ENTRY(cpu_do_switch_mm) | |
91 | mmid w1, x1 // get mm->context.id | |
92 | bfi x0, x1, #48, #16 // set the ASID | |
93 | msr ttbr0_el1, x0 // set TTBR0 | |
94 | isb | |
95 | ret | |
96 | ENDPROC(cpu_do_switch_mm) | |
97 | ||
9cce7a43 CM |
98 | .section ".text.init", #alloc, #execinstr |
99 | ||
100 | /* | |
101 | * __cpu_setup | |
102 | * | |
103 | * Initialise the processor for turning the MMU on. Return in x0 the | |
104 | * value of the SCTLR_EL1 register. | |
105 | */ | |
106 | ENTRY(__cpu_setup) | |
9cce7a43 CM |
107 | /* |
108 | * Preserve the link register across the function call. | |
109 | */ | |
110 | mov x28, lr | |
111 | bl __flush_dcache_all | |
112 | mov lr, x28 | |
113 | ic iallu // I+BTB cache invalidate | |
114 | dsb sy | |
115 | ||
116 | mov x0, #3 << 20 | |
117 | msr cpacr_el1, x0 // Enable FP/ASIMD | |
9c413e25 | 118 | msr mdscr_el1, xzr // Reset mdscr_el1 |
9cce7a43 CM |
119 | tlbi vmalle1is // invalidate I + D TLBs |
120 | /* | |
121 | * Memory region attributes for LPAE: | |
122 | * | |
123 | * n = AttrIndx[2:0] | |
124 | * n MAIR | |
125 | * DEVICE_nGnRnE 000 00000000 | |
126 | * DEVICE_nGnRE 001 00000100 | |
127 | * DEVICE_GRE 010 00001100 | |
128 | * NORMAL_NC 011 01000100 | |
129 | * NORMAL 100 11111111 | |
130 | */ | |
131 | ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \ | |
132 | MAIR(0x04, MT_DEVICE_nGnRE) | \ | |
133 | MAIR(0x0c, MT_DEVICE_GRE) | \ | |
134 | MAIR(0x44, MT_NORMAL_NC) | \ | |
135 | MAIR(0xff, MT_NORMAL) | |
136 | msr mair_el1, x5 | |
137 | /* | |
138 | * Prepare SCTLR | |
139 | */ | |
140 | adr x5, crval | |
141 | ldp w5, w6, [x5] | |
142 | mrs x0, sctlr_el1 | |
143 | bic x0, x0, x5 // clear bits | |
144 | orr x0, x0, x6 // set bits | |
145 | /* | |
146 | * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for | |
147 | * both user and kernel. | |
148 | */ | |
149 | ldr x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | TCR_IPS_40BIT | \ | |
d50240a5 | 150 | TCR_ASID16 | TCR_TBI0 | (1 << 31) |
9cce7a43 CM |
151 | #ifdef CONFIG_ARM64_64K_PAGES |
152 | orr x10, x10, TCR_TG0_64K | |
153 | orr x10, x10, TCR_TG1_64K | |
154 | #endif | |
155 | msr tcr_el1, x10 | |
156 | ret // return to head.S | |
157 | ENDPROC(__cpu_setup) | |
158 | ||
159 | /* | |
160 | * n n T | |
161 | * U E WT T UD US IHBS | |
162 | * CE0 XWHW CZ ME TEEA S | |
163 | * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM | |
164 | * 0011 0... 1101 ..0. ..0. 10.. .... .... < hardware reserved | |
165 | * .... .100 .... 01.1 11.1 ..01 0001 1101 < software settings | |
166 | */ | |
167 | .type crval, #object | |
168 | crval: | |
169 | .word 0x030802e2 // clear | |
170 | .word 0x0405d11d // set |