[mirror_ubuntu-jammy-kernel.git] / arch / arm64 / mm / proc.S

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Based on arch/arm/mm/proc.S
 *
 * Copyright (C) 2001 Deep Blue Solutions Ltd.
 * Copyright (C) 2012 ARM Ltd.
 * Author: Catalin Marinas <catalin.marinas@arm.com>
 */

#include <linux/init.h>
#include <linux/linkage.h>
#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/asm_pointer_auth.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/cpufeature.h>
#include <asm/alternative.h>
#include <asm/smp.h>
#include <asm/sysreg.h>

#ifdef CONFIG_ARM64_64K_PAGES
#define TCR_TG_FLAGS	TCR_TG0_64K | TCR_TG1_64K
#elif defined(CONFIG_ARM64_16K_PAGES)
#define TCR_TG_FLAGS	TCR_TG0_16K | TCR_TG1_16K
#else /* CONFIG_ARM64_4K_PAGES */
#define TCR_TG_FLAGS	TCR_TG0_4K | TCR_TG1_4K
#endif

#ifdef CONFIG_RANDOMIZE_BASE
#define TCR_KASLR_FLAGS	TCR_NFD1
#else
#define TCR_KASLR_FLAGS	0
#endif

#define TCR_SMP_FLAGS	TCR_SHARED

/* PTWs cacheable, inner/outer WBWA */
#define TCR_CACHE_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA

#ifdef CONFIG_KASAN_SW_TAGS
#define TCR_KASAN_SW_FLAGS TCR_TBI1 | TCR_TBID1
#else
#define TCR_KASAN_SW_FLAGS 0
#endif

#ifdef CONFIG_KASAN_HW_TAGS
#define TCR_KASAN_HW_FLAGS SYS_TCR_EL1_TCMA1 | TCR_TBI1
#else
#define TCR_KASAN_HW_FLAGS 0
#endif

/*
 * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and
 * changed during __cpu_setup to Normal Tagged if the system supports MTE.
 */
#define MAIR_EL1_SET							\
	(MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) |	\
	 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) |	\
	 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) |		\
	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) |		\
	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) |			\
	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT) |		\
	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED))

#ifdef CONFIG_CPU_PM
/**
 * cpu_do_suspend - save CPU registers context
 *
 * x0: virtual address of context pointer
 *
 * This must be kept in sync with struct cpu_suspend_ctx in <asm/suspend.h>.
 */
SYM_FUNC_START(cpu_do_suspend)
	mrs	x2, tpidr_el0
	mrs	x3, tpidrro_el0
	mrs	x4, contextidr_el1
	mrs	x5, osdlr_el1
	mrs	x6, cpacr_el1
	mrs	x7, tcr_el1
	mrs	x8, vbar_el1
	mrs	x9, mdscr_el1
	mrs	x10, oslsr_el1
	mrs	x11, sctlr_el1
alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
	mrs	x12, tpidr_el1
alternative_else
	mrs	x12, tpidr_el2
alternative_endif
	mrs	x13, sp_el0
	stp	x2, x3, [x0]
	stp	x4, x5, [x0, #16]
	stp	x6, x7, [x0, #32]
	stp	x8, x9, [x0, #48]
	stp	x10, x11, [x0, #64]
	stp	x12, x13, [x0, #80]
	/*
	 * Save x18 as it may be used as a platform register, e.g. by shadow
	 * call stack.
	 */
	str	x18, [x0, #96]
	ret
SYM_FUNC_END(cpu_do_suspend)

/**
 * cpu_do_resume - restore CPU register context
 *
 * x0: Address of context pointer
 */
	.pushsection ".idmap.text", "awx"
SYM_FUNC_START(cpu_do_resume)
	ldp	x2, x3, [x0]
	ldp	x4, x5, [x0, #16]
	ldp	x6, x8, [x0, #32]
	ldp	x9, x10, [x0, #48]
	ldp	x11, x12, [x0, #64]
	ldp	x13, x14, [x0, #80]
	/*
	 * Restore x18, as it may be used as a platform register, and clear
	 * the buffer to minimize the risk of exposure when used for shadow
	 * call stack.
	 */
	ldr	x18, [x0, #96]
	str	xzr, [x0, #96]
	msr	tpidr_el0, x2
	msr	tpidrro_el0, x3
	msr	contextidr_el1, x4
	msr	cpacr_el1, x6

	/* Don't change t0sz here, mask those bits when restoring */
	mrs	x7, tcr_el1
	bfi	x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH

	msr	tcr_el1, x8
	msr	vbar_el1, x9

	/*
	 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
	 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
	 * exception. Mask them until local_daif_restore() in cpu_suspend()
	 * resets them.
	 */
	disable_daif
	msr	mdscr_el1, x10

	msr	sctlr_el1, x12
alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
	msr	tpidr_el1, x13
alternative_else
	msr	tpidr_el2, x13
alternative_endif
	msr	sp_el0, x14
	/*
	 * Restore oslsr_el1 by writing oslar_el1
	 */
	msr	osdlr_el1, x5
	ubfx	x11, x11, #1, #1
	msr	oslar_el1, x11
	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
	reset_amuserenr_el0 x0			// Disable AMU access from EL0

alternative_if ARM64_HAS_RAS_EXTN
	msr_s	SYS_DISR_EL1, xzr
alternative_else_nop_endif

	ptrauth_keys_install_kernel_nosync x14, x1, x2, x3
	isb
	ret
SYM_FUNC_END(cpu_do_resume)
	.popsection
#endif

	.pushsection ".idmap.text", "awx"

.macro	__idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
	adrp	\tmp1, reserved_pg_dir
	phys_to_ttbr \tmp2, \tmp1
	offset_ttbr1 \tmp2, \tmp1
	msr	ttbr1_el1, \tmp2
	isb
	tlbi	vmalle1
	dsb	nsh
	isb
.endm

/*
 * void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1)
 *
 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
 * called by anything else. It can only be executed from a TTBR0 mapping.
 */
SYM_FUNC_START(idmap_cpu_replace_ttbr1)
	save_and_disable_daif flags=x2

	__idmap_cpu_set_reserved_ttbr1 x1, x3

	offset_ttbr1 x0, x3
	msr	ttbr1_el1, x0
	isb

	restore_daif x2

	ret
SYM_FUNC_END(idmap_cpu_replace_ttbr1)
	.popsection

#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
	.pushsection ".idmap.text", "awx"

	.macro	__idmap_kpti_get_pgtable_ent, type
	dc	cvac, cur_\()\type\()p		// Ensure any existing dirty
	dmb	sy				// lines are written back before
	ldr	\type, [cur_\()\type\()p]	// loading the entry
	tbz	\type, #0, skip_\()\type	// Skip invalid and
	tbnz	\type, #11, skip_\()\type	// non-global entries
	.endm

	.macro __idmap_kpti_put_pgtable_ent_ng, type
	orr	\type, \type, #PTE_NG		// Same bit for blocks and pages
	str	\type, [cur_\()\type\()p]	// Update the entry and ensure
	dmb	sy				// that it is visible to all
	dc	civac, cur_\()\type\()p		// CPUs.
	.endm

/*
 * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
 *
 * Called exactly once from stop_machine context by each CPU found during boot.
 */
__idmap_kpti_flag:
	.long	1
SYM_FUNC_START(idmap_kpti_install_ng_mappings)
	cpu		.req	w0
	num_cpus	.req	w1
	swapper_pa	.req	x2
	swapper_ttb	.req	x3
	flag_ptr	.req	x4
	cur_pgdp	.req	x5
	end_pgdp	.req	x6
	pgd		.req	x7
	cur_pudp	.req	x8
	end_pudp	.req	x9
	pud		.req	x10
	cur_pmdp	.req	x11
	end_pmdp	.req	x12
	pmd		.req	x13
	cur_ptep	.req	x14
	end_ptep	.req	x15
	pte		.req	x16

	mrs	swapper_ttb, ttbr1_el1
	restore_ttbr1	swapper_ttb
	adr	flag_ptr, __idmap_kpti_flag

	cbnz	cpu, __idmap_kpti_secondary

	/* We're the boot CPU. Wait for the others to catch up */
	sevl
1:	wfe
	ldaxr	w17, [flag_ptr]
	eor	w17, w17, num_cpus
	cbnz	w17, 1b

	/* We need to walk swapper, so turn off the MMU. */
	pre_disable_mmu_workaround
	mrs	x17, sctlr_el1
	bic	x17, x17, #SCTLR_ELx_M
	msr	sctlr_el1, x17
	isb

	/* Everybody is enjoying the idmap, so we can rewrite swapper. */
	/* PGD */
	mov	cur_pgdp, swapper_pa
	add	end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
do_pgd:	__idmap_kpti_get_pgtable_ent	pgd
	tbnz	pgd, #1, walk_puds
next_pgd:
	__idmap_kpti_put_pgtable_ent_ng	pgd
skip_pgd:
	add	cur_pgdp, cur_pgdp, #8
	cmp	cur_pgdp, end_pgdp
	b.ne	do_pgd

	/* Publish the updated tables and nuke all the TLBs */
	dsb	sy
	tlbi	vmalle1is
	dsb	ish
	isb

	/* We're done: fire up the MMU again */
	mrs	x17, sctlr_el1
	orr	x17, x17, #SCTLR_ELx_M
	msr	sctlr_el1, x17
	isb

	/*
	 * Invalidate the local I-cache so that any instructions fetched
	 * speculatively from the PoC are discarded, since they may have
	 * been dynamically patched at the PoU.
	 */
	ic	iallu
	dsb	nsh
	isb

	/* Set the flag to zero to indicate that we're all done */
	str	wzr, [flag_ptr]
	ret

	/* PUD */
walk_puds:
	.if CONFIG_PGTABLE_LEVELS > 3
	pte_to_phys	cur_pudp, pgd
	add	end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
do_pud:	__idmap_kpti_get_pgtable_ent	pud
	tbnz	pud, #1, walk_pmds
next_pud:
	__idmap_kpti_put_pgtable_ent_ng	pud
skip_pud:
	add	cur_pudp, cur_pudp, 8
	cmp	cur_pudp, end_pudp
	b.ne	do_pud
	b	next_pgd
	.else /* CONFIG_PGTABLE_LEVELS <= 3 */
	mov	pud, pgd
	b	walk_pmds
next_pud:
	b	next_pgd
	.endif

	/* PMD */
walk_pmds:
	.if CONFIG_PGTABLE_LEVELS > 2
	pte_to_phys	cur_pmdp, pud
	add	end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
do_pmd:	__idmap_kpti_get_pgtable_ent	pmd
	tbnz	pmd, #1, walk_ptes
next_pmd:
	__idmap_kpti_put_pgtable_ent_ng	pmd
skip_pmd:
	add	cur_pmdp, cur_pmdp, #8
	cmp	cur_pmdp, end_pmdp
	b.ne	do_pmd
	b	next_pud
	.else /* CONFIG_PGTABLE_LEVELS <= 2 */
	mov	pmd, pud
	b	walk_ptes
next_pmd:
	b	next_pud
	.endif

	/* PTE */
walk_ptes:
	pte_to_phys	cur_ptep, pmd
	add	end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
do_pte:	__idmap_kpti_get_pgtable_ent	pte
	__idmap_kpti_put_pgtable_ent_ng	pte
skip_pte:
	add	cur_ptep, cur_ptep, #8
	cmp	cur_ptep, end_ptep
	b.ne	do_pte
	b	next_pmd

	.unreq	cpu
	.unreq	num_cpus
	.unreq	swapper_pa
	.unreq	cur_pgdp
	.unreq	end_pgdp
	.unreq	pgd
	.unreq	cur_pudp
	.unreq	end_pudp
	.unreq	pud
	.unreq	cur_pmdp
	.unreq	end_pmdp
	.unreq	pmd
	.unreq	cur_ptep
	.unreq	end_ptep
	.unreq	pte

	/* Secondary CPUs end up here */
__idmap_kpti_secondary:
	/* Uninstall swapper before surgery begins */
	__idmap_cpu_set_reserved_ttbr1 x16, x17

	/* Increment the flag to let the boot CPU we're ready */
1:	ldxr	w16, [flag_ptr]
	add	w16, w16, #1
	stxr	w17, w16, [flag_ptr]
	cbnz	w17, 1b

	/* Wait for the boot CPU to finish messing around with swapper */
	sevl
1:	wfe
	ldxr	w16, [flag_ptr]
	cbnz	w16, 1b

	/* All done, act like nothing happened */
	offset_ttbr1 swapper_ttb, x16
	msr	ttbr1_el1, swapper_ttb
	isb
	ret

	.unreq	swapper_ttb
	.unreq	flag_ptr
SYM_FUNC_END(idmap_kpti_install_ng_mappings)
	.popsection
#endif

/*
 *	__cpu_setup
 *
 *	Initialise the processor for turning the MMU on.
 *
 * Output:
 *	Return in x0 the value of the SCTLR_EL1 register.
 */
	.pushsection ".idmap.text", "awx"
SYM_FUNC_START(__cpu_setup)
	tlbi	vmalle1				// Invalidate local TLB
	dsb	nsh

	mov	x1, #3 << 20
	msr	cpacr_el1, x1			// Enable FP/ASIMD
	mov	x1, #1 << 12			// Reset mdscr_el1 and disable
	msr	mdscr_el1, x1			// access to the DCC from EL0
	isb					// Unmask debug exceptions now,
	enable_dbg				// since this is per-cpu
	reset_pmuserenr_el0 x1			// Disable PMU access from EL0
	reset_amuserenr_el0 x1			// Disable AMU access from EL0

	/*
	 * Memory region attributes
	 */
	mov_q	x5, MAIR_EL1_SET
#ifdef CONFIG_ARM64_MTE
	mte_tcr	.req	x20

	mov	mte_tcr, #0

	/*
	 * Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported
	 * (ID_AA64PFR1_EL1[11:8] > 1).
	 */
	mrs	x10, ID_AA64PFR1_EL1
	ubfx	x10, x10, #ID_AA64PFR1_MTE_SHIFT, #4
	cmp	x10, #ID_AA64PFR1_MTE
	b.lt	1f

	/* Normal Tagged memory type at the corresponding MAIR index */
	mov	x10, #MAIR_ATTR_NORMAL_TAGGED
	bfi	x5, x10, #(8 *  MT_NORMAL_TAGGED), #8

	/* initialize GCR_EL1: all non-zero tags excluded by default */
	mov	x10, #(SYS_GCR_EL1_RRND | SYS_GCR_EL1_EXCL_MASK)
	msr_s	SYS_GCR_EL1, x10

	/* clear any pending tag check faults in TFSR*_EL1 */
	msr_s	SYS_TFSR_EL1, xzr
	msr_s	SYS_TFSRE0_EL1, xzr

	/* set the TCR_EL1 bits */
	mov_q	mte_tcr, TCR_KASAN_HW_FLAGS
1:
#endif
	msr	mair_el1, x5
	/*
	 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
	 * both user and kernel.
	 */
	mov_q	x10, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
			TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
			TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS
#ifdef CONFIG_ARM64_MTE
	orr	x10, x10, mte_tcr
	.unreq	mte_tcr
#endif
	tcr_clear_errata_bits x10, x9, x5

#ifdef CONFIG_ARM64_VA_BITS_52
	ldr_l		x9, vabits_actual
	sub		x9, xzr, x9
	add		x9, x9, #64
	tcr_set_t1sz	x10, x9
#else
	ldr_l		x9, idmap_t0sz
#endif
	tcr_set_t0sz	x10, x9

	/*
	 * Set the IPS bits in TCR_EL1.
	 */
	tcr_compute_pa_size x10, #TCR_IPS_SHIFT, x5, x6
#ifdef CONFIG_ARM64_HW_AFDBM
	/*
	 * Enable hardware update of the Access Flags bit.
	 * Hardware dirty bit management is enabled later,
	 * via capabilities.
	 */
	mrs	x9, ID_AA64MMFR1_EL1
	and	x9, x9, #0xf
	cbz	x9, 1f
	orr	x10, x10, #TCR_HA		// hardware Access flag update
1:
#endif	/* CONFIG_ARM64_HW_AFDBM */
	msr	tcr_el1, x10
	/*
	 * Prepare SCTLR
	 */
	mov_q	x0, INIT_SCTLR_EL1_MMU_ON
	ret					// return to head.S
SYM_FUNC_END(__cpu_setup)
Commit	Line	Data
caab277b	1	/* SPDX-License-Identifier: GPL-2.0-only */
9cce7a43 CM	2	/*
	3	* Based on arch/arm/mm/proc.S
	4	*
	5	* Copyright (C) 2001 Deep Blue Solutions Ltd.
	6	* Copyright (C) 2012 ARM Ltd.
	7	* Author: Catalin Marinas <catalin.marinas@arm.com>
9cce7a43 CM	8	*/
	9
	10	#include <linux/init.h>
	11	#include <linux/linkage.h>
65fddcfc	12	#include <linux/pgtable.h>
9cce7a43 CM	13	#include <asm/assembler.h>
9cce7a43 CM	14	#include <asm/asm-offsets.h>
e51f5f56	15	#include <asm/asm_pointer_auth.h>
9cce7a43	16	#include <asm/hwcap.h>
cabe1c81	17	#include <asm/pgtable-hwdef.h>
104a0c02 AP	18	#include <asm/cpufeature.h>
104a0c02 AP	19	#include <asm/alternative.h>
6982934e	20	#include <asm/smp.h>
3b714d24	21	#include <asm/sysreg.h>
9cce7a43	22
35a86976 CM	23	#ifdef CONFIG_ARM64_64K_PAGES
35a86976 CM	24	#define TCR_TG_FLAGS TCR_TG0_64K \| TCR_TG1_64K
44eaacf1 SP	25	#elif defined(CONFIG_ARM64_16K_PAGES)
	26	#define TCR_TG_FLAGS TCR_TG0_16K \| TCR_TG1_16K
	27	#else /* CONFIG_ARM64_4K_PAGES */
35a86976 CM	28	#define TCR_TG_FLAGS TCR_TG0_4K \| TCR_TG1_4K
	29	#endif
	30
e03e61c3 WD	31	#ifdef CONFIG_RANDOMIZE_BASE
	32	#define TCR_KASLR_FLAGS TCR_NFD1
	33	#else
	34	#define TCR_KASLR_FLAGS 0
	35	#endif
	36
35a86976	37	#define TCR_SMP_FLAGS TCR_SHARED
9cce7a43	38
35a86976 CM	39	/* PTWs cacheable, inner/outer WBWA */
	40	#define TCR_CACHE_FLAGS TCR_IRGN_WBWA \| TCR_ORGN_WBWA
	41
21696c16	42	#ifdef CONFIG_KASAN_SW_TAGS
bfc62c59	43	#define TCR_KASAN_SW_FLAGS TCR_TBI1 \| TCR_TBID1
21696c16	44	#else
bfc62c59 VF	45	#define TCR_KASAN_SW_FLAGS 0
	46	#endif
	47
	48	#ifdef CONFIG_KASAN_HW_TAGS
	49	#define TCR_KASAN_HW_FLAGS SYS_TCR_EL1_TCMA1 \| TCR_TBI1
	50	#else
	51	#define TCR_KASAN_HW_FLAGS 0
21696c16 AK	52	#endif
21696c16 AK	53
0178dc76 CM	54	/*
	55	* Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and
	56	* changed during __cpu_setup to Normal Tagged if the system supports MTE.
	57	*/
95b3f74b CM	58	#define MAIR_EL1_SET \
	59	(MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) \| \
	60	MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) \| \
	61	MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) \| \
	62	MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) \| \
	63	MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) \| \
0178dc76 CM	64	MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT) \| \
0178dc76 CM	65	MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED))
9cce7a43	66
af3cfdbf	67	#ifdef CONFIG_CPU_PM
6732bc65 LP	68	/**
	69	* cpu_do_suspend - save CPU registers context
	70	*
	71	* x0: virtual address of context pointer
6d37d81f ST	72	*
6d37d81f ST	73	* This must be kept in sync with struct cpu_suspend_ctx in <asm/suspend.h>.
6732bc65	74	*/
f4659254	75	SYM_FUNC_START(cpu_do_suspend)
6732bc65 LP	76	mrs x2, tpidr_el0
	77	mrs x3, tpidrro_el0
	78	mrs x4, contextidr_el1
827a108e JPB	79	mrs x5, osdlr_el1
	80	mrs x6, cpacr_el1
	81	mrs x7, tcr_el1
	82	mrs x8, vbar_el1
	83	mrs x9, mdscr_el1
	84	mrs x10, oslsr_el1
	85	mrs x11, sctlr_el1
6d99b689	86	alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
827a108e	87	mrs x12, tpidr_el1
6d99b689	88	alternative_else
827a108e	89	mrs x12, tpidr_el2
6d99b689	90	alternative_endif
827a108e	91	mrs x13, sp_el0
6732bc65	92	stp x2, x3, [x0]
827a108e JPB	93	stp x4, x5, [x0, #16]
	94	stp x6, x7, [x0, #32]
	95	stp x8, x9, [x0, #48]
	96	stp x10, x11, [x0, #64]
	97	stp x12, x13, [x0, #80]
6d37d81f ST	98	/*
	99	* Save x18 as it may be used as a platform register, e.g. by shadow
	100	* call stack.
	101	*/
	102	str x18, [x0, #96]
6732bc65	103	ret
f4659254	104	SYM_FUNC_END(cpu_do_suspend)
6732bc65 LP	105
	106	/**
	107	* cpu_do_resume - restore CPU register context
	108	*
cabe1c81	109	* x0: Address of context pointer
6732bc65	110	*/
439e70e2	111	.pushsection ".idmap.text", "awx"
f4659254	112	SYM_FUNC_START(cpu_do_resume)
6732bc65 LP	113	ldp x2, x3, [x0]
6732bc65 LP	114	ldp x4, x5, [x0, #16]
cabe1c81 JM	115	ldp x6, x8, [x0, #32]
	116	ldp x9, x10, [x0, #48]
	117	ldp x11, x12, [x0, #64]
623b476f	118	ldp x13, x14, [x0, #80]
6d37d81f ST	119	/*
	120	* Restore x18, as it may be used as a platform register, and clear
	121	* the buffer to minimize the risk of exposure when used for shadow
	122	* call stack.
	123	*/
	124	ldr x18, [x0, #96]
	125	str xzr, [x0, #96]
6732bc65 LP	126	msr tpidr_el0, x2
	127	msr tpidrro_el0, x3
	128	msr contextidr_el1, x4
6732bc65	129	msr cpacr_el1, x6
cabe1c81 JM	130
cabe1c81 JM	131	/* Don't change t0sz here, mask those bits when restoring */
827a108e JPB	132	mrs x7, tcr_el1
827a108e JPB	133	bfi x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
cabe1c81	134
6732bc65 LP	135	msr tcr_el1, x8
6732bc65 LP	136	msr vbar_el1, x9
744c6c37 JM	137
	138	/*
	139	* __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
	140	* debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
0fbeb318	141	* exception. Mask them until local_daif_restore() in cpu_suspend()
744c6c37 JM	142	* resets them.
744c6c37 JM	143	*/
0fbeb318	144	disable_daif
6732bc65	145	msr mdscr_el1, x10
744c6c37	146
cabe1c81	147	msr sctlr_el1, x12
6d99b689	148	alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
623b476f	149	msr tpidr_el1, x13
6d99b689 JM	150	alternative_else
	151	msr tpidr_el2, x13
	152	alternative_endif
623b476f	153	msr sp_el0, x14
6732bc65 LP	154	/*
	155	* Restore oslsr_el1 by writing oslar_el1
	156	*/
827a108e	157	msr osdlr_el1, x5
6732bc65 LP	158	ubfx x11, x11, #1, #1
6732bc65 LP	159	msr oslar_el1, x11
f436b2ac	160	reset_pmuserenr_el0 x0 // Disable PMU access from EL0
87a1f063	161	reset_amuserenr_el0 x0 // Disable AMU access from EL0
68ddbf09 JM	162
	163	alternative_if ARM64_HAS_RAS_EXTN
	164	msr_s SYS_DISR_EL1, xzr
	165	alternative_else_nop_endif
	166
d0055da5	167	ptrauth_keys_install_kernel_nosync x14, x1, x2, x3
6732bc65 LP	168	isb
6732bc65 LP	169	ret
f4659254	170	SYM_FUNC_END(cpu_do_resume)
b6113038	171	.popsection
6732bc65 LP	172	#endif
6732bc65 LP	173
439e70e2	174	.pushsection ".idmap.text", "awx"
f992b4df WD	175
f992b4df WD	176	.macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
833be850	177	adrp \tmp1, reserved_pg_dir
fa0465fc	178	phys_to_ttbr \tmp2, \tmp1
c812026c	179	offset_ttbr1 \tmp2, \tmp1
f992b4df WD	180	msr ttbr1_el1, \tmp2
	181	isb
	182	tlbi vmalle1
	183	dsb nsh
	184	isb
	185	.endm
	186
50e1881d	187	/*
5ffdfaed	188	* void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1)
50e1881d MR	189	*
	190	* This is the low-level counterpart to cpu_replace_ttbr1, and should not be
	191	* called by anything else. It can only be executed from a TTBR0 mapping.
	192	*/
f4659254	193	SYM_FUNC_START(idmap_cpu_replace_ttbr1)
0fbeb318	194	save_and_disable_daif flags=x2
50e1881d	195
f992b4df	196	__idmap_cpu_set_reserved_ttbr1 x1, x3
50e1881d	197
c812026c	198	offset_ttbr1 x0, x3
5ffdfaed	199	msr ttbr1_el1, x0
50e1881d MR	200	isb
50e1881d MR	201
0fbeb318	202	restore_daif x2
50e1881d MR	203
50e1881d MR	204	ret
f4659254	205	SYM_FUNC_END(idmap_cpu_replace_ttbr1)
50e1881d MR	206	.popsection
50e1881d MR	207
f992b4df	208	#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
439e70e2	209	.pushsection ".idmap.text", "awx"
f992b4df WD	210
	211	.macro __idmap_kpti_get_pgtable_ent, type
	212	dc cvac, cur_\()\type\()p // Ensure any existing dirty
	213	dmb sy // lines are written back before
	214	ldr \type, [cur_\()\type\()p] // loading the entry
2ce77f6d WD	215	tbz \type, #0, skip_\()\type // Skip invalid and
2ce77f6d WD	216	tbnz \type, #11, skip_\()\type // non-global entries
f992b4df WD	217	.endm
	218
	219	.macro __idmap_kpti_put_pgtable_ent_ng, type
	220	orr \type, \type, #PTE_NG // Same bit for blocks and pages
71c8fc0c WD	221	str \type, [cur_\()\type\()p] // Update the entry and ensure
	222	dmb sy // that it is visible to all
	223	dc civac, cur_\()\type\()p // CPUs.
f992b4df WD	224	.endm
	225
	226	/*
	227	* void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
	228	*
	229	* Called exactly once from stop_machine context by each CPU found during boot.
	230	*/
	231	__idmap_kpti_flag:
	232	.long 1
f4659254	233	SYM_FUNC_START(idmap_kpti_install_ng_mappings)
f992b4df WD	234	cpu .req w0
	235	num_cpus .req w1
	236	swapper_pa .req x2
	237	swapper_ttb .req x3
	238	flag_ptr .req x4
	239	cur_pgdp .req x5
	240	end_pgdp .req x6
	241	pgd .req x7
	242	cur_pudp .req x8
	243	end_pudp .req x9
	244	pud .req x10
	245	cur_pmdp .req x11
	246	end_pmdp .req x12
	247	pmd .req x13
	248	cur_ptep .req x14
	249	end_ptep .req x15
	250	pte .req x16
	251
	252	mrs swapper_ttb, ttbr1_el1
e842dfb5	253	restore_ttbr1 swapper_ttb
f992b4df WD	254	adr flag_ptr, __idmap_kpti_flag
	255
	256	cbnz cpu, __idmap_kpti_secondary
	257
	258	/* We're the boot CPU. Wait for the others to catch up */
	259	sevl
	260	1: wfe
e3ec6582 ST	261	ldaxr w17, [flag_ptr]
	262	eor w17, w17, num_cpus
	263	cbnz w17, 1b
f992b4df WD	264
	265	/* We need to walk swapper, so turn off the MMU. */
	266	pre_disable_mmu_workaround
e3ec6582 ST	267	mrs x17, sctlr_el1
	268	bic x17, x17, #SCTLR_ELx_M
	269	msr sctlr_el1, x17
f992b4df WD	270	isb
	271
	272	/* Everybody is enjoying the idmap, so we can rewrite swapper. */
	273	/* PGD */
	274	mov cur_pgdp, swapper_pa
	275	add end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
	276	do_pgd: __idmap_kpti_get_pgtable_ent pgd
	277	tbnz pgd, #1, walk_puds
f992b4df	278	next_pgd:
2ce77f6d WD	279	__idmap_kpti_put_pgtable_ent_ng pgd
2ce77f6d WD	280	skip_pgd:
f992b4df WD	281	add cur_pgdp, cur_pgdp, #8
	282	cmp cur_pgdp, end_pgdp
	283	b.ne do_pgd
	284
	285	/* Publish the updated tables and nuke all the TLBs */
	286	dsb sy
	287	tlbi vmalle1is
	288	dsb ish
	289	isb
	290
	291	/* We're done: fire up the MMU again */
e3ec6582 ST	292	mrs x17, sctlr_el1
	293	orr x17, x17, #SCTLR_ELx_M
	294	msr sctlr_el1, x17
f992b4df WD	295	isb
f992b4df WD	296
f32c7a8e MR	297	/*
	298	* Invalidate the local I-cache so that any instructions fetched
	299	* speculatively from the PoC are discarded, since they may have
	300	* been dynamically patched at the PoU.
	301	*/
	302	ic iallu
	303	dsb nsh
	304	isb
	305
f992b4df WD	306	/* Set the flag to zero to indicate that we're all done */
	307	str wzr, [flag_ptr]
	308	ret
	309
	310	/* PUD */
	311	walk_puds:
	312	.if CONFIG_PGTABLE_LEVELS > 3
	313	pte_to_phys cur_pudp, pgd
	314	add end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
	315	do_pud: __idmap_kpti_get_pgtable_ent pud
	316	tbnz pud, #1, walk_pmds
f992b4df	317	next_pud:
2ce77f6d WD	318	__idmap_kpti_put_pgtable_ent_ng pud
2ce77f6d WD	319	skip_pud:
f992b4df WD	320	add cur_pudp, cur_pudp, 8
	321	cmp cur_pudp, end_pudp
	322	b.ne do_pud
	323	b next_pgd
	324	.else /* CONFIG_PGTABLE_LEVELS <= 3 */
	325	mov pud, pgd
	326	b walk_pmds
	327	next_pud:
	328	b next_pgd
	329	.endif
	330
	331	/* PMD */
	332	walk_pmds:
	333	.if CONFIG_PGTABLE_LEVELS > 2
	334	pte_to_phys cur_pmdp, pud
	335	add end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
	336	do_pmd: __idmap_kpti_get_pgtable_ent pmd
	337	tbnz pmd, #1, walk_ptes
f992b4df	338	next_pmd:
2ce77f6d WD	339	__idmap_kpti_put_pgtable_ent_ng pmd
2ce77f6d WD	340	skip_pmd:
f992b4df WD	341	add cur_pmdp, cur_pmdp, #8
	342	cmp cur_pmdp, end_pmdp
	343	b.ne do_pmd
	344	b next_pud
	345	.else /* CONFIG_PGTABLE_LEVELS <= 2 */
	346	mov pmd, pud
	347	b walk_ptes
	348	next_pmd:
	349	b next_pud
	350	.endif
	351
	352	/* PTE */
	353	walk_ptes:
	354	pte_to_phys cur_ptep, pmd
	355	add end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
	356	do_pte: __idmap_kpti_get_pgtable_ent pte
	357	__idmap_kpti_put_pgtable_ent_ng pte
2ce77f6d	358	skip_pte:
f992b4df WD	359	add cur_ptep, cur_ptep, #8
	360	cmp cur_ptep, end_ptep
	361	b.ne do_pte
	362	b next_pmd
	363
e3ec6582 ST	364	.unreq cpu
	365	.unreq num_cpus
	366	.unreq swapper_pa
	367	.unreq cur_pgdp
	368	.unreq end_pgdp
	369	.unreq pgd
	370	.unreq cur_pudp
	371	.unreq end_pudp
	372	.unreq pud
	373	.unreq cur_pmdp
	374	.unreq end_pmdp
	375	.unreq pmd
	376	.unreq cur_ptep
	377	.unreq end_ptep
	378	.unreq pte
	379
f992b4df WD	380	/* Secondary CPUs end up here */
	381	__idmap_kpti_secondary:
	382	/* Uninstall swapper before surgery begins */
e3ec6582	383	__idmap_cpu_set_reserved_ttbr1 x16, x17
f992b4df WD	384
f992b4df WD	385	/* Increment the flag to let the boot CPU we're ready */
e3ec6582 ST	386	1: ldxr w16, [flag_ptr]
	387	add w16, w16, #1
	388	stxr w17, w16, [flag_ptr]
f992b4df WD	389	cbnz w17, 1b
	390
	391	/* Wait for the boot CPU to finish messing around with swapper */
	392	sevl
	393	1: wfe
e3ec6582 ST	394	ldxr w16, [flag_ptr]
e3ec6582 ST	395	cbnz w16, 1b
f992b4df WD	396
f992b4df WD	397	/* All done, act like nothing happened */
e3ec6582	398	offset_ttbr1 swapper_ttb, x16
f992b4df WD	399	msr ttbr1_el1, swapper_ttb
	400	isb
	401	ret
	402
f992b4df WD	403	.unreq swapper_ttb
f992b4df WD	404	.unreq flag_ptr
f4659254	405	SYM_FUNC_END(idmap_kpti_install_ng_mappings)
f992b4df WD	406	.popsection
	407	#endif
	408
9cce7a43 CM	409	/*
	410	* __cpu_setup
	411	*
df355101 ADK	412	* Initialise the processor for turning the MMU on.
df355101 ADK	413	*
df355101 ADK	414	* Output:
df355101 ADK	415	* Return in x0 the value of the SCTLR_EL1 register.
9cce7a43	416	*/
439e70e2	417	.pushsection ".idmap.text", "awx"
f4659254	418	SYM_FUNC_START(__cpu_setup)
fa7aae8a WD	419	tlbi vmalle1 // Invalidate local TLB
fa7aae8a WD	420	dsb nsh
9cce7a43	421
df355101 ADK	422	mov x1, #3 << 20
	423	msr cpacr_el1, x1 // Enable FP/ASIMD
	424	mov x1, #1 << 12 // Reset mdscr_el1 and disable
	425	msr mdscr_el1, x1 // access to the DCC from EL0
2ce39ad1 WD	426	isb // Unmask debug exceptions now,
2ce39ad1 WD	427	enable_dbg // since this is per-cpu
df355101	428	reset_pmuserenr_el0 x1 // Disable PMU access from EL0
44ca0e00	429	reset_amuserenr_el0 x1 // Disable AMU access from EL0
87a1f063	430
9cce7a43	431	/*
95b3f74b	432	* Memory region attributes
9cce7a43	433	*/
95b3f74b	434	mov_q x5, MAIR_EL1_SET
3b714d24	435	#ifdef CONFIG_ARM64_MTE
bfc62c59 VF	436	mte_tcr .req x20
	437
	438	mov mte_tcr, #0
	439
3b714d24 VF	440	/*
	441	* Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported
	442	* (ID_AA64PFR1_EL1[11:8] > 1).
	443	*/
	444	mrs x10, ID_AA64PFR1_EL1
	445	ubfx x10, x10, #ID_AA64PFR1_MTE_SHIFT, #4
	446	cmp x10, #ID_AA64PFR1_MTE
	447	b.lt 1f
	448
	449	/* Normal Tagged memory type at the corresponding MAIR index */
	450	mov x10, #MAIR_ATTR_NORMAL_TAGGED
	451	bfi x5, x10, #(8 * MT_NORMAL_TAGGED), #8
	452
	453	/* initialize GCR_EL1: all non-zero tags excluded by default */
	454	mov x10, #(SYS_GCR_EL1_RRND \| SYS_GCR_EL1_EXCL_MASK)
	455	msr_s SYS_GCR_EL1, x10
	456
	457	/* clear any pending tag check faults in TFSR_EL1 /
	458	msr_s SYS_TFSR_EL1, xzr
	459	msr_s SYS_TFSRE0_EL1, xzr
bfc62c59 VF	460
	461	/* set the TCR_EL1 bits */
	462	mov_q mte_tcr, TCR_KASAN_HW_FLAGS
3b714d24 VF	463	1:
3b714d24 VF	464	#endif
9cce7a43	465	msr mair_el1, x5
9cce7a43 CM	466	/*
	467	* Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
	468	* both user and kernel.
	469	*/
dc374b47	470	mov_q x10, TCR_TxSZ(VA_BITS) \| TCR_CACHE_FLAGS \| TCR_SMP_FLAGS \| \
e03e61c3	471	TCR_TG_FLAGS \| TCR_KASLR_FLAGS \| TCR_ASID16 \| \
bfc62c59 VF	472	TCR_TBI0 \| TCR_A1 \| TCR_KASAN_SW_FLAGS
	473	#ifdef CONFIG_ARM64_MTE
	474	orr x10, x10, mte_tcr
	475	.unreq mte_tcr
	476	#endif
3e32131a	477	tcr_clear_errata_bits x10, x9, x5
67e7fdfc	478
b6d00d47	479	#ifdef CONFIG_ARM64_VA_BITS_52
2c624fe6	480	ldr_l x9, vabits_actual
67e7fdfc SC	481	sub x9, xzr, x9
67e7fdfc SC	482	add x9, x9, #64
b6d00d47	483	tcr_set_t1sz x10, x9
67e7fdfc SC	484	#else
	485	ldr_l x9, idmap_t0sz
	486	#endif
	487	tcr_set_t0sz x10, x9
dd006da2	488
87366d8c	489	/*
787fd1d0	490	* Set the IPS bits in TCR_EL1.
87366d8c	491	*/
787fd1d0	492	tcr_compute_pa_size x10, #TCR_IPS_SHIFT, x5, x6
2f4b829c CM	493	#ifdef CONFIG_ARM64_HW_AFDBM
2f4b829c CM	494	/*
05abb595 SP	495	* Enable hardware update of the Access Flags bit.
	496	* Hardware dirty bit management is enabled later,
	497	* via capabilities.
2f4b829c CM	498	*/
	499	mrs x9, ID_AA64MMFR1_EL1
	500	and x9, x9, #0xf
05abb595 SP	501	cbz x9, 1f
	502	orr x10, x10, #TCR_HA // hardware Access flag update
	503	1:
2f4b829c	504	#endif /* CONFIG_ARM64_HW_AFDBM */
9cce7a43	505	msr tcr_el1, x10
df355101 ADK	506	/*
	507	* Prepare SCTLR
	508	*/
2ffac9e3	509	mov_q x0, INIT_SCTLR_EL1_MMU_ON
9cce7a43	510	ret // return to head.S
f4659254	511	SYM_FUNC_END(__cpu_setup)