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Commit | Line | Data |
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5f97f7f9 HS |
1 | /* |
2 | * Atomic operations that C can't guarantee us. Useful for | |
3 | * resource counting etc. | |
4 | * | |
5 | * But use these as seldom as possible since they are slower than | |
6 | * regular operations. | |
7 | * | |
8 | * Copyright (C) 2004-2006 Atmel Corporation | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | #ifndef __ASM_AVR32_ATOMIC_H | |
15 | #define __ASM_AVR32_ATOMIC_H | |
16 | ||
ea435467 | 17 | #include <linux/types.h> |
ae473946 | 18 | #include <asm/cmpxchg.h> |
5f97f7f9 | 19 | |
5f97f7f9 HS |
20 | #define ATOMIC_INIT(i) { (i) } |
21 | ||
62e8a325 PZ |
22 | #define atomic_read(v) READ_ONCE((v)->counter) |
23 | #define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i)) | |
5f97f7f9 | 24 | |
d325209b PZ |
25 | #define ATOMIC_OP_RETURN(op, asm_op, asm_con) \ |
26 | static inline int __atomic_##op##_return(int i, atomic_t *v) \ | |
27 | { \ | |
28 | int result; \ | |
29 | \ | |
30 | asm volatile( \ | |
31 | "/* atomic_" #op "_return */\n" \ | |
32 | "1: ssrf 5\n" \ | |
33 | " ld.w %0, %2\n" \ | |
34 | " " #asm_op " %0, %3\n" \ | |
35 | " stcond %1, %0\n" \ | |
36 | " brne 1b" \ | |
37 | : "=&r" (result), "=o" (v->counter) \ | |
38 | : "m" (v->counter), #asm_con (i) \ | |
39 | : "cc"); \ | |
40 | \ | |
41 | return result; \ | |
42 | } | |
43 | ||
1a6eafac PZ |
44 | #define ATOMIC_FETCH_OP(op, asm_op, asm_con) \ |
45 | static inline int __atomic_fetch_##op(int i, atomic_t *v) \ | |
46 | { \ | |
47 | int result, val; \ | |
48 | \ | |
49 | asm volatile( \ | |
50 | "/* atomic_fetch_" #op " */\n" \ | |
51 | "1: ssrf 5\n" \ | |
52 | " ld.w %0, %3\n" \ | |
53 | " mov %1, %0\n" \ | |
54 | " " #asm_op " %1, %4\n" \ | |
55 | " stcond %2, %1\n" \ | |
56 | " brne 1b" \ | |
57 | : "=&r" (result), "=&r" (val), "=o" (v->counter) \ | |
58 | : "m" (v->counter), #asm_con (i) \ | |
59 | : "cc"); \ | |
60 | \ | |
61 | return result; \ | |
62 | } | |
63 | ||
d325209b PZ |
64 | ATOMIC_OP_RETURN(sub, sub, rKs21) |
65 | ATOMIC_OP_RETURN(add, add, r) | |
1a6eafac PZ |
66 | ATOMIC_FETCH_OP (sub, sub, rKs21) |
67 | ATOMIC_FETCH_OP (add, add, r) | |
68 | ||
1a6eafac | 69 | #define ATOMIC_OPS(op, asm_op) \ |
f8a570e2 PZ |
70 | ATOMIC_OP_RETURN(op, asm_op, r) \ |
71 | static inline void atomic_##op(int i, atomic_t *v) \ | |
72 | { \ | |
73 | (void)__atomic_##op##_return(i, v); \ | |
1a6eafac PZ |
74 | } \ |
75 | ATOMIC_FETCH_OP(op, asm_op, r) \ | |
76 | static inline int atomic_fetch_##op(int i, atomic_t *v) \ | |
77 | { \ | |
78 | return __atomic_fetch_##op(i, v); \ | |
f8a570e2 PZ |
79 | } |
80 | ||
1a6eafac PZ |
81 | ATOMIC_OPS(and, and) |
82 | ATOMIC_OPS(or, or) | |
83 | ATOMIC_OPS(xor, eor) | |
f8a570e2 | 84 | |
1a6eafac PZ |
85 | #undef ATOMIC_OPS |
86 | #undef ATOMIC_FETCH_OP | |
d325209b PZ |
87 | #undef ATOMIC_OP_RETURN |
88 | ||
5f97f7f9 | 89 | /* |
d325209b PZ |
90 | * Probably found the reason why we want to use sub with the signed 21-bit |
91 | * limit, it uses one less register than the add instruction that can add up to | |
92 | * 32-bit values. | |
5f97f7f9 | 93 | * |
d325209b PZ |
94 | * Both instructions are 32-bit, to use a 16-bit instruction the immediate is |
95 | * very small; 4 bit. | |
96 | * | |
97 | * sub 32-bit, type IV, takes a register and subtracts a 21-bit immediate. | |
98 | * add 32-bit, type II, adds two register values together. | |
5f97f7f9 | 99 | */ |
d325209b PZ |
100 | #define IS_21BIT_CONST(i) \ |
101 | (__builtin_constant_p(i) && ((i) >= -1048575) && ((i) <= 1048576)) | |
5f97f7f9 HS |
102 | |
103 | /* | |
104 | * atomic_add_return - add integer to atomic variable | |
105 | * @i: integer value to add | |
106 | * @v: pointer of type atomic_t | |
107 | * | |
108 | * Atomically adds @i to @v. Returns the resulting value. | |
109 | */ | |
110 | static inline int atomic_add_return(int i, atomic_t *v) | |
111 | { | |
d325209b PZ |
112 | if (IS_21BIT_CONST(i)) |
113 | return __atomic_sub_return(-i, v); | |
5f97f7f9 | 114 | |
d325209b | 115 | return __atomic_add_return(i, v); |
5f97f7f9 HS |
116 | } |
117 | ||
1a6eafac PZ |
118 | static inline int atomic_fetch_add(int i, atomic_t *v) |
119 | { | |
120 | if (IS_21BIT_CONST(i)) | |
121 | return __atomic_fetch_sub(-i, v); | |
122 | ||
123 | return __atomic_fetch_add(i, v); | |
124 | } | |
125 | ||
5f97f7f9 | 126 | /* |
d325209b PZ |
127 | * atomic_sub_return - subtract the atomic variable |
128 | * @i: integer value to subtract | |
5f97f7f9 | 129 | * @v: pointer of type atomic_t |
5f97f7f9 | 130 | * |
d325209b PZ |
131 | * Atomically subtracts @i from @v. Returns the resulting value. |
132 | */ | |
133 | static inline int atomic_sub_return(int i, atomic_t *v) | |
5f97f7f9 | 134 | { |
d325209b PZ |
135 | if (IS_21BIT_CONST(i)) |
136 | return __atomic_sub_return(i, v); | |
5f97f7f9 | 137 | |
d325209b | 138 | return __atomic_add_return(-i, v); |
5f97f7f9 HS |
139 | } |
140 | ||
1a6eafac PZ |
141 | static inline int atomic_fetch_sub(int i, atomic_t *v) |
142 | { | |
143 | if (IS_21BIT_CONST(i)) | |
144 | return __atomic_fetch_sub(i, v); | |
145 | ||
146 | return __atomic_fetch_add(-i, v); | |
147 | } | |
148 | ||
5f97f7f9 | 149 | /* |
f24219b4 | 150 | * __atomic_add_unless - add unless the number is a given value |
5f97f7f9 HS |
151 | * @v: pointer of type atomic_t |
152 | * @a: the amount to add to v... | |
153 | * @u: ...unless v is equal to u. | |
154 | * | |
f24219b4 AS |
155 | * Atomically adds @a to @v, so long as it was not @u. |
156 | * Returns the old value of @v. | |
5f97f7f9 | 157 | */ |
f24219b4 | 158 | static inline int __atomic_add_unless(atomic_t *v, int a, int u) |
5f97f7f9 | 159 | { |
f24219b4 | 160 | int tmp, old = atomic_read(v); |
5f97f7f9 | 161 | |
d325209b PZ |
162 | if (IS_21BIT_CONST(a)) { |
163 | asm volatile( | |
164 | "/* __atomic_sub_unless */\n" | |
165 | "1: ssrf 5\n" | |
166 | " ld.w %0, %2\n" | |
167 | " cp.w %0, %4\n" | |
168 | " breq 1f\n" | |
169 | " sub %0, %3\n" | |
170 | " stcond %1, %0\n" | |
171 | " brne 1b\n" | |
172 | "1:" | |
173 | : "=&r"(tmp), "=o"(v->counter) | |
174 | : "m"(v->counter), "rKs21"(-a), "rKs21"(u) | |
175 | : "cc", "memory"); | |
176 | } else { | |
5f97f7f9 | 177 | asm volatile( |
f24219b4 | 178 | "/* __atomic_add_unless */\n" |
5f97f7f9 | 179 | "1: ssrf 5\n" |
f24219b4 AS |
180 | " ld.w %0, %2\n" |
181 | " cp.w %0, %4\n" | |
5f97f7f9 | 182 | " breq 1f\n" |
f24219b4 AS |
183 | " add %0, %3\n" |
184 | " stcond %1, %0\n" | |
5f97f7f9 | 185 | " brne 1b\n" |
5f97f7f9 | 186 | "1:" |
f24219b4 AS |
187 | : "=&r"(tmp), "=o"(v->counter) |
188 | : "m"(v->counter), "r"(a), "ir"(u) | |
5f97f7f9 HS |
189 | : "cc", "memory"); |
190 | } | |
191 | ||
f24219b4 | 192 | return old; |
5f97f7f9 HS |
193 | } |
194 | ||
d325209b PZ |
195 | #undef IS_21BIT_CONST |
196 | ||
5f97f7f9 HS |
197 | /* |
198 | * atomic_sub_if_positive - conditionally subtract integer from atomic variable | |
199 | * @i: integer value to subtract | |
200 | * @v: pointer of type atomic_t | |
201 | * | |
202 | * Atomically test @v and subtract @i if @v is greater or equal than @i. | |
203 | * The function returns the old value of @v minus @i. | |
204 | */ | |
205 | static inline int atomic_sub_if_positive(int i, atomic_t *v) | |
206 | { | |
207 | int result; | |
208 | ||
209 | asm volatile( | |
210 | "/* atomic_sub_if_positive */\n" | |
211 | "1: ssrf 5\n" | |
212 | " ld.w %0, %2\n" | |
213 | " sub %0, %3\n" | |
214 | " brlt 1f\n" | |
215 | " stcond %1, %0\n" | |
216 | " brne 1b\n" | |
217 | "1:" | |
218 | : "=&r"(result), "=o"(v->counter) | |
219 | : "m"(v->counter), "ir"(i) | |
220 | : "cc", "memory"); | |
221 | ||
222 | return result; | |
223 | } | |
224 | ||
225 | #define atomic_xchg(v, new) (xchg(&((v)->counter), new)) | |
a4022b0d | 226 | #define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n))) |
5f97f7f9 HS |
227 | |
228 | #define atomic_sub(i, v) (void)atomic_sub_return(i, v) | |
229 | #define atomic_add(i, v) (void)atomic_add_return(i, v) | |
230 | #define atomic_dec(v) atomic_sub(1, (v)) | |
231 | #define atomic_inc(v) atomic_add(1, (v)) | |
232 | ||
233 | #define atomic_dec_return(v) atomic_sub_return(1, v) | |
234 | #define atomic_inc_return(v) atomic_add_return(1, v) | |
235 | ||
236 | #define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0) | |
237 | #define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0) | |
238 | #define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0) | |
239 | #define atomic_add_negative(i, v) (atomic_add_return(i, v) < 0) | |
240 | ||
5f97f7f9 HS |
241 | #define atomic_dec_if_positive(v) atomic_sub_if_positive(1, v) |
242 | ||
5f97f7f9 | 243 | #endif /* __ASM_AVR32_ATOMIC_H */ |