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Commit | Line | Data |
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5f97f7f9 | 1 | /* |
8dfe8f29 | 2 | * AVR32 OCD Interface and register definitions |
5f97f7f9 | 3 | * |
8dfe8f29 | 4 | * Copyright (C) 2004-2007 Atmel Corporation |
5f97f7f9 HS |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #ifndef __ASM_AVR32_OCD_H | |
11 | #define __ASM_AVR32_OCD_H | |
12 | ||
8dfe8f29 HS |
13 | /* OCD Register offsets. Abbreviations used below: |
14 | * | |
15 | * BP Breakpoint | |
16 | * Comm Communication | |
17 | * DT Data Trace | |
18 | * PC Program Counter | |
19 | * PID Process ID | |
20 | * R/W Read/Write | |
21 | * WP Watchpoint | |
22 | */ | |
23 | #define OCD_DID 0x0000 /* Device ID */ | |
24 | #define OCD_DC 0x0008 /* Development Control */ | |
25 | #define OCD_DS 0x0010 /* Development Status */ | |
26 | #define OCD_RWCS 0x001c /* R/W Access Control */ | |
27 | #define OCD_RWA 0x0024 /* R/W Access Address */ | |
28 | #define OCD_RWD 0x0028 /* R/W Access Data */ | |
29 | #define OCD_WT 0x002c /* Watchpoint Trigger */ | |
30 | #define OCD_DTC 0x0034 /* Data Trace Control */ | |
31 | #define OCD_DTSA0 0x0038 /* DT Start Addr Channel 0 */ | |
32 | #define OCD_DTSA1 0x003c /* DT Start Addr Channel 1 */ | |
33 | #define OCD_DTEA0 0x0048 /* DT End Addr Channel 0 */ | |
34 | #define OCD_DTEA1 0x004c /* DT End Addr Channel 1 */ | |
35 | #define OCD_BWC0A 0x0058 /* PC BP/WP Control 0A */ | |
36 | #define OCD_BWC0B 0x005c /* PC BP/WP Control 0B */ | |
37 | #define OCD_BWC1A 0x0060 /* PC BP/WP Control 1A */ | |
38 | #define OCD_BWC1B 0x0064 /* PC BP/WP Control 1B */ | |
39 | #define OCD_BWC2A 0x0068 /* PC BP/WP Control 2A */ | |
40 | #define OCD_BWC2B 0x006c /* PC BP/WP Control 2B */ | |
41 | #define OCD_BWC3A 0x0070 /* Data BP/WP Control 3A */ | |
42 | #define OCD_BWC3B 0x0074 /* Data BP/WP Control 3B */ | |
43 | #define OCD_BWA0A 0x0078 /* PC BP/WP Address 0A */ | |
44 | #define OCD_BWA0B 0x007c /* PC BP/WP Address 0B */ | |
45 | #define OCD_BWA1A 0x0080 /* PC BP/WP Address 1A */ | |
46 | #define OCD_BWA1B 0x0084 /* PC BP/WP Address 1B */ | |
47 | #define OCD_BWA2A 0x0088 /* PC BP/WP Address 2A */ | |
48 | #define OCD_BWA2B 0x008c /* PC BP/WP Address 2B */ | |
49 | #define OCD_BWA3A 0x0090 /* Data BP/WP Address 3A */ | |
50 | #define OCD_BWA3B 0x0094 /* Data BP/WP Address 3B */ | |
51 | #define OCD_NXCFG 0x0100 /* Nexus Configuration */ | |
52 | #define OCD_DINST 0x0104 /* Debug Instruction */ | |
53 | #define OCD_DPC 0x0108 /* Debug Program Counter */ | |
54 | #define OCD_CPUCM 0x010c /* CPU Control Mask */ | |
55 | #define OCD_DCCPU 0x0110 /* Debug Comm CPU */ | |
56 | #define OCD_DCEMU 0x0114 /* Debug Comm Emulator */ | |
57 | #define OCD_DCSR 0x0118 /* Debug Comm Status */ | |
58 | #define OCD_PID 0x011c /* Ownership Trace PID */ | |
59 | #define OCD_EPC0 0x0120 /* Event Pair Control 0 */ | |
60 | #define OCD_EPC1 0x0124 /* Event Pair Control 1 */ | |
61 | #define OCD_EPC2 0x0128 /* Event Pair Control 2 */ | |
62 | #define OCD_EPC3 0x012c /* Event Pair Control 3 */ | |
63 | #define OCD_AXC 0x0130 /* AUX port Control */ | |
64 | ||
65 | /* Bits in DID */ | |
66 | #define OCD_DID_MID_START 1 | |
67 | #define OCD_DID_MID_SIZE 11 | |
68 | #define OCD_DID_PN_START 12 | |
69 | #define OCD_DID_PN_SIZE 16 | |
70 | #define OCD_DID_RN_START 28 | |
71 | #define OCD_DID_RN_SIZE 4 | |
72 | ||
73 | /* Bits in DC */ | |
74 | #define OCD_DC_TM_START 0 | |
75 | #define OCD_DC_TM_SIZE 2 | |
76 | #define OCD_DC_EIC_START 3 | |
77 | #define OCD_DC_EIC_SIZE 2 | |
78 | #define OCD_DC_OVC_START 5 | |
79 | #define OCD_DC_OVC_SIZE 3 | |
80 | #define OCD_DC_SS_BIT 8 | |
81 | #define OCD_DC_DBR_BIT 12 | |
82 | #define OCD_DC_DBE_BIT 13 | |
83 | #define OCD_DC_EOS_START 20 | |
84 | #define OCD_DC_EOS_SIZE 2 | |
85 | #define OCD_DC_SQA_BIT 22 | |
86 | #define OCD_DC_IRP_BIT 23 | |
87 | #define OCD_DC_IFM_BIT 24 | |
88 | #define OCD_DC_TOZ_BIT 25 | |
89 | #define OCD_DC_TSR_BIT 26 | |
90 | #define OCD_DC_RID_BIT 27 | |
91 | #define OCD_DC_ORP_BIT 28 | |
92 | #define OCD_DC_MM_BIT 29 | |
93 | #define OCD_DC_RES_BIT 30 | |
94 | #define OCD_DC_ABORT_BIT 31 | |
95 | ||
96 | /* Bits in DS */ | |
97 | #define OCD_DS_SSS_BIT 0 | |
98 | #define OCD_DS_SWB_BIT 1 | |
99 | #define OCD_DS_HWB_BIT 2 | |
100 | #define OCD_DS_HWE_BIT 3 | |
101 | #define OCD_DS_STP_BIT 4 | |
102 | #define OCD_DS_DBS_BIT 5 | |
103 | #define OCD_DS_BP_START 8 | |
104 | #define OCD_DS_BP_SIZE 8 | |
105 | #define OCD_DS_INC_BIT 24 | |
106 | #define OCD_DS_BOZ_BIT 25 | |
107 | #define OCD_DS_DBA_BIT 26 | |
108 | #define OCD_DS_EXB_BIT 27 | |
109 | #define OCD_DS_NTBF_BIT 28 | |
110 | ||
111 | /* Bits in RWCS */ | |
112 | #define OCD_RWCS_DV_BIT 0 | |
113 | #define OCD_RWCS_ERR_BIT 1 | |
114 | #define OCD_RWCS_CNT_START 2 | |
115 | #define OCD_RWCS_CNT_SIZE 14 | |
116 | #define OCD_RWCS_CRC_BIT 19 | |
117 | #define OCD_RWCS_NTBC_START 20 | |
118 | #define OCD_RWCS_NTBC_SIZE 2 | |
119 | #define OCD_RWCS_NTE_BIT 22 | |
120 | #define OCD_RWCS_NTAP_BIT 23 | |
121 | #define OCD_RWCS_WRAPPED_BIT 24 | |
122 | #define OCD_RWCS_CCTRL_START 25 | |
123 | #define OCD_RWCS_CCTRL_SIZE 2 | |
124 | #define OCD_RWCS_SZ_START 27 | |
125 | #define OCD_RWCS_SZ_SIZE 3 | |
126 | #define OCD_RWCS_RW_BIT 30 | |
127 | #define OCD_RWCS_AC_BIT 31 | |
128 | ||
129 | /* Bits in RWA */ | |
130 | #define OCD_RWA_RWA_START 0 | |
131 | #define OCD_RWA_RWA_SIZE 32 | |
132 | ||
133 | /* Bits in RWD */ | |
134 | #define OCD_RWD_RWD_START 0 | |
135 | #define OCD_RWD_RWD_SIZE 32 | |
136 | ||
137 | /* Bits in WT */ | |
138 | #define OCD_WT_DTE_START 20 | |
139 | #define OCD_WT_DTE_SIZE 3 | |
140 | #define OCD_WT_DTS_START 23 | |
141 | #define OCD_WT_DTS_SIZE 3 | |
142 | #define OCD_WT_PTE_START 26 | |
143 | #define OCD_WT_PTE_SIZE 3 | |
144 | #define OCD_WT_PTS_START 29 | |
145 | #define OCD_WT_PTS_SIZE 3 | |
146 | ||
147 | /* Bits in DTC */ | |
148 | #define OCD_DTC_T0WP_BIT 0 | |
149 | #define OCD_DTC_T1WP_BIT 1 | |
150 | #define OCD_DTC_ASID0EN_BIT 2 | |
151 | #define OCD_DTC_ASID0_START 3 | |
152 | #define OCD_DTC_ASID0_SIZE 8 | |
153 | #define OCD_DTC_ASID1EN_BIT 11 | |
154 | #define OCD_DTC_ASID1_START 12 | |
155 | #define OCD_DTC_ASID1_SIZE 8 | |
156 | #define OCD_DTC_RWT1_START 28 | |
157 | #define OCD_DTC_RWT1_SIZE 2 | |
158 | #define OCD_DTC_RWT0_START 30 | |
159 | #define OCD_DTC_RWT0_SIZE 2 | |
160 | ||
161 | /* Bits in DTSA0 */ | |
162 | #define OCD_DTSA0_DTSA_START 0 | |
163 | #define OCD_DTSA0_DTSA_SIZE 32 | |
164 | ||
165 | /* Bits in DTSA1 */ | |
166 | #define OCD_DTSA1_DTSA_START 0 | |
167 | #define OCD_DTSA1_DTSA_SIZE 32 | |
168 | ||
169 | /* Bits in DTEA0 */ | |
170 | #define OCD_DTEA0_DTEA_START 0 | |
171 | #define OCD_DTEA0_DTEA_SIZE 32 | |
172 | ||
173 | /* Bits in DTEA1 */ | |
174 | #define OCD_DTEA1_DTEA_START 0 | |
175 | #define OCD_DTEA1_DTEA_SIZE 32 | |
176 | ||
177 | /* Bits in BWC0A */ | |
178 | #define OCD_BWC0A_ASIDEN_BIT 0 | |
179 | #define OCD_BWC0A_ASID_START 1 | |
180 | #define OCD_BWC0A_ASID_SIZE 8 | |
181 | #define OCD_BWC0A_EOC_BIT 14 | |
182 | #define OCD_BWC0A_AME_BIT 25 | |
183 | #define OCD_BWC0A_BWE_START 30 | |
184 | #define OCD_BWC0A_BWE_SIZE 2 | |
185 | ||
186 | /* Bits in BWC0B */ | |
187 | #define OCD_BWC0B_ASIDEN_BIT 0 | |
188 | #define OCD_BWC0B_ASID_START 1 | |
189 | #define OCD_BWC0B_ASID_SIZE 8 | |
190 | #define OCD_BWC0B_EOC_BIT 14 | |
191 | #define OCD_BWC0B_AME_BIT 25 | |
192 | #define OCD_BWC0B_BWE_START 30 | |
193 | #define OCD_BWC0B_BWE_SIZE 2 | |
194 | ||
195 | /* Bits in BWC1A */ | |
196 | #define OCD_BWC1A_ASIDEN_BIT 0 | |
197 | #define OCD_BWC1A_ASID_START 1 | |
198 | #define OCD_BWC1A_ASID_SIZE 8 | |
199 | #define OCD_BWC1A_EOC_BIT 14 | |
200 | #define OCD_BWC1A_AME_BIT 25 | |
201 | #define OCD_BWC1A_BWE_START 30 | |
202 | #define OCD_BWC1A_BWE_SIZE 2 | |
203 | ||
204 | /* Bits in BWC1B */ | |
205 | #define OCD_BWC1B_ASIDEN_BIT 0 | |
206 | #define OCD_BWC1B_ASID_START 1 | |
207 | #define OCD_BWC1B_ASID_SIZE 8 | |
208 | #define OCD_BWC1B_EOC_BIT 14 | |
209 | #define OCD_BWC1B_AME_BIT 25 | |
210 | #define OCD_BWC1B_BWE_START 30 | |
211 | #define OCD_BWC1B_BWE_SIZE 2 | |
212 | ||
213 | /* Bits in BWC2A */ | |
214 | #define OCD_BWC2A_ASIDEN_BIT 0 | |
215 | #define OCD_BWC2A_ASID_START 1 | |
216 | #define OCD_BWC2A_ASID_SIZE 8 | |
217 | #define OCD_BWC2A_EOC_BIT 14 | |
218 | #define OCD_BWC2A_AMB_START 20 | |
219 | #define OCD_BWC2A_AMB_SIZE 5 | |
220 | #define OCD_BWC2A_AME_BIT 25 | |
221 | #define OCD_BWC2A_BWE_START 30 | |
222 | #define OCD_BWC2A_BWE_SIZE 2 | |
223 | ||
224 | /* Bits in BWC2B */ | |
225 | #define OCD_BWC2B_ASIDEN_BIT 0 | |
226 | #define OCD_BWC2B_ASID_START 1 | |
227 | #define OCD_BWC2B_ASID_SIZE 8 | |
228 | #define OCD_BWC2B_EOC_BIT 14 | |
229 | #define OCD_BWC2B_AME_BIT 25 | |
230 | #define OCD_BWC2B_BWE_START 30 | |
231 | #define OCD_BWC2B_BWE_SIZE 2 | |
232 | ||
233 | /* Bits in BWC3A */ | |
234 | #define OCD_BWC3A_ASIDEN_BIT 0 | |
235 | #define OCD_BWC3A_ASID_START 1 | |
236 | #define OCD_BWC3A_ASID_SIZE 8 | |
237 | #define OCD_BWC3A_SIZE_START 9 | |
238 | #define OCD_BWC3A_SIZE_SIZE 3 | |
239 | #define OCD_BWC3A_EOC_BIT 14 | |
240 | #define OCD_BWC3A_BWO_START 16 | |
241 | #define OCD_BWC3A_BWO_SIZE 2 | |
242 | #define OCD_BWC3A_BME_START 20 | |
243 | #define OCD_BWC3A_BME_SIZE 4 | |
244 | #define OCD_BWC3A_BRW_START 28 | |
245 | #define OCD_BWC3A_BRW_SIZE 2 | |
246 | #define OCD_BWC3A_BWE_START 30 | |
247 | #define OCD_BWC3A_BWE_SIZE 2 | |
248 | ||
249 | /* Bits in BWC3B */ | |
250 | #define OCD_BWC3B_ASIDEN_BIT 0 | |
251 | #define OCD_BWC3B_ASID_START 1 | |
252 | #define OCD_BWC3B_ASID_SIZE 8 | |
253 | #define OCD_BWC3B_SIZE_START 9 | |
254 | #define OCD_BWC3B_SIZE_SIZE 3 | |
255 | #define OCD_BWC3B_EOC_BIT 14 | |
256 | #define OCD_BWC3B_BWO_START 16 | |
257 | #define OCD_BWC3B_BWO_SIZE 2 | |
258 | #define OCD_BWC3B_BME_START 20 | |
259 | #define OCD_BWC3B_BME_SIZE 4 | |
260 | #define OCD_BWC3B_BRW_START 28 | |
261 | #define OCD_BWC3B_BRW_SIZE 2 | |
262 | #define OCD_BWC3B_BWE_START 30 | |
263 | #define OCD_BWC3B_BWE_SIZE 2 | |
264 | ||
265 | /* Bits in BWA0A */ | |
266 | #define OCD_BWA0A_BWA_START 0 | |
267 | #define OCD_BWA0A_BWA_SIZE 32 | |
268 | ||
269 | /* Bits in BWA0B */ | |
270 | #define OCD_BWA0B_BWA_START 0 | |
271 | #define OCD_BWA0B_BWA_SIZE 32 | |
272 | ||
273 | /* Bits in BWA1A */ | |
274 | #define OCD_BWA1A_BWA_START 0 | |
275 | #define OCD_BWA1A_BWA_SIZE 32 | |
276 | ||
277 | /* Bits in BWA1B */ | |
278 | #define OCD_BWA1B_BWA_START 0 | |
279 | #define OCD_BWA1B_BWA_SIZE 32 | |
280 | ||
281 | /* Bits in BWA2A */ | |
282 | #define OCD_BWA2A_BWA_START 0 | |
283 | #define OCD_BWA2A_BWA_SIZE 32 | |
284 | ||
285 | /* Bits in BWA2B */ | |
286 | #define OCD_BWA2B_BWA_START 0 | |
287 | #define OCD_BWA2B_BWA_SIZE 32 | |
288 | ||
289 | /* Bits in BWA3A */ | |
290 | #define OCD_BWA3A_BWA_START 0 | |
291 | #define OCD_BWA3A_BWA_SIZE 32 | |
292 | ||
293 | /* Bits in BWA3B */ | |
294 | #define OCD_BWA3B_BWA_START 0 | |
295 | #define OCD_BWA3B_BWA_SIZE 32 | |
296 | ||
297 | /* Bits in NXCFG */ | |
298 | #define OCD_NXCFG_NXARCH_START 0 | |
299 | #define OCD_NXCFG_NXARCH_SIZE 4 | |
300 | #define OCD_NXCFG_NXOCD_START 4 | |
301 | #define OCD_NXCFG_NXOCD_SIZE 4 | |
302 | #define OCD_NXCFG_NXPCB_START 8 | |
303 | #define OCD_NXCFG_NXPCB_SIZE 4 | |
304 | #define OCD_NXCFG_NXDB_START 12 | |
305 | #define OCD_NXCFG_NXDB_SIZE 4 | |
306 | #define OCD_NXCFG_MXMSEO_BIT 16 | |
307 | #define OCD_NXCFG_NXMDO_START 17 | |
308 | #define OCD_NXCFG_NXMDO_SIZE 4 | |
309 | #define OCD_NXCFG_NXPT_BIT 21 | |
310 | #define OCD_NXCFG_NXOT_BIT 22 | |
311 | #define OCD_NXCFG_NXDWT_BIT 23 | |
312 | #define OCD_NXCFG_NXDRT_BIT 24 | |
313 | #define OCD_NXCFG_NXDTC_START 25 | |
314 | #define OCD_NXCFG_NXDTC_SIZE 3 | |
315 | #define OCD_NXCFG_NXDMA_BIT 28 | |
316 | ||
317 | /* Bits in DINST */ | |
318 | #define OCD_DINST_DINST_START 0 | |
319 | #define OCD_DINST_DINST_SIZE 32 | |
320 | ||
321 | /* Bits in CPUCM */ | |
322 | #define OCD_CPUCM_BEM_BIT 1 | |
323 | #define OCD_CPUCM_FEM_BIT 2 | |
324 | #define OCD_CPUCM_REM_BIT 3 | |
325 | #define OCD_CPUCM_IBEM_BIT 4 | |
326 | #define OCD_CPUCM_IEEM_BIT 5 | |
327 | ||
328 | /* Bits in DCCPU */ | |
329 | #define OCD_DCCPU_DATA_START 0 | |
330 | #define OCD_DCCPU_DATA_SIZE 32 | |
331 | ||
332 | /* Bits in DCEMU */ | |
333 | #define OCD_DCEMU_DATA_START 0 | |
334 | #define OCD_DCEMU_DATA_SIZE 32 | |
335 | ||
336 | /* Bits in DCSR */ | |
337 | #define OCD_DCSR_CPUD_BIT 0 | |
338 | #define OCD_DCSR_EMUD_BIT 1 | |
339 | ||
340 | /* Bits in PID */ | |
341 | #define OCD_PID_PROCESS_START 0 | |
342 | #define OCD_PID_PROCESS_SIZE 32 | |
343 | ||
344 | /* Bits in EPC0 */ | |
345 | #define OCD_EPC0_RNG_START 0 | |
346 | #define OCD_EPC0_RNG_SIZE 2 | |
347 | #define OCD_EPC0_CE_BIT 4 | |
348 | #define OCD_EPC0_ECNT_START 16 | |
349 | #define OCD_EPC0_ECNT_SIZE 16 | |
350 | ||
351 | /* Bits in EPC1 */ | |
352 | #define OCD_EPC1_RNG_START 0 | |
353 | #define OCD_EPC1_RNG_SIZE 2 | |
354 | #define OCD_EPC1_ATB_BIT 5 | |
355 | #define OCD_EPC1_AM_BIT 6 | |
356 | ||
357 | /* Bits in EPC2 */ | |
358 | #define OCD_EPC2_RNG_START 0 | |
359 | #define OCD_EPC2_RNG_SIZE 2 | |
360 | #define OCD_EPC2_DB_START 2 | |
361 | #define OCD_EPC2_DB_SIZE 2 | |
362 | ||
363 | /* Bits in EPC3 */ | |
364 | #define OCD_EPC3_RNG_START 0 | |
365 | #define OCD_EPC3_RNG_SIZE 2 | |
366 | #define OCD_EPC3_DWE_BIT 2 | |
367 | ||
368 | /* Bits in AXC */ | |
369 | #define OCD_AXC_DIV_START 0 | |
370 | #define OCD_AXC_DIV_SIZE 4 | |
371 | #define OCD_AXC_AXE_BIT 8 | |
372 | #define OCD_AXC_AXS_BIT 9 | |
373 | #define OCD_AXC_DDR_BIT 10 | |
374 | #define OCD_AXC_LS_BIT 11 | |
375 | #define OCD_AXC_REX_BIT 12 | |
376 | #define OCD_AXC_REXTEN_BIT 13 | |
377 | ||
378 | /* Constants for DC:EIC */ | |
379 | #define OCD_EIC_PROGRAM_AND_DATA_TRACE 0 | |
380 | #define OCD_EIC_BREAKPOINT 1 | |
381 | #define OCD_EIC_NOP 2 | |
382 | ||
383 | /* Constants for DC:OVC */ | |
384 | #define OCD_OVC_OVERRUN 0 | |
385 | #define OCD_OVC_DELAY_CPU_BTM 1 | |
386 | #define OCD_OVC_DELAY_CPU_DTM 2 | |
387 | #define OCD_OVC_DELAY_CPU_BTM_DTM 3 | |
388 | ||
389 | /* Constants for DC:EOS */ | |
390 | #define OCD_EOS_NOP 0 | |
391 | #define OCD_EOS_DEBUG_MODE 1 | |
392 | #define OCD_EOS_BREAKPOINT_WATCHPOINT 2 | |
393 | #define OCD_EOS_THQ 3 | |
394 | ||
395 | /* Constants for RWCS:NTBC */ | |
396 | #define OCD_NTBC_OVERWRITE 0 | |
397 | #define OCD_NTBC_DISABLE 1 | |
398 | #define OCD_NTBC_BREAKPOINT 2 | |
399 | ||
400 | /* Constants for RWCS:CCTRL */ | |
401 | #define OCD_CCTRL_AUTO 0 | |
402 | #define OCD_CCTRL_CACHED 1 | |
403 | #define OCD_CCTRL_UNCACHED 2 | |
404 | ||
405 | /* Constants for RWCS:SZ */ | |
406 | #define OCD_SZ_BYTE 0 | |
407 | #define OCD_SZ_HALFWORD 1 | |
408 | #define OCD_SZ_WORD 2 | |
409 | ||
410 | /* Constants for WT:PTS */ | |
411 | #define OCD_PTS_DISABLED 0 | |
412 | #define OCD_PTS_PROGRAM_0B 1 | |
413 | #define OCD_PTS_PROGRAM_1A 2 | |
414 | #define OCD_PTS_PROGRAM_1B 3 | |
415 | #define OCD_PTS_PROGRAM_2A 4 | |
416 | #define OCD_PTS_PROGRAM_2B 5 | |
417 | #define OCD_PTS_DATA_3A 6 | |
418 | #define OCD_PTS_DATA_3B 7 | |
419 | ||
420 | /* Constants for DTC:RWT1 */ | |
421 | #define OCD_RWT1_NO_TRACE 0 | |
422 | #define OCD_RWT1_DATA_READ 1 | |
423 | #define OCD_RWT1_DATA_WRITE 2 | |
424 | #define OCD_RWT1_DATA_READ_WRITE 3 | |
425 | ||
426 | /* Constants for DTC:RWT0 */ | |
427 | #define OCD_RWT0_NO_TRACE 0 | |
428 | #define OCD_RWT0_DATA_READ 1 | |
429 | #define OCD_RWT0_DATA_WRITE 2 | |
430 | #define OCD_RWT0_DATA_READ_WRITE 3 | |
431 | ||
432 | /* Constants for BWC0A:BWE */ | |
433 | #define OCD_BWE_DISABLED 0 | |
434 | #define OCD_BWE_BREAKPOINT_ENABLED 1 | |
435 | #define OCD_BWE_WATCHPOINT_ENABLED 3 | |
436 | ||
437 | /* Constants for BWC0B:BWE */ | |
438 | #define OCD_BWE_DISABLED 0 | |
439 | #define OCD_BWE_BREAKPOINT_ENABLED 1 | |
440 | #define OCD_BWE_WATCHPOINT_ENABLED 3 | |
441 | ||
442 | /* Constants for BWC1A:BWE */ | |
443 | #define OCD_BWE_DISABLED 0 | |
444 | #define OCD_BWE_BREAKPOINT_ENABLED 1 | |
445 | #define OCD_BWE_WATCHPOINT_ENABLED 3 | |
446 | ||
447 | /* Constants for BWC1B:BWE */ | |
448 | #define OCD_BWE_DISABLED 0 | |
449 | #define OCD_BWE_BREAKPOINT_ENABLED 1 | |
450 | #define OCD_BWE_WATCHPOINT_ENABLED 3 | |
451 | ||
452 | /* Constants for BWC2A:BWE */ | |
453 | #define OCD_BWE_DISABLED 0 | |
454 | #define OCD_BWE_BREAKPOINT_ENABLED 1 | |
455 | #define OCD_BWE_WATCHPOINT_ENABLED 3 | |
456 | ||
457 | /* Constants for BWC2B:BWE */ | |
458 | #define OCD_BWE_DISABLED 0 | |
459 | #define OCD_BWE_BREAKPOINT_ENABLED 1 | |
460 | #define OCD_BWE_WATCHPOINT_ENABLED 3 | |
461 | ||
462 | /* Constants for BWC3A:SIZE */ | |
463 | #define OCD_SIZE_BYTE_ACCESS 4 | |
464 | #define OCD_SIZE_HALFWORD_ACCESS 5 | |
465 | #define OCD_SIZE_WORD_ACCESS 6 | |
466 | #define OCD_SIZE_DOUBLE_WORD_ACCESS 7 | |
467 | ||
468 | /* Constants for BWC3A:BRW */ | |
469 | #define OCD_BRW_READ_BREAK 0 | |
470 | #define OCD_BRW_WRITE_BREAK 1 | |
471 | #define OCD_BRW_ANY_ACCES_BREAK 2 | |
472 | ||
473 | /* Constants for BWC3A:BWE */ | |
474 | #define OCD_BWE_DISABLED 0 | |
475 | #define OCD_BWE_BREAKPOINT_ENABLED 1 | |
476 | #define OCD_BWE_WATCHPOINT_ENABLED 3 | |
477 | ||
478 | /* Constants for BWC3B:SIZE */ | |
479 | #define OCD_SIZE_BYTE_ACCESS 4 | |
480 | #define OCD_SIZE_HALFWORD_ACCESS 5 | |
481 | #define OCD_SIZE_WORD_ACCESS 6 | |
482 | #define OCD_SIZE_DOUBLE_WORD_ACCESS 7 | |
483 | ||
484 | /* Constants for BWC3B:BRW */ | |
485 | #define OCD_BRW_READ_BREAK 0 | |
486 | #define OCD_BRW_WRITE_BREAK 1 | |
487 | #define OCD_BRW_ANY_ACCES_BREAK 2 | |
488 | ||
489 | /* Constants for BWC3B:BWE */ | |
490 | #define OCD_BWE_DISABLED 0 | |
491 | #define OCD_BWE_BREAKPOINT_ENABLED 1 | |
492 | #define OCD_BWE_WATCHPOINT_ENABLED 3 | |
493 | ||
494 | /* Constants for EPC0:RNG */ | |
495 | #define OCD_RNG_DISABLED 0 | |
496 | #define OCD_RNG_EXCLUSIVE 1 | |
497 | #define OCD_RNG_INCLUSIVE 2 | |
498 | ||
499 | /* Constants for EPC1:RNG */ | |
500 | #define OCD_RNG_DISABLED 0 | |
501 | #define OCD_RNG_EXCLUSIVE 1 | |
502 | #define OCD_RNG_INCLUSIVE 2 | |
503 | ||
504 | /* Constants for EPC2:RNG */ | |
505 | #define OCD_RNG_DISABLED 0 | |
506 | #define OCD_RNG_EXCLUSIVE 1 | |
507 | #define OCD_RNG_INCLUSIVE 2 | |
508 | ||
509 | /* Constants for EPC2:DB */ | |
510 | #define OCD_DB_DISABLED 0 | |
511 | #define OCD_DB_CHAINED_B 1 | |
512 | #define OCD_DB_CHAINED_A 2 | |
513 | #define OCD_DB_AHAINED_A_AND_B 3 | |
514 | ||
515 | /* Constants for EPC3:RNG */ | |
516 | #define OCD_RNG_DISABLED 0 | |
517 | #define OCD_RNG_EXCLUSIVE 1 | |
518 | #define OCD_RNG_INCLUSIVE 2 | |
519 | ||
520 | #ifndef __ASSEMBLER__ | |
521 | ||
522 | /* Register access macros */ | |
523 | static inline unsigned long __ocd_read(unsigned int reg) | |
524 | { | |
525 | return __builtin_mfdr(reg); | |
526 | } | |
527 | ||
528 | static inline void __ocd_write(unsigned int reg, unsigned long value) | |
529 | { | |
530 | __builtin_mtdr(reg, value); | |
531 | } | |
532 | ||
533 | #define ocd_read(reg) __ocd_read(OCD_##reg) | |
534 | #define ocd_write(reg, value) __ocd_write(OCD_##reg, value) | |
535 | ||
13b54a50 HS |
536 | struct task_struct; |
537 | ||
538 | void ocd_enable(struct task_struct *child); | |
539 | void ocd_disable(struct task_struct *child); | |
540 | ||
8dfe8f29 | 541 | #endif /* !__ASSEMBLER__ */ |
5f97f7f9 HS |
542 | |
543 | #endif /* __ASM_AVR32_OCD_H */ |