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5f97f7f9 HS |
1 | /* |
2 | * Copyright (C) 2005-2006 Atmel Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | #include <linux/clk.h> | |
9 | #include <linux/init.h> | |
10 | #include <linux/platform_device.h> | |
11 | ||
12 | #include <asm/io.h> | |
13 | ||
c3e2a79c | 14 | #include <asm/arch/at32ap7000.h> |
5f97f7f9 HS |
15 | #include <asm/arch/board.h> |
16 | #include <asm/arch/portmux.h> | |
17 | #include <asm/arch/sm.h> | |
18 | ||
19 | #include "clock.h" | |
20 | #include "pio.h" | |
21 | #include "sm.h" | |
22 | ||
23 | #define PBMEM(base) \ | |
24 | { \ | |
25 | .start = base, \ | |
26 | .end = base + 0x3ff, \ | |
27 | .flags = IORESOURCE_MEM, \ | |
28 | } | |
29 | #define IRQ(num) \ | |
30 | { \ | |
31 | .start = num, \ | |
32 | .end = num, \ | |
33 | .flags = IORESOURCE_IRQ, \ | |
34 | } | |
35 | #define NAMED_IRQ(num, _name) \ | |
36 | { \ | |
37 | .start = num, \ | |
38 | .end = num, \ | |
39 | .name = _name, \ | |
40 | .flags = IORESOURCE_IRQ, \ | |
41 | } | |
42 | ||
43 | #define DEFINE_DEV(_name, _id) \ | |
44 | static struct platform_device _name##_id##_device = { \ | |
45 | .name = #_name, \ | |
46 | .id = _id, \ | |
47 | .resource = _name##_id##_resource, \ | |
48 | .num_resources = ARRAY_SIZE(_name##_id##_resource), \ | |
49 | } | |
50 | #define DEFINE_DEV_DATA(_name, _id) \ | |
51 | static struct platform_device _name##_id##_device = { \ | |
52 | .name = #_name, \ | |
53 | .id = _id, \ | |
54 | .dev = { \ | |
55 | .platform_data = &_name##_id##_data, \ | |
56 | }, \ | |
57 | .resource = _name##_id##_resource, \ | |
58 | .num_resources = ARRAY_SIZE(_name##_id##_resource), \ | |
59 | } | |
60 | ||
c3e2a79c HS |
61 | #define select_peripheral(pin, periph, flags) \ |
62 | at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags) | |
63 | ||
5f97f7f9 HS |
64 | #define DEV_CLK(_name, devname, bus, _index) \ |
65 | static struct clk devname##_##_name = { \ | |
66 | .name = #_name, \ | |
67 | .dev = &devname##_device.dev, \ | |
68 | .parent = &bus##_clk, \ | |
69 | .mode = bus##_clk_mode, \ | |
70 | .get_rate = bus##_clk_get_rate, \ | |
71 | .index = _index, \ | |
72 | } | |
73 | ||
5f97f7f9 HS |
74 | unsigned long at32ap7000_osc_rates[3] = { |
75 | [0] = 32768, | |
76 | /* FIXME: these are ATSTK1002-specific */ | |
77 | [1] = 20000000, | |
78 | [2] = 12000000, | |
79 | }; | |
80 | ||
81 | static unsigned long osc_get_rate(struct clk *clk) | |
82 | { | |
83 | return at32ap7000_osc_rates[clk->index]; | |
84 | } | |
85 | ||
86 | static unsigned long pll_get_rate(struct clk *clk, unsigned long control) | |
87 | { | |
88 | unsigned long div, mul, rate; | |
89 | ||
90 | if (!(control & SM_BIT(PLLEN))) | |
91 | return 0; | |
92 | ||
93 | div = SM_BFEXT(PLLDIV, control) + 1; | |
94 | mul = SM_BFEXT(PLLMUL, control) + 1; | |
95 | ||
96 | rate = clk->parent->get_rate(clk->parent); | |
97 | rate = (rate + div / 2) / div; | |
98 | rate *= mul; | |
99 | ||
100 | return rate; | |
101 | } | |
102 | ||
103 | static unsigned long pll0_get_rate(struct clk *clk) | |
104 | { | |
105 | u32 control; | |
106 | ||
107 | control = sm_readl(&system_manager, PM_PLL0); | |
108 | ||
109 | return pll_get_rate(clk, control); | |
110 | } | |
111 | ||
112 | static unsigned long pll1_get_rate(struct clk *clk) | |
113 | { | |
114 | u32 control; | |
115 | ||
116 | control = sm_readl(&system_manager, PM_PLL1); | |
117 | ||
118 | return pll_get_rate(clk, control); | |
119 | } | |
120 | ||
121 | /* | |
122 | * The AT32AP7000 has five primary clock sources: One 32kHz | |
123 | * oscillator, two crystal oscillators and two PLLs. | |
124 | */ | |
125 | static struct clk osc32k = { | |
126 | .name = "osc32k", | |
127 | .get_rate = osc_get_rate, | |
128 | .users = 1, | |
129 | .index = 0, | |
130 | }; | |
131 | static struct clk osc0 = { | |
132 | .name = "osc0", | |
133 | .get_rate = osc_get_rate, | |
134 | .users = 1, | |
135 | .index = 1, | |
136 | }; | |
137 | static struct clk osc1 = { | |
138 | .name = "osc1", | |
139 | .get_rate = osc_get_rate, | |
140 | .index = 2, | |
141 | }; | |
142 | static struct clk pll0 = { | |
143 | .name = "pll0", | |
144 | .get_rate = pll0_get_rate, | |
145 | .parent = &osc0, | |
146 | }; | |
147 | static struct clk pll1 = { | |
148 | .name = "pll1", | |
149 | .get_rate = pll1_get_rate, | |
150 | .parent = &osc0, | |
151 | }; | |
152 | ||
153 | /* | |
154 | * The main clock can be either osc0 or pll0. The boot loader may | |
155 | * have chosen one for us, so we don't really know which one until we | |
156 | * have a look at the SM. | |
157 | */ | |
158 | static struct clk *main_clock; | |
159 | ||
160 | /* | |
161 | * Synchronous clocks are generated from the main clock. The clocks | |
162 | * must satisfy the constraint | |
163 | * fCPU >= fHSB >= fPB | |
164 | * i.e. each clock must not be faster than its parent. | |
165 | */ | |
166 | static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift) | |
167 | { | |
168 | return main_clock->get_rate(main_clock) >> shift; | |
169 | }; | |
170 | ||
171 | static void cpu_clk_mode(struct clk *clk, int enabled) | |
172 | { | |
173 | struct at32_sm *sm = &system_manager; | |
174 | unsigned long flags; | |
175 | u32 mask; | |
176 | ||
177 | spin_lock_irqsave(&sm->lock, flags); | |
178 | mask = sm_readl(sm, PM_CPU_MASK); | |
179 | if (enabled) | |
180 | mask |= 1 << clk->index; | |
181 | else | |
182 | mask &= ~(1 << clk->index); | |
183 | sm_writel(sm, PM_CPU_MASK, mask); | |
184 | spin_unlock_irqrestore(&sm->lock, flags); | |
185 | } | |
186 | ||
187 | static unsigned long cpu_clk_get_rate(struct clk *clk) | |
188 | { | |
189 | unsigned long cksel, shift = 0; | |
190 | ||
191 | cksel = sm_readl(&system_manager, PM_CKSEL); | |
192 | if (cksel & SM_BIT(CPUDIV)) | |
193 | shift = SM_BFEXT(CPUSEL, cksel) + 1; | |
194 | ||
195 | return bus_clk_get_rate(clk, shift); | |
196 | } | |
197 | ||
198 | static void hsb_clk_mode(struct clk *clk, int enabled) | |
199 | { | |
200 | struct at32_sm *sm = &system_manager; | |
201 | unsigned long flags; | |
202 | u32 mask; | |
203 | ||
204 | spin_lock_irqsave(&sm->lock, flags); | |
205 | mask = sm_readl(sm, PM_HSB_MASK); | |
206 | if (enabled) | |
207 | mask |= 1 << clk->index; | |
208 | else | |
209 | mask &= ~(1 << clk->index); | |
210 | sm_writel(sm, PM_HSB_MASK, mask); | |
211 | spin_unlock_irqrestore(&sm->lock, flags); | |
212 | } | |
213 | ||
214 | static unsigned long hsb_clk_get_rate(struct clk *clk) | |
215 | { | |
216 | unsigned long cksel, shift = 0; | |
217 | ||
218 | cksel = sm_readl(&system_manager, PM_CKSEL); | |
219 | if (cksel & SM_BIT(HSBDIV)) | |
220 | shift = SM_BFEXT(HSBSEL, cksel) + 1; | |
221 | ||
222 | return bus_clk_get_rate(clk, shift); | |
223 | } | |
224 | ||
225 | static void pba_clk_mode(struct clk *clk, int enabled) | |
226 | { | |
227 | struct at32_sm *sm = &system_manager; | |
228 | unsigned long flags; | |
229 | u32 mask; | |
230 | ||
231 | spin_lock_irqsave(&sm->lock, flags); | |
232 | mask = sm_readl(sm, PM_PBA_MASK); | |
233 | if (enabled) | |
234 | mask |= 1 << clk->index; | |
235 | else | |
236 | mask &= ~(1 << clk->index); | |
237 | sm_writel(sm, PM_PBA_MASK, mask); | |
238 | spin_unlock_irqrestore(&sm->lock, flags); | |
239 | } | |
240 | ||
241 | static unsigned long pba_clk_get_rate(struct clk *clk) | |
242 | { | |
243 | unsigned long cksel, shift = 0; | |
244 | ||
245 | cksel = sm_readl(&system_manager, PM_CKSEL); | |
246 | if (cksel & SM_BIT(PBADIV)) | |
247 | shift = SM_BFEXT(PBASEL, cksel) + 1; | |
248 | ||
249 | return bus_clk_get_rate(clk, shift); | |
250 | } | |
251 | ||
252 | static void pbb_clk_mode(struct clk *clk, int enabled) | |
253 | { | |
254 | struct at32_sm *sm = &system_manager; | |
255 | unsigned long flags; | |
256 | u32 mask; | |
257 | ||
258 | spin_lock_irqsave(&sm->lock, flags); | |
259 | mask = sm_readl(sm, PM_PBB_MASK); | |
260 | if (enabled) | |
261 | mask |= 1 << clk->index; | |
262 | else | |
263 | mask &= ~(1 << clk->index); | |
264 | sm_writel(sm, PM_PBB_MASK, mask); | |
265 | spin_unlock_irqrestore(&sm->lock, flags); | |
266 | } | |
267 | ||
268 | static unsigned long pbb_clk_get_rate(struct clk *clk) | |
269 | { | |
270 | unsigned long cksel, shift = 0; | |
271 | ||
272 | cksel = sm_readl(&system_manager, PM_CKSEL); | |
273 | if (cksel & SM_BIT(PBBDIV)) | |
274 | shift = SM_BFEXT(PBBSEL, cksel) + 1; | |
275 | ||
276 | return bus_clk_get_rate(clk, shift); | |
277 | } | |
278 | ||
279 | static struct clk cpu_clk = { | |
280 | .name = "cpu", | |
281 | .get_rate = cpu_clk_get_rate, | |
282 | .users = 1, | |
283 | }; | |
284 | static struct clk hsb_clk = { | |
285 | .name = "hsb", | |
286 | .parent = &cpu_clk, | |
287 | .get_rate = hsb_clk_get_rate, | |
288 | }; | |
289 | static struct clk pba_clk = { | |
290 | .name = "pba", | |
291 | .parent = &hsb_clk, | |
292 | .mode = hsb_clk_mode, | |
293 | .get_rate = pba_clk_get_rate, | |
294 | .index = 1, | |
295 | }; | |
296 | static struct clk pbb_clk = { | |
297 | .name = "pbb", | |
298 | .parent = &hsb_clk, | |
299 | .mode = hsb_clk_mode, | |
300 | .get_rate = pbb_clk_get_rate, | |
301 | .users = 1, | |
302 | .index = 2, | |
303 | }; | |
304 | ||
305 | /* -------------------------------------------------------------------- | |
306 | * Generic Clock operations | |
307 | * -------------------------------------------------------------------- */ | |
308 | ||
309 | static void genclk_mode(struct clk *clk, int enabled) | |
310 | { | |
311 | u32 control; | |
312 | ||
313 | BUG_ON(clk->index > 7); | |
314 | ||
315 | control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index); | |
316 | if (enabled) | |
317 | control |= SM_BIT(CEN); | |
318 | else | |
319 | control &= ~SM_BIT(CEN); | |
320 | sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control); | |
321 | } | |
322 | ||
323 | static unsigned long genclk_get_rate(struct clk *clk) | |
324 | { | |
325 | u32 control; | |
326 | unsigned long div = 1; | |
327 | ||
328 | BUG_ON(clk->index > 7); | |
329 | ||
330 | if (!clk->parent) | |
331 | return 0; | |
332 | ||
333 | control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index); | |
334 | if (control & SM_BIT(DIVEN)) | |
335 | div = 2 * (SM_BFEXT(DIV, control) + 1); | |
336 | ||
337 | return clk->parent->get_rate(clk->parent) / div; | |
338 | } | |
339 | ||
340 | static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply) | |
341 | { | |
342 | u32 control; | |
343 | unsigned long parent_rate, actual_rate, div; | |
344 | ||
345 | BUG_ON(clk->index > 7); | |
346 | ||
347 | if (!clk->parent) | |
348 | return 0; | |
349 | ||
350 | parent_rate = clk->parent->get_rate(clk->parent); | |
351 | control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index); | |
352 | ||
353 | if (rate > 3 * parent_rate / 4) { | |
354 | actual_rate = parent_rate; | |
355 | control &= ~SM_BIT(DIVEN); | |
356 | } else { | |
357 | div = (parent_rate + rate) / (2 * rate) - 1; | |
358 | control = SM_BFINS(DIV, div, control) | SM_BIT(DIVEN); | |
359 | actual_rate = parent_rate / (2 * (div + 1)); | |
360 | } | |
361 | ||
362 | printk("clk %s: new rate %lu (actual rate %lu)\n", | |
363 | clk->name, rate, actual_rate); | |
364 | ||
365 | if (apply) | |
366 | sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, | |
367 | control); | |
368 | ||
369 | return actual_rate; | |
370 | } | |
371 | ||
372 | int genclk_set_parent(struct clk *clk, struct clk *parent) | |
373 | { | |
374 | u32 control; | |
375 | ||
376 | BUG_ON(clk->index > 7); | |
377 | ||
378 | printk("clk %s: new parent %s (was %s)\n", | |
379 | clk->name, parent->name, | |
380 | clk->parent ? clk->parent->name : "(null)"); | |
381 | ||
382 | control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index); | |
383 | ||
384 | if (parent == &osc1 || parent == &pll1) | |
385 | control |= SM_BIT(OSCSEL); | |
386 | else if (parent == &osc0 || parent == &pll0) | |
387 | control &= ~SM_BIT(OSCSEL); | |
388 | else | |
389 | return -EINVAL; | |
390 | ||
391 | if (parent == &pll0 || parent == &pll1) | |
392 | control |= SM_BIT(PLLSEL); | |
393 | else | |
394 | control &= ~SM_BIT(PLLSEL); | |
395 | ||
396 | sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control); | |
397 | clk->parent = parent; | |
398 | ||
399 | return 0; | |
400 | } | |
401 | ||
402 | /* -------------------------------------------------------------------- | |
403 | * System peripherals | |
404 | * -------------------------------------------------------------------- */ | |
405 | static struct resource sm_resource[] = { | |
406 | PBMEM(0xfff00000), | |
407 | NAMED_IRQ(19, "eim"), | |
408 | NAMED_IRQ(20, "pm"), | |
409 | NAMED_IRQ(21, "rtc"), | |
410 | }; | |
411 | struct platform_device at32_sm_device = { | |
412 | .name = "sm", | |
413 | .id = 0, | |
414 | .resource = sm_resource, | |
415 | .num_resources = ARRAY_SIZE(sm_resource), | |
416 | }; | |
417 | DEV_CLK(pclk, at32_sm, pbb, 0); | |
418 | ||
419 | static struct resource intc0_resource[] = { | |
420 | PBMEM(0xfff00400), | |
421 | }; | |
422 | struct platform_device at32_intc0_device = { | |
423 | .name = "intc", | |
424 | .id = 0, | |
425 | .resource = intc0_resource, | |
426 | .num_resources = ARRAY_SIZE(intc0_resource), | |
427 | }; | |
428 | DEV_CLK(pclk, at32_intc0, pbb, 1); | |
429 | ||
430 | static struct clk ebi_clk = { | |
431 | .name = "ebi", | |
432 | .parent = &hsb_clk, | |
433 | .mode = hsb_clk_mode, | |
434 | .get_rate = hsb_clk_get_rate, | |
435 | .users = 1, | |
436 | }; | |
437 | static struct clk hramc_clk = { | |
438 | .name = "hramc", | |
439 | .parent = &hsb_clk, | |
440 | .mode = hsb_clk_mode, | |
441 | .get_rate = hsb_clk_get_rate, | |
442 | .users = 1, | |
443 | }; | |
444 | ||
bc157b75 HS |
445 | static struct resource smc0_resource[] = { |
446 | PBMEM(0xfff03400), | |
447 | }; | |
448 | DEFINE_DEV(smc, 0); | |
449 | DEV_CLK(pclk, smc0, pbb, 13); | |
450 | DEV_CLK(mck, smc0, hsb, 0); | |
451 | ||
5f97f7f9 HS |
452 | static struct platform_device pdc_device = { |
453 | .name = "pdc", | |
454 | .id = 0, | |
455 | }; | |
456 | DEV_CLK(hclk, pdc, hsb, 4); | |
457 | DEV_CLK(pclk, pdc, pba, 16); | |
458 | ||
459 | static struct clk pico_clk = { | |
460 | .name = "pico", | |
461 | .parent = &cpu_clk, | |
462 | .mode = cpu_clk_mode, | |
463 | .get_rate = cpu_clk_get_rate, | |
464 | .users = 1, | |
465 | }; | |
466 | ||
467 | /* -------------------------------------------------------------------- | |
468 | * PIO | |
469 | * -------------------------------------------------------------------- */ | |
470 | ||
471 | static struct resource pio0_resource[] = { | |
472 | PBMEM(0xffe02800), | |
473 | IRQ(13), | |
474 | }; | |
475 | DEFINE_DEV(pio, 0); | |
476 | DEV_CLK(mck, pio0, pba, 10); | |
477 | ||
478 | static struct resource pio1_resource[] = { | |
479 | PBMEM(0xffe02c00), | |
480 | IRQ(14), | |
481 | }; | |
482 | DEFINE_DEV(pio, 1); | |
483 | DEV_CLK(mck, pio1, pba, 11); | |
484 | ||
485 | static struct resource pio2_resource[] = { | |
486 | PBMEM(0xffe03000), | |
487 | IRQ(15), | |
488 | }; | |
489 | DEFINE_DEV(pio, 2); | |
490 | DEV_CLK(mck, pio2, pba, 12); | |
491 | ||
492 | static struct resource pio3_resource[] = { | |
493 | PBMEM(0xffe03400), | |
494 | IRQ(16), | |
495 | }; | |
496 | DEFINE_DEV(pio, 3); | |
497 | DEV_CLK(mck, pio3, pba, 13); | |
498 | ||
7f9f4678 HS |
499 | static struct resource pio4_resource[] = { |
500 | PBMEM(0xffe03800), | |
501 | IRQ(17), | |
502 | }; | |
503 | DEFINE_DEV(pio, 4); | |
504 | DEV_CLK(mck, pio4, pba, 14); | |
505 | ||
5f97f7f9 HS |
506 | void __init at32_add_system_devices(void) |
507 | { | |
6a4e5227 | 508 | system_manager.eim_first_irq = EIM_IRQ_BASE; |
5f97f7f9 HS |
509 | |
510 | platform_device_register(&at32_sm_device); | |
511 | platform_device_register(&at32_intc0_device); | |
bc157b75 | 512 | platform_device_register(&smc0_device); |
5f97f7f9 HS |
513 | platform_device_register(&pdc_device); |
514 | ||
515 | platform_device_register(&pio0_device); | |
516 | platform_device_register(&pio1_device); | |
517 | platform_device_register(&pio2_device); | |
518 | platform_device_register(&pio3_device); | |
7f9f4678 | 519 | platform_device_register(&pio4_device); |
5f97f7f9 HS |
520 | } |
521 | ||
522 | /* -------------------------------------------------------------------- | |
523 | * USART | |
524 | * -------------------------------------------------------------------- */ | |
525 | ||
75d35213 HS |
526 | static struct atmel_uart_data atmel_usart0_data = { |
527 | .use_dma_tx = 1, | |
528 | .use_dma_rx = 1, | |
529 | }; | |
1e8ea802 | 530 | static struct resource atmel_usart0_resource[] = { |
5f97f7f9 | 531 | PBMEM(0xffe00c00), |
a3d912c8 | 532 | IRQ(6), |
5f97f7f9 | 533 | }; |
75d35213 | 534 | DEFINE_DEV_DATA(atmel_usart, 0); |
1e8ea802 | 535 | DEV_CLK(usart, atmel_usart0, pba, 4); |
5f97f7f9 | 536 | |
75d35213 HS |
537 | static struct atmel_uart_data atmel_usart1_data = { |
538 | .use_dma_tx = 1, | |
539 | .use_dma_rx = 1, | |
540 | }; | |
1e8ea802 | 541 | static struct resource atmel_usart1_resource[] = { |
5f97f7f9 HS |
542 | PBMEM(0xffe01000), |
543 | IRQ(7), | |
544 | }; | |
75d35213 | 545 | DEFINE_DEV_DATA(atmel_usart, 1); |
1e8ea802 | 546 | DEV_CLK(usart, atmel_usart1, pba, 4); |
5f97f7f9 | 547 | |
75d35213 HS |
548 | static struct atmel_uart_data atmel_usart2_data = { |
549 | .use_dma_tx = 1, | |
550 | .use_dma_rx = 1, | |
551 | }; | |
1e8ea802 | 552 | static struct resource atmel_usart2_resource[] = { |
5f97f7f9 HS |
553 | PBMEM(0xffe01400), |
554 | IRQ(8), | |
555 | }; | |
75d35213 | 556 | DEFINE_DEV_DATA(atmel_usart, 2); |
1e8ea802 | 557 | DEV_CLK(usart, atmel_usart2, pba, 5); |
5f97f7f9 | 558 | |
75d35213 HS |
559 | static struct atmel_uart_data atmel_usart3_data = { |
560 | .use_dma_tx = 1, | |
561 | .use_dma_rx = 1, | |
562 | }; | |
1e8ea802 | 563 | static struct resource atmel_usart3_resource[] = { |
5f97f7f9 HS |
564 | PBMEM(0xffe01800), |
565 | IRQ(9), | |
566 | }; | |
75d35213 | 567 | DEFINE_DEV_DATA(atmel_usart, 3); |
1e8ea802 | 568 | DEV_CLK(usart, atmel_usart3, pba, 6); |
5f97f7f9 HS |
569 | |
570 | static inline void configure_usart0_pins(void) | |
571 | { | |
c3e2a79c HS |
572 | select_peripheral(PA(8), PERIPH_B, 0); /* RXD */ |
573 | select_peripheral(PA(9), PERIPH_B, 0); /* TXD */ | |
5f97f7f9 HS |
574 | } |
575 | ||
576 | static inline void configure_usart1_pins(void) | |
577 | { | |
c3e2a79c HS |
578 | select_peripheral(PA(17), PERIPH_A, 0); /* RXD */ |
579 | select_peripheral(PA(18), PERIPH_A, 0); /* TXD */ | |
5f97f7f9 HS |
580 | } |
581 | ||
582 | static inline void configure_usart2_pins(void) | |
583 | { | |
c3e2a79c HS |
584 | select_peripheral(PB(26), PERIPH_B, 0); /* RXD */ |
585 | select_peripheral(PB(27), PERIPH_B, 0); /* TXD */ | |
5f97f7f9 HS |
586 | } |
587 | ||
588 | static inline void configure_usart3_pins(void) | |
589 | { | |
c3e2a79c HS |
590 | select_peripheral(PB(18), PERIPH_B, 0); /* RXD */ |
591 | select_peripheral(PB(17), PERIPH_B, 0); /* TXD */ | |
5f97f7f9 HS |
592 | } |
593 | ||
a3d912c8 | 594 | static struct platform_device *__initdata at32_usarts[4]; |
c194588d HS |
595 | |
596 | void __init at32_map_usart(unsigned int hw_id, unsigned int line) | |
5f97f7f9 HS |
597 | { |
598 | struct platform_device *pdev; | |
599 | ||
c194588d | 600 | switch (hw_id) { |
5f97f7f9 | 601 | case 0: |
1e8ea802 | 602 | pdev = &atmel_usart0_device; |
5f97f7f9 HS |
603 | configure_usart0_pins(); |
604 | break; | |
605 | case 1: | |
1e8ea802 | 606 | pdev = &atmel_usart1_device; |
5f97f7f9 HS |
607 | configure_usart1_pins(); |
608 | break; | |
609 | case 2: | |
1e8ea802 | 610 | pdev = &atmel_usart2_device; |
5f97f7f9 HS |
611 | configure_usart2_pins(); |
612 | break; | |
613 | case 3: | |
1e8ea802 | 614 | pdev = &atmel_usart3_device; |
5f97f7f9 HS |
615 | configure_usart3_pins(); |
616 | break; | |
617 | default: | |
c194588d | 618 | return; |
75d35213 HS |
619 | } |
620 | ||
621 | if (PXSEG(pdev->resource[0].start) == P4SEG) { | |
622 | /* Addresses in the P4 segment are permanently mapped 1:1 */ | |
623 | struct atmel_uart_data *data = pdev->dev.platform_data; | |
624 | data->regs = (void __iomem *)pdev->resource[0].start; | |
5f97f7f9 HS |
625 | } |
626 | ||
c194588d HS |
627 | pdev->id = line; |
628 | at32_usarts[line] = pdev; | |
5f97f7f9 HS |
629 | } |
630 | ||
631 | struct platform_device *__init at32_add_device_usart(unsigned int id) | |
632 | { | |
c194588d HS |
633 | platform_device_register(at32_usarts[id]); |
634 | return at32_usarts[id]; | |
5f97f7f9 HS |
635 | } |
636 | ||
73e2798b | 637 | struct platform_device *atmel_default_console_device; |
5f97f7f9 HS |
638 | |
639 | void __init at32_setup_serial_console(unsigned int usart_id) | |
640 | { | |
c194588d | 641 | atmel_default_console_device = at32_usarts[usart_id]; |
5f97f7f9 HS |
642 | } |
643 | ||
644 | /* -------------------------------------------------------------------- | |
645 | * Ethernet | |
646 | * -------------------------------------------------------------------- */ | |
647 | ||
648 | static struct eth_platform_data macb0_data; | |
649 | static struct resource macb0_resource[] = { | |
650 | PBMEM(0xfff01800), | |
651 | IRQ(25), | |
652 | }; | |
653 | DEFINE_DEV_DATA(macb, 0); | |
654 | DEV_CLK(hclk, macb0, hsb, 8); | |
655 | DEV_CLK(pclk, macb0, pbb, 6); | |
656 | ||
cfcb3a89 HS |
657 | static struct eth_platform_data macb1_data; |
658 | static struct resource macb1_resource[] = { | |
659 | PBMEM(0xfff01c00), | |
660 | IRQ(26), | |
661 | }; | |
662 | DEFINE_DEV_DATA(macb, 1); | |
663 | DEV_CLK(hclk, macb1, hsb, 9); | |
664 | DEV_CLK(pclk, macb1, pbb, 7); | |
665 | ||
5f97f7f9 HS |
666 | struct platform_device *__init |
667 | at32_add_device_eth(unsigned int id, struct eth_platform_data *data) | |
668 | { | |
669 | struct platform_device *pdev; | |
670 | ||
671 | switch (id) { | |
672 | case 0: | |
673 | pdev = &macb0_device; | |
674 | ||
c3e2a79c HS |
675 | select_peripheral(PC(3), PERIPH_A, 0); /* TXD0 */ |
676 | select_peripheral(PC(4), PERIPH_A, 0); /* TXD1 */ | |
677 | select_peripheral(PC(7), PERIPH_A, 0); /* TXEN */ | |
678 | select_peripheral(PC(8), PERIPH_A, 0); /* TXCK */ | |
679 | select_peripheral(PC(9), PERIPH_A, 0); /* RXD0 */ | |
680 | select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */ | |
681 | select_peripheral(PC(13), PERIPH_A, 0); /* RXER */ | |
682 | select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */ | |
683 | select_peripheral(PC(16), PERIPH_A, 0); /* MDC */ | |
684 | select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */ | |
5f97f7f9 HS |
685 | |
686 | if (!data->is_rmii) { | |
c3e2a79c HS |
687 | select_peripheral(PC(0), PERIPH_A, 0); /* COL */ |
688 | select_peripheral(PC(1), PERIPH_A, 0); /* CRS */ | |
689 | select_peripheral(PC(2), PERIPH_A, 0); /* TXER */ | |
690 | select_peripheral(PC(5), PERIPH_A, 0); /* TXD2 */ | |
691 | select_peripheral(PC(6), PERIPH_A, 0); /* TXD3 */ | |
692 | select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */ | |
693 | select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */ | |
694 | select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */ | |
695 | select_peripheral(PC(18), PERIPH_A, 0); /* SPD */ | |
5f97f7f9 HS |
696 | } |
697 | break; | |
698 | ||
cfcb3a89 HS |
699 | case 1: |
700 | pdev = &macb1_device; | |
701 | ||
702 | select_peripheral(PD(13), PERIPH_B, 0); /* TXD0 */ | |
703 | select_peripheral(PD(14), PERIPH_B, 0); /* TXD1 */ | |
704 | select_peripheral(PD(11), PERIPH_B, 0); /* TXEN */ | |
705 | select_peripheral(PD(12), PERIPH_B, 0); /* TXCK */ | |
706 | select_peripheral(PD(10), PERIPH_B, 0); /* RXD0 */ | |
707 | select_peripheral(PD(6), PERIPH_B, 0); /* RXD1 */ | |
708 | select_peripheral(PD(5), PERIPH_B, 0); /* RXER */ | |
709 | select_peripheral(PD(4), PERIPH_B, 0); /* RXDV */ | |
710 | select_peripheral(PD(3), PERIPH_B, 0); /* MDC */ | |
711 | select_peripheral(PD(2), PERIPH_B, 0); /* MDIO */ | |
712 | ||
713 | if (!data->is_rmii) { | |
714 | select_peripheral(PC(19), PERIPH_B, 0); /* COL */ | |
715 | select_peripheral(PC(23), PERIPH_B, 0); /* CRS */ | |
716 | select_peripheral(PC(26), PERIPH_B, 0); /* TXER */ | |
717 | select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */ | |
718 | select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */ | |
719 | select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */ | |
720 | select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */ | |
721 | select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */ | |
722 | select_peripheral(PD(15), PERIPH_B, 0); /* SPD */ | |
723 | } | |
724 | break; | |
725 | ||
5f97f7f9 HS |
726 | default: |
727 | return NULL; | |
728 | } | |
729 | ||
730 | memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data)); | |
731 | platform_device_register(pdev); | |
732 | ||
733 | return pdev; | |
734 | } | |
735 | ||
736 | /* -------------------------------------------------------------------- | |
737 | * SPI | |
738 | * -------------------------------------------------------------------- */ | |
3d60ee1b | 739 | static struct resource atmel_spi0_resource[] = { |
5f97f7f9 HS |
740 | PBMEM(0xffe00000), |
741 | IRQ(3), | |
742 | }; | |
3d60ee1b HS |
743 | DEFINE_DEV(atmel_spi, 0); |
744 | DEV_CLK(spi_clk, atmel_spi0, pba, 0); | |
745 | ||
746 | static struct resource atmel_spi1_resource[] = { | |
747 | PBMEM(0xffe00400), | |
748 | IRQ(4), | |
749 | }; | |
750 | DEFINE_DEV(atmel_spi, 1); | |
751 | DEV_CLK(spi_clk, atmel_spi1, pba, 1); | |
5f97f7f9 HS |
752 | |
753 | struct platform_device *__init at32_add_device_spi(unsigned int id) | |
754 | { | |
755 | struct platform_device *pdev; | |
756 | ||
757 | switch (id) { | |
758 | case 0: | |
3d60ee1b | 759 | pdev = &atmel_spi0_device; |
c3e2a79c HS |
760 | select_peripheral(PA(0), PERIPH_A, 0); /* MISO */ |
761 | select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */ | |
762 | select_peripheral(PA(2), PERIPH_A, 0); /* SCK */ | |
3d60ee1b HS |
763 | |
764 | /* NPCS[2:0] */ | |
765 | at32_select_gpio(GPIO_PIN_PA(3), | |
766 | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH); | |
767 | at32_select_gpio(GPIO_PIN_PA(4), | |
768 | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH); | |
769 | at32_select_gpio(GPIO_PIN_PA(5), | |
770 | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH); | |
771 | break; | |
772 | ||
773 | case 1: | |
774 | pdev = &atmel_spi1_device; | |
775 | select_peripheral(PB(0), PERIPH_B, 0); /* MISO */ | |
776 | select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */ | |
777 | select_peripheral(PB(5), PERIPH_B, 0); /* SCK */ | |
778 | ||
779 | /* NPCS[2:0] */ | |
780 | at32_select_gpio(GPIO_PIN_PB(2), | |
781 | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH); | |
782 | at32_select_gpio(GPIO_PIN_PB(3), | |
783 | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH); | |
784 | at32_select_gpio(GPIO_PIN_PB(4), | |
785 | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH); | |
5f97f7f9 HS |
786 | break; |
787 | ||
788 | default: | |
789 | return NULL; | |
790 | } | |
791 | ||
792 | platform_device_register(pdev); | |
793 | return pdev; | |
794 | } | |
795 | ||
796 | /* -------------------------------------------------------------------- | |
797 | * LCDC | |
798 | * -------------------------------------------------------------------- */ | |
799 | static struct lcdc_platform_data lcdc0_data; | |
800 | static struct resource lcdc0_resource[] = { | |
801 | { | |
802 | .start = 0xff000000, | |
803 | .end = 0xff000fff, | |
804 | .flags = IORESOURCE_MEM, | |
805 | }, | |
806 | IRQ(1), | |
807 | }; | |
808 | DEFINE_DEV_DATA(lcdc, 0); | |
809 | DEV_CLK(hclk, lcdc0, hsb, 7); | |
810 | static struct clk lcdc0_pixclk = { | |
811 | .name = "pixclk", | |
812 | .dev = &lcdc0_device.dev, | |
813 | .mode = genclk_mode, | |
814 | .get_rate = genclk_get_rate, | |
815 | .set_rate = genclk_set_rate, | |
816 | .set_parent = genclk_set_parent, | |
817 | .index = 7, | |
818 | }; | |
819 | ||
820 | struct platform_device *__init | |
821 | at32_add_device_lcdc(unsigned int id, struct lcdc_platform_data *data) | |
822 | { | |
823 | struct platform_device *pdev; | |
824 | ||
825 | switch (id) { | |
826 | case 0: | |
827 | pdev = &lcdc0_device; | |
c3e2a79c HS |
828 | select_peripheral(PC(19), PERIPH_A, 0); /* CC */ |
829 | select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */ | |
830 | select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */ | |
831 | select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */ | |
832 | select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */ | |
833 | select_peripheral(PC(24), PERIPH_A, 0); /* MODE */ | |
834 | select_peripheral(PC(25), PERIPH_A, 0); /* PWR */ | |
835 | select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */ | |
836 | select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */ | |
837 | select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */ | |
838 | select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */ | |
839 | select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */ | |
840 | select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */ | |
841 | select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */ | |
842 | select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */ | |
843 | select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */ | |
844 | select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */ | |
845 | select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */ | |
846 | select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */ | |
847 | select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */ | |
848 | select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */ | |
849 | select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */ | |
850 | select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */ | |
851 | select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */ | |
852 | select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */ | |
853 | select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */ | |
854 | select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */ | |
855 | select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */ | |
856 | select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */ | |
857 | select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */ | |
858 | select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */ | |
5f97f7f9 HS |
859 | |
860 | clk_set_parent(&lcdc0_pixclk, &pll0); | |
861 | clk_set_rate(&lcdc0_pixclk, clk_get_rate(&pll0)); | |
862 | break; | |
863 | ||
864 | default: | |
865 | return NULL; | |
866 | } | |
867 | ||
868 | memcpy(pdev->dev.platform_data, data, | |
869 | sizeof(struct lcdc_platform_data)); | |
870 | ||
871 | platform_device_register(pdev); | |
872 | return pdev; | |
873 | } | |
874 | ||
875 | struct clk *at32_clock_list[] = { | |
876 | &osc32k, | |
877 | &osc0, | |
878 | &osc1, | |
879 | &pll0, | |
880 | &pll1, | |
881 | &cpu_clk, | |
882 | &hsb_clk, | |
883 | &pba_clk, | |
884 | &pbb_clk, | |
885 | &at32_sm_pclk, | |
886 | &at32_intc0_pclk, | |
887 | &ebi_clk, | |
888 | &hramc_clk, | |
bc157b75 HS |
889 | &smc0_pclk, |
890 | &smc0_mck, | |
5f97f7f9 HS |
891 | &pdc_hclk, |
892 | &pdc_pclk, | |
893 | &pico_clk, | |
894 | &pio0_mck, | |
895 | &pio1_mck, | |
896 | &pio2_mck, | |
897 | &pio3_mck, | |
7f9f4678 | 898 | &pio4_mck, |
1e8ea802 HS |
899 | &atmel_usart0_usart, |
900 | &atmel_usart1_usart, | |
901 | &atmel_usart2_usart, | |
902 | &atmel_usart3_usart, | |
5f97f7f9 HS |
903 | &macb0_hclk, |
904 | &macb0_pclk, | |
cfcb3a89 HS |
905 | &macb1_hclk, |
906 | &macb1_pclk, | |
3d60ee1b HS |
907 | &atmel_spi0_spi_clk, |
908 | &atmel_spi1_spi_clk, | |
5f97f7f9 HS |
909 | &lcdc0_hclk, |
910 | &lcdc0_pixclk, | |
911 | }; | |
912 | unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list); | |
913 | ||
914 | void __init at32_portmux_init(void) | |
915 | { | |
916 | at32_init_pio(&pio0_device); | |
917 | at32_init_pio(&pio1_device); | |
918 | at32_init_pio(&pio2_device); | |
919 | at32_init_pio(&pio3_device); | |
7f9f4678 | 920 | at32_init_pio(&pio4_device); |
5f97f7f9 HS |
921 | } |
922 | ||
923 | void __init at32_clock_init(void) | |
924 | { | |
925 | struct at32_sm *sm = &system_manager; | |
926 | u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0; | |
927 | int i; | |
928 | ||
929 | if (sm_readl(sm, PM_MCCTRL) & SM_BIT(PLLSEL)) | |
930 | main_clock = &pll0; | |
931 | else | |
932 | main_clock = &osc0; | |
933 | ||
934 | if (sm_readl(sm, PM_PLL0) & SM_BIT(PLLOSC)) | |
935 | pll0.parent = &osc1; | |
936 | if (sm_readl(sm, PM_PLL1) & SM_BIT(PLLOSC)) | |
937 | pll1.parent = &osc1; | |
938 | ||
939 | /* | |
940 | * Turn on all clocks that have at least one user already, and | |
941 | * turn off everything else. We only do this for module | |
942 | * clocks, and even though it isn't particularly pretty to | |
943 | * check the address of the mode function, it should do the | |
944 | * trick... | |
945 | */ | |
946 | for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) { | |
947 | struct clk *clk = at32_clock_list[i]; | |
948 | ||
949 | if (clk->mode == &cpu_clk_mode) | |
950 | cpu_mask |= 1 << clk->index; | |
951 | else if (clk->mode == &hsb_clk_mode) | |
952 | hsb_mask |= 1 << clk->index; | |
953 | else if (clk->mode == &pba_clk_mode) | |
954 | pba_mask |= 1 << clk->index; | |
955 | else if (clk->mode == &pbb_clk_mode) | |
956 | pbb_mask |= 1 << clk->index; | |
957 | } | |
958 | ||
959 | sm_writel(sm, PM_CPU_MASK, cpu_mask); | |
960 | sm_writel(sm, PM_HSB_MASK, hsb_mask); | |
961 | sm_writel(sm, PM_PBA_MASK, pba_mask); | |
962 | sm_writel(sm, PM_PBB_MASK, pbb_mask); | |
963 | } |