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Commit | Line | Data |
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5f97f7f9 HS |
1 | /* |
2 | * Copyright (C) 2005-2006 Atmel Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | #include <linux/clk.h> | |
35bf50cc | 9 | #include <linux/delay.h> |
3bfb1d20 | 10 | #include <linux/dw_dmac.h> |
d0a2b7af | 11 | #include <linux/fb.h> |
5f97f7f9 HS |
12 | #include <linux/init.h> |
13 | #include <linux/platform_device.h> | |
6b84bbfc | 14 | #include <linux/dma-mapping.h> |
41d8ca45 | 15 | #include <linux/spi/spi.h> |
8d855317 | 16 | #include <linux/usb/atmel_usba_udc.h> |
5f97f7f9 | 17 | |
7d2be074 | 18 | #include <asm/atmel-mci.h> |
5f97f7f9 | 19 | #include <asm/io.h> |
e7ba176b | 20 | #include <asm/irq.h> |
5f97f7f9 | 21 | |
438ff3f3 | 22 | #include <asm/arch/at32ap700x.h> |
5f97f7f9 HS |
23 | #include <asm/arch/board.h> |
24 | #include <asm/arch/portmux.h> | |
b83d6ee1 | 25 | #include <asm/arch/sram.h> |
5f97f7f9 | 26 | |
d0a2b7af HS |
27 | #include <video/atmel_lcdc.h> |
28 | ||
5f97f7f9 | 29 | #include "clock.h" |
9c8f8e75 | 30 | #include "hmatrix.h" |
5f97f7f9 | 31 | #include "pio.h" |
7a5b8059 HS |
32 | #include "pm.h" |
33 | ||
5f97f7f9 HS |
34 | |
35 | #define PBMEM(base) \ | |
36 | { \ | |
37 | .start = base, \ | |
38 | .end = base + 0x3ff, \ | |
39 | .flags = IORESOURCE_MEM, \ | |
40 | } | |
41 | #define IRQ(num) \ | |
42 | { \ | |
43 | .start = num, \ | |
44 | .end = num, \ | |
45 | .flags = IORESOURCE_IRQ, \ | |
46 | } | |
47 | #define NAMED_IRQ(num, _name) \ | |
48 | { \ | |
49 | .start = num, \ | |
50 | .end = num, \ | |
51 | .name = _name, \ | |
52 | .flags = IORESOURCE_IRQ, \ | |
53 | } | |
54 | ||
6b84bbfc DB |
55 | /* REVISIT these assume *every* device supports DMA, but several |
56 | * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more. | |
57 | */ | |
5f97f7f9 | 58 | #define DEFINE_DEV(_name, _id) \ |
6b84bbfc | 59 | static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \ |
5f97f7f9 HS |
60 | static struct platform_device _name##_id##_device = { \ |
61 | .name = #_name, \ | |
62 | .id = _id, \ | |
6b84bbfc DB |
63 | .dev = { \ |
64 | .dma_mask = &_name##_id##_dma_mask, \ | |
65 | .coherent_dma_mask = DMA_32BIT_MASK, \ | |
66 | }, \ | |
5f97f7f9 HS |
67 | .resource = _name##_id##_resource, \ |
68 | .num_resources = ARRAY_SIZE(_name##_id##_resource), \ | |
69 | } | |
70 | #define DEFINE_DEV_DATA(_name, _id) \ | |
6b84bbfc | 71 | static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \ |
5f97f7f9 HS |
72 | static struct platform_device _name##_id##_device = { \ |
73 | .name = #_name, \ | |
74 | .id = _id, \ | |
75 | .dev = { \ | |
6b84bbfc | 76 | .dma_mask = &_name##_id##_dma_mask, \ |
5f97f7f9 | 77 | .platform_data = &_name##_id##_data, \ |
6b84bbfc | 78 | .coherent_dma_mask = DMA_32BIT_MASK, \ |
5f97f7f9 HS |
79 | }, \ |
80 | .resource = _name##_id##_resource, \ | |
81 | .num_resources = ARRAY_SIZE(_name##_id##_resource), \ | |
82 | } | |
83 | ||
c3e2a79c HS |
84 | #define select_peripheral(pin, periph, flags) \ |
85 | at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags) | |
86 | ||
5f97f7f9 HS |
87 | #define DEV_CLK(_name, devname, bus, _index) \ |
88 | static struct clk devname##_##_name = { \ | |
89 | .name = #_name, \ | |
90 | .dev = &devname##_device.dev, \ | |
91 | .parent = &bus##_clk, \ | |
92 | .mode = bus##_clk_mode, \ | |
93 | .get_rate = bus##_clk_get_rate, \ | |
94 | .index = _index, \ | |
95 | } | |
96 | ||
7a5b8059 HS |
97 | static DEFINE_SPINLOCK(pm_lock); |
98 | ||
35bf50cc HCE |
99 | static struct clk osc0; |
100 | static struct clk osc1; | |
101 | ||
5f97f7f9 HS |
102 | static unsigned long osc_get_rate(struct clk *clk) |
103 | { | |
60ed7951 | 104 | return at32_board_osc_rates[clk->index]; |
5f97f7f9 HS |
105 | } |
106 | ||
107 | static unsigned long pll_get_rate(struct clk *clk, unsigned long control) | |
108 | { | |
109 | unsigned long div, mul, rate; | |
110 | ||
7a5b8059 HS |
111 | div = PM_BFEXT(PLLDIV, control) + 1; |
112 | mul = PM_BFEXT(PLLMUL, control) + 1; | |
5f97f7f9 HS |
113 | |
114 | rate = clk->parent->get_rate(clk->parent); | |
115 | rate = (rate + div / 2) / div; | |
116 | rate *= mul; | |
117 | ||
118 | return rate; | |
119 | } | |
120 | ||
35bf50cc HCE |
121 | static long pll_set_rate(struct clk *clk, unsigned long rate, |
122 | u32 *pll_ctrl) | |
123 | { | |
124 | unsigned long mul; | |
125 | unsigned long mul_best_fit = 0; | |
126 | unsigned long div; | |
127 | unsigned long div_min; | |
128 | unsigned long div_max; | |
129 | unsigned long div_best_fit = 0; | |
130 | unsigned long base; | |
131 | unsigned long pll_in; | |
132 | unsigned long actual = 0; | |
133 | unsigned long rate_error; | |
134 | unsigned long rate_error_prev = ~0UL; | |
135 | u32 ctrl; | |
136 | ||
137 | /* Rate must be between 80 MHz and 200 Mhz. */ | |
138 | if (rate < 80000000UL || rate > 200000000UL) | |
139 | return -EINVAL; | |
140 | ||
141 | ctrl = PM_BF(PLLOPT, 4); | |
142 | base = clk->parent->get_rate(clk->parent); | |
143 | ||
144 | /* PLL input frequency must be between 6 MHz and 32 MHz. */ | |
145 | div_min = DIV_ROUND_UP(base, 32000000UL); | |
146 | div_max = base / 6000000UL; | |
147 | ||
148 | if (div_max < div_min) | |
149 | return -EINVAL; | |
150 | ||
151 | for (div = div_min; div <= div_max; div++) { | |
152 | pll_in = (base + div / 2) / div; | |
153 | mul = (rate + pll_in / 2) / pll_in; | |
154 | ||
155 | if (mul == 0) | |
156 | continue; | |
157 | ||
158 | actual = pll_in * mul; | |
159 | rate_error = abs(actual - rate); | |
160 | ||
161 | if (rate_error < rate_error_prev) { | |
162 | mul_best_fit = mul; | |
163 | div_best_fit = div; | |
164 | rate_error_prev = rate_error; | |
165 | } | |
166 | ||
167 | if (rate_error == 0) | |
168 | break; | |
169 | } | |
170 | ||
171 | if (div_best_fit == 0) | |
172 | return -EINVAL; | |
173 | ||
174 | ctrl |= PM_BF(PLLMUL, mul_best_fit - 1); | |
175 | ctrl |= PM_BF(PLLDIV, div_best_fit - 1); | |
176 | ctrl |= PM_BF(PLLCOUNT, 16); | |
177 | ||
178 | if (clk->parent == &osc1) | |
179 | ctrl |= PM_BIT(PLLOSC); | |
180 | ||
181 | *pll_ctrl = ctrl; | |
182 | ||
183 | return actual; | |
184 | } | |
185 | ||
5f97f7f9 HS |
186 | static unsigned long pll0_get_rate(struct clk *clk) |
187 | { | |
188 | u32 control; | |
189 | ||
7a5b8059 | 190 | control = pm_readl(PLL0); |
5f97f7f9 HS |
191 | |
192 | return pll_get_rate(clk, control); | |
193 | } | |
194 | ||
35bf50cc HCE |
195 | static void pll1_mode(struct clk *clk, int enabled) |
196 | { | |
197 | unsigned long timeout; | |
198 | u32 status; | |
199 | u32 ctrl; | |
200 | ||
201 | ctrl = pm_readl(PLL1); | |
202 | ||
203 | if (enabled) { | |
204 | if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) { | |
205 | pr_debug("clk %s: failed to enable, rate not set\n", | |
206 | clk->name); | |
207 | return; | |
208 | } | |
209 | ||
210 | ctrl |= PM_BIT(PLLEN); | |
211 | pm_writel(PLL1, ctrl); | |
212 | ||
213 | /* Wait for PLL lock. */ | |
214 | for (timeout = 10000; timeout; timeout--) { | |
215 | status = pm_readl(ISR); | |
216 | if (status & PM_BIT(LOCK1)) | |
217 | break; | |
218 | udelay(10); | |
219 | } | |
220 | ||
221 | if (!(status & PM_BIT(LOCK1))) | |
222 | printk(KERN_ERR "clk %s: timeout waiting for lock\n", | |
223 | clk->name); | |
224 | } else { | |
225 | ctrl &= ~PM_BIT(PLLEN); | |
226 | pm_writel(PLL1, ctrl); | |
227 | } | |
228 | } | |
229 | ||
5f97f7f9 HS |
230 | static unsigned long pll1_get_rate(struct clk *clk) |
231 | { | |
232 | u32 control; | |
233 | ||
7a5b8059 | 234 | control = pm_readl(PLL1); |
5f97f7f9 HS |
235 | |
236 | return pll_get_rate(clk, control); | |
237 | } | |
238 | ||
35bf50cc HCE |
239 | static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply) |
240 | { | |
241 | u32 ctrl = 0; | |
242 | unsigned long actual_rate; | |
243 | ||
244 | actual_rate = pll_set_rate(clk, rate, &ctrl); | |
245 | ||
246 | if (apply) { | |
247 | if (actual_rate != rate) | |
248 | return -EINVAL; | |
249 | if (clk->users > 0) | |
250 | return -EBUSY; | |
251 | pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n", | |
252 | clk->name, rate, actual_rate); | |
253 | pm_writel(PLL1, ctrl); | |
254 | } | |
255 | ||
256 | return actual_rate; | |
257 | } | |
258 | ||
259 | static int pll1_set_parent(struct clk *clk, struct clk *parent) | |
260 | { | |
261 | u32 ctrl; | |
262 | ||
263 | if (clk->users > 0) | |
264 | return -EBUSY; | |
265 | ||
266 | ctrl = pm_readl(PLL1); | |
267 | WARN_ON(ctrl & PM_BIT(PLLEN)); | |
268 | ||
269 | if (parent == &osc0) | |
270 | ctrl &= ~PM_BIT(PLLOSC); | |
271 | else if (parent == &osc1) | |
272 | ctrl |= PM_BIT(PLLOSC); | |
273 | else | |
274 | return -EINVAL; | |
275 | ||
276 | pm_writel(PLL1, ctrl); | |
277 | clk->parent = parent; | |
278 | ||
279 | return 0; | |
280 | } | |
281 | ||
5f97f7f9 HS |
282 | /* |
283 | * The AT32AP7000 has five primary clock sources: One 32kHz | |
284 | * oscillator, two crystal oscillators and two PLLs. | |
285 | */ | |
286 | static struct clk osc32k = { | |
287 | .name = "osc32k", | |
288 | .get_rate = osc_get_rate, | |
289 | .users = 1, | |
290 | .index = 0, | |
291 | }; | |
292 | static struct clk osc0 = { | |
293 | .name = "osc0", | |
294 | .get_rate = osc_get_rate, | |
295 | .users = 1, | |
296 | .index = 1, | |
297 | }; | |
298 | static struct clk osc1 = { | |
299 | .name = "osc1", | |
300 | .get_rate = osc_get_rate, | |
301 | .index = 2, | |
302 | }; | |
303 | static struct clk pll0 = { | |
304 | .name = "pll0", | |
305 | .get_rate = pll0_get_rate, | |
306 | .parent = &osc0, | |
307 | }; | |
308 | static struct clk pll1 = { | |
309 | .name = "pll1", | |
35bf50cc | 310 | .mode = pll1_mode, |
5f97f7f9 | 311 | .get_rate = pll1_get_rate, |
35bf50cc HCE |
312 | .set_rate = pll1_set_rate, |
313 | .set_parent = pll1_set_parent, | |
5f97f7f9 HS |
314 | .parent = &osc0, |
315 | }; | |
316 | ||
317 | /* | |
318 | * The main clock can be either osc0 or pll0. The boot loader may | |
319 | * have chosen one for us, so we don't really know which one until we | |
320 | * have a look at the SM. | |
321 | */ | |
322 | static struct clk *main_clock; | |
323 | ||
324 | /* | |
325 | * Synchronous clocks are generated from the main clock. The clocks | |
326 | * must satisfy the constraint | |
327 | * fCPU >= fHSB >= fPB | |
328 | * i.e. each clock must not be faster than its parent. | |
329 | */ | |
330 | static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift) | |
331 | { | |
332 | return main_clock->get_rate(main_clock) >> shift; | |
333 | }; | |
334 | ||
335 | static void cpu_clk_mode(struct clk *clk, int enabled) | |
336 | { | |
5f97f7f9 HS |
337 | unsigned long flags; |
338 | u32 mask; | |
339 | ||
7a5b8059 HS |
340 | spin_lock_irqsave(&pm_lock, flags); |
341 | mask = pm_readl(CPU_MASK); | |
5f97f7f9 HS |
342 | if (enabled) |
343 | mask |= 1 << clk->index; | |
344 | else | |
345 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
346 | pm_writel(CPU_MASK, mask); |
347 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
348 | } |
349 | ||
350 | static unsigned long cpu_clk_get_rate(struct clk *clk) | |
351 | { | |
352 | unsigned long cksel, shift = 0; | |
353 | ||
7a5b8059 HS |
354 | cksel = pm_readl(CKSEL); |
355 | if (cksel & PM_BIT(CPUDIV)) | |
356 | shift = PM_BFEXT(CPUSEL, cksel) + 1; | |
5f97f7f9 HS |
357 | |
358 | return bus_clk_get_rate(clk, shift); | |
359 | } | |
360 | ||
9e58e185 HCE |
361 | static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply) |
362 | { | |
363 | u32 control; | |
364 | unsigned long parent_rate, child_div, actual_rate, div; | |
365 | ||
366 | parent_rate = clk->parent->get_rate(clk->parent); | |
367 | control = pm_readl(CKSEL); | |
368 | ||
369 | if (control & PM_BIT(HSBDIV)) | |
370 | child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1); | |
371 | else | |
372 | child_div = 1; | |
373 | ||
374 | if (rate > 3 * (parent_rate / 4) || child_div == 1) { | |
375 | actual_rate = parent_rate; | |
376 | control &= ~PM_BIT(CPUDIV); | |
377 | } else { | |
378 | unsigned int cpusel; | |
379 | div = (parent_rate + rate / 2) / rate; | |
380 | if (div > child_div) | |
381 | div = child_div; | |
382 | cpusel = (div > 1) ? (fls(div) - 2) : 0; | |
383 | control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control); | |
384 | actual_rate = parent_rate / (1 << (cpusel + 1)); | |
385 | } | |
386 | ||
387 | pr_debug("clk %s: new rate %lu (actual rate %lu)\n", | |
388 | clk->name, rate, actual_rate); | |
389 | ||
390 | if (apply) | |
391 | pm_writel(CKSEL, control); | |
392 | ||
393 | return actual_rate; | |
394 | } | |
395 | ||
5f97f7f9 HS |
396 | static void hsb_clk_mode(struct clk *clk, int enabled) |
397 | { | |
5f97f7f9 HS |
398 | unsigned long flags; |
399 | u32 mask; | |
400 | ||
7a5b8059 HS |
401 | spin_lock_irqsave(&pm_lock, flags); |
402 | mask = pm_readl(HSB_MASK); | |
5f97f7f9 HS |
403 | if (enabled) |
404 | mask |= 1 << clk->index; | |
405 | else | |
406 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
407 | pm_writel(HSB_MASK, mask); |
408 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
409 | } |
410 | ||
411 | static unsigned long hsb_clk_get_rate(struct clk *clk) | |
412 | { | |
413 | unsigned long cksel, shift = 0; | |
414 | ||
7a5b8059 HS |
415 | cksel = pm_readl(CKSEL); |
416 | if (cksel & PM_BIT(HSBDIV)) | |
417 | shift = PM_BFEXT(HSBSEL, cksel) + 1; | |
5f97f7f9 HS |
418 | |
419 | return bus_clk_get_rate(clk, shift); | |
420 | } | |
421 | ||
422 | static void pba_clk_mode(struct clk *clk, int enabled) | |
423 | { | |
5f97f7f9 HS |
424 | unsigned long flags; |
425 | u32 mask; | |
426 | ||
7a5b8059 HS |
427 | spin_lock_irqsave(&pm_lock, flags); |
428 | mask = pm_readl(PBA_MASK); | |
5f97f7f9 HS |
429 | if (enabled) |
430 | mask |= 1 << clk->index; | |
431 | else | |
432 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
433 | pm_writel(PBA_MASK, mask); |
434 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
435 | } |
436 | ||
437 | static unsigned long pba_clk_get_rate(struct clk *clk) | |
438 | { | |
439 | unsigned long cksel, shift = 0; | |
440 | ||
7a5b8059 HS |
441 | cksel = pm_readl(CKSEL); |
442 | if (cksel & PM_BIT(PBADIV)) | |
443 | shift = PM_BFEXT(PBASEL, cksel) + 1; | |
5f97f7f9 HS |
444 | |
445 | return bus_clk_get_rate(clk, shift); | |
446 | } | |
447 | ||
448 | static void pbb_clk_mode(struct clk *clk, int enabled) | |
449 | { | |
5f97f7f9 HS |
450 | unsigned long flags; |
451 | u32 mask; | |
452 | ||
7a5b8059 HS |
453 | spin_lock_irqsave(&pm_lock, flags); |
454 | mask = pm_readl(PBB_MASK); | |
5f97f7f9 HS |
455 | if (enabled) |
456 | mask |= 1 << clk->index; | |
457 | else | |
458 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
459 | pm_writel(PBB_MASK, mask); |
460 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
461 | } |
462 | ||
463 | static unsigned long pbb_clk_get_rate(struct clk *clk) | |
464 | { | |
465 | unsigned long cksel, shift = 0; | |
466 | ||
7a5b8059 HS |
467 | cksel = pm_readl(CKSEL); |
468 | if (cksel & PM_BIT(PBBDIV)) | |
469 | shift = PM_BFEXT(PBBSEL, cksel) + 1; | |
5f97f7f9 HS |
470 | |
471 | return bus_clk_get_rate(clk, shift); | |
472 | } | |
473 | ||
474 | static struct clk cpu_clk = { | |
475 | .name = "cpu", | |
476 | .get_rate = cpu_clk_get_rate, | |
9e58e185 | 477 | .set_rate = cpu_clk_set_rate, |
5f97f7f9 HS |
478 | .users = 1, |
479 | }; | |
480 | static struct clk hsb_clk = { | |
481 | .name = "hsb", | |
482 | .parent = &cpu_clk, | |
483 | .get_rate = hsb_clk_get_rate, | |
484 | }; | |
485 | static struct clk pba_clk = { | |
486 | .name = "pba", | |
487 | .parent = &hsb_clk, | |
488 | .mode = hsb_clk_mode, | |
489 | .get_rate = pba_clk_get_rate, | |
490 | .index = 1, | |
491 | }; | |
492 | static struct clk pbb_clk = { | |
493 | .name = "pbb", | |
494 | .parent = &hsb_clk, | |
495 | .mode = hsb_clk_mode, | |
496 | .get_rate = pbb_clk_get_rate, | |
497 | .users = 1, | |
498 | .index = 2, | |
499 | }; | |
500 | ||
501 | /* -------------------------------------------------------------------- | |
502 | * Generic Clock operations | |
503 | * -------------------------------------------------------------------- */ | |
504 | ||
505 | static void genclk_mode(struct clk *clk, int enabled) | |
506 | { | |
507 | u32 control; | |
508 | ||
7a5b8059 | 509 | control = pm_readl(GCCTRL(clk->index)); |
5f97f7f9 | 510 | if (enabled) |
7a5b8059 | 511 | control |= PM_BIT(CEN); |
5f97f7f9 | 512 | else |
7a5b8059 HS |
513 | control &= ~PM_BIT(CEN); |
514 | pm_writel(GCCTRL(clk->index), control); | |
5f97f7f9 HS |
515 | } |
516 | ||
517 | static unsigned long genclk_get_rate(struct clk *clk) | |
518 | { | |
519 | u32 control; | |
520 | unsigned long div = 1; | |
521 | ||
7a5b8059 HS |
522 | control = pm_readl(GCCTRL(clk->index)); |
523 | if (control & PM_BIT(DIVEN)) | |
524 | div = 2 * (PM_BFEXT(DIV, control) + 1); | |
5f97f7f9 HS |
525 | |
526 | return clk->parent->get_rate(clk->parent) / div; | |
527 | } | |
528 | ||
529 | static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply) | |
530 | { | |
531 | u32 control; | |
532 | unsigned long parent_rate, actual_rate, div; | |
533 | ||
5f97f7f9 | 534 | parent_rate = clk->parent->get_rate(clk->parent); |
7a5b8059 | 535 | control = pm_readl(GCCTRL(clk->index)); |
5f97f7f9 HS |
536 | |
537 | if (rate > 3 * parent_rate / 4) { | |
538 | actual_rate = parent_rate; | |
7a5b8059 | 539 | control &= ~PM_BIT(DIVEN); |
5f97f7f9 HS |
540 | } else { |
541 | div = (parent_rate + rate) / (2 * rate) - 1; | |
7a5b8059 | 542 | control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN); |
5f97f7f9 HS |
543 | actual_rate = parent_rate / (2 * (div + 1)); |
544 | } | |
545 | ||
7a5b8059 HS |
546 | dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n", |
547 | clk->name, rate, actual_rate); | |
5f97f7f9 HS |
548 | |
549 | if (apply) | |
7a5b8059 | 550 | pm_writel(GCCTRL(clk->index), control); |
5f97f7f9 HS |
551 | |
552 | return actual_rate; | |
553 | } | |
554 | ||
555 | int genclk_set_parent(struct clk *clk, struct clk *parent) | |
556 | { | |
557 | u32 control; | |
558 | ||
7a5b8059 HS |
559 | dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n", |
560 | clk->name, parent->name, clk->parent->name); | |
5f97f7f9 | 561 | |
7a5b8059 | 562 | control = pm_readl(GCCTRL(clk->index)); |
5f97f7f9 HS |
563 | |
564 | if (parent == &osc1 || parent == &pll1) | |
7a5b8059 | 565 | control |= PM_BIT(OSCSEL); |
5f97f7f9 | 566 | else if (parent == &osc0 || parent == &pll0) |
7a5b8059 | 567 | control &= ~PM_BIT(OSCSEL); |
5f97f7f9 HS |
568 | else |
569 | return -EINVAL; | |
570 | ||
571 | if (parent == &pll0 || parent == &pll1) | |
7a5b8059 | 572 | control |= PM_BIT(PLLSEL); |
5f97f7f9 | 573 | else |
7a5b8059 | 574 | control &= ~PM_BIT(PLLSEL); |
5f97f7f9 | 575 | |
7a5b8059 | 576 | pm_writel(GCCTRL(clk->index), control); |
5f97f7f9 HS |
577 | clk->parent = parent; |
578 | ||
579 | return 0; | |
580 | } | |
581 | ||
7a5fe238 HS |
582 | static void __init genclk_init_parent(struct clk *clk) |
583 | { | |
584 | u32 control; | |
585 | struct clk *parent; | |
586 | ||
587 | BUG_ON(clk->index > 7); | |
588 | ||
7a5b8059 HS |
589 | control = pm_readl(GCCTRL(clk->index)); |
590 | if (control & PM_BIT(OSCSEL)) | |
591 | parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1; | |
7a5fe238 | 592 | else |
7a5b8059 | 593 | parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0; |
7a5fe238 HS |
594 | |
595 | clk->parent = parent; | |
596 | } | |
597 | ||
3bfb1d20 HS |
598 | static struct dw_dma_platform_data dw_dmac0_data = { |
599 | .nr_channels = 3, | |
600 | }; | |
601 | ||
602 | static struct resource dw_dmac0_resource[] = { | |
603 | PBMEM(0xff200000), | |
604 | IRQ(2), | |
605 | }; | |
606 | DEFINE_DEV_DATA(dw_dmac, 0); | |
607 | DEV_CLK(hclk, dw_dmac0, hsb, 10); | |
608 | ||
5f97f7f9 HS |
609 | /* -------------------------------------------------------------------- |
610 | * System peripherals | |
611 | * -------------------------------------------------------------------- */ | |
7a5b8059 HS |
612 | static struct resource at32_pm0_resource[] = { |
613 | { | |
614 | .start = 0xfff00000, | |
615 | .end = 0xfff0007f, | |
616 | .flags = IORESOURCE_MEM, | |
617 | }, | |
618 | IRQ(20), | |
5f97f7f9 | 619 | }; |
7a5b8059 HS |
620 | |
621 | static struct resource at32ap700x_rtc0_resource[] = { | |
622 | { | |
623 | .start = 0xfff00080, | |
624 | .end = 0xfff000af, | |
625 | .flags = IORESOURCE_MEM, | |
626 | }, | |
627 | IRQ(21), | |
5f97f7f9 | 628 | }; |
7a5b8059 HS |
629 | |
630 | static struct resource at32_wdt0_resource[] = { | |
631 | { | |
632 | .start = 0xfff000b0, | |
9797bed2 | 633 | .end = 0xfff000cf, |
7a5b8059 HS |
634 | .flags = IORESOURCE_MEM, |
635 | }, | |
636 | }; | |
637 | ||
638 | static struct resource at32_eic0_resource[] = { | |
639 | { | |
640 | .start = 0xfff00100, | |
641 | .end = 0xfff0013f, | |
642 | .flags = IORESOURCE_MEM, | |
643 | }, | |
644 | IRQ(19), | |
645 | }; | |
646 | ||
647 | DEFINE_DEV(at32_pm, 0); | |
648 | DEFINE_DEV(at32ap700x_rtc, 0); | |
649 | DEFINE_DEV(at32_wdt, 0); | |
650 | DEFINE_DEV(at32_eic, 0); | |
651 | ||
652 | /* | |
653 | * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this | |
654 | * is always running. | |
655 | */ | |
656 | static struct clk at32_pm_pclk = { | |
188ff65d | 657 | .name = "pclk", |
7a5b8059 | 658 | .dev = &at32_pm0_device.dev, |
188ff65d HS |
659 | .parent = &pbb_clk, |
660 | .mode = pbb_clk_mode, | |
661 | .get_rate = pbb_clk_get_rate, | |
662 | .users = 1, | |
663 | .index = 0, | |
664 | }; | |
5f97f7f9 HS |
665 | |
666 | static struct resource intc0_resource[] = { | |
667 | PBMEM(0xfff00400), | |
668 | }; | |
669 | struct platform_device at32_intc0_device = { | |
670 | .name = "intc", | |
671 | .id = 0, | |
672 | .resource = intc0_resource, | |
673 | .num_resources = ARRAY_SIZE(intc0_resource), | |
674 | }; | |
675 | DEV_CLK(pclk, at32_intc0, pbb, 1); | |
676 | ||
677 | static struct clk ebi_clk = { | |
678 | .name = "ebi", | |
679 | .parent = &hsb_clk, | |
680 | .mode = hsb_clk_mode, | |
681 | .get_rate = hsb_clk_get_rate, | |
682 | .users = 1, | |
683 | }; | |
684 | static struct clk hramc_clk = { | |
685 | .name = "hramc", | |
686 | .parent = &hsb_clk, | |
687 | .mode = hsb_clk_mode, | |
688 | .get_rate = hsb_clk_get_rate, | |
689 | .users = 1, | |
188ff65d | 690 | .index = 3, |
5f97f7f9 | 691 | }; |
7951f188 HS |
692 | static struct clk sdramc_clk = { |
693 | .name = "sdramc_clk", | |
694 | .parent = &pbb_clk, | |
695 | .mode = pbb_clk_mode, | |
696 | .get_rate = pbb_clk_get_rate, | |
697 | .users = 1, | |
698 | .index = 14, | |
699 | }; | |
5f97f7f9 | 700 | |
bc157b75 HS |
701 | static struct resource smc0_resource[] = { |
702 | PBMEM(0xfff03400), | |
703 | }; | |
704 | DEFINE_DEV(smc, 0); | |
705 | DEV_CLK(pclk, smc0, pbb, 13); | |
706 | DEV_CLK(mck, smc0, hsb, 0); | |
707 | ||
5f97f7f9 HS |
708 | static struct platform_device pdc_device = { |
709 | .name = "pdc", | |
710 | .id = 0, | |
711 | }; | |
712 | DEV_CLK(hclk, pdc, hsb, 4); | |
713 | DEV_CLK(pclk, pdc, pba, 16); | |
714 | ||
715 | static struct clk pico_clk = { | |
716 | .name = "pico", | |
717 | .parent = &cpu_clk, | |
718 | .mode = cpu_clk_mode, | |
719 | .get_rate = cpu_clk_get_rate, | |
720 | .users = 1, | |
721 | }; | |
722 | ||
9c8f8e75 HS |
723 | /* -------------------------------------------------------------------- |
724 | * HMATRIX | |
725 | * -------------------------------------------------------------------- */ | |
726 | ||
727 | static struct clk hmatrix_clk = { | |
728 | .name = "hmatrix_clk", | |
729 | .parent = &pbb_clk, | |
730 | .mode = pbb_clk_mode, | |
731 | .get_rate = pbb_clk_get_rate, | |
732 | .index = 2, | |
733 | .users = 1, | |
734 | }; | |
735 | #define HMATRIX_BASE ((void __iomem *)0xfff00800) | |
736 | ||
737 | #define hmatrix_readl(reg) \ | |
738 | __raw_readl((HMATRIX_BASE) + HMATRIX_##reg) | |
739 | #define hmatrix_writel(reg,value) \ | |
740 | __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg) | |
741 | ||
742 | /* | |
743 | * Set bits in the HMATRIX Special Function Register (SFR) used by the | |
744 | * External Bus Interface (EBI). This can be used to enable special | |
745 | * features like CompactFlash support, NAND Flash support, etc. on | |
746 | * certain chipselects. | |
747 | */ | |
748 | static inline void set_ebi_sfr_bits(u32 mask) | |
749 | { | |
750 | u32 sfr; | |
751 | ||
752 | clk_enable(&hmatrix_clk); | |
753 | sfr = hmatrix_readl(SFR4); | |
754 | sfr |= mask; | |
755 | hmatrix_writel(SFR4, sfr); | |
756 | clk_disable(&hmatrix_clk); | |
757 | } | |
758 | ||
7760989e | 759 | /* -------------------------------------------------------------------- |
e723ff66 | 760 | * Timer/Counter (TC) |
7760989e | 761 | * -------------------------------------------------------------------- */ |
e723ff66 DB |
762 | |
763 | static struct resource at32_tcb0_resource[] = { | |
7760989e HCE |
764 | PBMEM(0xfff00c00), |
765 | IRQ(22), | |
766 | }; | |
e723ff66 DB |
767 | static struct platform_device at32_tcb0_device = { |
768 | .name = "atmel_tcb", | |
7760989e | 769 | .id = 0, |
e723ff66 DB |
770 | .resource = at32_tcb0_resource, |
771 | .num_resources = ARRAY_SIZE(at32_tcb0_resource), | |
772 | }; | |
773 | DEV_CLK(t0_clk, at32_tcb0, pbb, 3); | |
774 | ||
775 | static struct resource at32_tcb1_resource[] = { | |
776 | PBMEM(0xfff01000), | |
777 | IRQ(23), | |
778 | }; | |
779 | static struct platform_device at32_tcb1_device = { | |
780 | .name = "atmel_tcb", | |
781 | .id = 1, | |
782 | .resource = at32_tcb1_resource, | |
783 | .num_resources = ARRAY_SIZE(at32_tcb1_resource), | |
7760989e | 784 | }; |
e723ff66 | 785 | DEV_CLK(t0_clk, at32_tcb1, pbb, 4); |
7760989e | 786 | |
5f97f7f9 HS |
787 | /* -------------------------------------------------------------------- |
788 | * PIO | |
789 | * -------------------------------------------------------------------- */ | |
790 | ||
791 | static struct resource pio0_resource[] = { | |
792 | PBMEM(0xffe02800), | |
793 | IRQ(13), | |
794 | }; | |
795 | DEFINE_DEV(pio, 0); | |
796 | DEV_CLK(mck, pio0, pba, 10); | |
797 | ||
798 | static struct resource pio1_resource[] = { | |
799 | PBMEM(0xffe02c00), | |
800 | IRQ(14), | |
801 | }; | |
802 | DEFINE_DEV(pio, 1); | |
803 | DEV_CLK(mck, pio1, pba, 11); | |
804 | ||
805 | static struct resource pio2_resource[] = { | |
806 | PBMEM(0xffe03000), | |
807 | IRQ(15), | |
808 | }; | |
809 | DEFINE_DEV(pio, 2); | |
810 | DEV_CLK(mck, pio2, pba, 12); | |
811 | ||
812 | static struct resource pio3_resource[] = { | |
813 | PBMEM(0xffe03400), | |
814 | IRQ(16), | |
815 | }; | |
816 | DEFINE_DEV(pio, 3); | |
817 | DEV_CLK(mck, pio3, pba, 13); | |
818 | ||
7f9f4678 HS |
819 | static struct resource pio4_resource[] = { |
820 | PBMEM(0xffe03800), | |
821 | IRQ(17), | |
822 | }; | |
823 | DEFINE_DEV(pio, 4); | |
824 | DEV_CLK(mck, pio4, pba, 14); | |
825 | ||
5f97f7f9 HS |
826 | void __init at32_add_system_devices(void) |
827 | { | |
7a5b8059 | 828 | platform_device_register(&at32_pm0_device); |
5f97f7f9 | 829 | platform_device_register(&at32_intc0_device); |
7a5b8059 HS |
830 | platform_device_register(&at32ap700x_rtc0_device); |
831 | platform_device_register(&at32_wdt0_device); | |
832 | platform_device_register(&at32_eic0_device); | |
bc157b75 | 833 | platform_device_register(&smc0_device); |
5f97f7f9 | 834 | platform_device_register(&pdc_device); |
3bfb1d20 | 835 | platform_device_register(&dw_dmac0_device); |
5f97f7f9 | 836 | |
e723ff66 DB |
837 | platform_device_register(&at32_tcb0_device); |
838 | platform_device_register(&at32_tcb1_device); | |
7760989e | 839 | |
5f97f7f9 HS |
840 | platform_device_register(&pio0_device); |
841 | platform_device_register(&pio1_device); | |
842 | platform_device_register(&pio2_device); | |
843 | platform_device_register(&pio3_device); | |
7f9f4678 | 844 | platform_device_register(&pio4_device); |
5f97f7f9 HS |
845 | } |
846 | ||
d86d314f HCE |
847 | /* -------------------------------------------------------------------- |
848 | * PSIF | |
849 | * -------------------------------------------------------------------- */ | |
850 | static struct resource atmel_psif0_resource[] __initdata = { | |
851 | { | |
852 | .start = 0xffe03c00, | |
853 | .end = 0xffe03cff, | |
854 | .flags = IORESOURCE_MEM, | |
855 | }, | |
856 | IRQ(18), | |
857 | }; | |
858 | static struct clk atmel_psif0_pclk = { | |
859 | .name = "pclk", | |
860 | .parent = &pba_clk, | |
861 | .mode = pba_clk_mode, | |
862 | .get_rate = pba_clk_get_rate, | |
863 | .index = 15, | |
864 | }; | |
865 | ||
866 | static struct resource atmel_psif1_resource[] __initdata = { | |
867 | { | |
868 | .start = 0xffe03d00, | |
869 | .end = 0xffe03dff, | |
870 | .flags = IORESOURCE_MEM, | |
871 | }, | |
872 | IRQ(18), | |
873 | }; | |
874 | static struct clk atmel_psif1_pclk = { | |
875 | .name = "pclk", | |
876 | .parent = &pba_clk, | |
877 | .mode = pba_clk_mode, | |
878 | .get_rate = pba_clk_get_rate, | |
879 | .index = 15, | |
880 | }; | |
881 | ||
882 | struct platform_device *__init at32_add_device_psif(unsigned int id) | |
883 | { | |
884 | struct platform_device *pdev; | |
885 | ||
886 | if (!(id == 0 || id == 1)) | |
887 | return NULL; | |
888 | ||
889 | pdev = platform_device_alloc("atmel_psif", id); | |
890 | if (!pdev) | |
891 | return NULL; | |
892 | ||
893 | switch (id) { | |
894 | case 0: | |
895 | if (platform_device_add_resources(pdev, atmel_psif0_resource, | |
896 | ARRAY_SIZE(atmel_psif0_resource))) | |
897 | goto err_add_resources; | |
898 | atmel_psif0_pclk.dev = &pdev->dev; | |
899 | select_peripheral(PA(8), PERIPH_A, 0); /* CLOCK */ | |
900 | select_peripheral(PA(9), PERIPH_A, 0); /* DATA */ | |
901 | break; | |
902 | case 1: | |
903 | if (platform_device_add_resources(pdev, atmel_psif1_resource, | |
904 | ARRAY_SIZE(atmel_psif1_resource))) | |
905 | goto err_add_resources; | |
906 | atmel_psif1_pclk.dev = &pdev->dev; | |
907 | select_peripheral(PB(11), PERIPH_A, 0); /* CLOCK */ | |
908 | select_peripheral(PB(12), PERIPH_A, 0); /* DATA */ | |
909 | break; | |
910 | default: | |
911 | return NULL; | |
912 | } | |
913 | ||
914 | platform_device_add(pdev); | |
915 | return pdev; | |
916 | ||
917 | err_add_resources: | |
918 | platform_device_put(pdev); | |
919 | return NULL; | |
920 | } | |
921 | ||
5f97f7f9 HS |
922 | /* -------------------------------------------------------------------- |
923 | * USART | |
924 | * -------------------------------------------------------------------- */ | |
925 | ||
75d35213 HS |
926 | static struct atmel_uart_data atmel_usart0_data = { |
927 | .use_dma_tx = 1, | |
928 | .use_dma_rx = 1, | |
929 | }; | |
1e8ea802 | 930 | static struct resource atmel_usart0_resource[] = { |
5f97f7f9 | 931 | PBMEM(0xffe00c00), |
a3d912c8 | 932 | IRQ(6), |
5f97f7f9 | 933 | }; |
75d35213 | 934 | DEFINE_DEV_DATA(atmel_usart, 0); |
80f76c54 | 935 | DEV_CLK(usart, atmel_usart0, pba, 3); |
5f97f7f9 | 936 | |
75d35213 HS |
937 | static struct atmel_uart_data atmel_usart1_data = { |
938 | .use_dma_tx = 1, | |
939 | .use_dma_rx = 1, | |
940 | }; | |
1e8ea802 | 941 | static struct resource atmel_usart1_resource[] = { |
5f97f7f9 HS |
942 | PBMEM(0xffe01000), |
943 | IRQ(7), | |
944 | }; | |
75d35213 | 945 | DEFINE_DEV_DATA(atmel_usart, 1); |
1e8ea802 | 946 | DEV_CLK(usart, atmel_usart1, pba, 4); |
5f97f7f9 | 947 | |
75d35213 HS |
948 | static struct atmel_uart_data atmel_usart2_data = { |
949 | .use_dma_tx = 1, | |
950 | .use_dma_rx = 1, | |
951 | }; | |
1e8ea802 | 952 | static struct resource atmel_usart2_resource[] = { |
5f97f7f9 HS |
953 | PBMEM(0xffe01400), |
954 | IRQ(8), | |
955 | }; | |
75d35213 | 956 | DEFINE_DEV_DATA(atmel_usart, 2); |
1e8ea802 | 957 | DEV_CLK(usart, atmel_usart2, pba, 5); |
5f97f7f9 | 958 | |
75d35213 HS |
959 | static struct atmel_uart_data atmel_usart3_data = { |
960 | .use_dma_tx = 1, | |
961 | .use_dma_rx = 1, | |
962 | }; | |
1e8ea802 | 963 | static struct resource atmel_usart3_resource[] = { |
5f97f7f9 HS |
964 | PBMEM(0xffe01800), |
965 | IRQ(9), | |
966 | }; | |
75d35213 | 967 | DEFINE_DEV_DATA(atmel_usart, 3); |
1e8ea802 | 968 | DEV_CLK(usart, atmel_usart3, pba, 6); |
5f97f7f9 HS |
969 | |
970 | static inline void configure_usart0_pins(void) | |
971 | { | |
c3e2a79c HS |
972 | select_peripheral(PA(8), PERIPH_B, 0); /* RXD */ |
973 | select_peripheral(PA(9), PERIPH_B, 0); /* TXD */ | |
5f97f7f9 HS |
974 | } |
975 | ||
976 | static inline void configure_usart1_pins(void) | |
977 | { | |
c3e2a79c HS |
978 | select_peripheral(PA(17), PERIPH_A, 0); /* RXD */ |
979 | select_peripheral(PA(18), PERIPH_A, 0); /* TXD */ | |
5f97f7f9 HS |
980 | } |
981 | ||
982 | static inline void configure_usart2_pins(void) | |
983 | { | |
c3e2a79c HS |
984 | select_peripheral(PB(26), PERIPH_B, 0); /* RXD */ |
985 | select_peripheral(PB(27), PERIPH_B, 0); /* TXD */ | |
5f97f7f9 HS |
986 | } |
987 | ||
988 | static inline void configure_usart3_pins(void) | |
989 | { | |
c3e2a79c HS |
990 | select_peripheral(PB(18), PERIPH_B, 0); /* RXD */ |
991 | select_peripheral(PB(17), PERIPH_B, 0); /* TXD */ | |
5f97f7f9 HS |
992 | } |
993 | ||
a3d912c8 | 994 | static struct platform_device *__initdata at32_usarts[4]; |
c194588d HS |
995 | |
996 | void __init at32_map_usart(unsigned int hw_id, unsigned int line) | |
5f97f7f9 HS |
997 | { |
998 | struct platform_device *pdev; | |
999 | ||
c194588d | 1000 | switch (hw_id) { |
5f97f7f9 | 1001 | case 0: |
1e8ea802 | 1002 | pdev = &atmel_usart0_device; |
5f97f7f9 HS |
1003 | configure_usart0_pins(); |
1004 | break; | |
1005 | case 1: | |
1e8ea802 | 1006 | pdev = &atmel_usart1_device; |
5f97f7f9 HS |
1007 | configure_usart1_pins(); |
1008 | break; | |
1009 | case 2: | |
1e8ea802 | 1010 | pdev = &atmel_usart2_device; |
5f97f7f9 HS |
1011 | configure_usart2_pins(); |
1012 | break; | |
1013 | case 3: | |
1e8ea802 | 1014 | pdev = &atmel_usart3_device; |
5f97f7f9 HS |
1015 | configure_usart3_pins(); |
1016 | break; | |
1017 | default: | |
c194588d | 1018 | return; |
75d35213 HS |
1019 | } |
1020 | ||
1021 | if (PXSEG(pdev->resource[0].start) == P4SEG) { | |
1022 | /* Addresses in the P4 segment are permanently mapped 1:1 */ | |
1023 | struct atmel_uart_data *data = pdev->dev.platform_data; | |
1024 | data->regs = (void __iomem *)pdev->resource[0].start; | |
5f97f7f9 HS |
1025 | } |
1026 | ||
c194588d HS |
1027 | pdev->id = line; |
1028 | at32_usarts[line] = pdev; | |
5f97f7f9 HS |
1029 | } |
1030 | ||
1031 | struct platform_device *__init at32_add_device_usart(unsigned int id) | |
1032 | { | |
c194588d HS |
1033 | platform_device_register(at32_usarts[id]); |
1034 | return at32_usarts[id]; | |
5f97f7f9 HS |
1035 | } |
1036 | ||
73e2798b | 1037 | struct platform_device *atmel_default_console_device; |
5f97f7f9 HS |
1038 | |
1039 | void __init at32_setup_serial_console(unsigned int usart_id) | |
1040 | { | |
c194588d | 1041 | atmel_default_console_device = at32_usarts[usart_id]; |
5f97f7f9 HS |
1042 | } |
1043 | ||
1044 | /* -------------------------------------------------------------------- | |
1045 | * Ethernet | |
1046 | * -------------------------------------------------------------------- */ | |
1047 | ||
438ff3f3 | 1048 | #ifdef CONFIG_CPU_AT32AP7000 |
5f97f7f9 HS |
1049 | static struct eth_platform_data macb0_data; |
1050 | static struct resource macb0_resource[] = { | |
1051 | PBMEM(0xfff01800), | |
1052 | IRQ(25), | |
1053 | }; | |
1054 | DEFINE_DEV_DATA(macb, 0); | |
1055 | DEV_CLK(hclk, macb0, hsb, 8); | |
1056 | DEV_CLK(pclk, macb0, pbb, 6); | |
1057 | ||
cfcb3a89 HS |
1058 | static struct eth_platform_data macb1_data; |
1059 | static struct resource macb1_resource[] = { | |
1060 | PBMEM(0xfff01c00), | |
1061 | IRQ(26), | |
1062 | }; | |
1063 | DEFINE_DEV_DATA(macb, 1); | |
1064 | DEV_CLK(hclk, macb1, hsb, 9); | |
1065 | DEV_CLK(pclk, macb1, pbb, 7); | |
1066 | ||
5f97f7f9 HS |
1067 | struct platform_device *__init |
1068 | at32_add_device_eth(unsigned int id, struct eth_platform_data *data) | |
1069 | { | |
1070 | struct platform_device *pdev; | |
1071 | ||
1072 | switch (id) { | |
1073 | case 0: | |
1074 | pdev = &macb0_device; | |
1075 | ||
c3e2a79c HS |
1076 | select_peripheral(PC(3), PERIPH_A, 0); /* TXD0 */ |
1077 | select_peripheral(PC(4), PERIPH_A, 0); /* TXD1 */ | |
1078 | select_peripheral(PC(7), PERIPH_A, 0); /* TXEN */ | |
1079 | select_peripheral(PC(8), PERIPH_A, 0); /* TXCK */ | |
1080 | select_peripheral(PC(9), PERIPH_A, 0); /* RXD0 */ | |
1081 | select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */ | |
1082 | select_peripheral(PC(13), PERIPH_A, 0); /* RXER */ | |
1083 | select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */ | |
1084 | select_peripheral(PC(16), PERIPH_A, 0); /* MDC */ | |
1085 | select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */ | |
5f97f7f9 HS |
1086 | |
1087 | if (!data->is_rmii) { | |
c3e2a79c HS |
1088 | select_peripheral(PC(0), PERIPH_A, 0); /* COL */ |
1089 | select_peripheral(PC(1), PERIPH_A, 0); /* CRS */ | |
1090 | select_peripheral(PC(2), PERIPH_A, 0); /* TXER */ | |
1091 | select_peripheral(PC(5), PERIPH_A, 0); /* TXD2 */ | |
1092 | select_peripheral(PC(6), PERIPH_A, 0); /* TXD3 */ | |
1093 | select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */ | |
1094 | select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */ | |
1095 | select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */ | |
1096 | select_peripheral(PC(18), PERIPH_A, 0); /* SPD */ | |
5f97f7f9 HS |
1097 | } |
1098 | break; | |
1099 | ||
cfcb3a89 HS |
1100 | case 1: |
1101 | pdev = &macb1_device; | |
1102 | ||
1103 | select_peripheral(PD(13), PERIPH_B, 0); /* TXD0 */ | |
1104 | select_peripheral(PD(14), PERIPH_B, 0); /* TXD1 */ | |
1105 | select_peripheral(PD(11), PERIPH_B, 0); /* TXEN */ | |
1106 | select_peripheral(PD(12), PERIPH_B, 0); /* TXCK */ | |
1107 | select_peripheral(PD(10), PERIPH_B, 0); /* RXD0 */ | |
1108 | select_peripheral(PD(6), PERIPH_B, 0); /* RXD1 */ | |
1109 | select_peripheral(PD(5), PERIPH_B, 0); /* RXER */ | |
1110 | select_peripheral(PD(4), PERIPH_B, 0); /* RXDV */ | |
1111 | select_peripheral(PD(3), PERIPH_B, 0); /* MDC */ | |
1112 | select_peripheral(PD(2), PERIPH_B, 0); /* MDIO */ | |
1113 | ||
1114 | if (!data->is_rmii) { | |
1115 | select_peripheral(PC(19), PERIPH_B, 0); /* COL */ | |
1116 | select_peripheral(PC(23), PERIPH_B, 0); /* CRS */ | |
1117 | select_peripheral(PC(26), PERIPH_B, 0); /* TXER */ | |
1118 | select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */ | |
1119 | select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */ | |
1120 | select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */ | |
1121 | select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */ | |
1122 | select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */ | |
1123 | select_peripheral(PD(15), PERIPH_B, 0); /* SPD */ | |
1124 | } | |
1125 | break; | |
1126 | ||
5f97f7f9 HS |
1127 | default: |
1128 | return NULL; | |
1129 | } | |
1130 | ||
1131 | memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data)); | |
1132 | platform_device_register(pdev); | |
1133 | ||
1134 | return pdev; | |
1135 | } | |
438ff3f3 | 1136 | #endif |
5f97f7f9 HS |
1137 | |
1138 | /* -------------------------------------------------------------------- | |
1139 | * SPI | |
1140 | * -------------------------------------------------------------------- */ | |
3d60ee1b | 1141 | static struct resource atmel_spi0_resource[] = { |
5f97f7f9 HS |
1142 | PBMEM(0xffe00000), |
1143 | IRQ(3), | |
1144 | }; | |
3d60ee1b HS |
1145 | DEFINE_DEV(atmel_spi, 0); |
1146 | DEV_CLK(spi_clk, atmel_spi0, pba, 0); | |
1147 | ||
1148 | static struct resource atmel_spi1_resource[] = { | |
1149 | PBMEM(0xffe00400), | |
1150 | IRQ(4), | |
1151 | }; | |
1152 | DEFINE_DEV(atmel_spi, 1); | |
1153 | DEV_CLK(spi_clk, atmel_spi1, pba, 1); | |
5f97f7f9 | 1154 | |
9a596a62 | 1155 | static void __init |
41d8ca45 HS |
1156 | at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, |
1157 | unsigned int n, const u8 *pins) | |
5f97f7f9 | 1158 | { |
41d8ca45 HS |
1159 | unsigned int pin, mode; |
1160 | ||
1161 | for (; n; n--, b++) { | |
1162 | b->bus_num = bus_num; | |
1163 | if (b->chip_select >= 4) | |
1164 | continue; | |
1165 | pin = (unsigned)b->controller_data; | |
1166 | if (!pin) { | |
1167 | pin = pins[b->chip_select]; | |
1168 | b->controller_data = (void *)pin; | |
1169 | } | |
1170 | mode = AT32_GPIOF_OUTPUT; | |
1171 | if (!(b->mode & SPI_CS_HIGH)) | |
1172 | mode |= AT32_GPIOF_HIGH; | |
1173 | at32_select_gpio(pin, mode); | |
1174 | } | |
1175 | } | |
1176 | ||
1177 | struct platform_device *__init | |
1178 | at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n) | |
1179 | { | |
1180 | /* | |
1181 | * Manage the chipselects as GPIOs, normally using the same pins | |
1182 | * the SPI controller expects; but boards can use other pins. | |
1183 | */ | |
1184 | static u8 __initdata spi0_pins[] = | |
1185 | { GPIO_PIN_PA(3), GPIO_PIN_PA(4), | |
1186 | GPIO_PIN_PA(5), GPIO_PIN_PA(20), }; | |
1187 | static u8 __initdata spi1_pins[] = | |
1188 | { GPIO_PIN_PB(2), GPIO_PIN_PB(3), | |
1189 | GPIO_PIN_PB(4), GPIO_PIN_PA(27), }; | |
5f97f7f9 HS |
1190 | struct platform_device *pdev; |
1191 | ||
1192 | switch (id) { | |
1193 | case 0: | |
3d60ee1b | 1194 | pdev = &atmel_spi0_device; |
9c2baf78 DB |
1195 | /* pullup MISO so a level is always defined */ |
1196 | select_peripheral(PA(0), PERIPH_A, AT32_GPIOF_PULLUP); | |
c3e2a79c HS |
1197 | select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */ |
1198 | select_peripheral(PA(2), PERIPH_A, 0); /* SCK */ | |
41d8ca45 | 1199 | at32_spi_setup_slaves(0, b, n, spi0_pins); |
3d60ee1b HS |
1200 | break; |
1201 | ||
1202 | case 1: | |
1203 | pdev = &atmel_spi1_device; | |
9c2baf78 DB |
1204 | /* pullup MISO so a level is always defined */ |
1205 | select_peripheral(PB(0), PERIPH_B, AT32_GPIOF_PULLUP); | |
3d60ee1b HS |
1206 | select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */ |
1207 | select_peripheral(PB(5), PERIPH_B, 0); /* SCK */ | |
41d8ca45 | 1208 | at32_spi_setup_slaves(1, b, n, spi1_pins); |
5f97f7f9 HS |
1209 | break; |
1210 | ||
1211 | default: | |
1212 | return NULL; | |
1213 | } | |
1214 | ||
41d8ca45 | 1215 | spi_register_board_info(b, n); |
5f97f7f9 HS |
1216 | platform_device_register(pdev); |
1217 | return pdev; | |
1218 | } | |
1219 | ||
2042c1c4 HS |
1220 | /* -------------------------------------------------------------------- |
1221 | * TWI | |
1222 | * -------------------------------------------------------------------- */ | |
1223 | static struct resource atmel_twi0_resource[] __initdata = { | |
1224 | PBMEM(0xffe00800), | |
1225 | IRQ(5), | |
1226 | }; | |
1227 | static struct clk atmel_twi0_pclk = { | |
1228 | .name = "twi_pclk", | |
1229 | .parent = &pba_clk, | |
1230 | .mode = pba_clk_mode, | |
1231 | .get_rate = pba_clk_get_rate, | |
1232 | .index = 2, | |
1233 | }; | |
1234 | ||
040b28fc BN |
1235 | struct platform_device *__init at32_add_device_twi(unsigned int id, |
1236 | struct i2c_board_info *b, | |
1237 | unsigned int n) | |
2042c1c4 HS |
1238 | { |
1239 | struct platform_device *pdev; | |
1240 | ||
1241 | if (id != 0) | |
1242 | return NULL; | |
1243 | ||
1244 | pdev = platform_device_alloc("atmel_twi", id); | |
1245 | if (!pdev) | |
1246 | return NULL; | |
1247 | ||
1248 | if (platform_device_add_resources(pdev, atmel_twi0_resource, | |
1249 | ARRAY_SIZE(atmel_twi0_resource))) | |
1250 | goto err_add_resources; | |
1251 | ||
1252 | select_peripheral(PA(6), PERIPH_A, 0); /* SDA */ | |
1253 | select_peripheral(PA(7), PERIPH_A, 0); /* SDL */ | |
1254 | ||
1255 | atmel_twi0_pclk.dev = &pdev->dev; | |
1256 | ||
040b28fc BN |
1257 | if (b) |
1258 | i2c_register_board_info(id, b, n); | |
1259 | ||
2042c1c4 HS |
1260 | platform_device_add(pdev); |
1261 | return pdev; | |
1262 | ||
1263 | err_add_resources: | |
1264 | platform_device_put(pdev); | |
1265 | return NULL; | |
1266 | } | |
1267 | ||
1268 | /* -------------------------------------------------------------------- | |
1269 | * MMC | |
1270 | * -------------------------------------------------------------------- */ | |
1271 | static struct resource atmel_mci0_resource[] __initdata = { | |
1272 | PBMEM(0xfff02400), | |
1273 | IRQ(28), | |
1274 | }; | |
1275 | static struct clk atmel_mci0_pclk = { | |
1276 | .name = "mci_clk", | |
1277 | .parent = &pbb_clk, | |
1278 | .mode = pbb_clk_mode, | |
1279 | .get_rate = pbb_clk_get_rate, | |
1280 | .index = 9, | |
1281 | }; | |
1282 | ||
7d2be074 HS |
1283 | struct platform_device *__init |
1284 | at32_add_device_mci(unsigned int id, struct mci_platform_data *data) | |
2042c1c4 | 1285 | { |
7d2be074 HS |
1286 | struct mci_platform_data _data; |
1287 | struct platform_device *pdev; | |
2042c1c4 HS |
1288 | |
1289 | if (id != 0) | |
1290 | return NULL; | |
1291 | ||
1292 | pdev = platform_device_alloc("atmel_mci", id); | |
1293 | if (!pdev) | |
7d2be074 | 1294 | goto fail; |
2042c1c4 HS |
1295 | |
1296 | if (platform_device_add_resources(pdev, atmel_mci0_resource, | |
1297 | ARRAY_SIZE(atmel_mci0_resource))) | |
7d2be074 HS |
1298 | goto fail; |
1299 | ||
1300 | if (!data) { | |
1301 | data = &_data; | |
1302 | memset(data, 0, sizeof(struct mci_platform_data)); | |
fbfca4b8 BN |
1303 | data->detect_pin = GPIO_PIN_NONE; |
1304 | data->wp_pin = GPIO_PIN_NONE; | |
7d2be074 HS |
1305 | } |
1306 | ||
1307 | if (platform_device_add_data(pdev, data, | |
1308 | sizeof(struct mci_platform_data))) | |
1309 | goto fail; | |
2042c1c4 HS |
1310 | |
1311 | select_peripheral(PA(10), PERIPH_A, 0); /* CLK */ | |
1312 | select_peripheral(PA(11), PERIPH_A, 0); /* CMD */ | |
1313 | select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */ | |
1314 | select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */ | |
1315 | select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */ | |
1316 | select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */ | |
1317 | ||
fbfca4b8 BN |
1318 | if (data->detect_pin != GPIO_PIN_NONE) |
1319 | at32_select_gpio(data->detect_pin, 0); | |
1320 | if (data->wp_pin != GPIO_PIN_NONE) | |
1321 | at32_select_gpio(data->wp_pin, 0); | |
7d2be074 | 1322 | |
2042c1c4 HS |
1323 | atmel_mci0_pclk.dev = &pdev->dev; |
1324 | ||
1325 | platform_device_add(pdev); | |
1326 | return pdev; | |
1327 | ||
7d2be074 | 1328 | fail: |
2042c1c4 HS |
1329 | platform_device_put(pdev); |
1330 | return NULL; | |
1331 | } | |
1332 | ||
5f97f7f9 HS |
1333 | /* -------------------------------------------------------------------- |
1334 | * LCDC | |
1335 | * -------------------------------------------------------------------- */ | |
438ff3f3 | 1336 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002) |
d0a2b7af HS |
1337 | static struct atmel_lcdfb_info atmel_lcdfb0_data; |
1338 | static struct resource atmel_lcdfb0_resource[] = { | |
5f97f7f9 HS |
1339 | { |
1340 | .start = 0xff000000, | |
1341 | .end = 0xff000fff, | |
1342 | .flags = IORESOURCE_MEM, | |
1343 | }, | |
1344 | IRQ(1), | |
d0a2b7af HS |
1345 | { |
1346 | /* Placeholder for pre-allocated fb memory */ | |
1347 | .start = 0x00000000, | |
1348 | .end = 0x00000000, | |
1349 | .flags = 0, | |
1350 | }, | |
5f97f7f9 | 1351 | }; |
d0a2b7af HS |
1352 | DEFINE_DEV_DATA(atmel_lcdfb, 0); |
1353 | DEV_CLK(hck1, atmel_lcdfb0, hsb, 7); | |
1354 | static struct clk atmel_lcdfb0_pixclk = { | |
1355 | .name = "lcdc_clk", | |
1356 | .dev = &atmel_lcdfb0_device.dev, | |
5f97f7f9 HS |
1357 | .mode = genclk_mode, |
1358 | .get_rate = genclk_get_rate, | |
1359 | .set_rate = genclk_set_rate, | |
1360 | .set_parent = genclk_set_parent, | |
1361 | .index = 7, | |
1362 | }; | |
1363 | ||
1364 | struct platform_device *__init | |
d0a2b7af | 1365 | at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data, |
47882cf6 HCE |
1366 | unsigned long fbmem_start, unsigned long fbmem_len, |
1367 | unsigned int pin_config) | |
5f97f7f9 HS |
1368 | { |
1369 | struct platform_device *pdev; | |
d0a2b7af HS |
1370 | struct atmel_lcdfb_info *info; |
1371 | struct fb_monspecs *monspecs; | |
1372 | struct fb_videomode *modedb; | |
1373 | unsigned int modedb_size; | |
1374 | ||
1375 | /* | |
1376 | * Do a deep copy of the fb data, monspecs and modedb. Make | |
1377 | * sure all allocations are done before setting up the | |
1378 | * portmux. | |
1379 | */ | |
1380 | monspecs = kmemdup(data->default_monspecs, | |
1381 | sizeof(struct fb_monspecs), GFP_KERNEL); | |
1382 | if (!monspecs) | |
1383 | return NULL; | |
1384 | ||
1385 | modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len; | |
1386 | modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL); | |
1387 | if (!modedb) | |
1388 | goto err_dup_modedb; | |
1389 | monspecs->modedb = modedb; | |
5f97f7f9 HS |
1390 | |
1391 | switch (id) { | |
1392 | case 0: | |
d0a2b7af | 1393 | pdev = &atmel_lcdfb0_device; |
47882cf6 HCE |
1394 | |
1395 | switch (pin_config) { | |
1396 | case 0: | |
1397 | select_peripheral(PC(19), PERIPH_A, 0); /* CC */ | |
1398 | select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */ | |
1399 | select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */ | |
1400 | select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */ | |
1401 | select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */ | |
1402 | select_peripheral(PC(24), PERIPH_A, 0); /* MODE */ | |
1403 | select_peripheral(PC(25), PERIPH_A, 0); /* PWR */ | |
1404 | select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */ | |
1405 | select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */ | |
1406 | select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */ | |
1407 | select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */ | |
1408 | select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */ | |
1409 | select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */ | |
1410 | select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */ | |
1411 | select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */ | |
1412 | select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */ | |
1413 | select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */ | |
1414 | select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */ | |
1415 | select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */ | |
1416 | select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */ | |
1417 | select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */ | |
1418 | select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */ | |
1419 | select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */ | |
1420 | select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */ | |
1421 | select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */ | |
1422 | select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */ | |
1423 | select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */ | |
1424 | select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */ | |
1425 | select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */ | |
1426 | select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */ | |
1427 | select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */ | |
1428 | break; | |
1429 | case 1: | |
1430 | select_peripheral(PE(0), PERIPH_B, 0); /* CC */ | |
1431 | select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */ | |
1432 | select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */ | |
1433 | select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */ | |
1434 | select_peripheral(PE(1), PERIPH_B, 0); /* DVAL */ | |
1435 | select_peripheral(PE(2), PERIPH_B, 0); /* MODE */ | |
1436 | select_peripheral(PC(25), PERIPH_A, 0); /* PWR */ | |
1437 | select_peripheral(PE(3), PERIPH_B, 0); /* DATA0 */ | |
1438 | select_peripheral(PE(4), PERIPH_B, 0); /* DATA1 */ | |
1439 | select_peripheral(PE(5), PERIPH_B, 0); /* DATA2 */ | |
1440 | select_peripheral(PE(6), PERIPH_B, 0); /* DATA3 */ | |
1441 | select_peripheral(PE(7), PERIPH_B, 0); /* DATA4 */ | |
1442 | select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */ | |
1443 | select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */ | |
1444 | select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */ | |
1445 | select_peripheral(PE(8), PERIPH_B, 0); /* DATA8 */ | |
1446 | select_peripheral(PE(9), PERIPH_B, 0); /* DATA9 */ | |
1447 | select_peripheral(PE(10), PERIPH_B, 0); /* DATA10 */ | |
1448 | select_peripheral(PE(11), PERIPH_B, 0); /* DATA11 */ | |
1449 | select_peripheral(PE(12), PERIPH_B, 0); /* DATA12 */ | |
1450 | select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */ | |
1451 | select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */ | |
1452 | select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */ | |
1453 | select_peripheral(PE(13), PERIPH_B, 0); /* DATA16 */ | |
1454 | select_peripheral(PE(14), PERIPH_B, 0); /* DATA17 */ | |
1455 | select_peripheral(PE(15), PERIPH_B, 0); /* DATA18 */ | |
1456 | select_peripheral(PE(16), PERIPH_B, 0); /* DATA19 */ | |
1457 | select_peripheral(PE(17), PERIPH_B, 0); /* DATA20 */ | |
1458 | select_peripheral(PE(18), PERIPH_B, 0); /* DATA21 */ | |
1459 | select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */ | |
1460 | select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */ | |
1461 | break; | |
1462 | default: | |
1463 | goto err_invalid_id; | |
1464 | } | |
5f97f7f9 | 1465 | |
d0a2b7af HS |
1466 | clk_set_parent(&atmel_lcdfb0_pixclk, &pll0); |
1467 | clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0)); | |
5f97f7f9 HS |
1468 | break; |
1469 | ||
1470 | default: | |
d0a2b7af | 1471 | goto err_invalid_id; |
5f97f7f9 HS |
1472 | } |
1473 | ||
d0a2b7af HS |
1474 | if (fbmem_len) { |
1475 | pdev->resource[2].start = fbmem_start; | |
1476 | pdev->resource[2].end = fbmem_start + fbmem_len - 1; | |
1477 | pdev->resource[2].flags = IORESOURCE_MEM; | |
1478 | } | |
1479 | ||
1480 | info = pdev->dev.platform_data; | |
1481 | memcpy(info, data, sizeof(struct atmel_lcdfb_info)); | |
1482 | info->default_monspecs = monspecs; | |
5f97f7f9 HS |
1483 | |
1484 | platform_device_register(pdev); | |
1485 | return pdev; | |
d0a2b7af HS |
1486 | |
1487 | err_invalid_id: | |
1488 | kfree(modedb); | |
1489 | err_dup_modedb: | |
1490 | kfree(monspecs); | |
1491 | return NULL; | |
5f97f7f9 | 1492 | } |
438ff3f3 | 1493 | #endif |
5f97f7f9 | 1494 | |
9a1e8eb1 DB |
1495 | /* -------------------------------------------------------------------- |
1496 | * PWM | |
1497 | * -------------------------------------------------------------------- */ | |
1498 | static struct resource atmel_pwm0_resource[] __initdata = { | |
1499 | PBMEM(0xfff01400), | |
1500 | IRQ(24), | |
1501 | }; | |
1502 | static struct clk atmel_pwm0_mck = { | |
8405996f | 1503 | .name = "pwm_clk", |
9a1e8eb1 DB |
1504 | .parent = &pbb_clk, |
1505 | .mode = pbb_clk_mode, | |
1506 | .get_rate = pbb_clk_get_rate, | |
1507 | .index = 5, | |
1508 | }; | |
1509 | ||
1510 | struct platform_device *__init at32_add_device_pwm(u32 mask) | |
1511 | { | |
1512 | struct platform_device *pdev; | |
1513 | ||
1514 | if (!mask) | |
1515 | return NULL; | |
1516 | ||
1517 | pdev = platform_device_alloc("atmel_pwm", 0); | |
1518 | if (!pdev) | |
1519 | return NULL; | |
1520 | ||
1521 | if (platform_device_add_resources(pdev, atmel_pwm0_resource, | |
1522 | ARRAY_SIZE(atmel_pwm0_resource))) | |
1523 | goto out_free_pdev; | |
1524 | ||
1525 | if (platform_device_add_data(pdev, &mask, sizeof(mask))) | |
1526 | goto out_free_pdev; | |
1527 | ||
1528 | if (mask & (1 << 0)) | |
1529 | select_peripheral(PA(28), PERIPH_A, 0); | |
1530 | if (mask & (1 << 1)) | |
1531 | select_peripheral(PA(29), PERIPH_A, 0); | |
1532 | if (mask & (1 << 2)) | |
1533 | select_peripheral(PA(21), PERIPH_B, 0); | |
1534 | if (mask & (1 << 3)) | |
1535 | select_peripheral(PA(22), PERIPH_B, 0); | |
1536 | ||
1537 | atmel_pwm0_mck.dev = &pdev->dev; | |
1538 | ||
1539 | platform_device_add(pdev); | |
1540 | ||
1541 | return pdev; | |
1542 | ||
1543 | out_free_pdev: | |
1544 | platform_device_put(pdev); | |
1545 | return NULL; | |
1546 | } | |
1547 | ||
9cf6cf58 HCE |
1548 | /* -------------------------------------------------------------------- |
1549 | * SSC | |
1550 | * -------------------------------------------------------------------- */ | |
1551 | static struct resource ssc0_resource[] = { | |
1552 | PBMEM(0xffe01c00), | |
1553 | IRQ(10), | |
1554 | }; | |
1555 | DEFINE_DEV(ssc, 0); | |
1556 | DEV_CLK(pclk, ssc0, pba, 7); | |
1557 | ||
1558 | static struct resource ssc1_resource[] = { | |
1559 | PBMEM(0xffe02000), | |
1560 | IRQ(11), | |
1561 | }; | |
1562 | DEFINE_DEV(ssc, 1); | |
1563 | DEV_CLK(pclk, ssc1, pba, 8); | |
1564 | ||
1565 | static struct resource ssc2_resource[] = { | |
1566 | PBMEM(0xffe02400), | |
1567 | IRQ(12), | |
1568 | }; | |
1569 | DEFINE_DEV(ssc, 2); | |
1570 | DEV_CLK(pclk, ssc2, pba, 9); | |
1571 | ||
1572 | struct platform_device *__init | |
1573 | at32_add_device_ssc(unsigned int id, unsigned int flags) | |
1574 | { | |
1575 | struct platform_device *pdev; | |
1576 | ||
1577 | switch (id) { | |
1578 | case 0: | |
1579 | pdev = &ssc0_device; | |
1580 | if (flags & ATMEL_SSC_RF) | |
1581 | select_peripheral(PA(21), PERIPH_A, 0); /* RF */ | |
1582 | if (flags & ATMEL_SSC_RK) | |
1583 | select_peripheral(PA(22), PERIPH_A, 0); /* RK */ | |
1584 | if (flags & ATMEL_SSC_TK) | |
1585 | select_peripheral(PA(23), PERIPH_A, 0); /* TK */ | |
1586 | if (flags & ATMEL_SSC_TF) | |
1587 | select_peripheral(PA(24), PERIPH_A, 0); /* TF */ | |
1588 | if (flags & ATMEL_SSC_TD) | |
1589 | select_peripheral(PA(25), PERIPH_A, 0); /* TD */ | |
1590 | if (flags & ATMEL_SSC_RD) | |
1591 | select_peripheral(PA(26), PERIPH_A, 0); /* RD */ | |
1592 | break; | |
1593 | case 1: | |
1594 | pdev = &ssc1_device; | |
1595 | if (flags & ATMEL_SSC_RF) | |
1596 | select_peripheral(PA(0), PERIPH_B, 0); /* RF */ | |
1597 | if (flags & ATMEL_SSC_RK) | |
1598 | select_peripheral(PA(1), PERIPH_B, 0); /* RK */ | |
1599 | if (flags & ATMEL_SSC_TK) | |
1600 | select_peripheral(PA(2), PERIPH_B, 0); /* TK */ | |
1601 | if (flags & ATMEL_SSC_TF) | |
1602 | select_peripheral(PA(3), PERIPH_B, 0); /* TF */ | |
1603 | if (flags & ATMEL_SSC_TD) | |
1604 | select_peripheral(PA(4), PERIPH_B, 0); /* TD */ | |
1605 | if (flags & ATMEL_SSC_RD) | |
1606 | select_peripheral(PA(5), PERIPH_B, 0); /* RD */ | |
1607 | break; | |
1608 | case 2: | |
1609 | pdev = &ssc2_device; | |
1610 | if (flags & ATMEL_SSC_TD) | |
1611 | select_peripheral(PB(13), PERIPH_A, 0); /* TD */ | |
1612 | if (flags & ATMEL_SSC_RD) | |
1613 | select_peripheral(PB(14), PERIPH_A, 0); /* RD */ | |
1614 | if (flags & ATMEL_SSC_TK) | |
1615 | select_peripheral(PB(15), PERIPH_A, 0); /* TK */ | |
1616 | if (flags & ATMEL_SSC_TF) | |
1617 | select_peripheral(PB(16), PERIPH_A, 0); /* TF */ | |
1618 | if (flags & ATMEL_SSC_RF) | |
1619 | select_peripheral(PB(17), PERIPH_A, 0); /* RF */ | |
1620 | if (flags & ATMEL_SSC_RK) | |
1621 | select_peripheral(PB(18), PERIPH_A, 0); /* RK */ | |
1622 | break; | |
1623 | default: | |
1624 | return NULL; | |
1625 | } | |
1626 | ||
1627 | platform_device_register(pdev); | |
1628 | return pdev; | |
1629 | } | |
1630 | ||
6fcf0615 HS |
1631 | /* -------------------------------------------------------------------- |
1632 | * USB Device Controller | |
1633 | * -------------------------------------------------------------------- */ | |
1634 | static struct resource usba0_resource[] __initdata = { | |
1635 | { | |
1636 | .start = 0xff300000, | |
1637 | .end = 0xff3fffff, | |
1638 | .flags = IORESOURCE_MEM, | |
1639 | }, { | |
1640 | .start = 0xfff03000, | |
1641 | .end = 0xfff033ff, | |
1642 | .flags = IORESOURCE_MEM, | |
1643 | }, | |
1644 | IRQ(31), | |
1645 | }; | |
1646 | static struct clk usba0_pclk = { | |
1647 | .name = "pclk", | |
1648 | .parent = &pbb_clk, | |
1649 | .mode = pbb_clk_mode, | |
1650 | .get_rate = pbb_clk_get_rate, | |
1651 | .index = 12, | |
1652 | }; | |
1653 | static struct clk usba0_hclk = { | |
1654 | .name = "hclk", | |
1655 | .parent = &hsb_clk, | |
1656 | .mode = hsb_clk_mode, | |
1657 | .get_rate = hsb_clk_get_rate, | |
1658 | .index = 6, | |
1659 | }; | |
1660 | ||
8d855317 SP |
1661 | #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \ |
1662 | [idx] = { \ | |
1663 | .name = nam, \ | |
1664 | .index = idx, \ | |
1665 | .fifo_size = maxpkt, \ | |
1666 | .nr_banks = maxbk, \ | |
1667 | .can_dma = dma, \ | |
1668 | .can_isoc = isoc, \ | |
1669 | } | |
1670 | ||
1671 | static struct usba_ep_data at32_usba_ep[] __initdata = { | |
1672 | EP("ep0", 0, 64, 1, 0, 0), | |
1673 | EP("ep1", 1, 512, 2, 1, 1), | |
1674 | EP("ep2", 2, 512, 2, 1, 1), | |
1675 | EP("ep3-int", 3, 64, 3, 1, 0), | |
1676 | EP("ep4-int", 4, 64, 3, 1, 0), | |
1677 | EP("ep5", 5, 1024, 3, 1, 1), | |
1678 | EP("ep6", 6, 1024, 3, 1, 1), | |
1679 | }; | |
1680 | ||
1681 | #undef EP | |
1682 | ||
6fcf0615 HS |
1683 | struct platform_device *__init |
1684 | at32_add_device_usba(unsigned int id, struct usba_platform_data *data) | |
1685 | { | |
8d855317 SP |
1686 | /* |
1687 | * pdata doesn't have room for any endpoints, so we need to | |
1688 | * append room for the ones we need right after it. | |
1689 | */ | |
1690 | struct { | |
1691 | struct usba_platform_data pdata; | |
1692 | struct usba_ep_data ep[7]; | |
1693 | } usba_data; | |
6fcf0615 HS |
1694 | struct platform_device *pdev; |
1695 | ||
1696 | if (id != 0) | |
1697 | return NULL; | |
1698 | ||
1699 | pdev = platform_device_alloc("atmel_usba_udc", 0); | |
1700 | if (!pdev) | |
1701 | return NULL; | |
1702 | ||
1703 | if (platform_device_add_resources(pdev, usba0_resource, | |
1704 | ARRAY_SIZE(usba0_resource))) | |
1705 | goto out_free_pdev; | |
1706 | ||
8d855317 SP |
1707 | if (data) |
1708 | usba_data.pdata.vbus_pin = data->vbus_pin; | |
1709 | else | |
1710 | usba_data.pdata.vbus_pin = -EINVAL; | |
6fcf0615 | 1711 | |
8d855317 SP |
1712 | data = &usba_data.pdata; |
1713 | data->num_ep = ARRAY_SIZE(at32_usba_ep); | |
1714 | memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep)); | |
1715 | ||
1716 | if (platform_device_add_data(pdev, data, sizeof(usba_data))) | |
1717 | goto out_free_pdev; | |
1718 | ||
1719 | if (data->vbus_pin >= 0) | |
1720 | at32_select_gpio(data->vbus_pin, 0); | |
6fcf0615 HS |
1721 | |
1722 | usba0_pclk.dev = &pdev->dev; | |
1723 | usba0_hclk.dev = &pdev->dev; | |
1724 | ||
1725 | platform_device_add(pdev); | |
1726 | ||
1727 | return pdev; | |
1728 | ||
1729 | out_free_pdev: | |
1730 | platform_device_put(pdev); | |
1731 | return NULL; | |
1732 | } | |
1733 | ||
48021bd9 | 1734 | /* -------------------------------------------------------------------- |
eaf5f925 | 1735 | * IDE / CompactFlash |
48021bd9 | 1736 | * -------------------------------------------------------------------- */ |
438ff3f3 | 1737 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001) |
eaf5f925 | 1738 | static struct resource at32_smc_cs4_resource[] __initdata = { |
48021bd9 KNG |
1739 | { |
1740 | .start = 0x04000000, | |
1741 | .end = 0x07ffffff, | |
1742 | .flags = IORESOURCE_MEM, | |
1743 | }, | |
1744 | IRQ(~0UL), /* Magic IRQ will be overridden */ | |
1745 | }; | |
eaf5f925 HS |
1746 | static struct resource at32_smc_cs5_resource[] __initdata = { |
1747 | { | |
1748 | .start = 0x20000000, | |
1749 | .end = 0x23ffffff, | |
1750 | .flags = IORESOURCE_MEM, | |
1751 | }, | |
1752 | IRQ(~0UL), /* Magic IRQ will be overridden */ | |
1753 | }; | |
48021bd9 | 1754 | |
eaf5f925 HS |
1755 | static int __init at32_init_ide_or_cf(struct platform_device *pdev, |
1756 | unsigned int cs, unsigned int extint) | |
48021bd9 | 1757 | { |
eaf5f925 HS |
1758 | static unsigned int extint_pin_map[4] __initdata = { |
1759 | GPIO_PIN_PB(25), | |
1760 | GPIO_PIN_PB(26), | |
1761 | GPIO_PIN_PB(27), | |
1762 | GPIO_PIN_PB(28), | |
1763 | }; | |
1764 | static bool common_pins_initialized __initdata = false; | |
48021bd9 | 1765 | unsigned int extint_pin; |
eaf5f925 | 1766 | int ret; |
48021bd9 | 1767 | |
eaf5f925 HS |
1768 | if (extint >= ARRAY_SIZE(extint_pin_map)) |
1769 | return -EINVAL; | |
1770 | extint_pin = extint_pin_map[extint]; | |
1771 | ||
1772 | switch (cs) { | |
1773 | case 4: | |
1774 | ret = platform_device_add_resources(pdev, | |
1775 | at32_smc_cs4_resource, | |
1776 | ARRAY_SIZE(at32_smc_cs4_resource)); | |
1777 | if (ret) | |
1778 | return ret; | |
1779 | ||
1780 | select_peripheral(PE(21), PERIPH_A, 0); /* NCS4 -> OE_N */ | |
1781 | set_ebi_sfr_bits(HMATRIX_BIT(CS4A)); | |
48021bd9 | 1782 | break; |
eaf5f925 HS |
1783 | case 5: |
1784 | ret = platform_device_add_resources(pdev, | |
1785 | at32_smc_cs5_resource, | |
1786 | ARRAY_SIZE(at32_smc_cs5_resource)); | |
1787 | if (ret) | |
1788 | return ret; | |
1789 | ||
1790 | select_peripheral(PE(22), PERIPH_A, 0); /* NCS5 -> OE_N */ | |
1791 | set_ebi_sfr_bits(HMATRIX_BIT(CS5A)); | |
48021bd9 KNG |
1792 | break; |
1793 | default: | |
eaf5f925 | 1794 | return -EINVAL; |
48021bd9 KNG |
1795 | } |
1796 | ||
eaf5f925 | 1797 | if (!common_pins_initialized) { |
48021bd9 KNG |
1798 | select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1 -> CS0_N */ |
1799 | select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2 -> CS1_N */ | |
48021bd9 KNG |
1800 | select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW -> DIR */ |
1801 | select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT <- IORDY */ | |
eaf5f925 | 1802 | common_pins_initialized = true; |
48021bd9 KNG |
1803 | } |
1804 | ||
1805 | at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH); | |
1806 | ||
1807 | pdev->resource[1].start = EIM_IRQ_BASE + extint; | |
1808 | pdev->resource[1].end = pdev->resource[1].start; | |
1809 | ||
eaf5f925 HS |
1810 | return 0; |
1811 | } | |
48021bd9 | 1812 | |
eaf5f925 HS |
1813 | struct platform_device *__init |
1814 | at32_add_device_ide(unsigned int id, unsigned int extint, | |
1815 | struct ide_platform_data *data) | |
1816 | { | |
1817 | struct platform_device *pdev; | |
1818 | ||
1819 | pdev = platform_device_alloc("at32_ide", id); | |
1820 | if (!pdev) | |
1821 | goto fail; | |
1822 | ||
1823 | if (platform_device_add_data(pdev, data, | |
1824 | sizeof(struct ide_platform_data))) | |
1825 | goto fail; | |
1826 | ||
1827 | if (at32_init_ide_or_cf(pdev, data->cs, extint)) | |
1828 | goto fail; | |
1829 | ||
1830 | platform_device_add(pdev); | |
1831 | return pdev; | |
1832 | ||
1833 | fail: | |
1834 | platform_device_put(pdev); | |
1835 | return NULL; | |
1836 | } | |
1837 | ||
1838 | struct platform_device *__init | |
1839 | at32_add_device_cf(unsigned int id, unsigned int extint, | |
1840 | struct cf_platform_data *data) | |
1841 | { | |
1842 | struct platform_device *pdev; | |
1843 | ||
1844 | pdev = platform_device_alloc("at32_cf", id); | |
1845 | if (!pdev) | |
1846 | goto fail; | |
48021bd9 | 1847 | |
eaf5f925 HS |
1848 | if (platform_device_add_data(pdev, data, |
1849 | sizeof(struct cf_platform_data))) | |
1850 | goto fail; | |
1851 | ||
1852 | if (at32_init_ide_or_cf(pdev, data->cs, extint)) | |
1853 | goto fail; | |
1854 | ||
1855 | if (data->detect_pin != GPIO_PIN_NONE) | |
1856 | at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH); | |
1857 | if (data->reset_pin != GPIO_PIN_NONE) | |
1858 | at32_select_gpio(data->reset_pin, 0); | |
1859 | if (data->vcc_pin != GPIO_PIN_NONE) | |
1860 | at32_select_gpio(data->vcc_pin, 0); | |
1861 | /* READY is used as extint, so we can't select it as gpio */ | |
1862 | ||
1863 | platform_device_add(pdev); | |
48021bd9 | 1864 | return pdev; |
eaf5f925 HS |
1865 | |
1866 | fail: | |
1867 | platform_device_put(pdev); | |
1868 | return NULL; | |
48021bd9 | 1869 | } |
438ff3f3 | 1870 | #endif |
48021bd9 | 1871 | |
62090a08 HS |
1872 | /* -------------------------------------------------------------------- |
1873 | * NAND Flash / SmartMedia | |
1874 | * -------------------------------------------------------------------- */ | |
1875 | static struct resource smc_cs3_resource[] __initdata = { | |
1876 | { | |
1877 | .start = 0x0c000000, | |
1878 | .end = 0x0fffffff, | |
1879 | .flags = IORESOURCE_MEM, | |
1880 | }, { | |
1881 | .start = 0xfff03c00, | |
1882 | .end = 0xfff03fff, | |
1883 | .flags = IORESOURCE_MEM, | |
1884 | }, | |
1885 | }; | |
1886 | ||
1887 | struct platform_device *__init | |
1888 | at32_add_device_nand(unsigned int id, struct atmel_nand_data *data) | |
1889 | { | |
1890 | struct platform_device *pdev; | |
1891 | ||
1892 | if (id != 0 || !data) | |
1893 | return NULL; | |
1894 | ||
1895 | pdev = platform_device_alloc("atmel_nand", id); | |
1896 | if (!pdev) | |
1897 | goto fail; | |
1898 | ||
1899 | if (platform_device_add_resources(pdev, smc_cs3_resource, | |
1900 | ARRAY_SIZE(smc_cs3_resource))) | |
1901 | goto fail; | |
1902 | ||
1903 | if (platform_device_add_data(pdev, data, | |
1904 | sizeof(struct atmel_nand_data))) | |
1905 | goto fail; | |
1906 | ||
1907 | set_ebi_sfr_bits(HMATRIX_BIT(CS3A)); | |
1908 | if (data->enable_pin) | |
1909 | at32_select_gpio(data->enable_pin, | |
1910 | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH); | |
1911 | if (data->rdy_pin) | |
1912 | at32_select_gpio(data->rdy_pin, 0); | |
1913 | if (data->det_pin) | |
1914 | at32_select_gpio(data->det_pin, 0); | |
1915 | ||
1916 | platform_device_add(pdev); | |
1917 | return pdev; | |
1918 | ||
1919 | fail: | |
1920 | platform_device_put(pdev); | |
1921 | return NULL; | |
1922 | } | |
1923 | ||
2042c1c4 HS |
1924 | /* -------------------------------------------------------------------- |
1925 | * AC97C | |
1926 | * -------------------------------------------------------------------- */ | |
1927 | static struct resource atmel_ac97c0_resource[] __initdata = { | |
1928 | PBMEM(0xfff02800), | |
1929 | IRQ(29), | |
1930 | }; | |
1931 | static struct clk atmel_ac97c0_pclk = { | |
1932 | .name = "pclk", | |
1933 | .parent = &pbb_clk, | |
1934 | .mode = pbb_clk_mode, | |
1935 | .get_rate = pbb_clk_get_rate, | |
1936 | .index = 10, | |
1937 | }; | |
1938 | ||
218df4a2 HCE |
1939 | struct platform_device *__init |
1940 | at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data) | |
2042c1c4 HS |
1941 | { |
1942 | struct platform_device *pdev; | |
218df4a2 | 1943 | struct ac97c_platform_data _data; |
2042c1c4 HS |
1944 | |
1945 | if (id != 0) | |
1946 | return NULL; | |
1947 | ||
1948 | pdev = platform_device_alloc("atmel_ac97c", id); | |
1949 | if (!pdev) | |
1950 | return NULL; | |
1951 | ||
1952 | if (platform_device_add_resources(pdev, atmel_ac97c0_resource, | |
1953 | ARRAY_SIZE(atmel_ac97c0_resource))) | |
218df4a2 HCE |
1954 | goto fail; |
1955 | ||
1956 | if (!data) { | |
1957 | data = &_data; | |
1958 | memset(data, 0, sizeof(struct ac97c_platform_data)); | |
1959 | data->reset_pin = GPIO_PIN_NONE; | |
1960 | } | |
1961 | ||
1962 | data->dma_rx_periph_id = 3; | |
1963 | data->dma_tx_periph_id = 4; | |
1964 | data->dma_controller_id = 0; | |
2042c1c4 | 1965 | |
218df4a2 HCE |
1966 | if (platform_device_add_data(pdev, data, |
1967 | sizeof(struct ac97c_platform_data))) | |
1968 | goto fail; | |
1969 | ||
1970 | select_peripheral(PB(20), PERIPH_B, 0); /* SDO */ | |
1971 | select_peripheral(PB(21), PERIPH_B, 0); /* SYNC */ | |
1972 | select_peripheral(PB(22), PERIPH_B, 0); /* SCLK */ | |
1973 | select_peripheral(PB(23), PERIPH_B, 0); /* SDI */ | |
1974 | ||
1975 | /* TODO: gpio_is_valid(data->reset_pin) with kernel 2.6.26. */ | |
1976 | if (data->reset_pin != GPIO_PIN_NONE) | |
1977 | at32_select_gpio(data->reset_pin, 0); | |
2042c1c4 HS |
1978 | |
1979 | atmel_ac97c0_pclk.dev = &pdev->dev; | |
1980 | ||
1981 | platform_device_add(pdev); | |
1982 | return pdev; | |
1983 | ||
218df4a2 | 1984 | fail: |
2042c1c4 HS |
1985 | platform_device_put(pdev); |
1986 | return NULL; | |
1987 | } | |
1988 | ||
1989 | /* -------------------------------------------------------------------- | |
1990 | * ABDAC | |
1991 | * -------------------------------------------------------------------- */ | |
1992 | static struct resource abdac0_resource[] __initdata = { | |
1993 | PBMEM(0xfff02000), | |
1994 | IRQ(27), | |
1995 | }; | |
1996 | static struct clk abdac0_pclk = { | |
1997 | .name = "pclk", | |
1998 | .parent = &pbb_clk, | |
1999 | .mode = pbb_clk_mode, | |
2000 | .get_rate = pbb_clk_get_rate, | |
2001 | .index = 8, | |
2002 | }; | |
2003 | static struct clk abdac0_sample_clk = { | |
2004 | .name = "sample_clk", | |
2005 | .mode = genclk_mode, | |
2006 | .get_rate = genclk_get_rate, | |
2007 | .set_rate = genclk_set_rate, | |
2008 | .set_parent = genclk_set_parent, | |
2009 | .index = 6, | |
2010 | }; | |
2011 | ||
2012 | struct platform_device *__init at32_add_device_abdac(unsigned int id) | |
2013 | { | |
2014 | struct platform_device *pdev; | |
2015 | ||
2016 | if (id != 0) | |
2017 | return NULL; | |
2018 | ||
2019 | pdev = platform_device_alloc("abdac", id); | |
2020 | if (!pdev) | |
2021 | return NULL; | |
2022 | ||
2023 | if (platform_device_add_resources(pdev, abdac0_resource, | |
2024 | ARRAY_SIZE(abdac0_resource))) | |
2025 | goto err_add_resources; | |
2026 | ||
2027 | select_peripheral(PB(20), PERIPH_A, 0); /* DATA1 */ | |
2028 | select_peripheral(PB(21), PERIPH_A, 0); /* DATA0 */ | |
2029 | select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1 */ | |
2030 | select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0 */ | |
2031 | ||
2032 | abdac0_pclk.dev = &pdev->dev; | |
2033 | abdac0_sample_clk.dev = &pdev->dev; | |
2034 | ||
2035 | platform_device_add(pdev); | |
2036 | return pdev; | |
2037 | ||
2038 | err_add_resources: | |
2039 | platform_device_put(pdev); | |
2040 | return NULL; | |
2041 | } | |
2042 | ||
7a5fe238 HS |
2043 | /* -------------------------------------------------------------------- |
2044 | * GCLK | |
2045 | * -------------------------------------------------------------------- */ | |
2046 | static struct clk gclk0 = { | |
2047 | .name = "gclk0", | |
2048 | .mode = genclk_mode, | |
2049 | .get_rate = genclk_get_rate, | |
2050 | .set_rate = genclk_set_rate, | |
2051 | .set_parent = genclk_set_parent, | |
2052 | .index = 0, | |
2053 | }; | |
2054 | static struct clk gclk1 = { | |
2055 | .name = "gclk1", | |
2056 | .mode = genclk_mode, | |
2057 | .get_rate = genclk_get_rate, | |
2058 | .set_rate = genclk_set_rate, | |
2059 | .set_parent = genclk_set_parent, | |
2060 | .index = 1, | |
2061 | }; | |
2062 | static struct clk gclk2 = { | |
2063 | .name = "gclk2", | |
2064 | .mode = genclk_mode, | |
2065 | .get_rate = genclk_get_rate, | |
2066 | .set_rate = genclk_set_rate, | |
2067 | .set_parent = genclk_set_parent, | |
2068 | .index = 2, | |
2069 | }; | |
2070 | static struct clk gclk3 = { | |
2071 | .name = "gclk3", | |
2072 | .mode = genclk_mode, | |
2073 | .get_rate = genclk_get_rate, | |
2074 | .set_rate = genclk_set_rate, | |
2075 | .set_parent = genclk_set_parent, | |
2076 | .index = 3, | |
2077 | }; | |
2078 | static struct clk gclk4 = { | |
2079 | .name = "gclk4", | |
2080 | .mode = genclk_mode, | |
2081 | .get_rate = genclk_get_rate, | |
2082 | .set_rate = genclk_set_rate, | |
2083 | .set_parent = genclk_set_parent, | |
2084 | .index = 4, | |
2085 | }; | |
2086 | ||
5f97f7f9 HS |
2087 | struct clk *at32_clock_list[] = { |
2088 | &osc32k, | |
2089 | &osc0, | |
2090 | &osc1, | |
2091 | &pll0, | |
2092 | &pll1, | |
2093 | &cpu_clk, | |
2094 | &hsb_clk, | |
2095 | &pba_clk, | |
2096 | &pbb_clk, | |
7a5b8059 | 2097 | &at32_pm_pclk, |
5f97f7f9 | 2098 | &at32_intc0_pclk, |
9c8f8e75 | 2099 | &hmatrix_clk, |
5f97f7f9 HS |
2100 | &ebi_clk, |
2101 | &hramc_clk, | |
7951f188 | 2102 | &sdramc_clk, |
bc157b75 HS |
2103 | &smc0_pclk, |
2104 | &smc0_mck, | |
5f97f7f9 HS |
2105 | &pdc_hclk, |
2106 | &pdc_pclk, | |
3bfb1d20 | 2107 | &dw_dmac0_hclk, |
5f97f7f9 HS |
2108 | &pico_clk, |
2109 | &pio0_mck, | |
2110 | &pio1_mck, | |
2111 | &pio2_mck, | |
2112 | &pio3_mck, | |
7f9f4678 | 2113 | &pio4_mck, |
e723ff66 DB |
2114 | &at32_tcb0_t0_clk, |
2115 | &at32_tcb1_t0_clk, | |
d86d314f HCE |
2116 | &atmel_psif0_pclk, |
2117 | &atmel_psif1_pclk, | |
1e8ea802 HS |
2118 | &atmel_usart0_usart, |
2119 | &atmel_usart1_usart, | |
2120 | &atmel_usart2_usart, | |
2121 | &atmel_usart3_usart, | |
9a1e8eb1 | 2122 | &atmel_pwm0_mck, |
438ff3f3 | 2123 | #if defined(CONFIG_CPU_AT32AP7000) |
5f97f7f9 HS |
2124 | &macb0_hclk, |
2125 | &macb0_pclk, | |
cfcb3a89 HS |
2126 | &macb1_hclk, |
2127 | &macb1_pclk, | |
438ff3f3 | 2128 | #endif |
3d60ee1b HS |
2129 | &atmel_spi0_spi_clk, |
2130 | &atmel_spi1_spi_clk, | |
2042c1c4 HS |
2131 | &atmel_twi0_pclk, |
2132 | &atmel_mci0_pclk, | |
438ff3f3 | 2133 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002) |
d0a2b7af HS |
2134 | &atmel_lcdfb0_hck1, |
2135 | &atmel_lcdfb0_pixclk, | |
438ff3f3 | 2136 | #endif |
9cf6cf58 HCE |
2137 | &ssc0_pclk, |
2138 | &ssc1_pclk, | |
2139 | &ssc2_pclk, | |
6fcf0615 HS |
2140 | &usba0_hclk, |
2141 | &usba0_pclk, | |
2042c1c4 HS |
2142 | &atmel_ac97c0_pclk, |
2143 | &abdac0_pclk, | |
2144 | &abdac0_sample_clk, | |
7a5fe238 HS |
2145 | &gclk0, |
2146 | &gclk1, | |
2147 | &gclk2, | |
2148 | &gclk3, | |
2149 | &gclk4, | |
5f97f7f9 HS |
2150 | }; |
2151 | unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list); | |
2152 | ||
65033ed7 | 2153 | void __init setup_platform(void) |
5f97f7f9 | 2154 | { |
5f97f7f9 HS |
2155 | u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0; |
2156 | int i; | |
2157 | ||
9e58e185 | 2158 | if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) { |
5f97f7f9 | 2159 | main_clock = &pll0; |
9e58e185 HCE |
2160 | cpu_clk.parent = &pll0; |
2161 | } else { | |
5f97f7f9 | 2162 | main_clock = &osc0; |
9e58e185 HCE |
2163 | cpu_clk.parent = &osc0; |
2164 | } | |
5f97f7f9 | 2165 | |
7a5b8059 | 2166 | if (pm_readl(PLL0) & PM_BIT(PLLOSC)) |
5f97f7f9 | 2167 | pll0.parent = &osc1; |
7a5b8059 | 2168 | if (pm_readl(PLL1) & PM_BIT(PLLOSC)) |
5f97f7f9 HS |
2169 | pll1.parent = &osc1; |
2170 | ||
7a5fe238 HS |
2171 | genclk_init_parent(&gclk0); |
2172 | genclk_init_parent(&gclk1); | |
2173 | genclk_init_parent(&gclk2); | |
2174 | genclk_init_parent(&gclk3); | |
2175 | genclk_init_parent(&gclk4); | |
438ff3f3 | 2176 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002) |
d0a2b7af | 2177 | genclk_init_parent(&atmel_lcdfb0_pixclk); |
438ff3f3 | 2178 | #endif |
2042c1c4 | 2179 | genclk_init_parent(&abdac0_sample_clk); |
7a5fe238 | 2180 | |
5f97f7f9 HS |
2181 | /* |
2182 | * Turn on all clocks that have at least one user already, and | |
2183 | * turn off everything else. We only do this for module | |
2184 | * clocks, and even though it isn't particularly pretty to | |
2185 | * check the address of the mode function, it should do the | |
2186 | * trick... | |
2187 | */ | |
2188 | for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) { | |
2189 | struct clk *clk = at32_clock_list[i]; | |
2190 | ||
188ff65d HS |
2191 | if (clk->users == 0) |
2192 | continue; | |
2193 | ||
5f97f7f9 HS |
2194 | if (clk->mode == &cpu_clk_mode) |
2195 | cpu_mask |= 1 << clk->index; | |
2196 | else if (clk->mode == &hsb_clk_mode) | |
2197 | hsb_mask |= 1 << clk->index; | |
2198 | else if (clk->mode == &pba_clk_mode) | |
2199 | pba_mask |= 1 << clk->index; | |
2200 | else if (clk->mode == &pbb_clk_mode) | |
2201 | pbb_mask |= 1 << clk->index; | |
2202 | } | |
2203 | ||
7a5b8059 HS |
2204 | pm_writel(CPU_MASK, cpu_mask); |
2205 | pm_writel(HSB_MASK, hsb_mask); | |
2206 | pm_writel(PBA_MASK, pba_mask); | |
2207 | pm_writel(PBB_MASK, pbb_mask); | |
65033ed7 HS |
2208 | |
2209 | /* Initialize the port muxes */ | |
2210 | at32_init_pio(&pio0_device); | |
2211 | at32_init_pio(&pio1_device); | |
2212 | at32_init_pio(&pio2_device); | |
2213 | at32_init_pio(&pio3_device); | |
2214 | at32_init_pio(&pio4_device); | |
5f97f7f9 | 2215 | } |
b83d6ee1 HS |
2216 | |
2217 | struct gen_pool *sram_pool; | |
2218 | ||
2219 | static int __init sram_init(void) | |
2220 | { | |
2221 | struct gen_pool *pool; | |
2222 | ||
2223 | /* 1KiB granularity */ | |
2224 | pool = gen_pool_create(10, -1); | |
2225 | if (!pool) | |
2226 | goto fail; | |
2227 | ||
2228 | if (gen_pool_add(pool, 0x24000000, 0x8000, -1)) | |
2229 | goto err_pool_add; | |
2230 | ||
2231 | sram_pool = pool; | |
2232 | return 0; | |
2233 | ||
2234 | err_pool_add: | |
2235 | gen_pool_destroy(pool); | |
2236 | fail: | |
2237 | pr_err("Failed to create SRAM pool\n"); | |
2238 | return -ENOMEM; | |
2239 | } | |
2240 | core_initcall(sram_init); |