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Commit | Line | Data |
---|---|---|
9e1b9b80 AJ |
1 | config SYMBOL_PREFIX |
2 | string | |
3 | default "_" | |
4 | ||
1394f032 | 5 | config MMU |
bac7d89e | 6 | def_bool n |
1394f032 BW |
7 | |
8 | config FPU | |
bac7d89e | 9 | def_bool n |
1394f032 BW |
10 | |
11 | config RWSEM_GENERIC_SPINLOCK | |
bac7d89e | 12 | def_bool y |
1394f032 BW |
13 | |
14 | config RWSEM_XCHGADD_ALGORITHM | |
bac7d89e | 15 | def_bool n |
1394f032 BW |
16 | |
17 | config BLACKFIN | |
bac7d89e | 18 | def_bool y |
652afdc3 | 19 | select HAVE_ARCH_KGDB |
e8f263df | 20 | select HAVE_ARCH_TRACEHOOK |
f5074429 MF |
21 | select HAVE_DYNAMIC_FTRACE |
22 | select HAVE_FTRACE_MCOUNT_RECORD | |
1ee76d7e | 23 | select HAVE_FUNCTION_GRAPH_TRACER |
1c873be7 | 24 | select HAVE_FUNCTION_TRACER |
aebfef03 | 25 | select HAVE_FUNCTION_TRACE_MCOUNT_TEST |
ec7748b5 | 26 | select HAVE_IDE |
d86bfb16 BS |
27 | select HAVE_KERNEL_GZIP if RAMKERNEL |
28 | select HAVE_KERNEL_BZIP2 if RAMKERNEL | |
29 | select HAVE_KERNEL_LZMA if RAMKERNEL | |
67df6cc6 | 30 | select HAVE_KERNEL_LZO if RAMKERNEL |
42d4b839 | 31 | select HAVE_OPROFILE |
a4f0b32c | 32 | select ARCH_WANT_OPTIONAL_GPIOLIB |
7b028863 TG |
33 | select HAVE_GENERIC_HARDIRQS |
34 | select GENERIC_IRQ_PROBE | |
35 | select IRQ_PER_CPU if SMP | |
1394f032 | 36 | |
ddf9ddac MF |
37 | config GENERIC_CSUM |
38 | def_bool y | |
39 | ||
70f12567 MF |
40 | config GENERIC_BUG |
41 | def_bool y | |
42 | depends on BUG | |
43 | ||
e3defffe | 44 | config ZONE_DMA |
bac7d89e | 45 | def_bool y |
e3defffe | 46 | |
1394f032 | 47 | config GENERIC_FIND_NEXT_BIT |
bac7d89e | 48 | def_bool y |
1394f032 | 49 | |
b2d1583f | 50 | config GENERIC_GPIO |
bac7d89e | 51 | def_bool y |
1394f032 BW |
52 | |
53 | config FORCE_MAX_ZONEORDER | |
54 | int | |
55 | default "14" | |
56 | ||
57 | config GENERIC_CALIBRATE_DELAY | |
bac7d89e | 58 | def_bool y |
1394f032 | 59 | |
6fa68e7a MF |
60 | config LOCKDEP_SUPPORT |
61 | def_bool y | |
62 | ||
c7b412f4 MF |
63 | config STACKTRACE_SUPPORT |
64 | def_bool y | |
65 | ||
8f86001f MF |
66 | config TRACE_IRQFLAGS_SUPPORT |
67 | def_bool y | |
1394f032 | 68 | |
1394f032 | 69 | source "init/Kconfig" |
dc52ddc0 | 70 | |
1394f032 BW |
71 | source "kernel/Kconfig.preempt" |
72 | ||
dc52ddc0 MH |
73 | source "kernel/Kconfig.freezer" |
74 | ||
1394f032 BW |
75 | menu "Blackfin Processor Options" |
76 | ||
77 | comment "Processor and Board Settings" | |
78 | ||
79 | choice | |
80 | prompt "CPU" | |
81 | default BF533 | |
82 | ||
2f6f4bcd BW |
83 | config BF512 |
84 | bool "BF512" | |
85 | help | |
86 | BF512 Processor Support. | |
87 | ||
88 | config BF514 | |
89 | bool "BF514" | |
90 | help | |
91 | BF514 Processor Support. | |
92 | ||
93 | config BF516 | |
94 | bool "BF516" | |
95 | help | |
96 | BF516 Processor Support. | |
97 | ||
98 | config BF518 | |
99 | bool "BF518" | |
100 | help | |
101 | BF518 Processor Support. | |
102 | ||
59003145 MH |
103 | config BF522 |
104 | bool "BF522" | |
105 | help | |
106 | BF522 Processor Support. | |
107 | ||
1545a111 MF |
108 | config BF523 |
109 | bool "BF523" | |
110 | help | |
111 | BF523 Processor Support. | |
112 | ||
113 | config BF524 | |
114 | bool "BF524" | |
115 | help | |
116 | BF524 Processor Support. | |
117 | ||
59003145 MH |
118 | config BF525 |
119 | bool "BF525" | |
120 | help | |
121 | BF525 Processor Support. | |
122 | ||
1545a111 MF |
123 | config BF526 |
124 | bool "BF526" | |
125 | help | |
126 | BF526 Processor Support. | |
127 | ||
59003145 MH |
128 | config BF527 |
129 | bool "BF527" | |
130 | help | |
131 | BF527 Processor Support. | |
132 | ||
1394f032 BW |
133 | config BF531 |
134 | bool "BF531" | |
135 | help | |
136 | BF531 Processor Support. | |
137 | ||
138 | config BF532 | |
139 | bool "BF532" | |
140 | help | |
141 | BF532 Processor Support. | |
142 | ||
143 | config BF533 | |
144 | bool "BF533" | |
145 | help | |
146 | BF533 Processor Support. | |
147 | ||
148 | config BF534 | |
149 | bool "BF534" | |
150 | help | |
151 | BF534 Processor Support. | |
152 | ||
153 | config BF536 | |
154 | bool "BF536" | |
155 | help | |
156 | BF536 Processor Support. | |
157 | ||
158 | config BF537 | |
159 | bool "BF537" | |
160 | help | |
161 | BF537 Processor Support. | |
162 | ||
dc26aec2 MH |
163 | config BF538 |
164 | bool "BF538" | |
165 | help | |
166 | BF538 Processor Support. | |
167 | ||
168 | config BF539 | |
169 | bool "BF539" | |
170 | help | |
171 | BF539 Processor Support. | |
172 | ||
5df326ac | 173 | config BF542_std |
24a07a12 RH |
174 | bool "BF542" |
175 | help | |
176 | BF542 Processor Support. | |
177 | ||
2f89c063 MF |
178 | config BF542M |
179 | bool "BF542m" | |
180 | help | |
181 | BF542 Processor Support. | |
182 | ||
5df326ac | 183 | config BF544_std |
24a07a12 RH |
184 | bool "BF544" |
185 | help | |
186 | BF544 Processor Support. | |
187 | ||
2f89c063 MF |
188 | config BF544M |
189 | bool "BF544m" | |
190 | help | |
191 | BF544 Processor Support. | |
192 | ||
5df326ac | 193 | config BF547_std |
7c7fd170 MF |
194 | bool "BF547" |
195 | help | |
196 | BF547 Processor Support. | |
197 | ||
2f89c063 MF |
198 | config BF547M |
199 | bool "BF547m" | |
200 | help | |
201 | BF547 Processor Support. | |
202 | ||
5df326ac | 203 | config BF548_std |
24a07a12 RH |
204 | bool "BF548" |
205 | help | |
206 | BF548 Processor Support. | |
207 | ||
2f89c063 MF |
208 | config BF548M |
209 | bool "BF548m" | |
210 | help | |
211 | BF548 Processor Support. | |
212 | ||
5df326ac | 213 | config BF549_std |
24a07a12 RH |
214 | bool "BF549" |
215 | help | |
216 | BF549 Processor Support. | |
217 | ||
2f89c063 MF |
218 | config BF549M |
219 | bool "BF549m" | |
220 | help | |
221 | BF549 Processor Support. | |
222 | ||
1394f032 BW |
223 | config BF561 |
224 | bool "BF561" | |
225 | help | |
cd88b4dc | 226 | BF561 Processor Support. |
1394f032 BW |
227 | |
228 | endchoice | |
229 | ||
46fa5eec GY |
230 | config SMP |
231 | depends on BF561 | |
0d152c27 | 232 | select TICKSOURCE_CORETMR |
46fa5eec GY |
233 | bool "Symmetric multi-processing support" |
234 | ---help--- | |
235 | This enables support for systems with more than one CPU, | |
236 | like the dual core BF561. If you have a system with only one | |
237 | CPU, say N. If you have a system with more than one CPU, say Y. | |
238 | ||
239 | If you don't know what to do here, say N. | |
240 | ||
241 | config NR_CPUS | |
242 | int | |
243 | depends on SMP | |
244 | default 2 if BF561 | |
245 | ||
0b39db28 GY |
246 | config HOTPLUG_CPU |
247 | bool "Support for hot-pluggable CPUs" | |
248 | depends on SMP && HOTPLUG | |
249 | default y | |
250 | ||
ead9b115 GY |
251 | config HAVE_LEGACY_PER_CPU_AREA |
252 | def_bool y | |
253 | depends on SMP | |
254 | ||
0c0497c2 MF |
255 | config BF_REV_MIN |
256 | int | |
2f89c063 | 257 | default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) |
0c0497c2 | 258 | default 2 if (BF537 || BF536 || BF534) |
2f89c063 | 259 | default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) |
2f6f4bcd | 260 | default 4 if (BF538 || BF539) |
0c0497c2 MF |
261 | |
262 | config BF_REV_MAX | |
263 | int | |
2f89c063 MF |
264 | default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) |
265 | default 3 if (BF537 || BF536 || BF534 || BF54xM) | |
2f6f4bcd | 266 | default 5 if (BF561 || BF538 || BF539) |
0c0497c2 MF |
267 | default 6 if (BF533 || BF532 || BF531) |
268 | ||
1394f032 BW |
269 | choice |
270 | prompt "Silicon Rev" | |
f8b55651 MF |
271 | default BF_REV_0_0 if (BF51x || BF52x) |
272 | default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) | |
2f89c063 | 273 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) |
24a07a12 RH |
274 | |
275 | config BF_REV_0_0 | |
276 | bool "0.0" | |
2f89c063 | 277 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
59003145 MH |
278 | |
279 | config BF_REV_0_1 | |
d07f4380 | 280 | bool "0.1" |
3d15f302 | 281 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
1394f032 BW |
282 | |
283 | config BF_REV_0_2 | |
284 | bool "0.2" | |
8060bb6f | 285 | depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) |
1394f032 BW |
286 | |
287 | config BF_REV_0_3 | |
288 | bool "0.3" | |
2f89c063 | 289 | depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) |
1394f032 BW |
290 | |
291 | config BF_REV_0_4 | |
292 | bool "0.4" | |
dc26aec2 | 293 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 BW |
294 | |
295 | config BF_REV_0_5 | |
296 | bool "0.5" | |
dc26aec2 | 297 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 | 298 | |
49f7253c MF |
299 | config BF_REV_0_6 |
300 | bool "0.6" | |
301 | depends on (BF533 || BF532 || BF531) | |
302 | ||
de3025f4 JZ |
303 | config BF_REV_ANY |
304 | bool "any" | |
305 | ||
306 | config BF_REV_NONE | |
307 | bool "none" | |
308 | ||
1394f032 BW |
309 | endchoice |
310 | ||
24a07a12 RH |
311 | config BF53x |
312 | bool | |
313 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) | |
314 | default y | |
315 | ||
1394f032 BW |
316 | config MEM_MT48LC64M4A2FB_7E |
317 | bool | |
318 | depends on (BFIN533_STAMP) | |
319 | default y | |
320 | ||
321 | config MEM_MT48LC16M16A2TG_75 | |
322 | bool | |
323 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | |
60584344 HK |
324 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \ |
325 | || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \ | |
326 | || BFIN527_BLUETECHNIX_CM) | |
1394f032 BW |
327 | default y |
328 | ||
329 | config MEM_MT48LC32M8A2_75 | |
330 | bool | |
084f9ebf | 331 | depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) |
1394f032 BW |
332 | default y |
333 | ||
334 | config MEM_MT48LC8M32B2B5_7 | |
335 | bool | |
336 | depends on (BFIN561_BLUETECHNIX_CM) | |
337 | default y | |
338 | ||
59003145 MH |
339 | config MEM_MT48LC32M16A2TG_75 |
340 | bool | |
8effc4a6 | 341 | depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL) |
59003145 MH |
342 | default y |
343 | ||
ee48efb5 GY |
344 | config MEM_MT48H32M16LFCJ_75 |
345 | bool | |
346 | depends on (BFIN526_EZBRD) | |
347 | default y | |
348 | ||
2f6f4bcd | 349 | source "arch/blackfin/mach-bf518/Kconfig" |
59003145 | 350 | source "arch/blackfin/mach-bf527/Kconfig" |
1394f032 BW |
351 | source "arch/blackfin/mach-bf533/Kconfig" |
352 | source "arch/blackfin/mach-bf561/Kconfig" | |
353 | source "arch/blackfin/mach-bf537/Kconfig" | |
dc26aec2 | 354 | source "arch/blackfin/mach-bf538/Kconfig" |
24a07a12 | 355 | source "arch/blackfin/mach-bf548/Kconfig" |
1394f032 BW |
356 | |
357 | menu "Board customizations" | |
358 | ||
359 | config CMDLINE_BOOL | |
360 | bool "Default bootloader kernel arguments" | |
361 | ||
362 | config CMDLINE | |
363 | string "Initial kernel command string" | |
364 | depends on CMDLINE_BOOL | |
365 | default "console=ttyBF0,57600" | |
366 | help | |
367 | If you don't have a boot loader capable of passing a command line string | |
368 | to the kernel, you may specify one here. As a minimum, you should specify | |
369 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). | |
370 | ||
5f004c20 MF |
371 | config BOOT_LOAD |
372 | hex "Kernel load address for booting" | |
373 | default "0x1000" | |
374 | range 0x1000 0x20000000 | |
375 | help | |
376 | This option allows you to set the load address of the kernel. | |
377 | This can be useful if you are on a board which has a small amount | |
378 | of memory or you wish to reserve some memory at the beginning of | |
379 | the address space. | |
380 | ||
381 | Note that you need to keep this value above 4k (0x1000) as this | |
382 | memory region is used to capture NULL pointer references as well | |
383 | as some core kernel functions. | |
384 | ||
8cc7117e MH |
385 | config ROM_BASE |
386 | hex "Kernel ROM Base" | |
86249911 | 387 | depends on ROMKERNEL |
d86bfb16 | 388 | default "0x20040040" |
8cc7117e MH |
389 | range 0x20000000 0x20400000 if !(BF54x || BF561) |
390 | range 0x20000000 0x30000000 if (BF54x || BF561) | |
391 | help | |
d86bfb16 BS |
392 | Make sure your ROM base does not include any file-header |
393 | information that is prepended to the kernel. | |
394 | ||
395 | For example, the bootable U-Boot format (created with | |
396 | mkimage) has a 64 byte header (0x40). So while the image | |
397 | you write to flash might start at say 0x20080000, you have | |
398 | to add 0x40 to get the kernel's ROM base as it will come | |
399 | after the header. | |
8cc7117e | 400 | |
f16295e7 | 401 | comment "Clock/PLL Setup" |
1394f032 BW |
402 | |
403 | config CLKIN_HZ | |
2fb6cb41 | 404 | int "Frequency of the crystal on the board in Hz" |
d0cb9b4e | 405 | default "10000000" if BFIN532_IP0X |
1394f032 | 406 | default "11059200" if BFIN533_STAMP |
d0cb9b4e MF |
407 | default "24576000" if PNAV10 |
408 | default "25000000" # most people use this | |
1394f032 | 409 | default "27000000" if BFIN533_EZKIT |
1394f032 | 410 | default "30000000" if BFIN561_EZKIT |
8effc4a6 | 411 | default "24000000" if BFIN527_AD7160EVAL |
1394f032 BW |
412 | help |
413 | The frequency of CLKIN crystal oscillator on the board in Hz. | |
2fb6cb41 SZ |
414 | Warning: This value should match the crystal on the board. Otherwise, |
415 | peripherals won't work properly. | |
1394f032 | 416 | |
f16295e7 RG |
417 | config BFIN_KERNEL_CLOCK |
418 | bool "Re-program Clocks while Kernel boots?" | |
419 | default n | |
420 | help | |
421 | This option decides if kernel clocks are re-programed from the | |
422 | bootloader settings. If the clocks are not set, the SDRAM settings | |
423 | are also not changed, and the Bootloader does 100% of the hardware | |
424 | configuration. | |
425 | ||
426 | config PLL_BYPASS | |
e4e9a7ad MF |
427 | bool "Bypass PLL" |
428 | depends on BFIN_KERNEL_CLOCK | |
429 | default n | |
f16295e7 RG |
430 | |
431 | config CLKIN_HALF | |
432 | bool "Half Clock In" | |
433 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
434 | default n | |
435 | help | |
436 | If this is set the clock will be divided by 2, before it goes to the PLL. | |
437 | ||
438 | config VCO_MULT | |
439 | int "VCO Multiplier" | |
440 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
441 | range 1 64 | |
442 | default "22" if BFIN533_EZKIT | |
443 | default "45" if BFIN533_STAMP | |
6924dfb0 | 444 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) |
f16295e7 | 445 | default "22" if BFIN533_BLUETECHNIX_CM |
60584344 | 446 | default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
f16295e7 | 447 | default "20" if BFIN561_EZKIT |
2f6f4bcd | 448 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) |
8effc4a6 | 449 | default "25" if BFIN527_AD7160EVAL |
f16295e7 RG |
450 | help |
451 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | |
452 | PLL Frequency = (Crystal Frequency) * (this setting) | |
453 | ||
454 | choice | |
455 | prompt "Core Clock Divider" | |
456 | depends on BFIN_KERNEL_CLOCK | |
457 | default CCLK_DIV_1 | |
458 | help | |
459 | This sets the frequency of the core. It can be 1, 2, 4 or 8 | |
460 | Core Frequency = (PLL frequency) / (this setting) | |
461 | ||
462 | config CCLK_DIV_1 | |
463 | bool "1" | |
464 | ||
465 | config CCLK_DIV_2 | |
466 | bool "2" | |
467 | ||
468 | config CCLK_DIV_4 | |
469 | bool "4" | |
470 | ||
471 | config CCLK_DIV_8 | |
472 | bool "8" | |
473 | endchoice | |
474 | ||
475 | config SCLK_DIV | |
476 | int "System Clock Divider" | |
477 | depends on BFIN_KERNEL_CLOCK | |
478 | range 1 15 | |
5f004c20 | 479 | default 5 |
f16295e7 RG |
480 | help |
481 | This sets the frequency of the system clock (including SDRAM or DDR). | |
482 | This can be between 1 and 15 | |
483 | System Clock = (PLL frequency) / (this setting) | |
484 | ||
5f004c20 MF |
485 | choice |
486 | prompt "DDR SDRAM Chip Type" | |
487 | depends on BFIN_KERNEL_CLOCK | |
488 | depends on BF54x | |
489 | default MEM_MT46V32M16_5B | |
490 | ||
491 | config MEM_MT46V32M16_6T | |
492 | bool "MT46V32M16_6T" | |
493 | ||
494 | config MEM_MT46V32M16_5B | |
495 | bool "MT46V32M16_5B" | |
496 | endchoice | |
497 | ||
73feb5c0 MH |
498 | choice |
499 | prompt "DDR/SDRAM Timing" | |
500 | depends on BFIN_KERNEL_CLOCK | |
501 | default BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
502 | help | |
503 | This option allows you to specify Blackfin SDRAM/DDR Timing parameters | |
504 | The calculated SDRAM timing parameters may not be 100% | |
505 | accurate - This option is therefore marked experimental. | |
506 | ||
507 | config BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
508 | bool "Calculate Timings (EXPERIMENTAL)" | |
509 | depends on EXPERIMENTAL | |
510 | ||
511 | config BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
512 | bool "Provide accurate Timings based on target SCLK" | |
513 | help | |
514 | Please consult the Blackfin Hardware Reference Manuals as well | |
515 | as the memory device datasheet. | |
516 | http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram | |
517 | endchoice | |
518 | ||
519 | menu "Memory Init Control" | |
520 | depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
521 | ||
522 | config MEM_DDRCTL0 | |
523 | depends on BF54x | |
524 | hex "DDRCTL0" | |
525 | default 0x0 | |
526 | ||
527 | config MEM_DDRCTL1 | |
528 | depends on BF54x | |
529 | hex "DDRCTL1" | |
530 | default 0x0 | |
531 | ||
532 | config MEM_DDRCTL2 | |
533 | depends on BF54x | |
534 | hex "DDRCTL2" | |
535 | default 0x0 | |
536 | ||
537 | config MEM_EBIU_DDRQUE | |
538 | depends on BF54x | |
539 | hex "DDRQUE" | |
540 | default 0x0 | |
541 | ||
542 | config MEM_SDRRC | |
543 | depends on !BF54x | |
544 | hex "SDRRC" | |
545 | default 0x0 | |
546 | ||
547 | config MEM_SDGCTL | |
548 | depends on !BF54x | |
549 | hex "SDGCTL" | |
550 | default 0x0 | |
551 | endmenu | |
552 | ||
f16295e7 RG |
553 | # |
554 | # Max & Min Speeds for various Chips | |
555 | # | |
556 | config MAX_VCO_HZ | |
557 | int | |
2f6f4bcd BW |
558 | default 400000000 if BF512 |
559 | default 400000000 if BF514 | |
560 | default 400000000 if BF516 | |
561 | default 400000000 if BF518 | |
7b06263b MF |
562 | default 400000000 if BF522 |
563 | default 600000000 if BF523 | |
1545a111 | 564 | default 400000000 if BF524 |
f16295e7 | 565 | default 600000000 if BF525 |
1545a111 | 566 | default 400000000 if BF526 |
f16295e7 RG |
567 | default 600000000 if BF527 |
568 | default 400000000 if BF531 | |
569 | default 400000000 if BF532 | |
570 | default 750000000 if BF533 | |
571 | default 500000000 if BF534 | |
572 | default 400000000 if BF536 | |
573 | default 600000000 if BF537 | |
f72eecb9 RG |
574 | default 533333333 if BF538 |
575 | default 533333333 if BF539 | |
f16295e7 | 576 | default 600000000 if BF542 |
f72eecb9 | 577 | default 533333333 if BF544 |
1545a111 MF |
578 | default 600000000 if BF547 |
579 | default 600000000 if BF548 | |
f72eecb9 | 580 | default 533333333 if BF549 |
f16295e7 RG |
581 | default 600000000 if BF561 |
582 | ||
583 | config MIN_VCO_HZ | |
584 | int | |
585 | default 50000000 | |
586 | ||
587 | config MAX_SCLK_HZ | |
588 | int | |
f72eecb9 | 589 | default 133333333 |
f16295e7 RG |
590 | |
591 | config MIN_SCLK_HZ | |
592 | int | |
593 | default 27000000 | |
594 | ||
595 | comment "Kernel Timer/Scheduler" | |
596 | ||
597 | source kernel/Kconfig.hz | |
598 | ||
8b5f79f9 VM |
599 | config GENERIC_CLOCKEVENTS |
600 | bool "Generic clock events" | |
8b5f79f9 VM |
601 | default y |
602 | ||
0d152c27 | 603 | menu "Clock event device" |
1fa9be72 | 604 | depends on GENERIC_CLOCKEVENTS |
1fa9be72 | 605 | config TICKSOURCE_GPTMR0 |
0d152c27 YL |
606 | bool "GPTimer0" |
607 | depends on !SMP | |
1fa9be72 | 608 | select BFIN_GPTIMERS |
1fa9be72 GY |
609 | |
610 | config TICKSOURCE_CORETMR | |
0d152c27 YL |
611 | bool "Core timer" |
612 | default y | |
613 | endmenu | |
1fa9be72 | 614 | |
0d152c27 | 615 | menu "Clock souce" |
8b5f79f9 | 616 | depends on GENERIC_CLOCKEVENTS |
0d152c27 YL |
617 | config CYCLES_CLOCKSOURCE |
618 | bool "CYCLES" | |
619 | default y | |
8b5f79f9 | 620 | depends on !BFIN_SCRATCH_REG_CYCLES |
1fa9be72 | 621 | depends on !SMP |
8b5f79f9 VM |
622 | help |
623 | If you say Y here, you will enable support for using the 'cycles' | |
624 | registers as a clock source. Doing so means you will be unable to | |
625 | safely write to the 'cycles' register during runtime. You will | |
626 | still be able to read it (such as for performance monitoring), but | |
627 | writing the registers will most likely crash the kernel. | |
628 | ||
1fa9be72 | 629 | config GPTMR0_CLOCKSOURCE |
0d152c27 | 630 | bool "GPTimer0" |
3aca47c0 | 631 | select BFIN_GPTIMERS |
1fa9be72 | 632 | depends on !TICKSOURCE_GPTMR0 |
0d152c27 | 633 | endmenu |
1fa9be72 | 634 | |
10f03f1a JS |
635 | config ARCH_USES_GETTIMEOFFSET |
636 | depends on !GENERIC_CLOCKEVENTS | |
637 | def_bool y | |
638 | ||
8b5f79f9 VM |
639 | source kernel/time/Kconfig |
640 | ||
5f004c20 | 641 | comment "Misc" |
971d5bc4 | 642 | |
f0b5d12f MF |
643 | choice |
644 | prompt "Blackfin Exception Scratch Register" | |
645 | default BFIN_SCRATCH_REG_RETN | |
646 | help | |
647 | Select the resource to reserve for the Exception handler: | |
648 | - RETN: Non-Maskable Interrupt (NMI) | |
649 | - RETE: Exception Return (JTAG/ICE) | |
650 | - CYCLES: Performance counter | |
651 | ||
652 | If you are unsure, please select "RETN". | |
653 | ||
654 | config BFIN_SCRATCH_REG_RETN | |
655 | bool "RETN" | |
656 | help | |
657 | Use the RETN register in the Blackfin exception handler | |
658 | as a stack scratch register. This means you cannot | |
659 | safely use NMI on the Blackfin while running Linux, but | |
660 | you can debug the system with a JTAG ICE and use the | |
661 | CYCLES performance registers. | |
662 | ||
663 | If you are unsure, please select "RETN". | |
664 | ||
665 | config BFIN_SCRATCH_REG_RETE | |
666 | bool "RETE" | |
667 | help | |
668 | Use the RETE register in the Blackfin exception handler | |
669 | as a stack scratch register. This means you cannot | |
670 | safely use a JTAG ICE while debugging a Blackfin board, | |
671 | but you can safely use the CYCLES performance registers | |
672 | and the NMI. | |
673 | ||
674 | If you are unsure, please select "RETN". | |
675 | ||
676 | config BFIN_SCRATCH_REG_CYCLES | |
677 | bool "CYCLES" | |
678 | help | |
679 | Use the CYCLES register in the Blackfin exception handler | |
680 | as a stack scratch register. This means you cannot | |
681 | safely use the CYCLES performance registers on a Blackfin | |
682 | board at anytime, but you can debug the system with a JTAG | |
683 | ICE and use the NMI. | |
684 | ||
685 | If you are unsure, please select "RETN". | |
686 | ||
687 | endchoice | |
688 | ||
1394f032 BW |
689 | endmenu |
690 | ||
691 | ||
692 | menu "Blackfin Kernel Optimizations" | |
46fa5eec | 693 | depends on !SMP |
1394f032 | 694 | |
1394f032 BW |
695 | comment "Memory Optimizations" |
696 | ||
697 | config I_ENTRY_L1 | |
698 | bool "Locate interrupt entry code in L1 Memory" | |
699 | default y | |
700 | help | |
01dd2fbf ML |
701 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
702 | into L1 instruction memory. (less latency) | |
1394f032 BW |
703 | |
704 | config EXCPT_IRQ_SYSC_L1 | |
01dd2fbf | 705 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
1394f032 BW |
706 | default y |
707 | help | |
01dd2fbf | 708 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
cfefe3c6 | 709 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
01dd2fbf | 710 | (less latency) |
1394f032 BW |
711 | |
712 | config DO_IRQ_L1 | |
713 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | |
714 | default y | |
715 | help | |
01dd2fbf ML |
716 | If enabled, the frequently called do_irq dispatcher function is linked |
717 | into L1 instruction memory. (less latency) | |
1394f032 BW |
718 | |
719 | config CORE_TIMER_IRQ_L1 | |
720 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | |
721 | default y | |
722 | help | |
01dd2fbf ML |
723 | If enabled, the frequently called timer_interrupt() function is linked |
724 | into L1 instruction memory. (less latency) | |
1394f032 BW |
725 | |
726 | config IDLE_L1 | |
727 | bool "Locate frequently idle function in L1 Memory" | |
728 | default y | |
729 | help | |
01dd2fbf ML |
730 | If enabled, the frequently called idle function is linked |
731 | into L1 instruction memory. (less latency) | |
1394f032 BW |
732 | |
733 | config SCHEDULE_L1 | |
734 | bool "Locate kernel schedule function in L1 Memory" | |
735 | default y | |
736 | help | |
01dd2fbf ML |
737 | If enabled, the frequently called kernel schedule is linked |
738 | into L1 instruction memory. (less latency) | |
1394f032 BW |
739 | |
740 | config ARITHMETIC_OPS_L1 | |
741 | bool "Locate kernel owned arithmetic functions in L1 Memory" | |
742 | default y | |
743 | help | |
01dd2fbf ML |
744 | If enabled, arithmetic functions are linked |
745 | into L1 instruction memory. (less latency) | |
1394f032 BW |
746 | |
747 | config ACCESS_OK_L1 | |
748 | bool "Locate access_ok function in L1 Memory" | |
749 | default y | |
750 | help | |
01dd2fbf ML |
751 | If enabled, the access_ok function is linked |
752 | into L1 instruction memory. (less latency) | |
1394f032 BW |
753 | |
754 | config MEMSET_L1 | |
755 | bool "Locate memset function in L1 Memory" | |
756 | default y | |
757 | help | |
01dd2fbf ML |
758 | If enabled, the memset function is linked |
759 | into L1 instruction memory. (less latency) | |
1394f032 BW |
760 | |
761 | config MEMCPY_L1 | |
762 | bool "Locate memcpy function in L1 Memory" | |
763 | default y | |
764 | help | |
01dd2fbf ML |
765 | If enabled, the memcpy function is linked |
766 | into L1 instruction memory. (less latency) | |
1394f032 | 767 | |
479ba603 RG |
768 | config STRCMP_L1 |
769 | bool "locate strcmp function in L1 Memory" | |
770 | default y | |
771 | help | |
772 | If enabled, the strcmp function is linked | |
773 | into L1 instruction memory (less latency). | |
774 | ||
775 | config STRNCMP_L1 | |
776 | bool "locate strncmp function in L1 Memory" | |
777 | default y | |
778 | help | |
779 | If enabled, the strncmp function is linked | |
780 | into L1 instruction memory (less latency). | |
781 | ||
782 | config STRCPY_L1 | |
783 | bool "locate strcpy function in L1 Memory" | |
784 | default y | |
785 | help | |
786 | If enabled, the strcpy function is linked | |
787 | into L1 instruction memory (less latency). | |
788 | ||
789 | config STRNCPY_L1 | |
790 | bool "locate strncpy function in L1 Memory" | |
791 | default y | |
792 | help | |
793 | If enabled, the strncpy function is linked | |
794 | into L1 instruction memory (less latency). | |
795 | ||
1394f032 BW |
796 | config SYS_BFIN_SPINLOCK_L1 |
797 | bool "Locate sys_bfin_spinlock function in L1 Memory" | |
798 | default y | |
799 | help | |
01dd2fbf ML |
800 | If enabled, sys_bfin_spinlock function is linked |
801 | into L1 instruction memory. (less latency) | |
1394f032 BW |
802 | |
803 | config IP_CHECKSUM_L1 | |
804 | bool "Locate IP Checksum function in L1 Memory" | |
805 | default n | |
806 | help | |
01dd2fbf ML |
807 | If enabled, the IP Checksum function is linked |
808 | into L1 instruction memory. (less latency) | |
1394f032 BW |
809 | |
810 | config CACHELINE_ALIGNED_L1 | |
811 | bool "Locate cacheline_aligned data to L1 Data Memory" | |
157cc5aa MH |
812 | default y if !BF54x |
813 | default n if BF54x | |
1394f032 BW |
814 | depends on !BF531 |
815 | help | |
692105b8 | 816 | If enabled, cacheline_aligned data is linked |
01dd2fbf | 817 | into L1 data memory. (less latency) |
1394f032 BW |
818 | |
819 | config SYSCALL_TAB_L1 | |
820 | bool "Locate Syscall Table L1 Data Memory" | |
821 | default n | |
822 | depends on !BF531 | |
823 | help | |
01dd2fbf ML |
824 | If enabled, the Syscall LUT is linked |
825 | into L1 data memory. (less latency) | |
1394f032 BW |
826 | |
827 | config CPLB_SWITCH_TAB_L1 | |
828 | bool "Locate CPLB Switch Tables L1 Data Memory" | |
829 | default n | |
830 | depends on !BF531 | |
831 | help | |
01dd2fbf ML |
832 | If enabled, the CPLB Switch Tables are linked |
833 | into L1 data memory. (less latency) | |
1394f032 | 834 | |
74181295 MF |
835 | config CACHE_FLUSH_L1 |
836 | bool "Locate cache flush funcs in L1 Inst Memory" | |
837 | default y | |
838 | help | |
839 | If enabled, the Blackfin cache flushing functions are linked | |
840 | into L1 instruction memory. | |
841 | ||
842 | Note that this might be required to address anomalies, but | |
843 | these functions are pretty small, so it shouldn't be too bad. | |
844 | If you are using a processor affected by an anomaly, the build | |
845 | system will double check for you and prevent it. | |
846 | ||
ca87b7ad GY |
847 | config APP_STACK_L1 |
848 | bool "Support locating application stack in L1 Scratch Memory" | |
849 | default y | |
850 | help | |
851 | If enabled the application stack can be located in L1 | |
852 | scratch memory (less latency). | |
853 | ||
854 | Currently only works with FLAT binaries. | |
855 | ||
6ad2b84c MF |
856 | config EXCEPTION_L1_SCRATCH |
857 | bool "Locate exception stack in L1 Scratch Memory" | |
858 | default n | |
f82e0a0c | 859 | depends on !APP_STACK_L1 |
6ad2b84c MF |
860 | help |
861 | Whenever an exception occurs, use the L1 Scratch memory for | |
862 | stack storage. You cannot place the stacks of FLAT binaries | |
863 | in L1 when using this option. | |
864 | ||
865 | If you don't use L1 Scratch, then you should say Y here. | |
866 | ||
251383c7 RG |
867 | comment "Speed Optimizations" |
868 | config BFIN_INS_LOWOVERHEAD | |
869 | bool "ins[bwl] low overhead, higher interrupt latency" | |
870 | default y | |
871 | help | |
872 | Reads on the Blackfin are speculative. In Blackfin terms, this means | |
873 | they can be interrupted at any time (even after they have been issued | |
874 | on to the external bus), and re-issued after the interrupt occurs. | |
875 | For memory - this is not a big deal, since memory does not change if | |
876 | it sees a read. | |
877 | ||
878 | If a FIFO is sitting on the end of the read, it will see two reads, | |
879 | when the core only sees one since the FIFO receives both the read | |
880 | which is cancelled (and not delivered to the core) and the one which | |
881 | is re-issued (which is delivered to the core). | |
882 | ||
883 | To solve this, interrupts are turned off before reads occur to | |
884 | I/O space. This option controls which the overhead/latency of | |
885 | controlling interrupts during this time | |
886 | "n" turns interrupts off every read | |
887 | (higher overhead, but lower interrupt latency) | |
888 | "y" turns interrupts off every loop | |
889 | (low overhead, but longer interrupt latency) | |
890 | ||
891 | default behavior is to leave this set to on (type "Y"). If you are experiencing | |
892 | interrupt latency issues, it is safe and OK to turn this off. | |
893 | ||
1394f032 BW |
894 | endmenu |
895 | ||
1394f032 BW |
896 | choice |
897 | prompt "Kernel executes from" | |
898 | help | |
899 | Choose the memory type that the kernel will be running in. | |
900 | ||
901 | config RAMKERNEL | |
902 | bool "RAM" | |
903 | help | |
904 | The kernel will be resident in RAM when running. | |
905 | ||
906 | config ROMKERNEL | |
907 | bool "ROM" | |
908 | help | |
909 | The kernel will be resident in FLASH/ROM when running. | |
910 | ||
911 | endchoice | |
912 | ||
56b4f07a MF |
913 | # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both |
914 | config XIP_KERNEL | |
915 | bool | |
916 | default y | |
917 | depends on ROMKERNEL | |
918 | ||
1394f032 BW |
919 | source "mm/Kconfig" |
920 | ||
780431e3 MF |
921 | config BFIN_GPTIMERS |
922 | tristate "Enable Blackfin General Purpose Timers API" | |
923 | default n | |
924 | help | |
925 | Enable support for the General Purpose Timers API. If you | |
926 | are unsure, say N. | |
927 | ||
928 | To compile this driver as a module, choose M here: the module | |
4737f097 | 929 | will be called gptimers. |
780431e3 | 930 | |
1394f032 | 931 | choice |
d292b000 | 932 | prompt "Uncached DMA region" |
1394f032 | 933 | default DMA_UNCACHED_1M |
86ad7932 CC |
934 | config DMA_UNCACHED_4M |
935 | bool "Enable 4M DMA region" | |
1394f032 BW |
936 | config DMA_UNCACHED_2M |
937 | bool "Enable 2M DMA region" | |
938 | config DMA_UNCACHED_1M | |
939 | bool "Enable 1M DMA region" | |
c45c0659 BS |
940 | config DMA_UNCACHED_512K |
941 | bool "Enable 512K DMA region" | |
942 | config DMA_UNCACHED_256K | |
943 | bool "Enable 256K DMA region" | |
944 | config DMA_UNCACHED_128K | |
945 | bool "Enable 128K DMA region" | |
1394f032 BW |
946 | config DMA_UNCACHED_NONE |
947 | bool "Disable DMA region" | |
948 | endchoice | |
949 | ||
950 | ||
951 | comment "Cache Support" | |
41ba653f | 952 | |
3bebca2d | 953 | config BFIN_ICACHE |
1394f032 | 954 | bool "Enable ICACHE" |
41ba653f | 955 | default y |
41ba653f JZ |
956 | config BFIN_EXTMEM_ICACHEABLE |
957 | bool "Enable ICACHE for external memory" | |
958 | depends on BFIN_ICACHE | |
959 | default y | |
960 | config BFIN_L2_ICACHEABLE | |
961 | bool "Enable ICACHE for L2 SRAM" | |
962 | depends on BFIN_ICACHE | |
963 | depends on BF54x || BF561 | |
964 | default n | |
965 | ||
3bebca2d | 966 | config BFIN_DCACHE |
1394f032 | 967 | bool "Enable DCACHE" |
41ba653f | 968 | default y |
3bebca2d | 969 | config BFIN_DCACHE_BANKA |
1394f032 | 970 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
3bebca2d | 971 | depends on BFIN_DCACHE && !BF531 |
1394f032 | 972 | default n |
41ba653f JZ |
973 | config BFIN_EXTMEM_DCACHEABLE |
974 | bool "Enable DCACHE for external memory" | |
3bebca2d | 975 | depends on BFIN_DCACHE |
41ba653f JZ |
976 | default y |
977 | choice | |
978 | prompt "External memory DCACHE policy" | |
979 | depends on BFIN_EXTMEM_DCACHEABLE | |
980 | default BFIN_EXTMEM_WRITEBACK if !SMP | |
981 | default BFIN_EXTMEM_WRITETHROUGH if SMP | |
982 | config BFIN_EXTMEM_WRITEBACK | |
1394f032 | 983 | bool "Write back" |
46fa5eec | 984 | depends on !SMP |
1394f032 BW |
985 | help |
986 | Write Back Policy: | |
987 | Cached data will be written back to SDRAM only when needed. | |
988 | This can give a nice increase in performance, but beware of | |
989 | broken drivers that do not properly invalidate/flush their | |
990 | cache. | |
991 | ||
992 | Write Through Policy: | |
993 | Cached data will always be written back to SDRAM when the | |
994 | cache is updated. This is a completely safe setting, but | |
995 | performance is worse than Write Back. | |
996 | ||
997 | If you are unsure of the options and you want to be safe, | |
998 | then go with Write Through. | |
999 | ||
41ba653f | 1000 | config BFIN_EXTMEM_WRITETHROUGH |
1394f032 BW |
1001 | bool "Write through" |
1002 | help | |
1003 | Write Back Policy: | |
1004 | Cached data will be written back to SDRAM only when needed. | |
1005 | This can give a nice increase in performance, but beware of | |
1006 | broken drivers that do not properly invalidate/flush their | |
1007 | cache. | |
1008 | ||
1009 | Write Through Policy: | |
1010 | Cached data will always be written back to SDRAM when the | |
1011 | cache is updated. This is a completely safe setting, but | |
1012 | performance is worse than Write Back. | |
1013 | ||
1014 | If you are unsure of the options and you want to be safe, | |
1015 | then go with Write Through. | |
1016 | ||
1017 | endchoice | |
1018 | ||
41ba653f JZ |
1019 | config BFIN_L2_DCACHEABLE |
1020 | bool "Enable DCACHE for L2 SRAM" | |
1021 | depends on BFIN_DCACHE | |
9c954f89 | 1022 | depends on (BF54x || BF561) && !SMP |
41ba653f | 1023 | default n |
5ba76675 | 1024 | choice |
41ba653f JZ |
1025 | prompt "L2 SRAM DCACHE policy" |
1026 | depends on BFIN_L2_DCACHEABLE | |
1027 | default BFIN_L2_WRITEBACK | |
1028 | config BFIN_L2_WRITEBACK | |
5ba76675 | 1029 | bool "Write back" |
5ba76675 | 1030 | |
41ba653f | 1031 | config BFIN_L2_WRITETHROUGH |
5ba76675 | 1032 | bool "Write through" |
5ba76675 | 1033 | endchoice |
f099f39a | 1034 | |
41ba653f JZ |
1035 | |
1036 | comment "Memory Protection Unit" | |
b97b8a99 BS |
1037 | config MPU |
1038 | bool "Enable the memory protection unit (EXPERIMENTAL)" | |
1039 | default n | |
1040 | help | |
1041 | Use the processor's MPU to protect applications from accessing | |
1042 | memory they do not own. This comes at a performance penalty | |
1043 | and is recommended only for debugging. | |
1044 | ||
692105b8 | 1045 | comment "Asynchronous Memory Configuration" |
1394f032 | 1046 | |
ddf416b2 | 1047 | menu "EBIU_AMGCTL Global Control" |
1394f032 BW |
1048 | config C_AMCKEN |
1049 | bool "Enable CLKOUT" | |
1050 | default y | |
1051 | ||
1052 | config C_CDPRIO | |
1053 | bool "DMA has priority over core for ext. accesses" | |
1054 | default n | |
1055 | ||
1056 | config C_B0PEN | |
1057 | depends on BF561 | |
1058 | bool "Bank 0 16 bit packing enable" | |
1059 | default y | |
1060 | ||
1061 | config C_B1PEN | |
1062 | depends on BF561 | |
1063 | bool "Bank 1 16 bit packing enable" | |
1064 | default y | |
1065 | ||
1066 | config C_B2PEN | |
1067 | depends on BF561 | |
1068 | bool "Bank 2 16 bit packing enable" | |
1069 | default y | |
1070 | ||
1071 | config C_B3PEN | |
1072 | depends on BF561 | |
1073 | bool "Bank 3 16 bit packing enable" | |
1074 | default n | |
1075 | ||
1076 | choice | |
692105b8 | 1077 | prompt "Enable Asynchronous Memory Banks" |
1394f032 BW |
1078 | default C_AMBEN_ALL |
1079 | ||
1080 | config C_AMBEN | |
1081 | bool "Disable All Banks" | |
1082 | ||
1083 | config C_AMBEN_B0 | |
1084 | bool "Enable Bank 0" | |
1085 | ||
1086 | config C_AMBEN_B0_B1 | |
1087 | bool "Enable Bank 0 & 1" | |
1088 | ||
1089 | config C_AMBEN_B0_B1_B2 | |
1090 | bool "Enable Bank 0 & 1 & 2" | |
1091 | ||
1092 | config C_AMBEN_ALL | |
1093 | bool "Enable All Banks" | |
1094 | endchoice | |
1095 | endmenu | |
1096 | ||
1097 | menu "EBIU_AMBCTL Control" | |
1098 | config BANK_0 | |
c8342f87 | 1099 | hex "Bank 0 (AMBCTL0.L)" |
1394f032 | 1100 | default 0x7BB0 |
c8342f87 MF |
1101 | help |
1102 | These are the low 16 bits of the EBIU_AMBCTL0 MMR which are | |
1103 | used to control the Asynchronous Memory Bank 0 settings. | |
1394f032 BW |
1104 | |
1105 | config BANK_1 | |
c8342f87 | 1106 | hex "Bank 1 (AMBCTL0.H)" |
1394f032 | 1107 | default 0x7BB0 |
197fba56 | 1108 | default 0x5558 if BF54x |
c8342f87 MF |
1109 | help |
1110 | These are the high 16 bits of the EBIU_AMBCTL0 MMR which are | |
1111 | used to control the Asynchronous Memory Bank 1 settings. | |
1394f032 BW |
1112 | |
1113 | config BANK_2 | |
c8342f87 | 1114 | hex "Bank 2 (AMBCTL1.L)" |
1394f032 | 1115 | default 0x7BB0 |
c8342f87 MF |
1116 | help |
1117 | These are the low 16 bits of the EBIU_AMBCTL1 MMR which are | |
1118 | used to control the Asynchronous Memory Bank 2 settings. | |
1394f032 BW |
1119 | |
1120 | config BANK_3 | |
c8342f87 | 1121 | hex "Bank 3 (AMBCTL1.H)" |
1394f032 | 1122 | default 0x99B3 |
c8342f87 MF |
1123 | help |
1124 | These are the high 16 bits of the EBIU_AMBCTL1 MMR which are | |
1125 | used to control the Asynchronous Memory Bank 3 settings. | |
1126 | ||
1394f032 BW |
1127 | endmenu |
1128 | ||
e40540b3 SZ |
1129 | config EBIU_MBSCTLVAL |
1130 | hex "EBIU Bank Select Control Register" | |
1131 | depends on BF54x | |
1132 | default 0 | |
1133 | ||
1134 | config EBIU_MODEVAL | |
1135 | hex "Flash Memory Mode Control Register" | |
1136 | depends on BF54x | |
1137 | default 1 | |
1138 | ||
1139 | config EBIU_FCTLVAL | |
1140 | hex "Flash Memory Bank Control Register" | |
1141 | depends on BF54x | |
1142 | default 6 | |
1394f032 BW |
1143 | endmenu |
1144 | ||
1145 | ############################################################################# | |
1146 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" | |
1147 | ||
1148 | config PCI | |
1149 | bool "PCI support" | |
a95ca3b2 | 1150 | depends on BROKEN |
1394f032 BW |
1151 | help |
1152 | Support for PCI bus. | |
1153 | ||
1154 | source "drivers/pci/Kconfig" | |
1155 | ||
1394f032 BW |
1156 | source "drivers/pcmcia/Kconfig" |
1157 | ||
1158 | source "drivers/pci/hotplug/Kconfig" | |
1159 | ||
1160 | endmenu | |
1161 | ||
1162 | menu "Executable file formats" | |
1163 | ||
1164 | source "fs/Kconfig.binfmt" | |
1165 | ||
1166 | endmenu | |
1167 | ||
1168 | menu "Power management options" | |
ad46163a | 1169 | |
1394f032 BW |
1170 | source "kernel/power/Kconfig" |
1171 | ||
f4cb5700 JB |
1172 | config ARCH_SUSPEND_POSSIBLE |
1173 | def_bool y | |
f4cb5700 | 1174 | |
1394f032 | 1175 | choice |
1efc80b5 | 1176 | prompt "Standby Power Saving Mode" |
1394f032 | 1177 | depends on PM |
cfefe3c6 MH |
1178 | default PM_BFIN_SLEEP_DEEPER |
1179 | config PM_BFIN_SLEEP_DEEPER | |
1180 | bool "Sleep Deeper" | |
1181 | help | |
1182 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic | |
1183 | power dissipation by disabling the clock to the processor core (CCLK). | |
1184 | Furthermore, Standby sets the internal power supply voltage (VDDINT) | |
1185 | to 0.85 V to provide the greatest power savings, while preserving the | |
1186 | processor state. | |
1187 | The PLL and system clock (SCLK) continue to operate at a very low | |
1188 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, | |
1189 | the SDRAM is put into Self Refresh Mode. Typically an external event | |
1190 | such as GPIO interrupt or RTC activity wakes up the processor. | |
1191 | Various Peripherals such as UART, SPORT, PPI may not function as | |
1192 | normal during Sleep Deeper, due to the reduced SCLK frequency. | |
1193 | When in the sleep mode, system DMA access to L1 memory is not supported. | |
1194 | ||
1efc80b5 MH |
1195 | If unsure, select "Sleep Deeper". |
1196 | ||
cfefe3c6 MH |
1197 | config PM_BFIN_SLEEP |
1198 | bool "Sleep" | |
1199 | help | |
1200 | Sleep Mode (High Power Savings) - The sleep mode reduces power | |
1201 | dissipation by disabling the clock to the processor core (CCLK). | |
1202 | The PLL and system clock (SCLK), however, continue to operate in | |
1203 | this mode. Typically an external event or RTC activity will wake | |
1efc80b5 MH |
1204 | up the processor. When in the sleep mode, system DMA access to L1 |
1205 | memory is not supported. | |
1206 | ||
1207 | If unsure, select "Sleep Deeper". | |
cfefe3c6 | 1208 | endchoice |
1394f032 | 1209 | |
1efc80b5 MH |
1210 | comment "Possible Suspend Mem / Hibernate Wake-Up Sources" |
1211 | depends on PM | |
1212 | ||
1efc80b5 MH |
1213 | config PM_BFIN_WAKE_PH6 |
1214 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" | |
2f6f4bcd | 1215 | depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) |
1efc80b5 MH |
1216 | default n |
1217 | help | |
1218 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) | |
1219 | ||
1efc80b5 MH |
1220 | config PM_BFIN_WAKE_GP |
1221 | bool "Allow Wake-Up from GPIOs" | |
1222 | depends on PM && BF54x | |
1223 | default n | |
1224 | help | |
1225 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) | |
19986289 MH |
1226 | (all processors, except ADSP-BF549). This option sets |
1227 | the general-purpose wake-up enable (GPWE) control bit to enable | |
1228 | wake-up upon detection of an active low signal on the /GPW (PH7) pin. | |
1229 | On ADSP-BF549 this option enables the the same functionality on the | |
1230 | /MRXON pin also PH7. | |
1231 | ||
1394f032 BW |
1232 | endmenu |
1233 | ||
1394f032 BW |
1234 | menu "CPU Frequency scaling" |
1235 | ||
1236 | source "drivers/cpufreq/Kconfig" | |
1237 | ||
5ad2ca5f MH |
1238 | config BFIN_CPU_FREQ |
1239 | bool | |
1240 | depends on CPU_FREQ | |
1241 | select CPU_FREQ_TABLE | |
1242 | default y | |
1243 | ||
14b03204 MH |
1244 | config CPU_VOLTAGE |
1245 | bool "CPU Voltage scaling" | |
73feb5c0 | 1246 | depends on EXPERIMENTAL |
14b03204 MH |
1247 | depends on CPU_FREQ |
1248 | default n | |
1249 | help | |
1250 | Say Y here if you want CPU voltage scaling according to the CPU frequency. | |
1251 | This option violates the PLL BYPASS recommendation in the Blackfin Processor | |
73feb5c0 | 1252 | manuals. There is a theoretical risk that during VDDINT transitions |
14b03204 MH |
1253 | the PLL may unlock. |
1254 | ||
1394f032 BW |
1255 | endmenu |
1256 | ||
1394f032 BW |
1257 | source "net/Kconfig" |
1258 | ||
1259 | source "drivers/Kconfig" | |
1260 | ||
872d024b MF |
1261 | source "drivers/firmware/Kconfig" |
1262 | ||
1394f032 BW |
1263 | source "fs/Kconfig" |
1264 | ||
74ce8322 | 1265 | source "arch/blackfin/Kconfig.debug" |
1394f032 BW |
1266 | |
1267 | source "security/Kconfig" | |
1268 | ||
1269 | source "crypto/Kconfig" | |
1270 | ||
1271 | source "lib/Kconfig" |