]>
Commit | Line | Data |
---|---|---|
9e1b9b80 AJ |
1 | config SYMBOL_PREFIX |
2 | string | |
3 | default "_" | |
4 | ||
1394f032 | 5 | config MMU |
bac7d89e | 6 | def_bool n |
1394f032 BW |
7 | |
8 | config FPU | |
bac7d89e | 9 | def_bool n |
1394f032 BW |
10 | |
11 | config RWSEM_GENERIC_SPINLOCK | |
bac7d89e | 12 | def_bool y |
1394f032 BW |
13 | |
14 | config RWSEM_XCHGADD_ALGORITHM | |
bac7d89e | 15 | def_bool n |
1394f032 BW |
16 | |
17 | config BLACKFIN | |
bac7d89e | 18 | def_bool y |
652afdc3 | 19 | select HAVE_ARCH_KGDB |
e8f263df | 20 | select HAVE_ARCH_TRACEHOOK |
f5074429 MF |
21 | select HAVE_DYNAMIC_FTRACE |
22 | select HAVE_FTRACE_MCOUNT_RECORD | |
1ee76d7e | 23 | select HAVE_FUNCTION_GRAPH_TRACER |
1c873be7 | 24 | select HAVE_FUNCTION_TRACER |
aebfef03 | 25 | select HAVE_FUNCTION_TRACE_MCOUNT_TEST |
ec7748b5 | 26 | select HAVE_IDE |
7db79172 | 27 | select HAVE_IRQ_WORK |
d86bfb16 BS |
28 | select HAVE_KERNEL_GZIP if RAMKERNEL |
29 | select HAVE_KERNEL_BZIP2 if RAMKERNEL | |
30 | select HAVE_KERNEL_LZMA if RAMKERNEL | |
67df6cc6 | 31 | select HAVE_KERNEL_LZO if RAMKERNEL |
42d4b839 | 32 | select HAVE_OPROFILE |
7db79172 | 33 | select HAVE_PERF_EVENTS |
a4f0b32c | 34 | select ARCH_WANT_OPTIONAL_GPIOLIB |
7b028863 | 35 | select HAVE_GENERIC_HARDIRQS |
bee18beb | 36 | select GENERIC_ATOMIC64 |
7b028863 TG |
37 | select GENERIC_IRQ_PROBE |
38 | select IRQ_PER_CPU if SMP | |
d314d74c | 39 | select HAVE_NMI_WATCHDOG if NMI_WATCHDOG |
1394f032 | 40 | |
ddf9ddac MF |
41 | config GENERIC_CSUM |
42 | def_bool y | |
43 | ||
70f12567 MF |
44 | config GENERIC_BUG |
45 | def_bool y | |
46 | depends on BUG | |
47 | ||
e3defffe | 48 | config ZONE_DMA |
bac7d89e | 49 | def_bool y |
e3defffe | 50 | |
b2d1583f | 51 | config GENERIC_GPIO |
bac7d89e | 52 | def_bool y |
1394f032 BW |
53 | |
54 | config FORCE_MAX_ZONEORDER | |
55 | int | |
56 | default "14" | |
57 | ||
58 | config GENERIC_CALIBRATE_DELAY | |
bac7d89e | 59 | def_bool y |
1394f032 | 60 | |
6fa68e7a MF |
61 | config LOCKDEP_SUPPORT |
62 | def_bool y | |
63 | ||
c7b412f4 MF |
64 | config STACKTRACE_SUPPORT |
65 | def_bool y | |
66 | ||
8f86001f MF |
67 | config TRACE_IRQFLAGS_SUPPORT |
68 | def_bool y | |
1394f032 | 69 | |
1394f032 | 70 | source "init/Kconfig" |
dc52ddc0 | 71 | |
1394f032 BW |
72 | source "kernel/Kconfig.preempt" |
73 | ||
dc52ddc0 MH |
74 | source "kernel/Kconfig.freezer" |
75 | ||
1394f032 BW |
76 | menu "Blackfin Processor Options" |
77 | ||
78 | comment "Processor and Board Settings" | |
79 | ||
80 | choice | |
81 | prompt "CPU" | |
82 | default BF533 | |
83 | ||
2f6f4bcd BW |
84 | config BF512 |
85 | bool "BF512" | |
86 | help | |
87 | BF512 Processor Support. | |
88 | ||
89 | config BF514 | |
90 | bool "BF514" | |
91 | help | |
92 | BF514 Processor Support. | |
93 | ||
94 | config BF516 | |
95 | bool "BF516" | |
96 | help | |
97 | BF516 Processor Support. | |
98 | ||
99 | config BF518 | |
100 | bool "BF518" | |
101 | help | |
102 | BF518 Processor Support. | |
103 | ||
59003145 MH |
104 | config BF522 |
105 | bool "BF522" | |
106 | help | |
107 | BF522 Processor Support. | |
108 | ||
1545a111 MF |
109 | config BF523 |
110 | bool "BF523" | |
111 | help | |
112 | BF523 Processor Support. | |
113 | ||
114 | config BF524 | |
115 | bool "BF524" | |
116 | help | |
117 | BF524 Processor Support. | |
118 | ||
59003145 MH |
119 | config BF525 |
120 | bool "BF525" | |
121 | help | |
122 | BF525 Processor Support. | |
123 | ||
1545a111 MF |
124 | config BF526 |
125 | bool "BF526" | |
126 | help | |
127 | BF526 Processor Support. | |
128 | ||
59003145 MH |
129 | config BF527 |
130 | bool "BF527" | |
131 | help | |
132 | BF527 Processor Support. | |
133 | ||
1394f032 BW |
134 | config BF531 |
135 | bool "BF531" | |
136 | help | |
137 | BF531 Processor Support. | |
138 | ||
139 | config BF532 | |
140 | bool "BF532" | |
141 | help | |
142 | BF532 Processor Support. | |
143 | ||
144 | config BF533 | |
145 | bool "BF533" | |
146 | help | |
147 | BF533 Processor Support. | |
148 | ||
149 | config BF534 | |
150 | bool "BF534" | |
151 | help | |
152 | BF534 Processor Support. | |
153 | ||
154 | config BF536 | |
155 | bool "BF536" | |
156 | help | |
157 | BF536 Processor Support. | |
158 | ||
159 | config BF537 | |
160 | bool "BF537" | |
161 | help | |
162 | BF537 Processor Support. | |
163 | ||
dc26aec2 MH |
164 | config BF538 |
165 | bool "BF538" | |
166 | help | |
167 | BF538 Processor Support. | |
168 | ||
169 | config BF539 | |
170 | bool "BF539" | |
171 | help | |
172 | BF539 Processor Support. | |
173 | ||
5df326ac | 174 | config BF542_std |
24a07a12 RH |
175 | bool "BF542" |
176 | help | |
177 | BF542 Processor Support. | |
178 | ||
2f89c063 MF |
179 | config BF542M |
180 | bool "BF542m" | |
181 | help | |
182 | BF542 Processor Support. | |
183 | ||
5df326ac | 184 | config BF544_std |
24a07a12 RH |
185 | bool "BF544" |
186 | help | |
187 | BF544 Processor Support. | |
188 | ||
2f89c063 MF |
189 | config BF544M |
190 | bool "BF544m" | |
191 | help | |
192 | BF544 Processor Support. | |
193 | ||
5df326ac | 194 | config BF547_std |
7c7fd170 MF |
195 | bool "BF547" |
196 | help | |
197 | BF547 Processor Support. | |
198 | ||
2f89c063 MF |
199 | config BF547M |
200 | bool "BF547m" | |
201 | help | |
202 | BF547 Processor Support. | |
203 | ||
5df326ac | 204 | config BF548_std |
24a07a12 RH |
205 | bool "BF548" |
206 | help | |
207 | BF548 Processor Support. | |
208 | ||
2f89c063 MF |
209 | config BF548M |
210 | bool "BF548m" | |
211 | help | |
212 | BF548 Processor Support. | |
213 | ||
5df326ac | 214 | config BF549_std |
24a07a12 RH |
215 | bool "BF549" |
216 | help | |
217 | BF549 Processor Support. | |
218 | ||
2f89c063 MF |
219 | config BF549M |
220 | bool "BF549m" | |
221 | help | |
222 | BF549 Processor Support. | |
223 | ||
1394f032 BW |
224 | config BF561 |
225 | bool "BF561" | |
226 | help | |
cd88b4dc | 227 | BF561 Processor Support. |
1394f032 BW |
228 | |
229 | endchoice | |
230 | ||
46fa5eec GY |
231 | config SMP |
232 | depends on BF561 | |
0d152c27 | 233 | select TICKSOURCE_CORETMR |
46fa5eec GY |
234 | bool "Symmetric multi-processing support" |
235 | ---help--- | |
236 | This enables support for systems with more than one CPU, | |
237 | like the dual core BF561. If you have a system with only one | |
238 | CPU, say N. If you have a system with more than one CPU, say Y. | |
239 | ||
240 | If you don't know what to do here, say N. | |
241 | ||
242 | config NR_CPUS | |
243 | int | |
244 | depends on SMP | |
245 | default 2 if BF561 | |
246 | ||
0b39db28 GY |
247 | config HOTPLUG_CPU |
248 | bool "Support for hot-pluggable CPUs" | |
249 | depends on SMP && HOTPLUG | |
250 | default y | |
251 | ||
0c0497c2 MF |
252 | config BF_REV_MIN |
253 | int | |
2f89c063 | 254 | default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) |
0c0497c2 | 255 | default 2 if (BF537 || BF536 || BF534) |
2f89c063 | 256 | default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) |
2f6f4bcd | 257 | default 4 if (BF538 || BF539) |
0c0497c2 MF |
258 | |
259 | config BF_REV_MAX | |
260 | int | |
2f89c063 MF |
261 | default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) |
262 | default 3 if (BF537 || BF536 || BF534 || BF54xM) | |
2f6f4bcd | 263 | default 5 if (BF561 || BF538 || BF539) |
0c0497c2 MF |
264 | default 6 if (BF533 || BF532 || BF531) |
265 | ||
1394f032 BW |
266 | choice |
267 | prompt "Silicon Rev" | |
f8b55651 MF |
268 | default BF_REV_0_0 if (BF51x || BF52x) |
269 | default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) | |
2f89c063 | 270 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) |
24a07a12 RH |
271 | |
272 | config BF_REV_0_0 | |
273 | bool "0.0" | |
2f89c063 | 274 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
59003145 MH |
275 | |
276 | config BF_REV_0_1 | |
d07f4380 | 277 | bool "0.1" |
3d15f302 | 278 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
1394f032 BW |
279 | |
280 | config BF_REV_0_2 | |
281 | bool "0.2" | |
8060bb6f | 282 | depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) |
1394f032 BW |
283 | |
284 | config BF_REV_0_3 | |
285 | bool "0.3" | |
2f89c063 | 286 | depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) |
1394f032 BW |
287 | |
288 | config BF_REV_0_4 | |
289 | bool "0.4" | |
dc26aec2 | 290 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 BW |
291 | |
292 | config BF_REV_0_5 | |
293 | bool "0.5" | |
dc26aec2 | 294 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 | 295 | |
49f7253c MF |
296 | config BF_REV_0_6 |
297 | bool "0.6" | |
298 | depends on (BF533 || BF532 || BF531) | |
299 | ||
de3025f4 JZ |
300 | config BF_REV_ANY |
301 | bool "any" | |
302 | ||
303 | config BF_REV_NONE | |
304 | bool "none" | |
305 | ||
1394f032 BW |
306 | endchoice |
307 | ||
24a07a12 RH |
308 | config BF53x |
309 | bool | |
310 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) | |
311 | default y | |
312 | ||
1394f032 BW |
313 | config MEM_MT48LC64M4A2FB_7E |
314 | bool | |
315 | depends on (BFIN533_STAMP) | |
316 | default y | |
317 | ||
318 | config MEM_MT48LC16M16A2TG_75 | |
319 | bool | |
320 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | |
60584344 HK |
321 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \ |
322 | || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \ | |
323 | || BFIN527_BLUETECHNIX_CM) | |
1394f032 BW |
324 | default y |
325 | ||
326 | config MEM_MT48LC32M8A2_75 | |
327 | bool | |
084f9ebf | 328 | depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) |
1394f032 BW |
329 | default y |
330 | ||
331 | config MEM_MT48LC8M32B2B5_7 | |
332 | bool | |
333 | depends on (BFIN561_BLUETECHNIX_CM) | |
334 | default y | |
335 | ||
59003145 MH |
336 | config MEM_MT48LC32M16A2TG_75 |
337 | bool | |
8effc4a6 | 338 | depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL) |
59003145 MH |
339 | default y |
340 | ||
ee48efb5 GY |
341 | config MEM_MT48H32M16LFCJ_75 |
342 | bool | |
343 | depends on (BFIN526_EZBRD) | |
344 | default y | |
345 | ||
2f6f4bcd | 346 | source "arch/blackfin/mach-bf518/Kconfig" |
59003145 | 347 | source "arch/blackfin/mach-bf527/Kconfig" |
1394f032 BW |
348 | source "arch/blackfin/mach-bf533/Kconfig" |
349 | source "arch/blackfin/mach-bf561/Kconfig" | |
350 | source "arch/blackfin/mach-bf537/Kconfig" | |
dc26aec2 | 351 | source "arch/blackfin/mach-bf538/Kconfig" |
24a07a12 | 352 | source "arch/blackfin/mach-bf548/Kconfig" |
1394f032 BW |
353 | |
354 | menu "Board customizations" | |
355 | ||
356 | config CMDLINE_BOOL | |
357 | bool "Default bootloader kernel arguments" | |
358 | ||
359 | config CMDLINE | |
360 | string "Initial kernel command string" | |
361 | depends on CMDLINE_BOOL | |
362 | default "console=ttyBF0,57600" | |
363 | help | |
364 | If you don't have a boot loader capable of passing a command line string | |
365 | to the kernel, you may specify one here. As a minimum, you should specify | |
366 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). | |
367 | ||
5f004c20 MF |
368 | config BOOT_LOAD |
369 | hex "Kernel load address for booting" | |
370 | default "0x1000" | |
371 | range 0x1000 0x20000000 | |
372 | help | |
373 | This option allows you to set the load address of the kernel. | |
374 | This can be useful if you are on a board which has a small amount | |
375 | of memory or you wish to reserve some memory at the beginning of | |
376 | the address space. | |
377 | ||
378 | Note that you need to keep this value above 4k (0x1000) as this | |
379 | memory region is used to capture NULL pointer references as well | |
380 | as some core kernel functions. | |
381 | ||
8cc7117e MH |
382 | config ROM_BASE |
383 | hex "Kernel ROM Base" | |
86249911 | 384 | depends on ROMKERNEL |
d86bfb16 | 385 | default "0x20040040" |
8cc7117e MH |
386 | range 0x20000000 0x20400000 if !(BF54x || BF561) |
387 | range 0x20000000 0x30000000 if (BF54x || BF561) | |
388 | help | |
d86bfb16 BS |
389 | Make sure your ROM base does not include any file-header |
390 | information that is prepended to the kernel. | |
391 | ||
392 | For example, the bootable U-Boot format (created with | |
393 | mkimage) has a 64 byte header (0x40). So while the image | |
394 | you write to flash might start at say 0x20080000, you have | |
395 | to add 0x40 to get the kernel's ROM base as it will come | |
396 | after the header. | |
8cc7117e | 397 | |
f16295e7 | 398 | comment "Clock/PLL Setup" |
1394f032 BW |
399 | |
400 | config CLKIN_HZ | |
2fb6cb41 | 401 | int "Frequency of the crystal on the board in Hz" |
d0cb9b4e | 402 | default "10000000" if BFIN532_IP0X |
1394f032 | 403 | default "11059200" if BFIN533_STAMP |
d0cb9b4e MF |
404 | default "24576000" if PNAV10 |
405 | default "25000000" # most people use this | |
1394f032 | 406 | default "27000000" if BFIN533_EZKIT |
1394f032 | 407 | default "30000000" if BFIN561_EZKIT |
8effc4a6 | 408 | default "24000000" if BFIN527_AD7160EVAL |
1394f032 BW |
409 | help |
410 | The frequency of CLKIN crystal oscillator on the board in Hz. | |
2fb6cb41 SZ |
411 | Warning: This value should match the crystal on the board. Otherwise, |
412 | peripherals won't work properly. | |
1394f032 | 413 | |
f16295e7 RG |
414 | config BFIN_KERNEL_CLOCK |
415 | bool "Re-program Clocks while Kernel boots?" | |
416 | default n | |
417 | help | |
418 | This option decides if kernel clocks are re-programed from the | |
419 | bootloader settings. If the clocks are not set, the SDRAM settings | |
420 | are also not changed, and the Bootloader does 100% of the hardware | |
421 | configuration. | |
422 | ||
423 | config PLL_BYPASS | |
e4e9a7ad MF |
424 | bool "Bypass PLL" |
425 | depends on BFIN_KERNEL_CLOCK | |
426 | default n | |
f16295e7 RG |
427 | |
428 | config CLKIN_HALF | |
429 | bool "Half Clock In" | |
430 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
431 | default n | |
432 | help | |
433 | If this is set the clock will be divided by 2, before it goes to the PLL. | |
434 | ||
435 | config VCO_MULT | |
436 | int "VCO Multiplier" | |
437 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
438 | range 1 64 | |
439 | default "22" if BFIN533_EZKIT | |
440 | default "45" if BFIN533_STAMP | |
6924dfb0 | 441 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) |
f16295e7 | 442 | default "22" if BFIN533_BLUETECHNIX_CM |
60584344 | 443 | default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
f16295e7 | 444 | default "20" if BFIN561_EZKIT |
2f6f4bcd | 445 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) |
8effc4a6 | 446 | default "25" if BFIN527_AD7160EVAL |
f16295e7 RG |
447 | help |
448 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | |
449 | PLL Frequency = (Crystal Frequency) * (this setting) | |
450 | ||
451 | choice | |
452 | prompt "Core Clock Divider" | |
453 | depends on BFIN_KERNEL_CLOCK | |
454 | default CCLK_DIV_1 | |
455 | help | |
456 | This sets the frequency of the core. It can be 1, 2, 4 or 8 | |
457 | Core Frequency = (PLL frequency) / (this setting) | |
458 | ||
459 | config CCLK_DIV_1 | |
460 | bool "1" | |
461 | ||
462 | config CCLK_DIV_2 | |
463 | bool "2" | |
464 | ||
465 | config CCLK_DIV_4 | |
466 | bool "4" | |
467 | ||
468 | config CCLK_DIV_8 | |
469 | bool "8" | |
470 | endchoice | |
471 | ||
472 | config SCLK_DIV | |
473 | int "System Clock Divider" | |
474 | depends on BFIN_KERNEL_CLOCK | |
475 | range 1 15 | |
5f004c20 | 476 | default 5 |
f16295e7 RG |
477 | help |
478 | This sets the frequency of the system clock (including SDRAM or DDR). | |
479 | This can be between 1 and 15 | |
480 | System Clock = (PLL frequency) / (this setting) | |
481 | ||
5f004c20 MF |
482 | choice |
483 | prompt "DDR SDRAM Chip Type" | |
484 | depends on BFIN_KERNEL_CLOCK | |
485 | depends on BF54x | |
486 | default MEM_MT46V32M16_5B | |
487 | ||
488 | config MEM_MT46V32M16_6T | |
489 | bool "MT46V32M16_6T" | |
490 | ||
491 | config MEM_MT46V32M16_5B | |
492 | bool "MT46V32M16_5B" | |
493 | endchoice | |
494 | ||
73feb5c0 MH |
495 | choice |
496 | prompt "DDR/SDRAM Timing" | |
497 | depends on BFIN_KERNEL_CLOCK | |
498 | default BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
499 | help | |
500 | This option allows you to specify Blackfin SDRAM/DDR Timing parameters | |
501 | The calculated SDRAM timing parameters may not be 100% | |
502 | accurate - This option is therefore marked experimental. | |
503 | ||
504 | config BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
505 | bool "Calculate Timings (EXPERIMENTAL)" | |
506 | depends on EXPERIMENTAL | |
507 | ||
508 | config BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
509 | bool "Provide accurate Timings based on target SCLK" | |
510 | help | |
511 | Please consult the Blackfin Hardware Reference Manuals as well | |
512 | as the memory device datasheet. | |
513 | http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram | |
514 | endchoice | |
515 | ||
516 | menu "Memory Init Control" | |
517 | depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
518 | ||
519 | config MEM_DDRCTL0 | |
520 | depends on BF54x | |
521 | hex "DDRCTL0" | |
522 | default 0x0 | |
523 | ||
524 | config MEM_DDRCTL1 | |
525 | depends on BF54x | |
526 | hex "DDRCTL1" | |
527 | default 0x0 | |
528 | ||
529 | config MEM_DDRCTL2 | |
530 | depends on BF54x | |
531 | hex "DDRCTL2" | |
532 | default 0x0 | |
533 | ||
534 | config MEM_EBIU_DDRQUE | |
535 | depends on BF54x | |
536 | hex "DDRQUE" | |
537 | default 0x0 | |
538 | ||
539 | config MEM_SDRRC | |
540 | depends on !BF54x | |
541 | hex "SDRRC" | |
542 | default 0x0 | |
543 | ||
544 | config MEM_SDGCTL | |
545 | depends on !BF54x | |
546 | hex "SDGCTL" | |
547 | default 0x0 | |
548 | endmenu | |
549 | ||
f16295e7 RG |
550 | # |
551 | # Max & Min Speeds for various Chips | |
552 | # | |
553 | config MAX_VCO_HZ | |
554 | int | |
2f6f4bcd BW |
555 | default 400000000 if BF512 |
556 | default 400000000 if BF514 | |
557 | default 400000000 if BF516 | |
558 | default 400000000 if BF518 | |
7b06263b MF |
559 | default 400000000 if BF522 |
560 | default 600000000 if BF523 | |
1545a111 | 561 | default 400000000 if BF524 |
f16295e7 | 562 | default 600000000 if BF525 |
1545a111 | 563 | default 400000000 if BF526 |
f16295e7 RG |
564 | default 600000000 if BF527 |
565 | default 400000000 if BF531 | |
566 | default 400000000 if BF532 | |
567 | default 750000000 if BF533 | |
568 | default 500000000 if BF534 | |
569 | default 400000000 if BF536 | |
570 | default 600000000 if BF537 | |
f72eecb9 RG |
571 | default 533333333 if BF538 |
572 | default 533333333 if BF539 | |
f16295e7 | 573 | default 600000000 if BF542 |
f72eecb9 | 574 | default 533333333 if BF544 |
1545a111 MF |
575 | default 600000000 if BF547 |
576 | default 600000000 if BF548 | |
f72eecb9 | 577 | default 533333333 if BF549 |
f16295e7 RG |
578 | default 600000000 if BF561 |
579 | ||
580 | config MIN_VCO_HZ | |
581 | int | |
582 | default 50000000 | |
583 | ||
584 | config MAX_SCLK_HZ | |
585 | int | |
f72eecb9 | 586 | default 133333333 |
f16295e7 RG |
587 | |
588 | config MIN_SCLK_HZ | |
589 | int | |
590 | default 27000000 | |
591 | ||
592 | comment "Kernel Timer/Scheduler" | |
593 | ||
594 | source kernel/Kconfig.hz | |
595 | ||
8b5f79f9 VM |
596 | config GENERIC_CLOCKEVENTS |
597 | bool "Generic clock events" | |
8b5f79f9 VM |
598 | default y |
599 | ||
0d152c27 | 600 | menu "Clock event device" |
1fa9be72 | 601 | depends on GENERIC_CLOCKEVENTS |
1fa9be72 | 602 | config TICKSOURCE_GPTMR0 |
0d152c27 YL |
603 | bool "GPTimer0" |
604 | depends on !SMP | |
1fa9be72 | 605 | select BFIN_GPTIMERS |
1fa9be72 GY |
606 | |
607 | config TICKSOURCE_CORETMR | |
0d152c27 YL |
608 | bool "Core timer" |
609 | default y | |
610 | endmenu | |
1fa9be72 | 611 | |
0d152c27 | 612 | menu "Clock souce" |
8b5f79f9 | 613 | depends on GENERIC_CLOCKEVENTS |
0d152c27 YL |
614 | config CYCLES_CLOCKSOURCE |
615 | bool "CYCLES" | |
616 | default y | |
8b5f79f9 | 617 | depends on !BFIN_SCRATCH_REG_CYCLES |
1fa9be72 | 618 | depends on !SMP |
8b5f79f9 VM |
619 | help |
620 | If you say Y here, you will enable support for using the 'cycles' | |
621 | registers as a clock source. Doing so means you will be unable to | |
622 | safely write to the 'cycles' register during runtime. You will | |
623 | still be able to read it (such as for performance monitoring), but | |
624 | writing the registers will most likely crash the kernel. | |
625 | ||
1fa9be72 | 626 | config GPTMR0_CLOCKSOURCE |
0d152c27 | 627 | bool "GPTimer0" |
3aca47c0 | 628 | select BFIN_GPTIMERS |
1fa9be72 | 629 | depends on !TICKSOURCE_GPTMR0 |
0d152c27 | 630 | endmenu |
1fa9be72 | 631 | |
10f03f1a JS |
632 | config ARCH_USES_GETTIMEOFFSET |
633 | depends on !GENERIC_CLOCKEVENTS | |
634 | def_bool y | |
635 | ||
8b5f79f9 VM |
636 | source kernel/time/Kconfig |
637 | ||
5f004c20 | 638 | comment "Misc" |
971d5bc4 | 639 | |
f0b5d12f MF |
640 | choice |
641 | prompt "Blackfin Exception Scratch Register" | |
642 | default BFIN_SCRATCH_REG_RETN | |
643 | help | |
644 | Select the resource to reserve for the Exception handler: | |
645 | - RETN: Non-Maskable Interrupt (NMI) | |
646 | - RETE: Exception Return (JTAG/ICE) | |
647 | - CYCLES: Performance counter | |
648 | ||
649 | If you are unsure, please select "RETN". | |
650 | ||
651 | config BFIN_SCRATCH_REG_RETN | |
652 | bool "RETN" | |
653 | help | |
654 | Use the RETN register in the Blackfin exception handler | |
655 | as a stack scratch register. This means you cannot | |
656 | safely use NMI on the Blackfin while running Linux, but | |
657 | you can debug the system with a JTAG ICE and use the | |
658 | CYCLES performance registers. | |
659 | ||
660 | If you are unsure, please select "RETN". | |
661 | ||
662 | config BFIN_SCRATCH_REG_RETE | |
663 | bool "RETE" | |
664 | help | |
665 | Use the RETE register in the Blackfin exception handler | |
666 | as a stack scratch register. This means you cannot | |
667 | safely use a JTAG ICE while debugging a Blackfin board, | |
668 | but you can safely use the CYCLES performance registers | |
669 | and the NMI. | |
670 | ||
671 | If you are unsure, please select "RETN". | |
672 | ||
673 | config BFIN_SCRATCH_REG_CYCLES | |
674 | bool "CYCLES" | |
675 | help | |
676 | Use the CYCLES register in the Blackfin exception handler | |
677 | as a stack scratch register. This means you cannot | |
678 | safely use the CYCLES performance registers on a Blackfin | |
679 | board at anytime, but you can debug the system with a JTAG | |
680 | ICE and use the NMI. | |
681 | ||
682 | If you are unsure, please select "RETN". | |
683 | ||
684 | endchoice | |
685 | ||
1394f032 BW |
686 | endmenu |
687 | ||
688 | ||
689 | menu "Blackfin Kernel Optimizations" | |
690 | ||
1394f032 BW |
691 | comment "Memory Optimizations" |
692 | ||
693 | config I_ENTRY_L1 | |
694 | bool "Locate interrupt entry code in L1 Memory" | |
695 | default y | |
820b127d | 696 | depends on !SMP |
1394f032 | 697 | help |
01dd2fbf ML |
698 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
699 | into L1 instruction memory. (less latency) | |
1394f032 BW |
700 | |
701 | config EXCPT_IRQ_SYSC_L1 | |
01dd2fbf | 702 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
1394f032 | 703 | default y |
820b127d | 704 | depends on !SMP |
1394f032 | 705 | help |
01dd2fbf | 706 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
cfefe3c6 | 707 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
01dd2fbf | 708 | (less latency) |
1394f032 BW |
709 | |
710 | config DO_IRQ_L1 | |
711 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | |
712 | default y | |
820b127d | 713 | depends on !SMP |
1394f032 | 714 | help |
01dd2fbf ML |
715 | If enabled, the frequently called do_irq dispatcher function is linked |
716 | into L1 instruction memory. (less latency) | |
1394f032 BW |
717 | |
718 | config CORE_TIMER_IRQ_L1 | |
719 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | |
720 | default y | |
820b127d | 721 | depends on !SMP |
1394f032 | 722 | help |
01dd2fbf ML |
723 | If enabled, the frequently called timer_interrupt() function is linked |
724 | into L1 instruction memory. (less latency) | |
1394f032 BW |
725 | |
726 | config IDLE_L1 | |
727 | bool "Locate frequently idle function in L1 Memory" | |
728 | default y | |
820b127d | 729 | depends on !SMP |
1394f032 | 730 | help |
01dd2fbf ML |
731 | If enabled, the frequently called idle function is linked |
732 | into L1 instruction memory. (less latency) | |
1394f032 BW |
733 | |
734 | config SCHEDULE_L1 | |
735 | bool "Locate kernel schedule function in L1 Memory" | |
736 | default y | |
820b127d | 737 | depends on !SMP |
1394f032 | 738 | help |
01dd2fbf ML |
739 | If enabled, the frequently called kernel schedule is linked |
740 | into L1 instruction memory. (less latency) | |
1394f032 BW |
741 | |
742 | config ARITHMETIC_OPS_L1 | |
743 | bool "Locate kernel owned arithmetic functions in L1 Memory" | |
744 | default y | |
820b127d | 745 | depends on !SMP |
1394f032 | 746 | help |
01dd2fbf ML |
747 | If enabled, arithmetic functions are linked |
748 | into L1 instruction memory. (less latency) | |
1394f032 BW |
749 | |
750 | config ACCESS_OK_L1 | |
751 | bool "Locate access_ok function in L1 Memory" | |
752 | default y | |
820b127d | 753 | depends on !SMP |
1394f032 | 754 | help |
01dd2fbf ML |
755 | If enabled, the access_ok function is linked |
756 | into L1 instruction memory. (less latency) | |
1394f032 BW |
757 | |
758 | config MEMSET_L1 | |
759 | bool "Locate memset function in L1 Memory" | |
760 | default y | |
820b127d | 761 | depends on !SMP |
1394f032 | 762 | help |
01dd2fbf ML |
763 | If enabled, the memset function is linked |
764 | into L1 instruction memory. (less latency) | |
1394f032 BW |
765 | |
766 | config MEMCPY_L1 | |
767 | bool "Locate memcpy function in L1 Memory" | |
768 | default y | |
820b127d | 769 | depends on !SMP |
1394f032 | 770 | help |
01dd2fbf ML |
771 | If enabled, the memcpy function is linked |
772 | into L1 instruction memory. (less latency) | |
1394f032 | 773 | |
479ba603 RG |
774 | config STRCMP_L1 |
775 | bool "locate strcmp function in L1 Memory" | |
776 | default y | |
820b127d | 777 | depends on !SMP |
479ba603 RG |
778 | help |
779 | If enabled, the strcmp function is linked | |
780 | into L1 instruction memory (less latency). | |
781 | ||
782 | config STRNCMP_L1 | |
783 | bool "locate strncmp function in L1 Memory" | |
784 | default y | |
820b127d | 785 | depends on !SMP |
479ba603 RG |
786 | help |
787 | If enabled, the strncmp function is linked | |
788 | into L1 instruction memory (less latency). | |
789 | ||
790 | config STRCPY_L1 | |
791 | bool "locate strcpy function in L1 Memory" | |
792 | default y | |
820b127d | 793 | depends on !SMP |
479ba603 RG |
794 | help |
795 | If enabled, the strcpy function is linked | |
796 | into L1 instruction memory (less latency). | |
797 | ||
798 | config STRNCPY_L1 | |
799 | bool "locate strncpy function in L1 Memory" | |
800 | default y | |
820b127d | 801 | depends on !SMP |
479ba603 RG |
802 | help |
803 | If enabled, the strncpy function is linked | |
804 | into L1 instruction memory (less latency). | |
805 | ||
1394f032 BW |
806 | config SYS_BFIN_SPINLOCK_L1 |
807 | bool "Locate sys_bfin_spinlock function in L1 Memory" | |
808 | default y | |
820b127d | 809 | depends on !SMP |
1394f032 | 810 | help |
01dd2fbf ML |
811 | If enabled, sys_bfin_spinlock function is linked |
812 | into L1 instruction memory. (less latency) | |
1394f032 BW |
813 | |
814 | config IP_CHECKSUM_L1 | |
815 | bool "Locate IP Checksum function in L1 Memory" | |
816 | default n | |
820b127d | 817 | depends on !SMP |
1394f032 | 818 | help |
01dd2fbf ML |
819 | If enabled, the IP Checksum function is linked |
820 | into L1 instruction memory. (less latency) | |
1394f032 BW |
821 | |
822 | config CACHELINE_ALIGNED_L1 | |
823 | bool "Locate cacheline_aligned data to L1 Data Memory" | |
157cc5aa MH |
824 | default y if !BF54x |
825 | default n if BF54x | |
820b127d | 826 | depends on !SMP && !BF531 |
1394f032 | 827 | help |
692105b8 | 828 | If enabled, cacheline_aligned data is linked |
01dd2fbf | 829 | into L1 data memory. (less latency) |
1394f032 BW |
830 | |
831 | config SYSCALL_TAB_L1 | |
832 | bool "Locate Syscall Table L1 Data Memory" | |
833 | default n | |
820b127d | 834 | depends on !SMP && !BF531 |
1394f032 | 835 | help |
01dd2fbf ML |
836 | If enabled, the Syscall LUT is linked |
837 | into L1 data memory. (less latency) | |
1394f032 BW |
838 | |
839 | config CPLB_SWITCH_TAB_L1 | |
840 | bool "Locate CPLB Switch Tables L1 Data Memory" | |
841 | default n | |
820b127d | 842 | depends on !SMP && !BF531 |
1394f032 | 843 | help |
01dd2fbf ML |
844 | If enabled, the CPLB Switch Tables are linked |
845 | into L1 data memory. (less latency) | |
1394f032 | 846 | |
820b127d MF |
847 | config ICACHE_FLUSH_L1 |
848 | bool "Locate icache flush funcs in L1 Inst Memory" | |
74181295 MF |
849 | default y |
850 | help | |
820b127d | 851 | If enabled, the Blackfin icache flushing functions are linked |
74181295 MF |
852 | into L1 instruction memory. |
853 | ||
854 | Note that this might be required to address anomalies, but | |
855 | these functions are pretty small, so it shouldn't be too bad. | |
856 | If you are using a processor affected by an anomaly, the build | |
857 | system will double check for you and prevent it. | |
858 | ||
820b127d MF |
859 | config DCACHE_FLUSH_L1 |
860 | bool "Locate dcache flush funcs in L1 Inst Memory" | |
861 | default y | |
862 | depends on !SMP | |
863 | help | |
864 | If enabled, the Blackfin dcache flushing functions are linked | |
865 | into L1 instruction memory. | |
866 | ||
ca87b7ad GY |
867 | config APP_STACK_L1 |
868 | bool "Support locating application stack in L1 Scratch Memory" | |
869 | default y | |
820b127d | 870 | depends on !SMP |
ca87b7ad GY |
871 | help |
872 | If enabled the application stack can be located in L1 | |
873 | scratch memory (less latency). | |
874 | ||
875 | Currently only works with FLAT binaries. | |
876 | ||
6ad2b84c MF |
877 | config EXCEPTION_L1_SCRATCH |
878 | bool "Locate exception stack in L1 Scratch Memory" | |
879 | default n | |
820b127d | 880 | depends on !SMP && !APP_STACK_L1 |
6ad2b84c MF |
881 | help |
882 | Whenever an exception occurs, use the L1 Scratch memory for | |
883 | stack storage. You cannot place the stacks of FLAT binaries | |
884 | in L1 when using this option. | |
885 | ||
886 | If you don't use L1 Scratch, then you should say Y here. | |
887 | ||
251383c7 RG |
888 | comment "Speed Optimizations" |
889 | config BFIN_INS_LOWOVERHEAD | |
890 | bool "ins[bwl] low overhead, higher interrupt latency" | |
891 | default y | |
820b127d | 892 | depends on !SMP |
251383c7 RG |
893 | help |
894 | Reads on the Blackfin are speculative. In Blackfin terms, this means | |
895 | they can be interrupted at any time (even after they have been issued | |
896 | on to the external bus), and re-issued after the interrupt occurs. | |
897 | For memory - this is not a big deal, since memory does not change if | |
898 | it sees a read. | |
899 | ||
900 | If a FIFO is sitting on the end of the read, it will see two reads, | |
901 | when the core only sees one since the FIFO receives both the read | |
902 | which is cancelled (and not delivered to the core) and the one which | |
903 | is re-issued (which is delivered to the core). | |
904 | ||
905 | To solve this, interrupts are turned off before reads occur to | |
906 | I/O space. This option controls which the overhead/latency of | |
907 | controlling interrupts during this time | |
908 | "n" turns interrupts off every read | |
909 | (higher overhead, but lower interrupt latency) | |
910 | "y" turns interrupts off every loop | |
911 | (low overhead, but longer interrupt latency) | |
912 | ||
913 | default behavior is to leave this set to on (type "Y"). If you are experiencing | |
914 | interrupt latency issues, it is safe and OK to turn this off. | |
915 | ||
1394f032 BW |
916 | endmenu |
917 | ||
1394f032 BW |
918 | choice |
919 | prompt "Kernel executes from" | |
920 | help | |
921 | Choose the memory type that the kernel will be running in. | |
922 | ||
923 | config RAMKERNEL | |
924 | bool "RAM" | |
925 | help | |
926 | The kernel will be resident in RAM when running. | |
927 | ||
928 | config ROMKERNEL | |
929 | bool "ROM" | |
930 | help | |
931 | The kernel will be resident in FLASH/ROM when running. | |
932 | ||
933 | endchoice | |
934 | ||
56b4f07a MF |
935 | # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both |
936 | config XIP_KERNEL | |
937 | bool | |
938 | default y | |
939 | depends on ROMKERNEL | |
940 | ||
1394f032 BW |
941 | source "mm/Kconfig" |
942 | ||
780431e3 MF |
943 | config BFIN_GPTIMERS |
944 | tristate "Enable Blackfin General Purpose Timers API" | |
945 | default n | |
946 | help | |
947 | Enable support for the General Purpose Timers API. If you | |
948 | are unsure, say N. | |
949 | ||
950 | To compile this driver as a module, choose M here: the module | |
4737f097 | 951 | will be called gptimers. |
780431e3 | 952 | |
006669ec MF |
953 | config HAVE_PWM |
954 | tristate "Enable PWM API support" | |
955 | depends on BFIN_GPTIMERS | |
956 | help | |
957 | Enable support for the Pulse Width Modulation framework (as | |
958 | found in linux/pwm.h). | |
959 | ||
960 | To compile this driver as a module, choose M here: the module | |
961 | will be called pwm. | |
962 | ||
1394f032 | 963 | choice |
d292b000 | 964 | prompt "Uncached DMA region" |
1394f032 | 965 | default DMA_UNCACHED_1M |
86ad7932 CC |
966 | config DMA_UNCACHED_4M |
967 | bool "Enable 4M DMA region" | |
1394f032 BW |
968 | config DMA_UNCACHED_2M |
969 | bool "Enable 2M DMA region" | |
970 | config DMA_UNCACHED_1M | |
971 | bool "Enable 1M DMA region" | |
c45c0659 BS |
972 | config DMA_UNCACHED_512K |
973 | bool "Enable 512K DMA region" | |
974 | config DMA_UNCACHED_256K | |
975 | bool "Enable 256K DMA region" | |
976 | config DMA_UNCACHED_128K | |
977 | bool "Enable 128K DMA region" | |
1394f032 BW |
978 | config DMA_UNCACHED_NONE |
979 | bool "Disable DMA region" | |
980 | endchoice | |
981 | ||
982 | ||
983 | comment "Cache Support" | |
41ba653f | 984 | |
3bebca2d | 985 | config BFIN_ICACHE |
1394f032 | 986 | bool "Enable ICACHE" |
41ba653f | 987 | default y |
41ba653f JZ |
988 | config BFIN_EXTMEM_ICACHEABLE |
989 | bool "Enable ICACHE for external memory" | |
990 | depends on BFIN_ICACHE | |
991 | default y | |
992 | config BFIN_L2_ICACHEABLE | |
993 | bool "Enable ICACHE for L2 SRAM" | |
994 | depends on BFIN_ICACHE | |
995 | depends on BF54x || BF561 | |
996 | default n | |
997 | ||
3bebca2d | 998 | config BFIN_DCACHE |
1394f032 | 999 | bool "Enable DCACHE" |
41ba653f | 1000 | default y |
3bebca2d | 1001 | config BFIN_DCACHE_BANKA |
1394f032 | 1002 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
3bebca2d | 1003 | depends on BFIN_DCACHE && !BF531 |
1394f032 | 1004 | default n |
41ba653f JZ |
1005 | config BFIN_EXTMEM_DCACHEABLE |
1006 | bool "Enable DCACHE for external memory" | |
3bebca2d | 1007 | depends on BFIN_DCACHE |
41ba653f JZ |
1008 | default y |
1009 | choice | |
1010 | prompt "External memory DCACHE policy" | |
1011 | depends on BFIN_EXTMEM_DCACHEABLE | |
1012 | default BFIN_EXTMEM_WRITEBACK if !SMP | |
1013 | default BFIN_EXTMEM_WRITETHROUGH if SMP | |
1014 | config BFIN_EXTMEM_WRITEBACK | |
1394f032 | 1015 | bool "Write back" |
46fa5eec | 1016 | depends on !SMP |
1394f032 BW |
1017 | help |
1018 | Write Back Policy: | |
1019 | Cached data will be written back to SDRAM only when needed. | |
1020 | This can give a nice increase in performance, but beware of | |
1021 | broken drivers that do not properly invalidate/flush their | |
1022 | cache. | |
1023 | ||
1024 | Write Through Policy: | |
1025 | Cached data will always be written back to SDRAM when the | |
1026 | cache is updated. This is a completely safe setting, but | |
1027 | performance is worse than Write Back. | |
1028 | ||
1029 | If you are unsure of the options and you want to be safe, | |
1030 | then go with Write Through. | |
1031 | ||
41ba653f | 1032 | config BFIN_EXTMEM_WRITETHROUGH |
1394f032 BW |
1033 | bool "Write through" |
1034 | help | |
1035 | Write Back Policy: | |
1036 | Cached data will be written back to SDRAM only when needed. | |
1037 | This can give a nice increase in performance, but beware of | |
1038 | broken drivers that do not properly invalidate/flush their | |
1039 | cache. | |
1040 | ||
1041 | Write Through Policy: | |
1042 | Cached data will always be written back to SDRAM when the | |
1043 | cache is updated. This is a completely safe setting, but | |
1044 | performance is worse than Write Back. | |
1045 | ||
1046 | If you are unsure of the options and you want to be safe, | |
1047 | then go with Write Through. | |
1048 | ||
1049 | endchoice | |
1050 | ||
41ba653f JZ |
1051 | config BFIN_L2_DCACHEABLE |
1052 | bool "Enable DCACHE for L2 SRAM" | |
1053 | depends on BFIN_DCACHE | |
9c954f89 | 1054 | depends on (BF54x || BF561) && !SMP |
41ba653f | 1055 | default n |
5ba76675 | 1056 | choice |
41ba653f JZ |
1057 | prompt "L2 SRAM DCACHE policy" |
1058 | depends on BFIN_L2_DCACHEABLE | |
1059 | default BFIN_L2_WRITEBACK | |
1060 | config BFIN_L2_WRITEBACK | |
5ba76675 | 1061 | bool "Write back" |
5ba76675 | 1062 | |
41ba653f | 1063 | config BFIN_L2_WRITETHROUGH |
5ba76675 | 1064 | bool "Write through" |
5ba76675 | 1065 | endchoice |
f099f39a | 1066 | |
41ba653f JZ |
1067 | |
1068 | comment "Memory Protection Unit" | |
b97b8a99 BS |
1069 | config MPU |
1070 | bool "Enable the memory protection unit (EXPERIMENTAL)" | |
1071 | default n | |
1072 | help | |
1073 | Use the processor's MPU to protect applications from accessing | |
1074 | memory they do not own. This comes at a performance penalty | |
1075 | and is recommended only for debugging. | |
1076 | ||
692105b8 | 1077 | comment "Asynchronous Memory Configuration" |
1394f032 | 1078 | |
ddf416b2 | 1079 | menu "EBIU_AMGCTL Global Control" |
1394f032 BW |
1080 | config C_AMCKEN |
1081 | bool "Enable CLKOUT" | |
1082 | default y | |
1083 | ||
1084 | config C_CDPRIO | |
1085 | bool "DMA has priority over core for ext. accesses" | |
1086 | default n | |
1087 | ||
1088 | config C_B0PEN | |
1089 | depends on BF561 | |
1090 | bool "Bank 0 16 bit packing enable" | |
1091 | default y | |
1092 | ||
1093 | config C_B1PEN | |
1094 | depends on BF561 | |
1095 | bool "Bank 1 16 bit packing enable" | |
1096 | default y | |
1097 | ||
1098 | config C_B2PEN | |
1099 | depends on BF561 | |
1100 | bool "Bank 2 16 bit packing enable" | |
1101 | default y | |
1102 | ||
1103 | config C_B3PEN | |
1104 | depends on BF561 | |
1105 | bool "Bank 3 16 bit packing enable" | |
1106 | default n | |
1107 | ||
1108 | choice | |
692105b8 | 1109 | prompt "Enable Asynchronous Memory Banks" |
1394f032 BW |
1110 | default C_AMBEN_ALL |
1111 | ||
1112 | config C_AMBEN | |
1113 | bool "Disable All Banks" | |
1114 | ||
1115 | config C_AMBEN_B0 | |
1116 | bool "Enable Bank 0" | |
1117 | ||
1118 | config C_AMBEN_B0_B1 | |
1119 | bool "Enable Bank 0 & 1" | |
1120 | ||
1121 | config C_AMBEN_B0_B1_B2 | |
1122 | bool "Enable Bank 0 & 1 & 2" | |
1123 | ||
1124 | config C_AMBEN_ALL | |
1125 | bool "Enable All Banks" | |
1126 | endchoice | |
1127 | endmenu | |
1128 | ||
1129 | menu "EBIU_AMBCTL Control" | |
1130 | config BANK_0 | |
c8342f87 | 1131 | hex "Bank 0 (AMBCTL0.L)" |
1394f032 | 1132 | default 0x7BB0 |
c8342f87 MF |
1133 | help |
1134 | These are the low 16 bits of the EBIU_AMBCTL0 MMR which are | |
1135 | used to control the Asynchronous Memory Bank 0 settings. | |
1394f032 BW |
1136 | |
1137 | config BANK_1 | |
c8342f87 | 1138 | hex "Bank 1 (AMBCTL0.H)" |
1394f032 | 1139 | default 0x7BB0 |
197fba56 | 1140 | default 0x5558 if BF54x |
c8342f87 MF |
1141 | help |
1142 | These are the high 16 bits of the EBIU_AMBCTL0 MMR which are | |
1143 | used to control the Asynchronous Memory Bank 1 settings. | |
1394f032 BW |
1144 | |
1145 | config BANK_2 | |
c8342f87 | 1146 | hex "Bank 2 (AMBCTL1.L)" |
1394f032 | 1147 | default 0x7BB0 |
c8342f87 MF |
1148 | help |
1149 | These are the low 16 bits of the EBIU_AMBCTL1 MMR which are | |
1150 | used to control the Asynchronous Memory Bank 2 settings. | |
1394f032 BW |
1151 | |
1152 | config BANK_3 | |
c8342f87 | 1153 | hex "Bank 3 (AMBCTL1.H)" |
1394f032 | 1154 | default 0x99B3 |
c8342f87 MF |
1155 | help |
1156 | These are the high 16 bits of the EBIU_AMBCTL1 MMR which are | |
1157 | used to control the Asynchronous Memory Bank 3 settings. | |
1158 | ||
1394f032 BW |
1159 | endmenu |
1160 | ||
e40540b3 SZ |
1161 | config EBIU_MBSCTLVAL |
1162 | hex "EBIU Bank Select Control Register" | |
1163 | depends on BF54x | |
1164 | default 0 | |
1165 | ||
1166 | config EBIU_MODEVAL | |
1167 | hex "Flash Memory Mode Control Register" | |
1168 | depends on BF54x | |
1169 | default 1 | |
1170 | ||
1171 | config EBIU_FCTLVAL | |
1172 | hex "Flash Memory Bank Control Register" | |
1173 | depends on BF54x | |
1174 | default 6 | |
1394f032 BW |
1175 | endmenu |
1176 | ||
1177 | ############################################################################# | |
1178 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" | |
1179 | ||
1180 | config PCI | |
1181 | bool "PCI support" | |
a95ca3b2 | 1182 | depends on BROKEN |
1394f032 BW |
1183 | help |
1184 | Support for PCI bus. | |
1185 | ||
1186 | source "drivers/pci/Kconfig" | |
1187 | ||
1394f032 BW |
1188 | source "drivers/pcmcia/Kconfig" |
1189 | ||
1190 | source "drivers/pci/hotplug/Kconfig" | |
1191 | ||
1192 | endmenu | |
1193 | ||
1194 | menu "Executable file formats" | |
1195 | ||
1196 | source "fs/Kconfig.binfmt" | |
1197 | ||
1198 | endmenu | |
1199 | ||
1200 | menu "Power management options" | |
ad46163a | 1201 | |
1394f032 BW |
1202 | source "kernel/power/Kconfig" |
1203 | ||
f4cb5700 JB |
1204 | config ARCH_SUSPEND_POSSIBLE |
1205 | def_bool y | |
f4cb5700 | 1206 | |
1394f032 | 1207 | choice |
1efc80b5 | 1208 | prompt "Standby Power Saving Mode" |
1394f032 | 1209 | depends on PM |
cfefe3c6 MH |
1210 | default PM_BFIN_SLEEP_DEEPER |
1211 | config PM_BFIN_SLEEP_DEEPER | |
1212 | bool "Sleep Deeper" | |
1213 | help | |
1214 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic | |
1215 | power dissipation by disabling the clock to the processor core (CCLK). | |
1216 | Furthermore, Standby sets the internal power supply voltage (VDDINT) | |
1217 | to 0.85 V to provide the greatest power savings, while preserving the | |
1218 | processor state. | |
1219 | The PLL and system clock (SCLK) continue to operate at a very low | |
1220 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, | |
1221 | the SDRAM is put into Self Refresh Mode. Typically an external event | |
1222 | such as GPIO interrupt or RTC activity wakes up the processor. | |
1223 | Various Peripherals such as UART, SPORT, PPI may not function as | |
1224 | normal during Sleep Deeper, due to the reduced SCLK frequency. | |
1225 | When in the sleep mode, system DMA access to L1 memory is not supported. | |
1226 | ||
1efc80b5 MH |
1227 | If unsure, select "Sleep Deeper". |
1228 | ||
cfefe3c6 MH |
1229 | config PM_BFIN_SLEEP |
1230 | bool "Sleep" | |
1231 | help | |
1232 | Sleep Mode (High Power Savings) - The sleep mode reduces power | |
1233 | dissipation by disabling the clock to the processor core (CCLK). | |
1234 | The PLL and system clock (SCLK), however, continue to operate in | |
1235 | this mode. Typically an external event or RTC activity will wake | |
1efc80b5 MH |
1236 | up the processor. When in the sleep mode, system DMA access to L1 |
1237 | memory is not supported. | |
1238 | ||
1239 | If unsure, select "Sleep Deeper". | |
cfefe3c6 | 1240 | endchoice |
1394f032 | 1241 | |
1efc80b5 MH |
1242 | comment "Possible Suspend Mem / Hibernate Wake-Up Sources" |
1243 | depends on PM | |
1244 | ||
1efc80b5 MH |
1245 | config PM_BFIN_WAKE_PH6 |
1246 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" | |
2f6f4bcd | 1247 | depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) |
1efc80b5 MH |
1248 | default n |
1249 | help | |
1250 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) | |
1251 | ||
1efc80b5 MH |
1252 | config PM_BFIN_WAKE_GP |
1253 | bool "Allow Wake-Up from GPIOs" | |
1254 | depends on PM && BF54x | |
1255 | default n | |
1256 | help | |
1257 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) | |
19986289 MH |
1258 | (all processors, except ADSP-BF549). This option sets |
1259 | the general-purpose wake-up enable (GPWE) control bit to enable | |
1260 | wake-up upon detection of an active low signal on the /GPW (PH7) pin. | |
1261 | On ADSP-BF549 this option enables the the same functionality on the | |
1262 | /MRXON pin also PH7. | |
1263 | ||
1394f032 BW |
1264 | endmenu |
1265 | ||
1394f032 BW |
1266 | menu "CPU Frequency scaling" |
1267 | ||
1268 | source "drivers/cpufreq/Kconfig" | |
1269 | ||
5ad2ca5f MH |
1270 | config BFIN_CPU_FREQ |
1271 | bool | |
1272 | depends on CPU_FREQ | |
1273 | select CPU_FREQ_TABLE | |
1274 | default y | |
1275 | ||
14b03204 MH |
1276 | config CPU_VOLTAGE |
1277 | bool "CPU Voltage scaling" | |
73feb5c0 | 1278 | depends on EXPERIMENTAL |
14b03204 MH |
1279 | depends on CPU_FREQ |
1280 | default n | |
1281 | help | |
1282 | Say Y here if you want CPU voltage scaling according to the CPU frequency. | |
1283 | This option violates the PLL BYPASS recommendation in the Blackfin Processor | |
73feb5c0 | 1284 | manuals. There is a theoretical risk that during VDDINT transitions |
14b03204 MH |
1285 | the PLL may unlock. |
1286 | ||
1394f032 BW |
1287 | endmenu |
1288 | ||
1394f032 BW |
1289 | source "net/Kconfig" |
1290 | ||
1291 | source "drivers/Kconfig" | |
1292 | ||
872d024b MF |
1293 | source "drivers/firmware/Kconfig" |
1294 | ||
1394f032 BW |
1295 | source "fs/Kconfig" |
1296 | ||
74ce8322 | 1297 | source "arch/blackfin/Kconfig.debug" |
1394f032 BW |
1298 | |
1299 | source "security/Kconfig" | |
1300 | ||
1301 | source "crypto/Kconfig" | |
1302 | ||
1303 | source "lib/Kconfig" |