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Commit | Line | Data |
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1394f032 BW |
1 | # |
2 | # For a description of the syntax of this configuration file, | |
3 | # see Documentation/kbuild/kconfig-language.txt. | |
4 | # | |
5 | ||
53f8a252 | 6 | mainmenu "Blackfin Kernel Configuration" |
1394f032 BW |
7 | |
8 | config MMU | |
bac7d89e | 9 | def_bool n |
1394f032 BW |
10 | |
11 | config FPU | |
bac7d89e | 12 | def_bool n |
1394f032 BW |
13 | |
14 | config RWSEM_GENERIC_SPINLOCK | |
bac7d89e | 15 | def_bool y |
1394f032 BW |
16 | |
17 | config RWSEM_XCHGADD_ALGORITHM | |
bac7d89e | 18 | def_bool n |
1394f032 BW |
19 | |
20 | config BLACKFIN | |
bac7d89e | 21 | def_bool y |
1c873be7 | 22 | select HAVE_FUNCTION_TRACER |
ec7748b5 | 23 | select HAVE_IDE |
538067c8 MF |
24 | select HAVE_KERNEL_GZIP |
25 | select HAVE_KERNEL_BZIP2 | |
26 | select HAVE_KERNEL_LZMA | |
42d4b839 | 27 | select HAVE_OPROFILE |
a4f0b32c | 28 | select ARCH_WANT_OPTIONAL_GPIOLIB |
1394f032 | 29 | |
70f12567 MF |
30 | config GENERIC_BUG |
31 | def_bool y | |
32 | depends on BUG | |
33 | ||
e3defffe | 34 | config ZONE_DMA |
bac7d89e | 35 | def_bool y |
e3defffe | 36 | |
1394f032 | 37 | config GENERIC_FIND_NEXT_BIT |
bac7d89e | 38 | def_bool y |
1394f032 BW |
39 | |
40 | config GENERIC_HWEIGHT | |
bac7d89e | 41 | def_bool y |
1394f032 BW |
42 | |
43 | config GENERIC_HARDIRQS | |
bac7d89e | 44 | def_bool y |
1394f032 BW |
45 | |
46 | config GENERIC_IRQ_PROBE | |
bac7d89e | 47 | def_bool y |
1394f032 | 48 | |
b2d1583f | 49 | config GENERIC_GPIO |
bac7d89e | 50 | def_bool y |
1394f032 BW |
51 | |
52 | config FORCE_MAX_ZONEORDER | |
53 | int | |
54 | default "14" | |
55 | ||
56 | config GENERIC_CALIBRATE_DELAY | |
bac7d89e | 57 | def_bool y |
1394f032 | 58 | |
6fa68e7a MF |
59 | config LOCKDEP_SUPPORT |
60 | def_bool y | |
61 | ||
c7b412f4 MF |
62 | config STACKTRACE_SUPPORT |
63 | def_bool y | |
64 | ||
8f86001f MF |
65 | config TRACE_IRQFLAGS_SUPPORT |
66 | def_bool y | |
67 | ||
1394f032 | 68 | source "init/Kconfig" |
dc52ddc0 | 69 | |
1394f032 BW |
70 | source "kernel/Kconfig.preempt" |
71 | ||
dc52ddc0 MH |
72 | source "kernel/Kconfig.freezer" |
73 | ||
1394f032 BW |
74 | menu "Blackfin Processor Options" |
75 | ||
76 | comment "Processor and Board Settings" | |
77 | ||
78 | choice | |
79 | prompt "CPU" | |
80 | default BF533 | |
81 | ||
2f6f4bcd BW |
82 | config BF512 |
83 | bool "BF512" | |
84 | help | |
85 | BF512 Processor Support. | |
86 | ||
87 | config BF514 | |
88 | bool "BF514" | |
89 | help | |
90 | BF514 Processor Support. | |
91 | ||
92 | config BF516 | |
93 | bool "BF516" | |
94 | help | |
95 | BF516 Processor Support. | |
96 | ||
97 | config BF518 | |
98 | bool "BF518" | |
99 | help | |
100 | BF518 Processor Support. | |
101 | ||
59003145 MH |
102 | config BF522 |
103 | bool "BF522" | |
104 | help | |
105 | BF522 Processor Support. | |
106 | ||
1545a111 MF |
107 | config BF523 |
108 | bool "BF523" | |
109 | help | |
110 | BF523 Processor Support. | |
111 | ||
112 | config BF524 | |
113 | bool "BF524" | |
114 | help | |
115 | BF524 Processor Support. | |
116 | ||
59003145 MH |
117 | config BF525 |
118 | bool "BF525" | |
119 | help | |
120 | BF525 Processor Support. | |
121 | ||
1545a111 MF |
122 | config BF526 |
123 | bool "BF526" | |
124 | help | |
125 | BF526 Processor Support. | |
126 | ||
59003145 MH |
127 | config BF527 |
128 | bool "BF527" | |
129 | help | |
130 | BF527 Processor Support. | |
131 | ||
1394f032 BW |
132 | config BF531 |
133 | bool "BF531" | |
134 | help | |
135 | BF531 Processor Support. | |
136 | ||
137 | config BF532 | |
138 | bool "BF532" | |
139 | help | |
140 | BF532 Processor Support. | |
141 | ||
142 | config BF533 | |
143 | bool "BF533" | |
144 | help | |
145 | BF533 Processor Support. | |
146 | ||
147 | config BF534 | |
148 | bool "BF534" | |
149 | help | |
150 | BF534 Processor Support. | |
151 | ||
152 | config BF536 | |
153 | bool "BF536" | |
154 | help | |
155 | BF536 Processor Support. | |
156 | ||
157 | config BF537 | |
158 | bool "BF537" | |
159 | help | |
160 | BF537 Processor Support. | |
161 | ||
dc26aec2 MH |
162 | config BF538 |
163 | bool "BF538" | |
164 | help | |
165 | BF538 Processor Support. | |
166 | ||
167 | config BF539 | |
168 | bool "BF539" | |
169 | help | |
170 | BF539 Processor Support. | |
171 | ||
24a07a12 RH |
172 | config BF542 |
173 | bool "BF542" | |
174 | help | |
175 | BF542 Processor Support. | |
176 | ||
2f89c063 MF |
177 | config BF542M |
178 | bool "BF542m" | |
179 | help | |
180 | BF542 Processor Support. | |
181 | ||
24a07a12 RH |
182 | config BF544 |
183 | bool "BF544" | |
184 | help | |
185 | BF544 Processor Support. | |
186 | ||
2f89c063 MF |
187 | config BF544M |
188 | bool "BF544m" | |
189 | help | |
190 | BF544 Processor Support. | |
191 | ||
7c7fd170 MF |
192 | config BF547 |
193 | bool "BF547" | |
194 | help | |
195 | BF547 Processor Support. | |
196 | ||
2f89c063 MF |
197 | config BF547M |
198 | bool "BF547m" | |
199 | help | |
200 | BF547 Processor Support. | |
201 | ||
24a07a12 RH |
202 | config BF548 |
203 | bool "BF548" | |
204 | help | |
205 | BF548 Processor Support. | |
206 | ||
2f89c063 MF |
207 | config BF548M |
208 | bool "BF548m" | |
209 | help | |
210 | BF548 Processor Support. | |
211 | ||
24a07a12 RH |
212 | config BF549 |
213 | bool "BF549" | |
214 | help | |
215 | BF549 Processor Support. | |
216 | ||
2f89c063 MF |
217 | config BF549M |
218 | bool "BF549m" | |
219 | help | |
220 | BF549 Processor Support. | |
221 | ||
1394f032 BW |
222 | config BF561 |
223 | bool "BF561" | |
224 | help | |
cd88b4dc | 225 | BF561 Processor Support. |
1394f032 BW |
226 | |
227 | endchoice | |
228 | ||
46fa5eec GY |
229 | config SMP |
230 | depends on BF561 | |
9b9bfded | 231 | select GENERIC_TIME |
46fa5eec GY |
232 | bool "Symmetric multi-processing support" |
233 | ---help--- | |
234 | This enables support for systems with more than one CPU, | |
235 | like the dual core BF561. If you have a system with only one | |
236 | CPU, say N. If you have a system with more than one CPU, say Y. | |
237 | ||
238 | If you don't know what to do here, say N. | |
239 | ||
240 | config NR_CPUS | |
241 | int | |
242 | depends on SMP | |
243 | default 2 if BF561 | |
244 | ||
245 | config IRQ_PER_CPU | |
246 | bool | |
247 | depends on SMP | |
248 | default y | |
249 | ||
0c0497c2 MF |
250 | config BF_REV_MIN |
251 | int | |
2f89c063 | 252 | default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) |
0c0497c2 | 253 | default 2 if (BF537 || BF536 || BF534) |
2f89c063 | 254 | default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) |
2f6f4bcd | 255 | default 4 if (BF538 || BF539) |
0c0497c2 MF |
256 | |
257 | config BF_REV_MAX | |
258 | int | |
2f89c063 MF |
259 | default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) |
260 | default 3 if (BF537 || BF536 || BF534 || BF54xM) | |
2f6f4bcd | 261 | default 5 if (BF561 || BF538 || BF539) |
0c0497c2 MF |
262 | default 6 if (BF533 || BF532 || BF531) |
263 | ||
1394f032 BW |
264 | choice |
265 | prompt "Silicon Rev" | |
f8b55651 MF |
266 | default BF_REV_0_0 if (BF51x || BF52x) |
267 | default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) | |
2f89c063 | 268 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) |
24a07a12 RH |
269 | |
270 | config BF_REV_0_0 | |
271 | bool "0.0" | |
2f89c063 | 272 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
59003145 MH |
273 | |
274 | config BF_REV_0_1 | |
d07f4380 | 275 | bool "0.1" |
2f89c063 | 276 | depends on (BF52x || (BF54x && !BF54xM)) |
1394f032 BW |
277 | |
278 | config BF_REV_0_2 | |
279 | bool "0.2" | |
2f89c063 | 280 | depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) |
1394f032 BW |
281 | |
282 | config BF_REV_0_3 | |
283 | bool "0.3" | |
2f89c063 | 284 | depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) |
1394f032 BW |
285 | |
286 | config BF_REV_0_4 | |
287 | bool "0.4" | |
dc26aec2 | 288 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 BW |
289 | |
290 | config BF_REV_0_5 | |
291 | bool "0.5" | |
dc26aec2 | 292 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 | 293 | |
49f7253c MF |
294 | config BF_REV_0_6 |
295 | bool "0.6" | |
296 | depends on (BF533 || BF532 || BF531) | |
297 | ||
de3025f4 JZ |
298 | config BF_REV_ANY |
299 | bool "any" | |
300 | ||
301 | config BF_REV_NONE | |
302 | bool "none" | |
303 | ||
1394f032 BW |
304 | endchoice |
305 | ||
2f6f4bcd BW |
306 | config BF51x |
307 | bool | |
308 | depends on (BF512 || BF514 || BF516 || BF518) | |
309 | default y | |
310 | ||
59003145 MH |
311 | config BF52x |
312 | bool | |
1545a111 | 313 | depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527) |
59003145 MH |
314 | default y |
315 | ||
24a07a12 RH |
316 | config BF53x |
317 | bool | |
318 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) | |
319 | default y | |
320 | ||
2f89c063 MF |
321 | config BF54xM |
322 | bool | |
323 | depends on (BF542M || BF544M || BF547M || BF548M || BF549M) | |
324 | default y | |
325 | ||
24a07a12 RH |
326 | config BF54x |
327 | bool | |
2f89c063 | 328 | depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM) |
24a07a12 RH |
329 | default y |
330 | ||
1394f032 BW |
331 | config MEM_GENERIC_BOARD |
332 | bool | |
333 | depends on GENERIC_BOARD | |
334 | default y | |
335 | ||
336 | config MEM_MT48LC64M4A2FB_7E | |
337 | bool | |
338 | depends on (BFIN533_STAMP) | |
339 | default y | |
340 | ||
341 | config MEM_MT48LC16M16A2TG_75 | |
342 | bool | |
343 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | |
ab472a04 | 344 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \ |
9db144fe | 345 | || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM) |
1394f032 BW |
346 | default y |
347 | ||
348 | config MEM_MT48LC32M8A2_75 | |
349 | bool | |
dc26aec2 | 350 | depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) |
1394f032 BW |
351 | default y |
352 | ||
353 | config MEM_MT48LC8M32B2B5_7 | |
354 | bool | |
355 | depends on (BFIN561_BLUETECHNIX_CM) | |
356 | default y | |
357 | ||
59003145 MH |
358 | config MEM_MT48LC32M16A2TG_75 |
359 | bool | |
8cc7117e | 360 | depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD) |
59003145 MH |
361 | default y |
362 | ||
4934540d SZ |
363 | config MEM_MT48LC32M8A2_75 |
364 | bool | |
365 | depends on (BFIN518F_EZBRD) | |
366 | default y | |
367 | ||
2f6f4bcd | 368 | source "arch/blackfin/mach-bf518/Kconfig" |
59003145 | 369 | source "arch/blackfin/mach-bf527/Kconfig" |
1394f032 BW |
370 | source "arch/blackfin/mach-bf533/Kconfig" |
371 | source "arch/blackfin/mach-bf561/Kconfig" | |
372 | source "arch/blackfin/mach-bf537/Kconfig" | |
dc26aec2 | 373 | source "arch/blackfin/mach-bf538/Kconfig" |
24a07a12 | 374 | source "arch/blackfin/mach-bf548/Kconfig" |
1394f032 BW |
375 | |
376 | menu "Board customizations" | |
377 | ||
378 | config CMDLINE_BOOL | |
379 | bool "Default bootloader kernel arguments" | |
380 | ||
381 | config CMDLINE | |
382 | string "Initial kernel command string" | |
383 | depends on CMDLINE_BOOL | |
384 | default "console=ttyBF0,57600" | |
385 | help | |
386 | If you don't have a boot loader capable of passing a command line string | |
387 | to the kernel, you may specify one here. As a minimum, you should specify | |
388 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). | |
389 | ||
5f004c20 MF |
390 | config BOOT_LOAD |
391 | hex "Kernel load address for booting" | |
392 | default "0x1000" | |
393 | range 0x1000 0x20000000 | |
394 | help | |
395 | This option allows you to set the load address of the kernel. | |
396 | This can be useful if you are on a board which has a small amount | |
397 | of memory or you wish to reserve some memory at the beginning of | |
398 | the address space. | |
399 | ||
400 | Note that you need to keep this value above 4k (0x1000) as this | |
401 | memory region is used to capture NULL pointer references as well | |
402 | as some core kernel functions. | |
403 | ||
8cc7117e MH |
404 | config ROM_BASE |
405 | hex "Kernel ROM Base" | |
86249911 | 406 | depends on ROMKERNEL |
8cc7117e MH |
407 | default "0x20040000" |
408 | range 0x20000000 0x20400000 if !(BF54x || BF561) | |
409 | range 0x20000000 0x30000000 if (BF54x || BF561) | |
410 | help | |
411 | ||
f16295e7 | 412 | comment "Clock/PLL Setup" |
1394f032 BW |
413 | |
414 | config CLKIN_HZ | |
2fb6cb41 | 415 | int "Frequency of the crystal on the board in Hz" |
1394f032 BW |
416 | default "11059200" if BFIN533_STAMP |
417 | default "27000000" if BFIN533_EZKIT | |
2f6f4bcd | 418 | default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD) |
1394f032 BW |
419 | default "30000000" if BFIN561_EZKIT |
420 | default "24576000" if PNAV10 | |
5d1617b2 | 421 | default "10000000" if BFIN532_IP0X |
1394f032 BW |
422 | help |
423 | The frequency of CLKIN crystal oscillator on the board in Hz. | |
2fb6cb41 SZ |
424 | Warning: This value should match the crystal on the board. Otherwise, |
425 | peripherals won't work properly. | |
1394f032 | 426 | |
f16295e7 RG |
427 | config BFIN_KERNEL_CLOCK |
428 | bool "Re-program Clocks while Kernel boots?" | |
429 | default n | |
430 | help | |
431 | This option decides if kernel clocks are re-programed from the | |
432 | bootloader settings. If the clocks are not set, the SDRAM settings | |
433 | are also not changed, and the Bootloader does 100% of the hardware | |
434 | configuration. | |
435 | ||
436 | config PLL_BYPASS | |
e4e9a7ad MF |
437 | bool "Bypass PLL" |
438 | depends on BFIN_KERNEL_CLOCK | |
439 | default n | |
f16295e7 RG |
440 | |
441 | config CLKIN_HALF | |
442 | bool "Half Clock In" | |
443 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
444 | default n | |
445 | help | |
446 | If this is set the clock will be divided by 2, before it goes to the PLL. | |
447 | ||
448 | config VCO_MULT | |
449 | int "VCO Multiplier" | |
450 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
451 | range 1 64 | |
452 | default "22" if BFIN533_EZKIT | |
453 | default "45" if BFIN533_STAMP | |
dc26aec2 | 454 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) |
f16295e7 | 455 | default "22" if BFIN533_BLUETECHNIX_CM |
9db144fe | 456 | default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
f16295e7 | 457 | default "20" if BFIN561_EZKIT |
2f6f4bcd | 458 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) |
f16295e7 RG |
459 | help |
460 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | |
461 | PLL Frequency = (Crystal Frequency) * (this setting) | |
462 | ||
463 | choice | |
464 | prompt "Core Clock Divider" | |
465 | depends on BFIN_KERNEL_CLOCK | |
466 | default CCLK_DIV_1 | |
467 | help | |
468 | This sets the frequency of the core. It can be 1, 2, 4 or 8 | |
469 | Core Frequency = (PLL frequency) / (this setting) | |
470 | ||
471 | config CCLK_DIV_1 | |
472 | bool "1" | |
473 | ||
474 | config CCLK_DIV_2 | |
475 | bool "2" | |
476 | ||
477 | config CCLK_DIV_4 | |
478 | bool "4" | |
479 | ||
480 | config CCLK_DIV_8 | |
481 | bool "8" | |
482 | endchoice | |
483 | ||
484 | config SCLK_DIV | |
485 | int "System Clock Divider" | |
486 | depends on BFIN_KERNEL_CLOCK | |
487 | range 1 15 | |
5f004c20 | 488 | default 5 |
f16295e7 RG |
489 | help |
490 | This sets the frequency of the system clock (including SDRAM or DDR). | |
491 | This can be between 1 and 15 | |
492 | System Clock = (PLL frequency) / (this setting) | |
493 | ||
5f004c20 MF |
494 | choice |
495 | prompt "DDR SDRAM Chip Type" | |
496 | depends on BFIN_KERNEL_CLOCK | |
497 | depends on BF54x | |
498 | default MEM_MT46V32M16_5B | |
499 | ||
500 | config MEM_MT46V32M16_6T | |
501 | bool "MT46V32M16_6T" | |
502 | ||
503 | config MEM_MT46V32M16_5B | |
504 | bool "MT46V32M16_5B" | |
505 | endchoice | |
506 | ||
73feb5c0 MH |
507 | choice |
508 | prompt "DDR/SDRAM Timing" | |
509 | depends on BFIN_KERNEL_CLOCK | |
510 | default BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
511 | help | |
512 | This option allows you to specify Blackfin SDRAM/DDR Timing parameters | |
513 | The calculated SDRAM timing parameters may not be 100% | |
514 | accurate - This option is therefore marked experimental. | |
515 | ||
516 | config BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
517 | bool "Calculate Timings (EXPERIMENTAL)" | |
518 | depends on EXPERIMENTAL | |
519 | ||
520 | config BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
521 | bool "Provide accurate Timings based on target SCLK" | |
522 | help | |
523 | Please consult the Blackfin Hardware Reference Manuals as well | |
524 | as the memory device datasheet. | |
525 | http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram | |
526 | endchoice | |
527 | ||
528 | menu "Memory Init Control" | |
529 | depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
530 | ||
531 | config MEM_DDRCTL0 | |
532 | depends on BF54x | |
533 | hex "DDRCTL0" | |
534 | default 0x0 | |
535 | ||
536 | config MEM_DDRCTL1 | |
537 | depends on BF54x | |
538 | hex "DDRCTL1" | |
539 | default 0x0 | |
540 | ||
541 | config MEM_DDRCTL2 | |
542 | depends on BF54x | |
543 | hex "DDRCTL2" | |
544 | default 0x0 | |
545 | ||
546 | config MEM_EBIU_DDRQUE | |
547 | depends on BF54x | |
548 | hex "DDRQUE" | |
549 | default 0x0 | |
550 | ||
551 | config MEM_SDRRC | |
552 | depends on !BF54x | |
553 | hex "SDRRC" | |
554 | default 0x0 | |
555 | ||
556 | config MEM_SDGCTL | |
557 | depends on !BF54x | |
558 | hex "SDGCTL" | |
559 | default 0x0 | |
560 | endmenu | |
561 | ||
f16295e7 RG |
562 | # |
563 | # Max & Min Speeds for various Chips | |
564 | # | |
565 | config MAX_VCO_HZ | |
566 | int | |
2f6f4bcd BW |
567 | default 400000000 if BF512 |
568 | default 400000000 if BF514 | |
569 | default 400000000 if BF516 | |
570 | default 400000000 if BF518 | |
f16295e7 | 571 | default 600000000 if BF522 |
1545a111 MF |
572 | default 400000000 if BF523 |
573 | default 400000000 if BF524 | |
f16295e7 | 574 | default 600000000 if BF525 |
1545a111 | 575 | default 400000000 if BF526 |
f16295e7 RG |
576 | default 600000000 if BF527 |
577 | default 400000000 if BF531 | |
578 | default 400000000 if BF532 | |
579 | default 750000000 if BF533 | |
580 | default 500000000 if BF534 | |
581 | default 400000000 if BF536 | |
582 | default 600000000 if BF537 | |
f72eecb9 RG |
583 | default 533333333 if BF538 |
584 | default 533333333 if BF539 | |
f16295e7 | 585 | default 600000000 if BF542 |
f72eecb9 | 586 | default 533333333 if BF544 |
1545a111 MF |
587 | default 600000000 if BF547 |
588 | default 600000000 if BF548 | |
f72eecb9 | 589 | default 533333333 if BF549 |
f16295e7 RG |
590 | default 600000000 if BF561 |
591 | ||
592 | config MIN_VCO_HZ | |
593 | int | |
594 | default 50000000 | |
595 | ||
596 | config MAX_SCLK_HZ | |
597 | int | |
f72eecb9 | 598 | default 133333333 |
f16295e7 RG |
599 | |
600 | config MIN_SCLK_HZ | |
601 | int | |
602 | default 27000000 | |
603 | ||
604 | comment "Kernel Timer/Scheduler" | |
605 | ||
606 | source kernel/Kconfig.hz | |
607 | ||
8b5f79f9 VM |
608 | config GENERIC_TIME |
609 | bool "Generic time" | |
610 | default y | |
611 | ||
612 | config GENERIC_CLOCKEVENTS | |
613 | bool "Generic clock events" | |
614 | depends on GENERIC_TIME | |
615 | default y | |
616 | ||
1fa9be72 GY |
617 | choice |
618 | prompt "Kernel Tick Source" | |
619 | depends on GENERIC_CLOCKEVENTS | |
620 | default TICKSOURCE_CORETMR | |
621 | ||
622 | config TICKSOURCE_GPTMR0 | |
623 | bool "Gptimer0 (SCLK domain)" | |
624 | select BFIN_GPTIMERS | |
625 | depends on !IPIPE | |
626 | ||
627 | config TICKSOURCE_CORETMR | |
628 | bool "Core timer (CCLK domain)" | |
629 | ||
630 | endchoice | |
631 | ||
8b5f79f9 | 632 | config CYCLES_CLOCKSOURCE |
1fa9be72 | 633 | bool "Use 'CYCLES' as a clocksource" |
8b5f79f9 VM |
634 | depends on GENERIC_CLOCKEVENTS |
635 | depends on !BFIN_SCRATCH_REG_CYCLES | |
1fa9be72 | 636 | depends on !SMP |
8b5f79f9 VM |
637 | help |
638 | If you say Y here, you will enable support for using the 'cycles' | |
639 | registers as a clock source. Doing so means you will be unable to | |
640 | safely write to the 'cycles' register during runtime. You will | |
641 | still be able to read it (such as for performance monitoring), but | |
642 | writing the registers will most likely crash the kernel. | |
643 | ||
1fa9be72 GY |
644 | config GPTMR0_CLOCKSOURCE |
645 | bool "Use GPTimer0 as a clocksource (higher rating)" | |
646 | depends on GENERIC_CLOCKEVENTS | |
647 | depends on !TICKSOURCE_GPTMR0 | |
648 | ||
8b5f79f9 VM |
649 | source kernel/time/Kconfig |
650 | ||
5f004c20 | 651 | comment "Misc" |
971d5bc4 | 652 | |
f0b5d12f MF |
653 | choice |
654 | prompt "Blackfin Exception Scratch Register" | |
655 | default BFIN_SCRATCH_REG_RETN | |
656 | help | |
657 | Select the resource to reserve for the Exception handler: | |
658 | - RETN: Non-Maskable Interrupt (NMI) | |
659 | - RETE: Exception Return (JTAG/ICE) | |
660 | - CYCLES: Performance counter | |
661 | ||
662 | If you are unsure, please select "RETN". | |
663 | ||
664 | config BFIN_SCRATCH_REG_RETN | |
665 | bool "RETN" | |
666 | help | |
667 | Use the RETN register in the Blackfin exception handler | |
668 | as a stack scratch register. This means you cannot | |
669 | safely use NMI on the Blackfin while running Linux, but | |
670 | you can debug the system with a JTAG ICE and use the | |
671 | CYCLES performance registers. | |
672 | ||
673 | If you are unsure, please select "RETN". | |
674 | ||
675 | config BFIN_SCRATCH_REG_RETE | |
676 | bool "RETE" | |
677 | help | |
678 | Use the RETE register in the Blackfin exception handler | |
679 | as a stack scratch register. This means you cannot | |
680 | safely use a JTAG ICE while debugging a Blackfin board, | |
681 | but you can safely use the CYCLES performance registers | |
682 | and the NMI. | |
683 | ||
684 | If you are unsure, please select "RETN". | |
685 | ||
686 | config BFIN_SCRATCH_REG_CYCLES | |
687 | bool "CYCLES" | |
688 | help | |
689 | Use the CYCLES register in the Blackfin exception handler | |
690 | as a stack scratch register. This means you cannot | |
691 | safely use the CYCLES performance registers on a Blackfin | |
692 | board at anytime, but you can debug the system with a JTAG | |
693 | ICE and use the NMI. | |
694 | ||
695 | If you are unsure, please select "RETN". | |
696 | ||
697 | endchoice | |
698 | ||
1394f032 BW |
699 | endmenu |
700 | ||
701 | ||
702 | menu "Blackfin Kernel Optimizations" | |
46fa5eec | 703 | depends on !SMP |
1394f032 | 704 | |
1394f032 BW |
705 | comment "Memory Optimizations" |
706 | ||
707 | config I_ENTRY_L1 | |
708 | bool "Locate interrupt entry code in L1 Memory" | |
709 | default y | |
710 | help | |
01dd2fbf ML |
711 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
712 | into L1 instruction memory. (less latency) | |
1394f032 BW |
713 | |
714 | config EXCPT_IRQ_SYSC_L1 | |
01dd2fbf | 715 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
1394f032 BW |
716 | default y |
717 | help | |
01dd2fbf | 718 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
cfefe3c6 | 719 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
01dd2fbf | 720 | (less latency) |
1394f032 BW |
721 | |
722 | config DO_IRQ_L1 | |
723 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | |
724 | default y | |
725 | help | |
01dd2fbf ML |
726 | If enabled, the frequently called do_irq dispatcher function is linked |
727 | into L1 instruction memory. (less latency) | |
1394f032 BW |
728 | |
729 | config CORE_TIMER_IRQ_L1 | |
730 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | |
731 | default y | |
732 | help | |
01dd2fbf ML |
733 | If enabled, the frequently called timer_interrupt() function is linked |
734 | into L1 instruction memory. (less latency) | |
1394f032 BW |
735 | |
736 | config IDLE_L1 | |
737 | bool "Locate frequently idle function in L1 Memory" | |
738 | default y | |
739 | help | |
01dd2fbf ML |
740 | If enabled, the frequently called idle function is linked |
741 | into L1 instruction memory. (less latency) | |
1394f032 BW |
742 | |
743 | config SCHEDULE_L1 | |
744 | bool "Locate kernel schedule function in L1 Memory" | |
745 | default y | |
746 | help | |
01dd2fbf ML |
747 | If enabled, the frequently called kernel schedule is linked |
748 | into L1 instruction memory. (less latency) | |
1394f032 BW |
749 | |
750 | config ARITHMETIC_OPS_L1 | |
751 | bool "Locate kernel owned arithmetic functions in L1 Memory" | |
752 | default y | |
753 | help | |
01dd2fbf ML |
754 | If enabled, arithmetic functions are linked |
755 | into L1 instruction memory. (less latency) | |
1394f032 BW |
756 | |
757 | config ACCESS_OK_L1 | |
758 | bool "Locate access_ok function in L1 Memory" | |
759 | default y | |
760 | help | |
01dd2fbf ML |
761 | If enabled, the access_ok function is linked |
762 | into L1 instruction memory. (less latency) | |
1394f032 BW |
763 | |
764 | config MEMSET_L1 | |
765 | bool "Locate memset function in L1 Memory" | |
766 | default y | |
767 | help | |
01dd2fbf ML |
768 | If enabled, the memset function is linked |
769 | into L1 instruction memory. (less latency) | |
1394f032 BW |
770 | |
771 | config MEMCPY_L1 | |
772 | bool "Locate memcpy function in L1 Memory" | |
773 | default y | |
774 | help | |
01dd2fbf ML |
775 | If enabled, the memcpy function is linked |
776 | into L1 instruction memory. (less latency) | |
1394f032 BW |
777 | |
778 | config SYS_BFIN_SPINLOCK_L1 | |
779 | bool "Locate sys_bfin_spinlock function in L1 Memory" | |
780 | default y | |
781 | help | |
01dd2fbf ML |
782 | If enabled, sys_bfin_spinlock function is linked |
783 | into L1 instruction memory. (less latency) | |
1394f032 BW |
784 | |
785 | config IP_CHECKSUM_L1 | |
786 | bool "Locate IP Checksum function in L1 Memory" | |
787 | default n | |
788 | help | |
01dd2fbf ML |
789 | If enabled, the IP Checksum function is linked |
790 | into L1 instruction memory. (less latency) | |
1394f032 BW |
791 | |
792 | config CACHELINE_ALIGNED_L1 | |
793 | bool "Locate cacheline_aligned data to L1 Data Memory" | |
157cc5aa MH |
794 | default y if !BF54x |
795 | default n if BF54x | |
1394f032 BW |
796 | depends on !BF531 |
797 | help | |
692105b8 | 798 | If enabled, cacheline_aligned data is linked |
01dd2fbf | 799 | into L1 data memory. (less latency) |
1394f032 BW |
800 | |
801 | config SYSCALL_TAB_L1 | |
802 | bool "Locate Syscall Table L1 Data Memory" | |
803 | default n | |
804 | depends on !BF531 | |
805 | help | |
01dd2fbf ML |
806 | If enabled, the Syscall LUT is linked |
807 | into L1 data memory. (less latency) | |
1394f032 BW |
808 | |
809 | config CPLB_SWITCH_TAB_L1 | |
810 | bool "Locate CPLB Switch Tables L1 Data Memory" | |
811 | default n | |
812 | depends on !BF531 | |
813 | help | |
01dd2fbf ML |
814 | If enabled, the CPLB Switch Tables are linked |
815 | into L1 data memory. (less latency) | |
1394f032 | 816 | |
ca87b7ad GY |
817 | config APP_STACK_L1 |
818 | bool "Support locating application stack in L1 Scratch Memory" | |
819 | default y | |
820 | help | |
821 | If enabled the application stack can be located in L1 | |
822 | scratch memory (less latency). | |
823 | ||
824 | Currently only works with FLAT binaries. | |
825 | ||
6ad2b84c MF |
826 | config EXCEPTION_L1_SCRATCH |
827 | bool "Locate exception stack in L1 Scratch Memory" | |
828 | default n | |
f82e0a0c | 829 | depends on !APP_STACK_L1 |
6ad2b84c MF |
830 | help |
831 | Whenever an exception occurs, use the L1 Scratch memory for | |
832 | stack storage. You cannot place the stacks of FLAT binaries | |
833 | in L1 when using this option. | |
834 | ||
835 | If you don't use L1 Scratch, then you should say Y here. | |
836 | ||
251383c7 RG |
837 | comment "Speed Optimizations" |
838 | config BFIN_INS_LOWOVERHEAD | |
839 | bool "ins[bwl] low overhead, higher interrupt latency" | |
840 | default y | |
841 | help | |
842 | Reads on the Blackfin are speculative. In Blackfin terms, this means | |
843 | they can be interrupted at any time (even after they have been issued | |
844 | on to the external bus), and re-issued after the interrupt occurs. | |
845 | For memory - this is not a big deal, since memory does not change if | |
846 | it sees a read. | |
847 | ||
848 | If a FIFO is sitting on the end of the read, it will see two reads, | |
849 | when the core only sees one since the FIFO receives both the read | |
850 | which is cancelled (and not delivered to the core) and the one which | |
851 | is re-issued (which is delivered to the core). | |
852 | ||
853 | To solve this, interrupts are turned off before reads occur to | |
854 | I/O space. This option controls which the overhead/latency of | |
855 | controlling interrupts during this time | |
856 | "n" turns interrupts off every read | |
857 | (higher overhead, but lower interrupt latency) | |
858 | "y" turns interrupts off every loop | |
859 | (low overhead, but longer interrupt latency) | |
860 | ||
861 | default behavior is to leave this set to on (type "Y"). If you are experiencing | |
862 | interrupt latency issues, it is safe and OK to turn this off. | |
863 | ||
1394f032 BW |
864 | endmenu |
865 | ||
1394f032 BW |
866 | choice |
867 | prompt "Kernel executes from" | |
868 | help | |
869 | Choose the memory type that the kernel will be running in. | |
870 | ||
871 | config RAMKERNEL | |
872 | bool "RAM" | |
873 | help | |
874 | The kernel will be resident in RAM when running. | |
875 | ||
876 | config ROMKERNEL | |
877 | bool "ROM" | |
878 | help | |
879 | The kernel will be resident in FLASH/ROM when running. | |
880 | ||
881 | endchoice | |
882 | ||
883 | source "mm/Kconfig" | |
884 | ||
780431e3 MF |
885 | config BFIN_GPTIMERS |
886 | tristate "Enable Blackfin General Purpose Timers API" | |
887 | default n | |
888 | help | |
889 | Enable support for the General Purpose Timers API. If you | |
890 | are unsure, say N. | |
891 | ||
892 | To compile this driver as a module, choose M here: the module | |
893 | will be called gptimers.ko. | |
894 | ||
1394f032 | 895 | choice |
d292b000 | 896 | prompt "Uncached DMA region" |
1394f032 | 897 | default DMA_UNCACHED_1M |
86ad7932 CC |
898 | config DMA_UNCACHED_4M |
899 | bool "Enable 4M DMA region" | |
1394f032 BW |
900 | config DMA_UNCACHED_2M |
901 | bool "Enable 2M DMA region" | |
902 | config DMA_UNCACHED_1M | |
903 | bool "Enable 1M DMA region" | |
904 | config DMA_UNCACHED_NONE | |
905 | bool "Disable DMA region" | |
906 | endchoice | |
907 | ||
908 | ||
909 | comment "Cache Support" | |
3bebca2d | 910 | config BFIN_ICACHE |
1394f032 | 911 | bool "Enable ICACHE" |
3bebca2d | 912 | config BFIN_DCACHE |
1394f032 | 913 | bool "Enable DCACHE" |
3bebca2d | 914 | config BFIN_DCACHE_BANKA |
1394f032 | 915 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
3bebca2d | 916 | depends on BFIN_DCACHE && !BF531 |
1394f032 | 917 | default n |
3bebca2d RG |
918 | config BFIN_ICACHE_LOCK |
919 | bool "Enable Instruction Cache Locking" | |
1394f032 BW |
920 | |
921 | choice | |
5ba76675 | 922 | prompt "External memory cache policy" |
3bebca2d | 923 | depends on BFIN_DCACHE |
46fa5eec GY |
924 | default BFIN_WB if !SMP |
925 | default BFIN_WT if SMP | |
3bebca2d | 926 | config BFIN_WB |
1394f032 | 927 | bool "Write back" |
46fa5eec | 928 | depends on !SMP |
1394f032 BW |
929 | help |
930 | Write Back Policy: | |
931 | Cached data will be written back to SDRAM only when needed. | |
932 | This can give a nice increase in performance, but beware of | |
933 | broken drivers that do not properly invalidate/flush their | |
934 | cache. | |
935 | ||
936 | Write Through Policy: | |
937 | Cached data will always be written back to SDRAM when the | |
938 | cache is updated. This is a completely safe setting, but | |
939 | performance is worse than Write Back. | |
940 | ||
941 | If you are unsure of the options and you want to be safe, | |
942 | then go with Write Through. | |
943 | ||
3bebca2d | 944 | config BFIN_WT |
1394f032 BW |
945 | bool "Write through" |
946 | help | |
947 | Write Back Policy: | |
948 | Cached data will be written back to SDRAM only when needed. | |
949 | This can give a nice increase in performance, but beware of | |
950 | broken drivers that do not properly invalidate/flush their | |
951 | cache. | |
952 | ||
953 | Write Through Policy: | |
954 | Cached data will always be written back to SDRAM when the | |
955 | cache is updated. This is a completely safe setting, but | |
956 | performance is worse than Write Back. | |
957 | ||
958 | If you are unsure of the options and you want to be safe, | |
959 | then go with Write Through. | |
960 | ||
961 | endchoice | |
962 | ||
5ba76675 GY |
963 | choice |
964 | prompt "L2 SRAM cache policy" | |
965 | depends on (BF54x || BF561) | |
966 | default BFIN_L2_WT | |
967 | config BFIN_L2_WB | |
968 | bool "Write back" | |
969 | depends on !SMP | |
970 | ||
971 | config BFIN_L2_WT | |
972 | bool "Write through" | |
973 | depends on !SMP | |
974 | ||
975 | config BFIN_L2_NOT_CACHED | |
976 | bool "Not cached" | |
977 | ||
978 | endchoice | |
f099f39a | 979 | |
b97b8a99 BS |
980 | config MPU |
981 | bool "Enable the memory protection unit (EXPERIMENTAL)" | |
982 | default n | |
983 | help | |
984 | Use the processor's MPU to protect applications from accessing | |
985 | memory they do not own. This comes at a performance penalty | |
986 | and is recommended only for debugging. | |
987 | ||
692105b8 | 988 | comment "Asynchronous Memory Configuration" |
1394f032 | 989 | |
ddf416b2 | 990 | menu "EBIU_AMGCTL Global Control" |
1394f032 BW |
991 | config C_AMCKEN |
992 | bool "Enable CLKOUT" | |
993 | default y | |
994 | ||
995 | config C_CDPRIO | |
996 | bool "DMA has priority over core for ext. accesses" | |
997 | default n | |
998 | ||
999 | config C_B0PEN | |
1000 | depends on BF561 | |
1001 | bool "Bank 0 16 bit packing enable" | |
1002 | default y | |
1003 | ||
1004 | config C_B1PEN | |
1005 | depends on BF561 | |
1006 | bool "Bank 1 16 bit packing enable" | |
1007 | default y | |
1008 | ||
1009 | config C_B2PEN | |
1010 | depends on BF561 | |
1011 | bool "Bank 2 16 bit packing enable" | |
1012 | default y | |
1013 | ||
1014 | config C_B3PEN | |
1015 | depends on BF561 | |
1016 | bool "Bank 3 16 bit packing enable" | |
1017 | default n | |
1018 | ||
1019 | choice | |
692105b8 | 1020 | prompt "Enable Asynchronous Memory Banks" |
1394f032 BW |
1021 | default C_AMBEN_ALL |
1022 | ||
1023 | config C_AMBEN | |
1024 | bool "Disable All Banks" | |
1025 | ||
1026 | config C_AMBEN_B0 | |
1027 | bool "Enable Bank 0" | |
1028 | ||
1029 | config C_AMBEN_B0_B1 | |
1030 | bool "Enable Bank 0 & 1" | |
1031 | ||
1032 | config C_AMBEN_B0_B1_B2 | |
1033 | bool "Enable Bank 0 & 1 & 2" | |
1034 | ||
1035 | config C_AMBEN_ALL | |
1036 | bool "Enable All Banks" | |
1037 | endchoice | |
1038 | endmenu | |
1039 | ||
1040 | menu "EBIU_AMBCTL Control" | |
1041 | config BANK_0 | |
c8342f87 | 1042 | hex "Bank 0 (AMBCTL0.L)" |
1394f032 | 1043 | default 0x7BB0 |
c8342f87 MF |
1044 | help |
1045 | These are the low 16 bits of the EBIU_AMBCTL0 MMR which are | |
1046 | used to control the Asynchronous Memory Bank 0 settings. | |
1394f032 BW |
1047 | |
1048 | config BANK_1 | |
c8342f87 | 1049 | hex "Bank 1 (AMBCTL0.H)" |
1394f032 | 1050 | default 0x7BB0 |
197fba56 | 1051 | default 0x5558 if BF54x |
c8342f87 MF |
1052 | help |
1053 | These are the high 16 bits of the EBIU_AMBCTL0 MMR which are | |
1054 | used to control the Asynchronous Memory Bank 1 settings. | |
1394f032 BW |
1055 | |
1056 | config BANK_2 | |
c8342f87 | 1057 | hex "Bank 2 (AMBCTL1.L)" |
1394f032 | 1058 | default 0x7BB0 |
c8342f87 MF |
1059 | help |
1060 | These are the low 16 bits of the EBIU_AMBCTL1 MMR which are | |
1061 | used to control the Asynchronous Memory Bank 2 settings. | |
1394f032 BW |
1062 | |
1063 | config BANK_3 | |
c8342f87 | 1064 | hex "Bank 3 (AMBCTL1.H)" |
1394f032 | 1065 | default 0x99B3 |
c8342f87 MF |
1066 | help |
1067 | These are the high 16 bits of the EBIU_AMBCTL1 MMR which are | |
1068 | used to control the Asynchronous Memory Bank 3 settings. | |
1069 | ||
1394f032 BW |
1070 | endmenu |
1071 | ||
e40540b3 SZ |
1072 | config EBIU_MBSCTLVAL |
1073 | hex "EBIU Bank Select Control Register" | |
1074 | depends on BF54x | |
1075 | default 0 | |
1076 | ||
1077 | config EBIU_MODEVAL | |
1078 | hex "Flash Memory Mode Control Register" | |
1079 | depends on BF54x | |
1080 | default 1 | |
1081 | ||
1082 | config EBIU_FCTLVAL | |
1083 | hex "Flash Memory Bank Control Register" | |
1084 | depends on BF54x | |
1085 | default 6 | |
1394f032 BW |
1086 | endmenu |
1087 | ||
1088 | ############################################################################# | |
1089 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" | |
1090 | ||
1091 | config PCI | |
1092 | bool "PCI support" | |
a95ca3b2 | 1093 | depends on BROKEN |
1394f032 BW |
1094 | help |
1095 | Support for PCI bus. | |
1096 | ||
1097 | source "drivers/pci/Kconfig" | |
1098 | ||
1099 | config HOTPLUG | |
1100 | bool "Support for hot-pluggable device" | |
1101 | help | |
1102 | Say Y here if you want to plug devices into your computer while | |
1103 | the system is running, and be able to use them quickly. In many | |
1104 | cases, the devices can likewise be unplugged at any time too. | |
1105 | ||
1106 | One well known example of this is PCMCIA- or PC-cards, credit-card | |
1107 | size devices such as network cards, modems or hard drives which are | |
1108 | plugged into slots found on all modern laptop computers. Another | |
1109 | example, used on modern desktops as well as laptops, is USB. | |
1110 | ||
a81792f6 JB |
1111 | Enable HOTPLUG and build a modular kernel. Get agent software |
1112 | (from <http://linux-hotplug.sourceforge.net/>) and install it. | |
1394f032 BW |
1113 | Then your kernel will automatically call out to a user mode "policy |
1114 | agent" (/sbin/hotplug) to load modules and set up software needed | |
1115 | to use devices as you hotplug them. | |
1116 | ||
1117 | source "drivers/pcmcia/Kconfig" | |
1118 | ||
1119 | source "drivers/pci/hotplug/Kconfig" | |
1120 | ||
1121 | endmenu | |
1122 | ||
1123 | menu "Executable file formats" | |
1124 | ||
1125 | source "fs/Kconfig.binfmt" | |
1126 | ||
1127 | endmenu | |
1128 | ||
1129 | menu "Power management options" | |
1130 | source "kernel/power/Kconfig" | |
1131 | ||
f4cb5700 JB |
1132 | config ARCH_SUSPEND_POSSIBLE |
1133 | def_bool y | |
1134 | depends on !SMP | |
1135 | ||
1394f032 | 1136 | choice |
1efc80b5 | 1137 | prompt "Standby Power Saving Mode" |
1394f032 | 1138 | depends on PM |
cfefe3c6 MH |
1139 | default PM_BFIN_SLEEP_DEEPER |
1140 | config PM_BFIN_SLEEP_DEEPER | |
1141 | bool "Sleep Deeper" | |
1142 | help | |
1143 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic | |
1144 | power dissipation by disabling the clock to the processor core (CCLK). | |
1145 | Furthermore, Standby sets the internal power supply voltage (VDDINT) | |
1146 | to 0.85 V to provide the greatest power savings, while preserving the | |
1147 | processor state. | |
1148 | The PLL and system clock (SCLK) continue to operate at a very low | |
1149 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, | |
1150 | the SDRAM is put into Self Refresh Mode. Typically an external event | |
1151 | such as GPIO interrupt or RTC activity wakes up the processor. | |
1152 | Various Peripherals such as UART, SPORT, PPI may not function as | |
1153 | normal during Sleep Deeper, due to the reduced SCLK frequency. | |
1154 | When in the sleep mode, system DMA access to L1 memory is not supported. | |
1155 | ||
1efc80b5 MH |
1156 | If unsure, select "Sleep Deeper". |
1157 | ||
cfefe3c6 MH |
1158 | config PM_BFIN_SLEEP |
1159 | bool "Sleep" | |
1160 | help | |
1161 | Sleep Mode (High Power Savings) - The sleep mode reduces power | |
1162 | dissipation by disabling the clock to the processor core (CCLK). | |
1163 | The PLL and system clock (SCLK), however, continue to operate in | |
1164 | this mode. Typically an external event or RTC activity will wake | |
1efc80b5 MH |
1165 | up the processor. When in the sleep mode, system DMA access to L1 |
1166 | memory is not supported. | |
1167 | ||
1168 | If unsure, select "Sleep Deeper". | |
cfefe3c6 | 1169 | endchoice |
1394f032 | 1170 | |
1394f032 | 1171 | config PM_WAKEUP_BY_GPIO |
1efc80b5 | 1172 | bool "Allow Wakeup from Standby by GPIO" |
ff19fed4 | 1173 | depends on PM && !BF54x |
1394f032 BW |
1174 | |
1175 | config PM_WAKEUP_GPIO_NUMBER | |
1efc80b5 | 1176 | int "GPIO number" |
1394f032 BW |
1177 | range 0 47 |
1178 | depends on PM_WAKEUP_BY_GPIO | |
d1a3336e | 1179 | default 2 |
1394f032 BW |
1180 | |
1181 | choice | |
1182 | prompt "GPIO Polarity" | |
1183 | depends on PM_WAKEUP_BY_GPIO | |
1184 | default PM_WAKEUP_GPIO_POLAR_H | |
1185 | config PM_WAKEUP_GPIO_POLAR_H | |
1186 | bool "Active High" | |
1187 | config PM_WAKEUP_GPIO_POLAR_L | |
1188 | bool "Active Low" | |
1189 | config PM_WAKEUP_GPIO_POLAR_EDGE_F | |
1190 | bool "Falling EDGE" | |
1191 | config PM_WAKEUP_GPIO_POLAR_EDGE_R | |
1192 | bool "Rising EDGE" | |
1193 | config PM_WAKEUP_GPIO_POLAR_EDGE_B | |
1194 | bool "Both EDGE" | |
1195 | endchoice | |
1196 | ||
1efc80b5 MH |
1197 | comment "Possible Suspend Mem / Hibernate Wake-Up Sources" |
1198 | depends on PM | |
1199 | ||
1efc80b5 MH |
1200 | config PM_BFIN_WAKE_PH6 |
1201 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" | |
2f6f4bcd | 1202 | depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) |
1efc80b5 MH |
1203 | default n |
1204 | help | |
1205 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) | |
1206 | ||
1efc80b5 MH |
1207 | config PM_BFIN_WAKE_GP |
1208 | bool "Allow Wake-Up from GPIOs" | |
1209 | depends on PM && BF54x | |
1210 | default n | |
1211 | help | |
1212 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) | |
19986289 MH |
1213 | (all processors, except ADSP-BF549). This option sets |
1214 | the general-purpose wake-up enable (GPWE) control bit to enable | |
1215 | wake-up upon detection of an active low signal on the /GPW (PH7) pin. | |
1216 | On ADSP-BF549 this option enables the the same functionality on the | |
1217 | /MRXON pin also PH7. | |
1218 | ||
1394f032 BW |
1219 | endmenu |
1220 | ||
1394f032 BW |
1221 | menu "CPU Frequency scaling" |
1222 | ||
1223 | source "drivers/cpufreq/Kconfig" | |
1224 | ||
5ad2ca5f MH |
1225 | config BFIN_CPU_FREQ |
1226 | bool | |
1227 | depends on CPU_FREQ | |
1228 | select CPU_FREQ_TABLE | |
1229 | default y | |
1230 | ||
14b03204 MH |
1231 | config CPU_VOLTAGE |
1232 | bool "CPU Voltage scaling" | |
73feb5c0 | 1233 | depends on EXPERIMENTAL |
14b03204 MH |
1234 | depends on CPU_FREQ |
1235 | default n | |
1236 | help | |
1237 | Say Y here if you want CPU voltage scaling according to the CPU frequency. | |
1238 | This option violates the PLL BYPASS recommendation in the Blackfin Processor | |
73feb5c0 | 1239 | manuals. There is a theoretical risk that during VDDINT transitions |
14b03204 MH |
1240 | the PLL may unlock. |
1241 | ||
1394f032 BW |
1242 | endmenu |
1243 | ||
1394f032 BW |
1244 | source "net/Kconfig" |
1245 | ||
1246 | source "drivers/Kconfig" | |
1247 | ||
1248 | source "fs/Kconfig" | |
1249 | ||
74ce8322 | 1250 | source "arch/blackfin/Kconfig.debug" |
1394f032 BW |
1251 | |
1252 | source "security/Kconfig" | |
1253 | ||
1254 | source "crypto/Kconfig" | |
1255 | ||
1256 | source "lib/Kconfig" |