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Commit | Line | Data |
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1394f032 BW |
1 | # |
2 | # For a description of the syntax of this configuration file, | |
3 | # see Documentation/kbuild/kconfig-language.txt. | |
4 | # | |
5 | ||
53f8a252 | 6 | mainmenu "Blackfin Kernel Configuration" |
1394f032 BW |
7 | |
8 | config MMU | |
9 | bool | |
10 | default n | |
11 | ||
12 | config FPU | |
13 | bool | |
14 | default n | |
15 | ||
16 | config RWSEM_GENERIC_SPINLOCK | |
17 | bool | |
18 | default y | |
19 | ||
20 | config RWSEM_XCHGADD_ALGORITHM | |
21 | bool | |
22 | default n | |
23 | ||
24 | config BLACKFIN | |
25 | bool | |
26 | default y | |
ec7748b5 | 27 | select HAVE_IDE |
42d4b839 | 28 | select HAVE_OPROFILE |
1394f032 | 29 | |
e3defffe AL |
30 | config ZONE_DMA |
31 | bool | |
32 | default y | |
33 | ||
1394f032 BW |
34 | config GENERIC_FIND_NEXT_BIT |
35 | bool | |
36 | default y | |
37 | ||
38 | config GENERIC_HWEIGHT | |
39 | bool | |
40 | default y | |
41 | ||
42 | config GENERIC_HARDIRQS | |
43 | bool | |
44 | default y | |
45 | ||
46 | config GENERIC_IRQ_PROBE | |
e4e9a7ad | 47 | bool |
1394f032 BW |
48 | default y |
49 | ||
b2d1583f | 50 | config GENERIC_GPIO |
1394f032 BW |
51 | bool |
52 | default y | |
53 | ||
54 | config FORCE_MAX_ZONEORDER | |
55 | int | |
56 | default "14" | |
57 | ||
58 | config GENERIC_CALIBRATE_DELAY | |
59 | bool | |
60 | default y | |
61 | ||
7d2284b0 MD |
62 | config HARDWARE_PM |
63 | def_bool y | |
64 | depends on OPROFILE | |
65 | ||
1394f032 BW |
66 | source "init/Kconfig" |
67 | source "kernel/Kconfig.preempt" | |
68 | ||
69 | menu "Blackfin Processor Options" | |
70 | ||
71 | comment "Processor and Board Settings" | |
72 | ||
73 | choice | |
74 | prompt "CPU" | |
75 | default BF533 | |
76 | ||
59003145 MH |
77 | config BF522 |
78 | bool "BF522" | |
79 | help | |
80 | BF522 Processor Support. | |
81 | ||
1545a111 MF |
82 | config BF523 |
83 | bool "BF523" | |
84 | help | |
85 | BF523 Processor Support. | |
86 | ||
87 | config BF524 | |
88 | bool "BF524" | |
89 | help | |
90 | BF524 Processor Support. | |
91 | ||
59003145 MH |
92 | config BF525 |
93 | bool "BF525" | |
94 | help | |
95 | BF525 Processor Support. | |
96 | ||
1545a111 MF |
97 | config BF526 |
98 | bool "BF526" | |
99 | help | |
100 | BF526 Processor Support. | |
101 | ||
59003145 MH |
102 | config BF527 |
103 | bool "BF527" | |
104 | help | |
105 | BF527 Processor Support. | |
106 | ||
1394f032 BW |
107 | config BF531 |
108 | bool "BF531" | |
109 | help | |
110 | BF531 Processor Support. | |
111 | ||
112 | config BF532 | |
113 | bool "BF532" | |
114 | help | |
115 | BF532 Processor Support. | |
116 | ||
117 | config BF533 | |
118 | bool "BF533" | |
119 | help | |
120 | BF533 Processor Support. | |
121 | ||
122 | config BF534 | |
123 | bool "BF534" | |
124 | help | |
125 | BF534 Processor Support. | |
126 | ||
127 | config BF536 | |
128 | bool "BF536" | |
129 | help | |
130 | BF536 Processor Support. | |
131 | ||
132 | config BF537 | |
133 | bool "BF537" | |
134 | help | |
135 | BF537 Processor Support. | |
136 | ||
24a07a12 RH |
137 | config BF542 |
138 | bool "BF542" | |
139 | help | |
140 | BF542 Processor Support. | |
141 | ||
142 | config BF544 | |
143 | bool "BF544" | |
144 | help | |
145 | BF544 Processor Support. | |
146 | ||
7c7fd170 MF |
147 | config BF547 |
148 | bool "BF547" | |
149 | help | |
150 | BF547 Processor Support. | |
151 | ||
24a07a12 RH |
152 | config BF548 |
153 | bool "BF548" | |
154 | help | |
155 | BF548 Processor Support. | |
156 | ||
157 | config BF549 | |
158 | bool "BF549" | |
159 | help | |
160 | BF549 Processor Support. | |
161 | ||
1394f032 BW |
162 | config BF561 |
163 | bool "BF561" | |
164 | help | |
cd88b4dc | 165 | BF561 Processor Support. |
1394f032 BW |
166 | |
167 | endchoice | |
168 | ||
169 | choice | |
170 | prompt "Silicon Rev" | |
46ce0d9a MF |
171 | default BF_REV_0_1 if (BF52x || BF54x) |
172 | default BF_REV_0_2 if (BF534 || BF536 || BF537) | |
173 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561) | |
24a07a12 RH |
174 | |
175 | config BF_REV_0_0 | |
176 | bool "0.0" | |
d07f4380 | 177 | depends on (BF52x || BF54x) |
59003145 MH |
178 | |
179 | config BF_REV_0_1 | |
d07f4380 MF |
180 | bool "0.1" |
181 | depends on (BF52x || BF54x) | |
1394f032 BW |
182 | |
183 | config BF_REV_0_2 | |
184 | bool "0.2" | |
185 | depends on (BF537 || BF536 || BF534) | |
186 | ||
187 | config BF_REV_0_3 | |
188 | bool "0.3" | |
189 | depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) | |
190 | ||
191 | config BF_REV_0_4 | |
192 | bool "0.4" | |
193 | depends on (BF561 || BF533 || BF532 || BF531) | |
194 | ||
195 | config BF_REV_0_5 | |
196 | bool "0.5" | |
197 | depends on (BF561 || BF533 || BF532 || BF531) | |
198 | ||
de3025f4 JZ |
199 | config BF_REV_ANY |
200 | bool "any" | |
201 | ||
202 | config BF_REV_NONE | |
203 | bool "none" | |
204 | ||
1394f032 BW |
205 | endchoice |
206 | ||
59003145 MH |
207 | config BF52x |
208 | bool | |
1545a111 | 209 | depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527) |
59003145 MH |
210 | default y |
211 | ||
24a07a12 RH |
212 | config BF53x |
213 | bool | |
214 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) | |
215 | default y | |
216 | ||
217 | config BF54x | |
218 | bool | |
7c7fd170 | 219 | depends on (BF542 || BF544 || BF547 || BF548 || BF549) |
24a07a12 RH |
220 | default y |
221 | ||
1394f032 BW |
222 | config MEM_GENERIC_BOARD |
223 | bool | |
224 | depends on GENERIC_BOARD | |
225 | default y | |
226 | ||
227 | config MEM_MT48LC64M4A2FB_7E | |
228 | bool | |
229 | depends on (BFIN533_STAMP) | |
230 | default y | |
231 | ||
232 | config MEM_MT48LC16M16A2TG_75 | |
233 | bool | |
234 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | |
ab472a04 | 235 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \ |
9db144fe | 236 | || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM) |
1394f032 BW |
237 | default y |
238 | ||
239 | config MEM_MT48LC32M8A2_75 | |
240 | bool | |
241 | depends on (BFIN537_STAMP || PNAV10) | |
242 | default y | |
243 | ||
244 | config MEM_MT48LC8M32B2B5_7 | |
245 | bool | |
246 | depends on (BFIN561_BLUETECHNIX_CM) | |
247 | default y | |
248 | ||
59003145 MH |
249 | config MEM_MT48LC32M16A2TG_75 |
250 | bool | |
8cc7117e | 251 | depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD) |
59003145 MH |
252 | default y |
253 | ||
59003145 | 254 | source "arch/blackfin/mach-bf527/Kconfig" |
1394f032 BW |
255 | source "arch/blackfin/mach-bf533/Kconfig" |
256 | source "arch/blackfin/mach-bf561/Kconfig" | |
257 | source "arch/blackfin/mach-bf537/Kconfig" | |
24a07a12 | 258 | source "arch/blackfin/mach-bf548/Kconfig" |
1394f032 BW |
259 | |
260 | menu "Board customizations" | |
261 | ||
262 | config CMDLINE_BOOL | |
263 | bool "Default bootloader kernel arguments" | |
264 | ||
265 | config CMDLINE | |
266 | string "Initial kernel command string" | |
267 | depends on CMDLINE_BOOL | |
268 | default "console=ttyBF0,57600" | |
269 | help | |
270 | If you don't have a boot loader capable of passing a command line string | |
271 | to the kernel, you may specify one here. As a minimum, you should specify | |
272 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). | |
273 | ||
5f004c20 MF |
274 | config BOOT_LOAD |
275 | hex "Kernel load address for booting" | |
276 | default "0x1000" | |
277 | range 0x1000 0x20000000 | |
278 | help | |
279 | This option allows you to set the load address of the kernel. | |
280 | This can be useful if you are on a board which has a small amount | |
281 | of memory or you wish to reserve some memory at the beginning of | |
282 | the address space. | |
283 | ||
284 | Note that you need to keep this value above 4k (0x1000) as this | |
285 | memory region is used to capture NULL pointer references as well | |
286 | as some core kernel functions. | |
287 | ||
8cc7117e MH |
288 | config ROM_BASE |
289 | hex "Kernel ROM Base" | |
290 | default "0x20040000" | |
291 | range 0x20000000 0x20400000 if !(BF54x || BF561) | |
292 | range 0x20000000 0x30000000 if (BF54x || BF561) | |
293 | help | |
294 | ||
f16295e7 | 295 | comment "Clock/PLL Setup" |
1394f032 BW |
296 | |
297 | config CLKIN_HZ | |
2fb6cb41 | 298 | int "Frequency of the crystal on the board in Hz" |
1394f032 BW |
299 | default "11059200" if BFIN533_STAMP |
300 | default "27000000" if BFIN533_EZKIT | |
8cc7117e | 301 | default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD) |
1394f032 BW |
302 | default "30000000" if BFIN561_EZKIT |
303 | default "24576000" if PNAV10 | |
5d1617b2 | 304 | default "10000000" if BFIN532_IP0X |
1394f032 BW |
305 | help |
306 | The frequency of CLKIN crystal oscillator on the board in Hz. | |
2fb6cb41 SZ |
307 | Warning: This value should match the crystal on the board. Otherwise, |
308 | peripherals won't work properly. | |
1394f032 | 309 | |
f16295e7 RG |
310 | config BFIN_KERNEL_CLOCK |
311 | bool "Re-program Clocks while Kernel boots?" | |
312 | default n | |
313 | help | |
314 | This option decides if kernel clocks are re-programed from the | |
315 | bootloader settings. If the clocks are not set, the SDRAM settings | |
316 | are also not changed, and the Bootloader does 100% of the hardware | |
317 | configuration. | |
318 | ||
319 | config PLL_BYPASS | |
e4e9a7ad MF |
320 | bool "Bypass PLL" |
321 | depends on BFIN_KERNEL_CLOCK | |
322 | default n | |
f16295e7 RG |
323 | |
324 | config CLKIN_HALF | |
325 | bool "Half Clock In" | |
326 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
327 | default n | |
328 | help | |
329 | If this is set the clock will be divided by 2, before it goes to the PLL. | |
330 | ||
331 | config VCO_MULT | |
332 | int "VCO Multiplier" | |
333 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
334 | range 1 64 | |
335 | default "22" if BFIN533_EZKIT | |
336 | default "45" if BFIN533_STAMP | |
db68254f | 337 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM) |
f16295e7 | 338 | default "22" if BFIN533_BLUETECHNIX_CM |
9db144fe | 339 | default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
f16295e7 | 340 | default "20" if BFIN561_EZKIT |
8cc7117e | 341 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD) |
f16295e7 RG |
342 | help |
343 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | |
344 | PLL Frequency = (Crystal Frequency) * (this setting) | |
345 | ||
346 | choice | |
347 | prompt "Core Clock Divider" | |
348 | depends on BFIN_KERNEL_CLOCK | |
349 | default CCLK_DIV_1 | |
350 | help | |
351 | This sets the frequency of the core. It can be 1, 2, 4 or 8 | |
352 | Core Frequency = (PLL frequency) / (this setting) | |
353 | ||
354 | config CCLK_DIV_1 | |
355 | bool "1" | |
356 | ||
357 | config CCLK_DIV_2 | |
358 | bool "2" | |
359 | ||
360 | config CCLK_DIV_4 | |
361 | bool "4" | |
362 | ||
363 | config CCLK_DIV_8 | |
364 | bool "8" | |
365 | endchoice | |
366 | ||
367 | config SCLK_DIV | |
368 | int "System Clock Divider" | |
369 | depends on BFIN_KERNEL_CLOCK | |
370 | range 1 15 | |
5f004c20 | 371 | default 5 |
f16295e7 RG |
372 | help |
373 | This sets the frequency of the system clock (including SDRAM or DDR). | |
374 | This can be between 1 and 15 | |
375 | System Clock = (PLL frequency) / (this setting) | |
376 | ||
5f004c20 MF |
377 | choice |
378 | prompt "DDR SDRAM Chip Type" | |
379 | depends on BFIN_KERNEL_CLOCK | |
380 | depends on BF54x | |
381 | default MEM_MT46V32M16_5B | |
382 | ||
383 | config MEM_MT46V32M16_6T | |
384 | bool "MT46V32M16_6T" | |
385 | ||
386 | config MEM_MT46V32M16_5B | |
387 | bool "MT46V32M16_5B" | |
388 | endchoice | |
389 | ||
7eb2c23f MF |
390 | config MAX_MEM_SIZE |
391 | int "Max SDRAM Memory Size in MBytes" | |
392 | depends on !MPU | |
393 | default 512 | |
394 | help | |
395 | This is the max memory size that the kernel will create CPLB | |
396 | tables for. Your system will not be able to handle any more. | |
397 | ||
f16295e7 RG |
398 | # |
399 | # Max & Min Speeds for various Chips | |
400 | # | |
401 | config MAX_VCO_HZ | |
402 | int | |
403 | default 600000000 if BF522 | |
1545a111 MF |
404 | default 400000000 if BF523 |
405 | default 400000000 if BF524 | |
f16295e7 | 406 | default 600000000 if BF525 |
1545a111 | 407 | default 400000000 if BF526 |
f16295e7 RG |
408 | default 600000000 if BF527 |
409 | default 400000000 if BF531 | |
410 | default 400000000 if BF532 | |
411 | default 750000000 if BF533 | |
412 | default 500000000 if BF534 | |
413 | default 400000000 if BF536 | |
414 | default 600000000 if BF537 | |
f72eecb9 RG |
415 | default 533333333 if BF538 |
416 | default 533333333 if BF539 | |
f16295e7 | 417 | default 600000000 if BF542 |
f72eecb9 | 418 | default 533333333 if BF544 |
1545a111 MF |
419 | default 600000000 if BF547 |
420 | default 600000000 if BF548 | |
f72eecb9 | 421 | default 533333333 if BF549 |
f16295e7 RG |
422 | default 600000000 if BF561 |
423 | ||
424 | config MIN_VCO_HZ | |
425 | int | |
426 | default 50000000 | |
427 | ||
428 | config MAX_SCLK_HZ | |
429 | int | |
f72eecb9 | 430 | default 133333333 |
f16295e7 RG |
431 | |
432 | config MIN_SCLK_HZ | |
433 | int | |
434 | default 27000000 | |
435 | ||
436 | comment "Kernel Timer/Scheduler" | |
437 | ||
438 | source kernel/Kconfig.hz | |
439 | ||
8b5f79f9 VM |
440 | config GENERIC_TIME |
441 | bool "Generic time" | |
442 | default y | |
443 | ||
444 | config GENERIC_CLOCKEVENTS | |
445 | bool "Generic clock events" | |
446 | depends on GENERIC_TIME | |
447 | default y | |
448 | ||
449 | config CYCLES_CLOCKSOURCE | |
450 | bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)" | |
451 | depends on EXPERIMENTAL | |
452 | depends on GENERIC_CLOCKEVENTS | |
453 | depends on !BFIN_SCRATCH_REG_CYCLES | |
454 | default n | |
455 | help | |
456 | If you say Y here, you will enable support for using the 'cycles' | |
457 | registers as a clock source. Doing so means you will be unable to | |
458 | safely write to the 'cycles' register during runtime. You will | |
459 | still be able to read it (such as for performance monitoring), but | |
460 | writing the registers will most likely crash the kernel. | |
461 | ||
462 | source kernel/time/Kconfig | |
463 | ||
5f004c20 | 464 | comment "Misc" |
971d5bc4 | 465 | |
f0b5d12f MF |
466 | choice |
467 | prompt "Blackfin Exception Scratch Register" | |
468 | default BFIN_SCRATCH_REG_RETN | |
469 | help | |
470 | Select the resource to reserve for the Exception handler: | |
471 | - RETN: Non-Maskable Interrupt (NMI) | |
472 | - RETE: Exception Return (JTAG/ICE) | |
473 | - CYCLES: Performance counter | |
474 | ||
475 | If you are unsure, please select "RETN". | |
476 | ||
477 | config BFIN_SCRATCH_REG_RETN | |
478 | bool "RETN" | |
479 | help | |
480 | Use the RETN register in the Blackfin exception handler | |
481 | as a stack scratch register. This means you cannot | |
482 | safely use NMI on the Blackfin while running Linux, but | |
483 | you can debug the system with a JTAG ICE and use the | |
484 | CYCLES performance registers. | |
485 | ||
486 | If you are unsure, please select "RETN". | |
487 | ||
488 | config BFIN_SCRATCH_REG_RETE | |
489 | bool "RETE" | |
490 | help | |
491 | Use the RETE register in the Blackfin exception handler | |
492 | as a stack scratch register. This means you cannot | |
493 | safely use a JTAG ICE while debugging a Blackfin board, | |
494 | but you can safely use the CYCLES performance registers | |
495 | and the NMI. | |
496 | ||
497 | If you are unsure, please select "RETN". | |
498 | ||
499 | config BFIN_SCRATCH_REG_CYCLES | |
500 | bool "CYCLES" | |
501 | help | |
502 | Use the CYCLES register in the Blackfin exception handler | |
503 | as a stack scratch register. This means you cannot | |
504 | safely use the CYCLES performance registers on a Blackfin | |
505 | board at anytime, but you can debug the system with a JTAG | |
506 | ICE and use the NMI. | |
507 | ||
508 | If you are unsure, please select "RETN". | |
509 | ||
510 | endchoice | |
511 | ||
1394f032 BW |
512 | endmenu |
513 | ||
514 | ||
515 | menu "Blackfin Kernel Optimizations" | |
516 | ||
1394f032 BW |
517 | comment "Memory Optimizations" |
518 | ||
519 | config I_ENTRY_L1 | |
520 | bool "Locate interrupt entry code in L1 Memory" | |
521 | default y | |
522 | help | |
01dd2fbf ML |
523 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
524 | into L1 instruction memory. (less latency) | |
1394f032 BW |
525 | |
526 | config EXCPT_IRQ_SYSC_L1 | |
01dd2fbf | 527 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
1394f032 BW |
528 | default y |
529 | help | |
01dd2fbf | 530 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
cfefe3c6 | 531 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
01dd2fbf | 532 | (less latency) |
1394f032 BW |
533 | |
534 | config DO_IRQ_L1 | |
535 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | |
536 | default y | |
537 | help | |
01dd2fbf ML |
538 | If enabled, the frequently called do_irq dispatcher function is linked |
539 | into L1 instruction memory. (less latency) | |
1394f032 BW |
540 | |
541 | config CORE_TIMER_IRQ_L1 | |
542 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | |
543 | default y | |
544 | help | |
01dd2fbf ML |
545 | If enabled, the frequently called timer_interrupt() function is linked |
546 | into L1 instruction memory. (less latency) | |
1394f032 BW |
547 | |
548 | config IDLE_L1 | |
549 | bool "Locate frequently idle function in L1 Memory" | |
550 | default y | |
551 | help | |
01dd2fbf ML |
552 | If enabled, the frequently called idle function is linked |
553 | into L1 instruction memory. (less latency) | |
1394f032 BW |
554 | |
555 | config SCHEDULE_L1 | |
556 | bool "Locate kernel schedule function in L1 Memory" | |
557 | default y | |
558 | help | |
01dd2fbf ML |
559 | If enabled, the frequently called kernel schedule is linked |
560 | into L1 instruction memory. (less latency) | |
1394f032 BW |
561 | |
562 | config ARITHMETIC_OPS_L1 | |
563 | bool "Locate kernel owned arithmetic functions in L1 Memory" | |
564 | default y | |
565 | help | |
01dd2fbf ML |
566 | If enabled, arithmetic functions are linked |
567 | into L1 instruction memory. (less latency) | |
1394f032 BW |
568 | |
569 | config ACCESS_OK_L1 | |
570 | bool "Locate access_ok function in L1 Memory" | |
571 | default y | |
572 | help | |
01dd2fbf ML |
573 | If enabled, the access_ok function is linked |
574 | into L1 instruction memory. (less latency) | |
1394f032 BW |
575 | |
576 | config MEMSET_L1 | |
577 | bool "Locate memset function in L1 Memory" | |
578 | default y | |
579 | help | |
01dd2fbf ML |
580 | If enabled, the memset function is linked |
581 | into L1 instruction memory. (less latency) | |
1394f032 BW |
582 | |
583 | config MEMCPY_L1 | |
584 | bool "Locate memcpy function in L1 Memory" | |
585 | default y | |
586 | help | |
01dd2fbf ML |
587 | If enabled, the memcpy function is linked |
588 | into L1 instruction memory. (less latency) | |
1394f032 BW |
589 | |
590 | config SYS_BFIN_SPINLOCK_L1 | |
591 | bool "Locate sys_bfin_spinlock function in L1 Memory" | |
592 | default y | |
593 | help | |
01dd2fbf ML |
594 | If enabled, sys_bfin_spinlock function is linked |
595 | into L1 instruction memory. (less latency) | |
1394f032 BW |
596 | |
597 | config IP_CHECKSUM_L1 | |
598 | bool "Locate IP Checksum function in L1 Memory" | |
599 | default n | |
600 | help | |
01dd2fbf ML |
601 | If enabled, the IP Checksum function is linked |
602 | into L1 instruction memory. (less latency) | |
1394f032 BW |
603 | |
604 | config CACHELINE_ALIGNED_L1 | |
605 | bool "Locate cacheline_aligned data to L1 Data Memory" | |
157cc5aa MH |
606 | default y if !BF54x |
607 | default n if BF54x | |
1394f032 BW |
608 | depends on !BF531 |
609 | help | |
01dd2fbf ML |
610 | If enabled, cacheline_anligned data is linked |
611 | into L1 data memory. (less latency) | |
1394f032 BW |
612 | |
613 | config SYSCALL_TAB_L1 | |
614 | bool "Locate Syscall Table L1 Data Memory" | |
615 | default n | |
616 | depends on !BF531 | |
617 | help | |
01dd2fbf ML |
618 | If enabled, the Syscall LUT is linked |
619 | into L1 data memory. (less latency) | |
1394f032 BW |
620 | |
621 | config CPLB_SWITCH_TAB_L1 | |
622 | bool "Locate CPLB Switch Tables L1 Data Memory" | |
623 | default n | |
624 | depends on !BF531 | |
625 | help | |
01dd2fbf ML |
626 | If enabled, the CPLB Switch Tables are linked |
627 | into L1 data memory. (less latency) | |
1394f032 | 628 | |
ca87b7ad GY |
629 | config APP_STACK_L1 |
630 | bool "Support locating application stack in L1 Scratch Memory" | |
631 | default y | |
632 | help | |
633 | If enabled the application stack can be located in L1 | |
634 | scratch memory (less latency). | |
635 | ||
636 | Currently only works with FLAT binaries. | |
637 | ||
251383c7 RG |
638 | comment "Speed Optimizations" |
639 | config BFIN_INS_LOWOVERHEAD | |
640 | bool "ins[bwl] low overhead, higher interrupt latency" | |
641 | default y | |
642 | help | |
643 | Reads on the Blackfin are speculative. In Blackfin terms, this means | |
644 | they can be interrupted at any time (even after they have been issued | |
645 | on to the external bus), and re-issued after the interrupt occurs. | |
646 | For memory - this is not a big deal, since memory does not change if | |
647 | it sees a read. | |
648 | ||
649 | If a FIFO is sitting on the end of the read, it will see two reads, | |
650 | when the core only sees one since the FIFO receives both the read | |
651 | which is cancelled (and not delivered to the core) and the one which | |
652 | is re-issued (which is delivered to the core). | |
653 | ||
654 | To solve this, interrupts are turned off before reads occur to | |
655 | I/O space. This option controls which the overhead/latency of | |
656 | controlling interrupts during this time | |
657 | "n" turns interrupts off every read | |
658 | (higher overhead, but lower interrupt latency) | |
659 | "y" turns interrupts off every loop | |
660 | (low overhead, but longer interrupt latency) | |
661 | ||
662 | default behavior is to leave this set to on (type "Y"). If you are experiencing | |
663 | interrupt latency issues, it is safe and OK to turn this off. | |
664 | ||
1394f032 BW |
665 | endmenu |
666 | ||
667 | ||
668 | choice | |
669 | prompt "Kernel executes from" | |
670 | help | |
671 | Choose the memory type that the kernel will be running in. | |
672 | ||
673 | config RAMKERNEL | |
674 | bool "RAM" | |
675 | help | |
676 | The kernel will be resident in RAM when running. | |
677 | ||
678 | config ROMKERNEL | |
679 | bool "ROM" | |
680 | help | |
681 | The kernel will be resident in FLASH/ROM when running. | |
682 | ||
683 | endchoice | |
684 | ||
685 | source "mm/Kconfig" | |
686 | ||
780431e3 MF |
687 | config BFIN_GPTIMERS |
688 | tristate "Enable Blackfin General Purpose Timers API" | |
689 | default n | |
690 | help | |
691 | Enable support for the General Purpose Timers API. If you | |
692 | are unsure, say N. | |
693 | ||
694 | To compile this driver as a module, choose M here: the module | |
695 | will be called gptimers.ko. | |
696 | ||
1394f032 BW |
697 | config BFIN_DMA_5XX |
698 | bool "Enable DMA Support" | |
59003145 | 699 | depends on (BF52x || BF53x || BF561 || BF54x) |
1394f032 BW |
700 | default y |
701 | help | |
702 | DMA driver for BF5xx. | |
703 | ||
704 | choice | |
705 | prompt "Uncached SDRAM region" | |
706 | default DMA_UNCACHED_1M | |
247537b9 | 707 | depends on BFIN_DMA_5XX |
86ad7932 CC |
708 | config DMA_UNCACHED_4M |
709 | bool "Enable 4M DMA region" | |
1394f032 BW |
710 | config DMA_UNCACHED_2M |
711 | bool "Enable 2M DMA region" | |
712 | config DMA_UNCACHED_1M | |
713 | bool "Enable 1M DMA region" | |
714 | config DMA_UNCACHED_NONE | |
715 | bool "Disable DMA region" | |
716 | endchoice | |
717 | ||
718 | ||
719 | comment "Cache Support" | |
3bebca2d | 720 | config BFIN_ICACHE |
1394f032 | 721 | bool "Enable ICACHE" |
3bebca2d | 722 | config BFIN_DCACHE |
1394f032 | 723 | bool "Enable DCACHE" |
3bebca2d | 724 | config BFIN_DCACHE_BANKA |
1394f032 | 725 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
3bebca2d | 726 | depends on BFIN_DCACHE && !BF531 |
1394f032 | 727 | default n |
3bebca2d RG |
728 | config BFIN_ICACHE_LOCK |
729 | bool "Enable Instruction Cache Locking" | |
1394f032 BW |
730 | |
731 | choice | |
732 | prompt "Policy" | |
3bebca2d RG |
733 | depends on BFIN_DCACHE |
734 | default BFIN_WB | |
735 | config BFIN_WB | |
1394f032 BW |
736 | bool "Write back" |
737 | help | |
738 | Write Back Policy: | |
739 | Cached data will be written back to SDRAM only when needed. | |
740 | This can give a nice increase in performance, but beware of | |
741 | broken drivers that do not properly invalidate/flush their | |
742 | cache. | |
743 | ||
744 | Write Through Policy: | |
745 | Cached data will always be written back to SDRAM when the | |
746 | cache is updated. This is a completely safe setting, but | |
747 | performance is worse than Write Back. | |
748 | ||
749 | If you are unsure of the options and you want to be safe, | |
750 | then go with Write Through. | |
751 | ||
3bebca2d | 752 | config BFIN_WT |
1394f032 BW |
753 | bool "Write through" |
754 | help | |
755 | Write Back Policy: | |
756 | Cached data will be written back to SDRAM only when needed. | |
757 | This can give a nice increase in performance, but beware of | |
758 | broken drivers that do not properly invalidate/flush their | |
759 | cache. | |
760 | ||
761 | Write Through Policy: | |
762 | Cached data will always be written back to SDRAM when the | |
763 | cache is updated. This is a completely safe setting, but | |
764 | performance is worse than Write Back. | |
765 | ||
766 | If you are unsure of the options and you want to be safe, | |
767 | then go with Write Through. | |
768 | ||
769 | endchoice | |
770 | ||
b97b8a99 BS |
771 | config MPU |
772 | bool "Enable the memory protection unit (EXPERIMENTAL)" | |
773 | default n | |
774 | help | |
775 | Use the processor's MPU to protect applications from accessing | |
776 | memory they do not own. This comes at a performance penalty | |
777 | and is recommended only for debugging. | |
778 | ||
1394f032 BW |
779 | comment "Asynchonous Memory Configuration" |
780 | ||
ddf416b2 | 781 | menu "EBIU_AMGCTL Global Control" |
1394f032 BW |
782 | config C_AMCKEN |
783 | bool "Enable CLKOUT" | |
784 | default y | |
785 | ||
786 | config C_CDPRIO | |
787 | bool "DMA has priority over core for ext. accesses" | |
788 | default n | |
789 | ||
790 | config C_B0PEN | |
791 | depends on BF561 | |
792 | bool "Bank 0 16 bit packing enable" | |
793 | default y | |
794 | ||
795 | config C_B1PEN | |
796 | depends on BF561 | |
797 | bool "Bank 1 16 bit packing enable" | |
798 | default y | |
799 | ||
800 | config C_B2PEN | |
801 | depends on BF561 | |
802 | bool "Bank 2 16 bit packing enable" | |
803 | default y | |
804 | ||
805 | config C_B3PEN | |
806 | depends on BF561 | |
807 | bool "Bank 3 16 bit packing enable" | |
808 | default n | |
809 | ||
810 | choice | |
811 | prompt"Enable Asynchonous Memory Banks" | |
812 | default C_AMBEN_ALL | |
813 | ||
814 | config C_AMBEN | |
815 | bool "Disable All Banks" | |
816 | ||
817 | config C_AMBEN_B0 | |
818 | bool "Enable Bank 0" | |
819 | ||
820 | config C_AMBEN_B0_B1 | |
821 | bool "Enable Bank 0 & 1" | |
822 | ||
823 | config C_AMBEN_B0_B1_B2 | |
824 | bool "Enable Bank 0 & 1 & 2" | |
825 | ||
826 | config C_AMBEN_ALL | |
827 | bool "Enable All Banks" | |
828 | endchoice | |
829 | endmenu | |
830 | ||
831 | menu "EBIU_AMBCTL Control" | |
832 | config BANK_0 | |
833 | hex "Bank 0" | |
834 | default 0x7BB0 | |
835 | ||
836 | config BANK_1 | |
837 | hex "Bank 1" | |
838 | default 0x7BB0 | |
197fba56 | 839 | default 0x5558 if BF54x |
1394f032 BW |
840 | |
841 | config BANK_2 | |
842 | hex "Bank 2" | |
843 | default 0x7BB0 | |
844 | ||
845 | config BANK_3 | |
846 | hex "Bank 3" | |
847 | default 0x99B3 | |
848 | endmenu | |
849 | ||
e40540b3 SZ |
850 | config EBIU_MBSCTLVAL |
851 | hex "EBIU Bank Select Control Register" | |
852 | depends on BF54x | |
853 | default 0 | |
854 | ||
855 | config EBIU_MODEVAL | |
856 | hex "Flash Memory Mode Control Register" | |
857 | depends on BF54x | |
858 | default 1 | |
859 | ||
860 | config EBIU_FCTLVAL | |
861 | hex "Flash Memory Bank Control Register" | |
862 | depends on BF54x | |
863 | default 6 | |
1394f032 BW |
864 | endmenu |
865 | ||
866 | ############################################################################# | |
867 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" | |
868 | ||
869 | config PCI | |
870 | bool "PCI support" | |
a95ca3b2 | 871 | depends on BROKEN |
1394f032 BW |
872 | help |
873 | Support for PCI bus. | |
874 | ||
875 | source "drivers/pci/Kconfig" | |
876 | ||
877 | config HOTPLUG | |
878 | bool "Support for hot-pluggable device" | |
879 | help | |
880 | Say Y here if you want to plug devices into your computer while | |
881 | the system is running, and be able to use them quickly. In many | |
882 | cases, the devices can likewise be unplugged at any time too. | |
883 | ||
884 | One well known example of this is PCMCIA- or PC-cards, credit-card | |
885 | size devices such as network cards, modems or hard drives which are | |
886 | plugged into slots found on all modern laptop computers. Another | |
887 | example, used on modern desktops as well as laptops, is USB. | |
888 | ||
a81792f6 JB |
889 | Enable HOTPLUG and build a modular kernel. Get agent software |
890 | (from <http://linux-hotplug.sourceforge.net/>) and install it. | |
1394f032 BW |
891 | Then your kernel will automatically call out to a user mode "policy |
892 | agent" (/sbin/hotplug) to load modules and set up software needed | |
893 | to use devices as you hotplug them. | |
894 | ||
895 | source "drivers/pcmcia/Kconfig" | |
896 | ||
897 | source "drivers/pci/hotplug/Kconfig" | |
898 | ||
899 | endmenu | |
900 | ||
901 | menu "Executable file formats" | |
902 | ||
903 | source "fs/Kconfig.binfmt" | |
904 | ||
905 | endmenu | |
906 | ||
907 | menu "Power management options" | |
908 | source "kernel/power/Kconfig" | |
909 | ||
f4cb5700 JB |
910 | config ARCH_SUSPEND_POSSIBLE |
911 | def_bool y | |
912 | depends on !SMP | |
913 | ||
1394f032 | 914 | choice |
1efc80b5 | 915 | prompt "Standby Power Saving Mode" |
1394f032 | 916 | depends on PM |
cfefe3c6 MH |
917 | default PM_BFIN_SLEEP_DEEPER |
918 | config PM_BFIN_SLEEP_DEEPER | |
919 | bool "Sleep Deeper" | |
920 | help | |
921 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic | |
922 | power dissipation by disabling the clock to the processor core (CCLK). | |
923 | Furthermore, Standby sets the internal power supply voltage (VDDINT) | |
924 | to 0.85 V to provide the greatest power savings, while preserving the | |
925 | processor state. | |
926 | The PLL and system clock (SCLK) continue to operate at a very low | |
927 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, | |
928 | the SDRAM is put into Self Refresh Mode. Typically an external event | |
929 | such as GPIO interrupt or RTC activity wakes up the processor. | |
930 | Various Peripherals such as UART, SPORT, PPI may not function as | |
931 | normal during Sleep Deeper, due to the reduced SCLK frequency. | |
932 | When in the sleep mode, system DMA access to L1 memory is not supported. | |
933 | ||
1efc80b5 MH |
934 | If unsure, select "Sleep Deeper". |
935 | ||
cfefe3c6 MH |
936 | config PM_BFIN_SLEEP |
937 | bool "Sleep" | |
938 | help | |
939 | Sleep Mode (High Power Savings) - The sleep mode reduces power | |
940 | dissipation by disabling the clock to the processor core (CCLK). | |
941 | The PLL and system clock (SCLK), however, continue to operate in | |
942 | this mode. Typically an external event or RTC activity will wake | |
1efc80b5 MH |
943 | up the processor. When in the sleep mode, system DMA access to L1 |
944 | memory is not supported. | |
945 | ||
946 | If unsure, select "Sleep Deeper". | |
cfefe3c6 | 947 | endchoice |
1394f032 | 948 | |
1394f032 | 949 | config PM_WAKEUP_BY_GPIO |
1efc80b5 | 950 | bool "Allow Wakeup from Standby by GPIO" |
1394f032 BW |
951 | |
952 | config PM_WAKEUP_GPIO_NUMBER | |
1efc80b5 | 953 | int "GPIO number" |
1394f032 BW |
954 | range 0 47 |
955 | depends on PM_WAKEUP_BY_GPIO | |
956 | default 2 if BFIN537_STAMP | |
957 | ||
958 | choice | |
959 | prompt "GPIO Polarity" | |
960 | depends on PM_WAKEUP_BY_GPIO | |
961 | default PM_WAKEUP_GPIO_POLAR_H | |
962 | config PM_WAKEUP_GPIO_POLAR_H | |
963 | bool "Active High" | |
964 | config PM_WAKEUP_GPIO_POLAR_L | |
965 | bool "Active Low" | |
966 | config PM_WAKEUP_GPIO_POLAR_EDGE_F | |
967 | bool "Falling EDGE" | |
968 | config PM_WAKEUP_GPIO_POLAR_EDGE_R | |
969 | bool "Rising EDGE" | |
970 | config PM_WAKEUP_GPIO_POLAR_EDGE_B | |
971 | bool "Both EDGE" | |
972 | endchoice | |
973 | ||
1efc80b5 MH |
974 | comment "Possible Suspend Mem / Hibernate Wake-Up Sources" |
975 | depends on PM | |
976 | ||
1efc80b5 MH |
977 | config PM_BFIN_WAKE_PH6 |
978 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" | |
979 | depends on PM && (BF52x || BF534 || BF536 || BF537) | |
980 | default n | |
981 | help | |
982 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) | |
983 | ||
1efc80b5 MH |
984 | config PM_BFIN_WAKE_GP |
985 | bool "Allow Wake-Up from GPIOs" | |
986 | depends on PM && BF54x | |
987 | default n | |
988 | help | |
989 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) | |
1394f032 BW |
990 | endmenu |
991 | ||
1394f032 BW |
992 | menu "CPU Frequency scaling" |
993 | ||
994 | source "drivers/cpufreq/Kconfig" | |
995 | ||
14b03204 MH |
996 | config CPU_VOLTAGE |
997 | bool "CPU Voltage scaling" | |
998 | depends on EXPERIMENTAL | |
999 | depends on CPU_FREQ | |
1000 | default n | |
1001 | help | |
1002 | Say Y here if you want CPU voltage scaling according to the CPU frequency. | |
1003 | This option violates the PLL BYPASS recommendation in the Blackfin Processor | |
1004 | manuals. There is a theoretical risk that during VDDINT transitions | |
1005 | the PLL may unlock. | |
1006 | ||
1394f032 BW |
1007 | endmenu |
1008 | ||
1394f032 BW |
1009 | source "net/Kconfig" |
1010 | ||
1011 | source "drivers/Kconfig" | |
1012 | ||
1013 | source "fs/Kconfig" | |
1014 | ||
74ce8322 | 1015 | source "arch/blackfin/Kconfig.debug" |
1394f032 BW |
1016 | |
1017 | source "security/Kconfig" | |
1018 | ||
1019 | source "crypto/Kconfig" | |
1020 | ||
1021 | source "lib/Kconfig" |