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Commit | Line | Data |
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1394f032 BW |
1 | # |
2 | # For a description of the syntax of this configuration file, | |
3 | # see Documentation/kbuild/kconfig-language.txt. | |
4 | # | |
5 | ||
53f8a252 | 6 | mainmenu "Blackfin Kernel Configuration" |
1394f032 BW |
7 | |
8 | config MMU | |
9 | bool | |
10 | default n | |
11 | ||
12 | config FPU | |
13 | bool | |
14 | default n | |
15 | ||
16 | config RWSEM_GENERIC_SPINLOCK | |
17 | bool | |
18 | default y | |
19 | ||
20 | config RWSEM_XCHGADD_ALGORITHM | |
21 | bool | |
22 | default n | |
23 | ||
24 | config BLACKFIN | |
25 | bool | |
26 | default y | |
27 | ||
e3defffe AL |
28 | config ZONE_DMA |
29 | bool | |
30 | default y | |
31 | ||
1394f032 BW |
32 | config SEMAPHORE_SLEEPERS |
33 | bool | |
34 | default y | |
35 | ||
36 | config GENERIC_FIND_NEXT_BIT | |
37 | bool | |
38 | default y | |
39 | ||
40 | config GENERIC_HWEIGHT | |
41 | bool | |
42 | default y | |
43 | ||
44 | config GENERIC_HARDIRQS | |
45 | bool | |
46 | default y | |
47 | ||
48 | config GENERIC_IRQ_PROBE | |
e4e9a7ad | 49 | bool |
1394f032 BW |
50 | default y |
51 | ||
52 | config GENERIC_TIME | |
53 | bool | |
54 | default n | |
55 | ||
b2d1583f | 56 | config GENERIC_GPIO |
1394f032 BW |
57 | bool |
58 | default y | |
59 | ||
60 | config FORCE_MAX_ZONEORDER | |
61 | int | |
62 | default "14" | |
63 | ||
64 | config GENERIC_CALIBRATE_DELAY | |
65 | bool | |
66 | default y | |
67 | ||
7d2284b0 MD |
68 | config HARDWARE_PM |
69 | def_bool y | |
70 | depends on OPROFILE | |
71 | ||
1394f032 BW |
72 | source "init/Kconfig" |
73 | source "kernel/Kconfig.preempt" | |
74 | ||
75 | menu "Blackfin Processor Options" | |
76 | ||
77 | comment "Processor and Board Settings" | |
78 | ||
79 | choice | |
80 | prompt "CPU" | |
81 | default BF533 | |
82 | ||
59003145 MH |
83 | config BF522 |
84 | bool "BF522" | |
85 | help | |
86 | BF522 Processor Support. | |
87 | ||
1545a111 MF |
88 | config BF523 |
89 | bool "BF523" | |
90 | help | |
91 | BF523 Processor Support. | |
92 | ||
93 | config BF524 | |
94 | bool "BF524" | |
95 | help | |
96 | BF524 Processor Support. | |
97 | ||
59003145 MH |
98 | config BF525 |
99 | bool "BF525" | |
100 | help | |
101 | BF525 Processor Support. | |
102 | ||
1545a111 MF |
103 | config BF526 |
104 | bool "BF526" | |
105 | help | |
106 | BF526 Processor Support. | |
107 | ||
59003145 MH |
108 | config BF527 |
109 | bool "BF527" | |
110 | help | |
111 | BF527 Processor Support. | |
112 | ||
1394f032 BW |
113 | config BF531 |
114 | bool "BF531" | |
115 | help | |
116 | BF531 Processor Support. | |
117 | ||
118 | config BF532 | |
119 | bool "BF532" | |
120 | help | |
121 | BF532 Processor Support. | |
122 | ||
123 | config BF533 | |
124 | bool "BF533" | |
125 | help | |
126 | BF533 Processor Support. | |
127 | ||
128 | config BF534 | |
129 | bool "BF534" | |
130 | help | |
131 | BF534 Processor Support. | |
132 | ||
133 | config BF536 | |
134 | bool "BF536" | |
135 | help | |
136 | BF536 Processor Support. | |
137 | ||
138 | config BF537 | |
139 | bool "BF537" | |
140 | help | |
141 | BF537 Processor Support. | |
142 | ||
24a07a12 RH |
143 | config BF542 |
144 | bool "BF542" | |
145 | help | |
146 | BF542 Processor Support. | |
147 | ||
148 | config BF544 | |
149 | bool "BF544" | |
150 | help | |
151 | BF544 Processor Support. | |
152 | ||
7c7fd170 MF |
153 | config BF547 |
154 | bool "BF547" | |
155 | help | |
156 | BF547 Processor Support. | |
157 | ||
24a07a12 RH |
158 | config BF548 |
159 | bool "BF548" | |
160 | help | |
161 | BF548 Processor Support. | |
162 | ||
163 | config BF549 | |
164 | bool "BF549" | |
165 | help | |
166 | BF549 Processor Support. | |
167 | ||
1394f032 BW |
168 | config BF561 |
169 | bool "BF561" | |
170 | help | |
171 | Not Supported Yet - Work in progress - BF561 Processor Support. | |
172 | ||
173 | endchoice | |
174 | ||
175 | choice | |
176 | prompt "Silicon Rev" | |
59003145 | 177 | default BF_REV_0_1 if BF527 |
1394f032 BW |
178 | default BF_REV_0_2 if BF537 |
179 | default BF_REV_0_3 if BF533 | |
24a07a12 RH |
180 | default BF_REV_0_0 if BF549 |
181 | ||
182 | config BF_REV_0_0 | |
183 | bool "0.0" | |
d07f4380 | 184 | depends on (BF52x || BF54x) |
59003145 MH |
185 | |
186 | config BF_REV_0_1 | |
d07f4380 MF |
187 | bool "0.1" |
188 | depends on (BF52x || BF54x) | |
1394f032 BW |
189 | |
190 | config BF_REV_0_2 | |
191 | bool "0.2" | |
192 | depends on (BF537 || BF536 || BF534) | |
193 | ||
194 | config BF_REV_0_3 | |
195 | bool "0.3" | |
196 | depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) | |
197 | ||
198 | config BF_REV_0_4 | |
199 | bool "0.4" | |
200 | depends on (BF561 || BF533 || BF532 || BF531) | |
201 | ||
202 | config BF_REV_0_5 | |
203 | bool "0.5" | |
204 | depends on (BF561 || BF533 || BF532 || BF531) | |
205 | ||
de3025f4 JZ |
206 | config BF_REV_ANY |
207 | bool "any" | |
208 | ||
209 | config BF_REV_NONE | |
210 | bool "none" | |
211 | ||
1394f032 BW |
212 | endchoice |
213 | ||
59003145 MH |
214 | config BF52x |
215 | bool | |
1545a111 | 216 | depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527) |
59003145 MH |
217 | default y |
218 | ||
24a07a12 RH |
219 | config BF53x |
220 | bool | |
221 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) | |
222 | default y | |
223 | ||
224 | config BF54x | |
225 | bool | |
7c7fd170 | 226 | depends on (BF542 || BF544 || BF547 || BF548 || BF549) |
24a07a12 RH |
227 | default y |
228 | ||
1394f032 BW |
229 | config BFIN_DUAL_CORE |
230 | bool | |
231 | depends on (BF561) | |
232 | default y | |
233 | ||
234 | config BFIN_SINGLE_CORE | |
235 | bool | |
236 | depends on !BFIN_DUAL_CORE | |
237 | default y | |
238 | ||
1394f032 BW |
239 | config MEM_GENERIC_BOARD |
240 | bool | |
241 | depends on GENERIC_BOARD | |
242 | default y | |
243 | ||
244 | config MEM_MT48LC64M4A2FB_7E | |
245 | bool | |
246 | depends on (BFIN533_STAMP) | |
247 | default y | |
248 | ||
249 | config MEM_MT48LC16M16A2TG_75 | |
250 | bool | |
251 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | |
ab472a04 JH |
252 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \ |
253 | || H8606_HVSISTEMAS) | |
1394f032 BW |
254 | default y |
255 | ||
256 | config MEM_MT48LC32M8A2_75 | |
257 | bool | |
258 | depends on (BFIN537_STAMP || PNAV10) | |
259 | default y | |
260 | ||
261 | config MEM_MT48LC8M32B2B5_7 | |
262 | bool | |
263 | depends on (BFIN561_BLUETECHNIX_CM) | |
264 | default y | |
265 | ||
59003145 MH |
266 | config MEM_MT48LC32M16A2TG_75 |
267 | bool | |
268 | depends on (BFIN527_EZKIT) | |
269 | default y | |
270 | ||
59003145 | 271 | source "arch/blackfin/mach-bf527/Kconfig" |
1394f032 BW |
272 | source "arch/blackfin/mach-bf533/Kconfig" |
273 | source "arch/blackfin/mach-bf561/Kconfig" | |
274 | source "arch/blackfin/mach-bf537/Kconfig" | |
24a07a12 | 275 | source "arch/blackfin/mach-bf548/Kconfig" |
1394f032 BW |
276 | |
277 | menu "Board customizations" | |
278 | ||
279 | config CMDLINE_BOOL | |
280 | bool "Default bootloader kernel arguments" | |
281 | ||
282 | config CMDLINE | |
283 | string "Initial kernel command string" | |
284 | depends on CMDLINE_BOOL | |
285 | default "console=ttyBF0,57600" | |
286 | help | |
287 | If you don't have a boot loader capable of passing a command line string | |
288 | to the kernel, you may specify one here. As a minimum, you should specify | |
289 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). | |
290 | ||
f16295e7 | 291 | comment "Clock/PLL Setup" |
1394f032 BW |
292 | |
293 | config CLKIN_HZ | |
294 | int "Crystal Frequency in Hz" | |
295 | default "11059200" if BFIN533_STAMP | |
296 | default "27000000" if BFIN533_EZKIT | |
ab472a04 | 297 | default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS) |
1394f032 BW |
298 | default "30000000" if BFIN561_EZKIT |
299 | default "24576000" if PNAV10 | |
300 | help | |
301 | The frequency of CLKIN crystal oscillator on the board in Hz. | |
302 | ||
f16295e7 RG |
303 | config BFIN_KERNEL_CLOCK |
304 | bool "Re-program Clocks while Kernel boots?" | |
305 | default n | |
306 | help | |
307 | This option decides if kernel clocks are re-programed from the | |
308 | bootloader settings. If the clocks are not set, the SDRAM settings | |
309 | are also not changed, and the Bootloader does 100% of the hardware | |
310 | configuration. | |
311 | ||
312 | config PLL_BYPASS | |
e4e9a7ad MF |
313 | bool "Bypass PLL" |
314 | depends on BFIN_KERNEL_CLOCK | |
315 | default n | |
f16295e7 RG |
316 | |
317 | config CLKIN_HALF | |
318 | bool "Half Clock In" | |
319 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
320 | default n | |
321 | help | |
322 | If this is set the clock will be divided by 2, before it goes to the PLL. | |
323 | ||
324 | config VCO_MULT | |
325 | int "VCO Multiplier" | |
326 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
327 | range 1 64 | |
328 | default "22" if BFIN533_EZKIT | |
329 | default "45" if BFIN533_STAMP | |
971d5bc4 | 330 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT) |
f16295e7 RG |
331 | default "22" if BFIN533_BLUETECHNIX_CM |
332 | default "20" if BFIN537_BLUETECHNIX_CM | |
333 | default "20" if BFIN561_BLUETECHNIX_CM | |
334 | default "20" if BFIN561_EZKIT | |
ab472a04 | 335 | default "16" if H8606_HVSISTEMAS |
f16295e7 RG |
336 | help |
337 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | |
338 | PLL Frequency = (Crystal Frequency) * (this setting) | |
339 | ||
340 | choice | |
341 | prompt "Core Clock Divider" | |
342 | depends on BFIN_KERNEL_CLOCK | |
343 | default CCLK_DIV_1 | |
344 | help | |
345 | This sets the frequency of the core. It can be 1, 2, 4 or 8 | |
346 | Core Frequency = (PLL frequency) / (this setting) | |
347 | ||
348 | config CCLK_DIV_1 | |
349 | bool "1" | |
350 | ||
351 | config CCLK_DIV_2 | |
352 | bool "2" | |
353 | ||
354 | config CCLK_DIV_4 | |
355 | bool "4" | |
356 | ||
357 | config CCLK_DIV_8 | |
358 | bool "8" | |
359 | endchoice | |
360 | ||
361 | config SCLK_DIV | |
362 | int "System Clock Divider" | |
363 | depends on BFIN_KERNEL_CLOCK | |
364 | range 1 15 | |
365 | default 5 if BFIN533_EZKIT | |
366 | default 5 if BFIN533_STAMP | |
971d5bc4 | 367 | default 4 if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT) |
f16295e7 RG |
368 | default 5 if BFIN533_BLUETECHNIX_CM |
369 | default 4 if BFIN537_BLUETECHNIX_CM | |
370 | default 4 if BFIN561_BLUETECHNIX_CM | |
371 | default 5 if BFIN561_EZKIT | |
ab472a04 | 372 | default 3 if H8606_HVSISTEMAS |
f16295e7 RG |
373 | help |
374 | This sets the frequency of the system clock (including SDRAM or DDR). | |
375 | This can be between 1 and 15 | |
376 | System Clock = (PLL frequency) / (this setting) | |
377 | ||
378 | # | |
379 | # Max & Min Speeds for various Chips | |
380 | # | |
381 | config MAX_VCO_HZ | |
382 | int | |
383 | default 600000000 if BF522 | |
1545a111 MF |
384 | default 400000000 if BF523 |
385 | default 400000000 if BF524 | |
f16295e7 | 386 | default 600000000 if BF525 |
1545a111 | 387 | default 400000000 if BF526 |
f16295e7 RG |
388 | default 600000000 if BF527 |
389 | default 400000000 if BF531 | |
390 | default 400000000 if BF532 | |
391 | default 750000000 if BF533 | |
392 | default 500000000 if BF534 | |
393 | default 400000000 if BF536 | |
394 | default 600000000 if BF537 | |
f72eecb9 RG |
395 | default 533333333 if BF538 |
396 | default 533333333 if BF539 | |
f16295e7 | 397 | default 600000000 if BF542 |
f72eecb9 | 398 | default 533333333 if BF544 |
1545a111 MF |
399 | default 600000000 if BF547 |
400 | default 600000000 if BF548 | |
f72eecb9 | 401 | default 533333333 if BF549 |
f16295e7 RG |
402 | default 600000000 if BF561 |
403 | ||
404 | config MIN_VCO_HZ | |
405 | int | |
406 | default 50000000 | |
407 | ||
408 | config MAX_SCLK_HZ | |
409 | int | |
f72eecb9 | 410 | default 133333333 |
f16295e7 RG |
411 | |
412 | config MIN_SCLK_HZ | |
413 | int | |
414 | default 27000000 | |
415 | ||
416 | comment "Kernel Timer/Scheduler" | |
417 | ||
418 | source kernel/Kconfig.hz | |
419 | ||
420 | comment "Memory Setup" | |
421 | ||
1394f032 BW |
422 | config MEM_SIZE |
423 | int "SDRAM Memory Size in MBytes" | |
424 | default 32 if BFIN533_EZKIT | |
59003145 | 425 | default 64 if BFIN527_EZKIT |
1394f032 | 426 | default 64 if BFIN537_STAMP |
971d5bc4 | 427 | default 64 if BFIN548_EZKIT |
1394f032 BW |
428 | default 64 if BFIN561_EZKIT |
429 | default 128 if BFIN533_STAMP | |
430 | default 64 if PNAV10 | |
ab472a04 | 431 | default 32 if H8606_HVSISTEMAS |
1394f032 BW |
432 | |
433 | config MEM_ADD_WIDTH | |
434 | int "SDRAM Memory Address Width" | |
971d5bc4 | 435 | depends on (!BF54x) |
1394f032 BW |
436 | default 9 if BFIN533_EZKIT |
437 | default 9 if BFIN561_EZKIT | |
ab472a04 | 438 | default 9 if H8606_HVSISTEMAS |
59003145 | 439 | default 10 if BFIN527_EZKIT |
1394f032 BW |
440 | default 10 if BFIN537_STAMP |
441 | default 11 if BFIN533_STAMP | |
442 | default 10 if PNAV10 | |
443 | ||
971d5bc4 SZ |
444 | |
445 | choice | |
446 | prompt "DDR SDRAM Chip Type" | |
447 | depends on BFIN548_EZKIT | |
448 | default MEM_MT46V32M16_5B | |
449 | ||
450 | config MEM_MT46V32M16_6T | |
451 | bool "MT46V32M16_6T" | |
452 | ||
453 | config MEM_MT46V32M16_5B | |
454 | bool "MT46V32M16_5B" | |
455 | endchoice | |
456 | ||
1394f032 BW |
457 | config ENET_FLASH_PIN |
458 | int "PF port/pin used for flash and ethernet sharing" | |
459 | depends on (BFIN533_STAMP) | |
460 | default 0 | |
461 | help | |
462 | PF port/pin used for flash and ethernet sharing to allow other PF | |
463 | pins to be used on other platforms without having to touch common | |
464 | code. | |
465 | For example: PF0 --> 0,PF1 --> 1,PF2 --> 2, etc. | |
466 | ||
467 | config BOOT_LOAD | |
468 | hex "Kernel load address for booting" | |
469 | default "0x1000" | |
2d8f161f | 470 | range 0x1000 0x20000000 |
1394f032 BW |
471 | help |
472 | This option allows you to set the load address of the kernel. | |
473 | This can be useful if you are on a board which has a small amount | |
474 | of memory or you wish to reserve some memory at the beginning of | |
475 | the address space. | |
476 | ||
2d8f161f MF |
477 | Note that you need to keep this value above 4k (0x1000) as this |
478 | memory region is used to capture NULL pointer references as well | |
479 | as some core kernel functions. | |
1394f032 | 480 | |
f0b5d12f MF |
481 | choice |
482 | prompt "Blackfin Exception Scratch Register" | |
483 | default BFIN_SCRATCH_REG_RETN | |
484 | help | |
485 | Select the resource to reserve for the Exception handler: | |
486 | - RETN: Non-Maskable Interrupt (NMI) | |
487 | - RETE: Exception Return (JTAG/ICE) | |
488 | - CYCLES: Performance counter | |
489 | ||
490 | If you are unsure, please select "RETN". | |
491 | ||
492 | config BFIN_SCRATCH_REG_RETN | |
493 | bool "RETN" | |
494 | help | |
495 | Use the RETN register in the Blackfin exception handler | |
496 | as a stack scratch register. This means you cannot | |
497 | safely use NMI on the Blackfin while running Linux, but | |
498 | you can debug the system with a JTAG ICE and use the | |
499 | CYCLES performance registers. | |
500 | ||
501 | If you are unsure, please select "RETN". | |
502 | ||
503 | config BFIN_SCRATCH_REG_RETE | |
504 | bool "RETE" | |
505 | help | |
506 | Use the RETE register in the Blackfin exception handler | |
507 | as a stack scratch register. This means you cannot | |
508 | safely use a JTAG ICE while debugging a Blackfin board, | |
509 | but you can safely use the CYCLES performance registers | |
510 | and the NMI. | |
511 | ||
512 | If you are unsure, please select "RETN". | |
513 | ||
514 | config BFIN_SCRATCH_REG_CYCLES | |
515 | bool "CYCLES" | |
516 | help | |
517 | Use the CYCLES register in the Blackfin exception handler | |
518 | as a stack scratch register. This means you cannot | |
519 | safely use the CYCLES performance registers on a Blackfin | |
520 | board at anytime, but you can debug the system with a JTAG | |
521 | ICE and use the NMI. | |
522 | ||
523 | If you are unsure, please select "RETN". | |
524 | ||
525 | endchoice | |
526 | ||
1394f032 BW |
527 | endmenu |
528 | ||
529 | ||
530 | menu "Blackfin Kernel Optimizations" | |
531 | ||
1394f032 BW |
532 | comment "Memory Optimizations" |
533 | ||
534 | config I_ENTRY_L1 | |
535 | bool "Locate interrupt entry code in L1 Memory" | |
536 | default y | |
537 | help | |
01dd2fbf ML |
538 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
539 | into L1 instruction memory. (less latency) | |
1394f032 BW |
540 | |
541 | config EXCPT_IRQ_SYSC_L1 | |
01dd2fbf | 542 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
1394f032 BW |
543 | default y |
544 | help | |
01dd2fbf ML |
545 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
546 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. | |
547 | (less latency) | |
1394f032 BW |
548 | |
549 | config DO_IRQ_L1 | |
550 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | |
551 | default y | |
552 | help | |
01dd2fbf ML |
553 | If enabled, the frequently called do_irq dispatcher function is linked |
554 | into L1 instruction memory. (less latency) | |
1394f032 BW |
555 | |
556 | config CORE_TIMER_IRQ_L1 | |
557 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | |
558 | default y | |
559 | help | |
01dd2fbf ML |
560 | If enabled, the frequently called timer_interrupt() function is linked |
561 | into L1 instruction memory. (less latency) | |
1394f032 BW |
562 | |
563 | config IDLE_L1 | |
564 | bool "Locate frequently idle function in L1 Memory" | |
565 | default y | |
566 | help | |
01dd2fbf ML |
567 | If enabled, the frequently called idle function is linked |
568 | into L1 instruction memory. (less latency) | |
1394f032 BW |
569 | |
570 | config SCHEDULE_L1 | |
571 | bool "Locate kernel schedule function in L1 Memory" | |
572 | default y | |
573 | help | |
01dd2fbf ML |
574 | If enabled, the frequently called kernel schedule is linked |
575 | into L1 instruction memory. (less latency) | |
1394f032 BW |
576 | |
577 | config ARITHMETIC_OPS_L1 | |
578 | bool "Locate kernel owned arithmetic functions in L1 Memory" | |
579 | default y | |
580 | help | |
01dd2fbf ML |
581 | If enabled, arithmetic functions are linked |
582 | into L1 instruction memory. (less latency) | |
1394f032 BW |
583 | |
584 | config ACCESS_OK_L1 | |
585 | bool "Locate access_ok function in L1 Memory" | |
586 | default y | |
587 | help | |
01dd2fbf ML |
588 | If enabled, the access_ok function is linked |
589 | into L1 instruction memory. (less latency) | |
1394f032 BW |
590 | |
591 | config MEMSET_L1 | |
592 | bool "Locate memset function in L1 Memory" | |
593 | default y | |
594 | help | |
01dd2fbf ML |
595 | If enabled, the memset function is linked |
596 | into L1 instruction memory. (less latency) | |
1394f032 BW |
597 | |
598 | config MEMCPY_L1 | |
599 | bool "Locate memcpy function in L1 Memory" | |
600 | default y | |
601 | help | |
01dd2fbf ML |
602 | If enabled, the memcpy function is linked |
603 | into L1 instruction memory. (less latency) | |
1394f032 BW |
604 | |
605 | config SYS_BFIN_SPINLOCK_L1 | |
606 | bool "Locate sys_bfin_spinlock function in L1 Memory" | |
607 | default y | |
608 | help | |
01dd2fbf ML |
609 | If enabled, sys_bfin_spinlock function is linked |
610 | into L1 instruction memory. (less latency) | |
1394f032 BW |
611 | |
612 | config IP_CHECKSUM_L1 | |
613 | bool "Locate IP Checksum function in L1 Memory" | |
614 | default n | |
615 | help | |
01dd2fbf ML |
616 | If enabled, the IP Checksum function is linked |
617 | into L1 instruction memory. (less latency) | |
1394f032 BW |
618 | |
619 | config CACHELINE_ALIGNED_L1 | |
620 | bool "Locate cacheline_aligned data to L1 Data Memory" | |
157cc5aa MH |
621 | default y if !BF54x |
622 | default n if BF54x | |
1394f032 BW |
623 | depends on !BF531 |
624 | help | |
01dd2fbf ML |
625 | If enabled, cacheline_anligned data is linked |
626 | into L1 data memory. (less latency) | |
1394f032 BW |
627 | |
628 | config SYSCALL_TAB_L1 | |
629 | bool "Locate Syscall Table L1 Data Memory" | |
630 | default n | |
631 | depends on !BF531 | |
632 | help | |
01dd2fbf ML |
633 | If enabled, the Syscall LUT is linked |
634 | into L1 data memory. (less latency) | |
1394f032 BW |
635 | |
636 | config CPLB_SWITCH_TAB_L1 | |
637 | bool "Locate CPLB Switch Tables L1 Data Memory" | |
638 | default n | |
639 | depends on !BF531 | |
640 | help | |
01dd2fbf ML |
641 | If enabled, the CPLB Switch Tables are linked |
642 | into L1 data memory. (less latency) | |
1394f032 BW |
643 | |
644 | endmenu | |
645 | ||
646 | ||
647 | choice | |
648 | prompt "Kernel executes from" | |
649 | help | |
650 | Choose the memory type that the kernel will be running in. | |
651 | ||
652 | config RAMKERNEL | |
653 | bool "RAM" | |
654 | help | |
655 | The kernel will be resident in RAM when running. | |
656 | ||
657 | config ROMKERNEL | |
658 | bool "ROM" | |
659 | help | |
660 | The kernel will be resident in FLASH/ROM when running. | |
661 | ||
662 | endchoice | |
663 | ||
664 | source "mm/Kconfig" | |
665 | ||
db0fa206 BW |
666 | config LARGE_ALLOCS |
667 | bool "Allow allocating large blocks (> 1MB) of memory" | |
668 | help | |
669 | Allow the slab memory allocator to keep chains for very large | |
670 | memory sizes - upto 32MB. You may need this if your system has | |
671 | a lot of RAM, and you need to able to allocate very large | |
672 | contiguous chunks. If unsure, say N. | |
673 | ||
780431e3 MF |
674 | config BFIN_GPTIMERS |
675 | tristate "Enable Blackfin General Purpose Timers API" | |
676 | default n | |
677 | help | |
678 | Enable support for the General Purpose Timers API. If you | |
679 | are unsure, say N. | |
680 | ||
681 | To compile this driver as a module, choose M here: the module | |
682 | will be called gptimers.ko. | |
683 | ||
1394f032 BW |
684 | config BFIN_DMA_5XX |
685 | bool "Enable DMA Support" | |
59003145 | 686 | depends on (BF52x || BF53x || BF561 || BF54x) |
1394f032 BW |
687 | default y |
688 | help | |
689 | DMA driver for BF5xx. | |
690 | ||
691 | choice | |
692 | prompt "Uncached SDRAM region" | |
693 | default DMA_UNCACHED_1M | |
247537b9 | 694 | depends on BFIN_DMA_5XX |
1394f032 BW |
695 | config DMA_UNCACHED_2M |
696 | bool "Enable 2M DMA region" | |
697 | config DMA_UNCACHED_1M | |
698 | bool "Enable 1M DMA region" | |
699 | config DMA_UNCACHED_NONE | |
700 | bool "Disable DMA region" | |
701 | endchoice | |
702 | ||
703 | ||
704 | comment "Cache Support" | |
3bebca2d | 705 | config BFIN_ICACHE |
1394f032 | 706 | bool "Enable ICACHE" |
3bebca2d | 707 | config BFIN_DCACHE |
1394f032 | 708 | bool "Enable DCACHE" |
3bebca2d | 709 | config BFIN_DCACHE_BANKA |
1394f032 | 710 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
3bebca2d | 711 | depends on BFIN_DCACHE && !BF531 |
1394f032 | 712 | default n |
3bebca2d RG |
713 | config BFIN_ICACHE_LOCK |
714 | bool "Enable Instruction Cache Locking" | |
1394f032 BW |
715 | |
716 | choice | |
717 | prompt "Policy" | |
3bebca2d RG |
718 | depends on BFIN_DCACHE |
719 | default BFIN_WB | |
720 | config BFIN_WB | |
1394f032 BW |
721 | bool "Write back" |
722 | help | |
723 | Write Back Policy: | |
724 | Cached data will be written back to SDRAM only when needed. | |
725 | This can give a nice increase in performance, but beware of | |
726 | broken drivers that do not properly invalidate/flush their | |
727 | cache. | |
728 | ||
729 | Write Through Policy: | |
730 | Cached data will always be written back to SDRAM when the | |
731 | cache is updated. This is a completely safe setting, but | |
732 | performance is worse than Write Back. | |
733 | ||
734 | If you are unsure of the options and you want to be safe, | |
735 | then go with Write Through. | |
736 | ||
3bebca2d | 737 | config BFIN_WT |
1394f032 BW |
738 | bool "Write through" |
739 | help | |
740 | Write Back Policy: | |
741 | Cached data will be written back to SDRAM only when needed. | |
742 | This can give a nice increase in performance, but beware of | |
743 | broken drivers that do not properly invalidate/flush their | |
744 | cache. | |
745 | ||
746 | Write Through Policy: | |
747 | Cached data will always be written back to SDRAM when the | |
748 | cache is updated. This is a completely safe setting, but | |
749 | performance is worse than Write Back. | |
750 | ||
751 | If you are unsure of the options and you want to be safe, | |
752 | then go with Write Through. | |
753 | ||
754 | endchoice | |
755 | ||
756 | config L1_MAX_PIECE | |
757 | int "Set the max L1 SRAM pieces" | |
758 | default 16 | |
759 | help | |
760 | Set the max memory pieces for the L1 SRAM allocation algorithm. | |
761 | Min value is 16. Max value is 1024. | |
762 | ||
b97b8a99 BS |
763 | |
764 | config MPU | |
765 | bool "Enable the memory protection unit (EXPERIMENTAL)" | |
766 | default n | |
767 | help | |
768 | Use the processor's MPU to protect applications from accessing | |
769 | memory they do not own. This comes at a performance penalty | |
770 | and is recommended only for debugging. | |
771 | ||
1394f032 BW |
772 | comment "Asynchonous Memory Configuration" |
773 | ||
ddf416b2 | 774 | menu "EBIU_AMGCTL Global Control" |
1394f032 BW |
775 | config C_AMCKEN |
776 | bool "Enable CLKOUT" | |
777 | default y | |
778 | ||
779 | config C_CDPRIO | |
780 | bool "DMA has priority over core for ext. accesses" | |
781 | default n | |
782 | ||
783 | config C_B0PEN | |
784 | depends on BF561 | |
785 | bool "Bank 0 16 bit packing enable" | |
786 | default y | |
787 | ||
788 | config C_B1PEN | |
789 | depends on BF561 | |
790 | bool "Bank 1 16 bit packing enable" | |
791 | default y | |
792 | ||
793 | config C_B2PEN | |
794 | depends on BF561 | |
795 | bool "Bank 2 16 bit packing enable" | |
796 | default y | |
797 | ||
798 | config C_B3PEN | |
799 | depends on BF561 | |
800 | bool "Bank 3 16 bit packing enable" | |
801 | default n | |
802 | ||
803 | choice | |
804 | prompt"Enable Asynchonous Memory Banks" | |
805 | default C_AMBEN_ALL | |
806 | ||
807 | config C_AMBEN | |
808 | bool "Disable All Banks" | |
809 | ||
810 | config C_AMBEN_B0 | |
811 | bool "Enable Bank 0" | |
812 | ||
813 | config C_AMBEN_B0_B1 | |
814 | bool "Enable Bank 0 & 1" | |
815 | ||
816 | config C_AMBEN_B0_B1_B2 | |
817 | bool "Enable Bank 0 & 1 & 2" | |
818 | ||
819 | config C_AMBEN_ALL | |
820 | bool "Enable All Banks" | |
821 | endchoice | |
822 | endmenu | |
823 | ||
824 | menu "EBIU_AMBCTL Control" | |
825 | config BANK_0 | |
826 | hex "Bank 0" | |
827 | default 0x7BB0 | |
828 | ||
829 | config BANK_1 | |
830 | hex "Bank 1" | |
831 | default 0x7BB0 | |
832 | ||
833 | config BANK_2 | |
834 | hex "Bank 2" | |
835 | default 0x7BB0 | |
836 | ||
837 | config BANK_3 | |
838 | hex "Bank 3" | |
839 | default 0x99B3 | |
840 | endmenu | |
841 | ||
e40540b3 SZ |
842 | config EBIU_MBSCTLVAL |
843 | hex "EBIU Bank Select Control Register" | |
844 | depends on BF54x | |
845 | default 0 | |
846 | ||
847 | config EBIU_MODEVAL | |
848 | hex "Flash Memory Mode Control Register" | |
849 | depends on BF54x | |
850 | default 1 | |
851 | ||
852 | config EBIU_FCTLVAL | |
853 | hex "Flash Memory Bank Control Register" | |
854 | depends on BF54x | |
855 | default 6 | |
1394f032 BW |
856 | endmenu |
857 | ||
858 | ############################################################################# | |
859 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" | |
860 | ||
861 | config PCI | |
862 | bool "PCI support" | |
863 | help | |
864 | Support for PCI bus. | |
865 | ||
866 | source "drivers/pci/Kconfig" | |
867 | ||
868 | config HOTPLUG | |
869 | bool "Support for hot-pluggable device" | |
870 | help | |
871 | Say Y here if you want to plug devices into your computer while | |
872 | the system is running, and be able to use them quickly. In many | |
873 | cases, the devices can likewise be unplugged at any time too. | |
874 | ||
875 | One well known example of this is PCMCIA- or PC-cards, credit-card | |
876 | size devices such as network cards, modems or hard drives which are | |
877 | plugged into slots found on all modern laptop computers. Another | |
878 | example, used on modern desktops as well as laptops, is USB. | |
879 | ||
880 | Enable HOTPLUG and KMOD, and build a modular kernel. Get agent | |
881 | software (at <http://linux-hotplug.sourceforge.net/>) and install it. | |
882 | Then your kernel will automatically call out to a user mode "policy | |
883 | agent" (/sbin/hotplug) to load modules and set up software needed | |
884 | to use devices as you hotplug them. | |
885 | ||
886 | source "drivers/pcmcia/Kconfig" | |
887 | ||
888 | source "drivers/pci/hotplug/Kconfig" | |
889 | ||
890 | endmenu | |
891 | ||
892 | menu "Executable file formats" | |
893 | ||
894 | source "fs/Kconfig.binfmt" | |
895 | ||
896 | endmenu | |
897 | ||
898 | menu "Power management options" | |
899 | source "kernel/power/Kconfig" | |
900 | ||
f4cb5700 JB |
901 | config ARCH_SUSPEND_POSSIBLE |
902 | def_bool y | |
903 | depends on !SMP | |
904 | ||
1394f032 BW |
905 | choice |
906 | prompt "Select PM Wakeup Event Source" | |
907 | default PM_WAKEUP_GPIO_BY_SIC_IWR | |
908 | depends on PM | |
909 | help | |
910 | If you have a GPIO already configured as input with the corresponding PORTx_MASK | |
911 | bit set - "Specify Wakeup Event by SIC_IWR value" | |
912 | ||
913 | config PM_WAKEUP_GPIO_BY_SIC_IWR | |
914 | bool "Specify Wakeup Event by SIC_IWR value" | |
915 | config PM_WAKEUP_BY_GPIO | |
916 | bool "Cause Wakeup Event by GPIO" | |
917 | config PM_WAKEUP_GPIO_API | |
918 | bool "Configure Wakeup Event by PM GPIO API" | |
919 | ||
920 | endchoice | |
921 | ||
922 | config PM_WAKEUP_SIC_IWR | |
923 | hex "Wakeup Events (SIC_IWR)" | |
924 | depends on PM_WAKEUP_GPIO_BY_SIC_IWR | |
03c57328 SZ |
925 | default 0x8 if (BF537 || BF536 || BF534) |
926 | default 0x80 if (BF533 || BF532 || BF531) | |
927 | default 0x80 if (BF54x) | |
928 | default 0x80 if (BF52x) | |
1394f032 BW |
929 | |
930 | config PM_WAKEUP_GPIO_NUMBER | |
931 | int "Wakeup GPIO number" | |
932 | range 0 47 | |
933 | depends on PM_WAKEUP_BY_GPIO | |
934 | default 2 if BFIN537_STAMP | |
935 | ||
936 | choice | |
937 | prompt "GPIO Polarity" | |
938 | depends on PM_WAKEUP_BY_GPIO | |
939 | default PM_WAKEUP_GPIO_POLAR_H | |
940 | config PM_WAKEUP_GPIO_POLAR_H | |
941 | bool "Active High" | |
942 | config PM_WAKEUP_GPIO_POLAR_L | |
943 | bool "Active Low" | |
944 | config PM_WAKEUP_GPIO_POLAR_EDGE_F | |
945 | bool "Falling EDGE" | |
946 | config PM_WAKEUP_GPIO_POLAR_EDGE_R | |
947 | bool "Rising EDGE" | |
948 | config PM_WAKEUP_GPIO_POLAR_EDGE_B | |
949 | bool "Both EDGE" | |
950 | endchoice | |
951 | ||
952 | endmenu | |
953 | ||
24a07a12 | 954 | if (BF537 || BF533 || BF54x) |
1394f032 BW |
955 | |
956 | menu "CPU Frequency scaling" | |
957 | ||
958 | source "drivers/cpufreq/Kconfig" | |
959 | ||
960 | config CPU_FREQ | |
961 | bool | |
962 | default n | |
963 | help | |
964 | If you want to enable this option, you should select the | |
965 | DPMC driver from Character Devices. | |
966 | endmenu | |
967 | ||
968 | endif | |
969 | ||
970 | source "net/Kconfig" | |
971 | ||
972 | source "drivers/Kconfig" | |
973 | ||
974 | source "fs/Kconfig" | |
975 | ||
09cadedb | 976 | source "kernel/Kconfig.instrumentation" |
1394f032 | 977 | |
74ce8322 | 978 | source "arch/blackfin/Kconfig.debug" |
1394f032 BW |
979 | |
980 | source "security/Kconfig" | |
981 | ||
982 | source "crypto/Kconfig" | |
983 | ||
984 | source "lib/Kconfig" |