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[mirror_ubuntu-artful-kernel.git] / arch / blackfin / kernel / bfin_gpio.c
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1394f032
BW		 1/*
2 * File: arch/blackfin/kernel/bfin_gpio.c
3 * Based on:
4 * Author: Michael Hennerich (hennerich@blackfin.uclinux.org)
5 *
6 * Created:
7 * Description: GPIO Abstraction Layer
8 *
9 * Modified:
a2c8cfef 10 * Copyright 2008 Analog Devices Inc.
1394f032
BW		 11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
168f1212 30#include <linux/delay.h>
1394f032
BW		 31#include <linux/module.h>
32#include <linux/err.h>
1545a111 33#include <linux/proc_fs.h>
1394f032
BW		 34#include <asm/blackfin.h>
35#include <asm/gpio.h>
c58c2140 36#include <asm/portmux.h>
1394f032
BW		 37#include <linux/irq.h>
38
2b39331a
MH		 39#if ANOMALY_05000311 || ANOMALY_05000323
40enum {
41 AWA_data = SYSCR,
42 AWA_data_clear = SYSCR,
43 AWA_data_set = SYSCR,
44 AWA_toggle = SYSCR,
6ed83942
GY		 45 AWA_maska = BFIN_UART_SCR,
46 AWA_maska_clear = BFIN_UART_SCR,
47 AWA_maska_set = BFIN_UART_SCR,
48 AWA_maska_toggle = BFIN_UART_SCR,
49 AWA_maskb = BFIN_UART_GCTL,
50 AWA_maskb_clear = BFIN_UART_GCTL,
51 AWA_maskb_set = BFIN_UART_GCTL,
52 AWA_maskb_toggle = BFIN_UART_GCTL,
2b39331a
MH		 53 AWA_dir = SPORT1_STAT,
54 AWA_polar = SPORT1_STAT,
55 AWA_edge = SPORT1_STAT,
56 AWA_both = SPORT1_STAT,
57#if ANOMALY_05000311
58 AWA_inen = TIMER_ENABLE,
59#elif ANOMALY_05000323
60 AWA_inen = DMA1_1_CONFIG,
61#endif
62};
63 /* Anomaly Workaround */
64#define AWA_DUMMY_READ(name) bfin_read16(AWA_ ## name)
65#else
66#define AWA_DUMMY_READ(...) do { } while (0)
67#endif
68
f556309e 69static struct gpio_port_t * const gpio_array[] = {
dc26aec2 70#if defined(BF533_FAMILY) || defined(BF538_FAMILY)
1394f032 71 (struct gpio_port_t *) FIO_FLAG_D,
f556309e 72#elif defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
1394f032
BW		 73 (struct gpio_port_t *) PORTFIO,
74 (struct gpio_port_t *) PORTGIO,
75 (struct gpio_port_t *) PORTHIO,
f556309e
MF		 76#elif defined(BF561_FAMILY)
77 (struct gpio_port_t *) FIO0_FLAG_D,
78 (struct gpio_port_t *) FIO1_FLAG_D,
79 (struct gpio_port_t *) FIO2_FLAG_D,
80#elif defined(BF548_FAMILY)
81 (struct gpio_port_t *)PORTA_FER,
82 (struct gpio_port_t *)PORTB_FER,
83 (struct gpio_port_t *)PORTC_FER,
84 (struct gpio_port_t *)PORTD_FER,
85 (struct gpio_port_t *)PORTE_FER,
86 (struct gpio_port_t *)PORTF_FER,
87 (struct gpio_port_t *)PORTG_FER,
88 (struct gpio_port_t *)PORTH_FER,
89 (struct gpio_port_t *)PORTI_FER,
90 (struct gpio_port_t *)PORTJ_FER,
91#else
92# error no gpio arrays defined
93#endif
1394f032
BW		 94};
95
f556309e
MF		 96#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
97static unsigned short * const port_fer[] = {
1394f032
BW		 98 (unsigned short *) PORTF_FER,
99 (unsigned short *) PORTG_FER,
100 (unsigned short *) PORTH_FER,
101};
1394f032 102
f556309e
MF		 103# if !defined(BF537_FAMILY)
104static unsigned short * const port_mux[] = {
59003145
MH		 105 (unsigned short *) PORTF_MUX,
106 (unsigned short *) PORTG_MUX,
107 (unsigned short *) PORTH_MUX,
108};
109
110static const
111u8 pmux_offset[][16] =
112 {{ 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 4, 6, 8, 8, 10, 10 }, /* PORTF */
113 { 0, 0, 0, 0, 0, 2, 2, 4, 4, 6, 8, 10, 10, 10, 12, 12 }, /* PORTG */
114 { 0, 0, 0, 0, 0, 0, 0, 0, 2, 4, 4, 4, 4, 4, 4, 4 }, /* PORTH */
115 };
f556309e 116# endif
d2b11a46
MH		 117#endif
118
397861cd 119static unsigned short reserved_gpio_map[GPIO_BANK_NUM];
fac3cf43 120static unsigned short reserved_peri_map[gpio_bank(MAX_RESOURCES)];
9570ff4a 121static unsigned short reserved_gpio_irq_map[GPIO_BANK_NUM];
c58c2140 122
8c613623
MH		 123#define RESOURCE_LABEL_SIZE 16
124
fac3cf43 125static struct str_ident {
8c613623 126 char name[RESOURCE_LABEL_SIZE];
fac3cf43 127} str_ident[MAX_RESOURCES];
1394f032 128
1efc80b5 129#if defined(CONFIG_PM)
397861cd 130static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM];
59003145
MH		 131#endif
132
a2c8cfef 133inline int check_gpio(unsigned gpio)
d2b11a46 134{
27228b2e 135#if defined(BF548_FAMILY)
d2b11a46
MH		 136 if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
137 || gpio == GPIO_PH14 || gpio == GPIO_PH15
27228b2e 138 || gpio == GPIO_PJ14 || gpio == GPIO_PJ15)
d2b11a46 139 return -EINVAL;
27228b2e 140#endif
e7613aab 141 if (gpio >= MAX_BLACKFIN_GPIOS)
1394f032
BW		 142 return -EINVAL;
143 return 0;
144}
145
74c04503 146static void gpio_error(unsigned gpio)
acbcd263
MH		 147{
148 printk(KERN_ERR "bfin-gpio: GPIO %d wasn't requested!\n", gpio);
149}
150
c58c2140
MH		 151static void set_label(unsigned short ident, const char *label)
152{
e9fae189 153 if (label) {
8c613623 154 strncpy(str_ident[ident].name, label,
c58c2140 155 RESOURCE_LABEL_SIZE);
8c613623 156 str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0;
c58c2140
MH		 157 }
158}
159
160static char *get_label(unsigned short ident)
161{
8c613623 162 return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN");
c58c2140
MH		 163}
164
165static int cmp_label(unsigned short ident, const char *label)
166{
fac3cf43
MH		 167 if (label == NULL) {
168 dump_stack();
169 printk(KERN_ERR "Please provide none-null label\n");
170 }
171
e9fae189 172 if (label)
1f7d373f 173 return strcmp(str_ident[ident].name, label);
c58c2140
MH		 174 else
175 return -EINVAL;
176}
177
a2c8cfef 178static void port_setup(unsigned gpio, unsigned short usage)
1394f032 179{
a2d03a1d
MF		 180 if (check_gpio(gpio))
181 return;
182
183#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
184 if (usage == GPIO_USAGE)
185 *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
186 else
187 *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
188 SSYNC();
d2b11a46 189#elif defined(BF548_FAMILY)
d2b11a46
MH		 190 if (usage == GPIO_USAGE)
191 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
192 else
193 gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
194 SSYNC();
1394f032 195#endif
a2d03a1d 196}
1394f032 197
c58c2140 198#ifdef BF537_FAMILY
8c613623
MH		 199static struct {
200 unsigned short res;
201 unsigned short offset;
202} port_mux_lut[] = {
203 {.res = P_PPI0_D13, .offset = 11},
204 {.res = P_PPI0_D14, .offset = 11},
205 {.res = P_PPI0_D15, .offset = 11},
206 {.res = P_SPORT1_TFS, .offset = 11},
207 {.res = P_SPORT1_TSCLK, .offset = 11},
208 {.res = P_SPORT1_DTPRI, .offset = 11},
209 {.res = P_PPI0_D10, .offset = 10},
210 {.res = P_PPI0_D11, .offset = 10},
211 {.res = P_PPI0_D12, .offset = 10},
212 {.res = P_SPORT1_RSCLK, .offset = 10},
213 {.res = P_SPORT1_RFS, .offset = 10},
214 {.res = P_SPORT1_DRPRI, .offset = 10},
215 {.res = P_PPI0_D8, .offset = 9},
216 {.res = P_PPI0_D9, .offset = 9},
217 {.res = P_SPORT1_DRSEC, .offset = 9},
218 {.res = P_SPORT1_DTSEC, .offset = 9},
219 {.res = P_TMR2, .offset = 8},
220 {.res = P_PPI0_FS3, .offset = 8},
221 {.res = P_TMR3, .offset = 7},
222 {.res = P_SPI0_SSEL4, .offset = 7},
223 {.res = P_TMR4, .offset = 6},
224 {.res = P_SPI0_SSEL5, .offset = 6},
225 {.res = P_TMR5, .offset = 5},
226 {.res = P_SPI0_SSEL6, .offset = 5},
227 {.res = P_UART1_RX, .offset = 4},
228 {.res = P_UART1_TX, .offset = 4},
229 {.res = P_TMR6, .offset = 4},
230 {.res = P_TMR7, .offset = 4},
231 {.res = P_UART0_RX, .offset = 3},
232 {.res = P_UART0_TX, .offset = 3},
233 {.res = P_DMAR0, .offset = 3},
234 {.res = P_DMAR1, .offset = 3},
235 {.res = P_SPORT0_DTSEC, .offset = 1},
236 {.res = P_SPORT0_DRSEC, .offset = 1},
237 {.res = P_CAN0_RX, .offset = 1},
238 {.res = P_CAN0_TX, .offset = 1},
239 {.res = P_SPI0_SSEL7, .offset = 1},
240 {.res = P_SPORT0_TFS, .offset = 0},
241 {.res = P_SPORT0_DTPRI, .offset = 0},
242 {.res = P_SPI0_SSEL2, .offset = 0},
243 {.res = P_SPI0_SSEL3, .offset = 0},
c58c2140
MH		 244};
245
f556309e 246static void portmux_setup(unsigned short per)
c58c2140 247{
8c613623 248 u16 y, offset, muxreg;
f556309e 249 u16 function = P_FUNCT2MUX(per);
c58c2140 250
8c613623
MH		 251 for (y = 0; y < ARRAY_SIZE(port_mux_lut); y++) {
252 if (port_mux_lut[y].res == per) {
c58c2140
MH		 253
254 /* SET PORTMUX REG */
255
8c613623 256 offset = port_mux_lut[y].offset;
c58c2140
MH		 257 muxreg = bfin_read_PORT_MUX();
258
d171c233 259 if (offset != 1)
c58c2140 260 muxreg &= ~(1 << offset);
d171c233 261 else
c58c2140 262 muxreg &= ~(3 << 1);
c58c2140
MH		 263
264 muxreg |= (function << offset);
265 bfin_write_PORT_MUX(muxreg);
266 }
267 }
268}
d2b11a46 269#elif defined(BF548_FAMILY)
f556309e 270inline void portmux_setup(unsigned short per)
d2b11a46
MH		 271{
272 u32 pmux;
f556309e
MF		 273 u16 ident = P_IDENT(per);
274 u16 function = P_FUNCT2MUX(per);
d2b11a46 275
f556309e 276 pmux = gpio_array[gpio_bank(ident)]->port_mux;
d2b11a46 277
f556309e
MF		 278 pmux &= ~(0x3 << (2 * gpio_sub_n(ident)));
279 pmux |= (function & 0x3) << (2 * gpio_sub_n(ident));
d2b11a46 280
f556309e 281 gpio_array[gpio_bank(ident)]->port_mux = pmux;
d2b11a46
MH		 282}
283
f556309e 284inline u16 get_portmux(unsigned short per)
d2b11a46
MH		 285{
286 u32 pmux;
f556309e 287 u16 ident = P_IDENT(per);
c58c2140 288
f556309e 289 pmux = gpio_array[gpio_bank(ident)]->port_mux;
d2b11a46 290
f556309e 291 return (pmux >> (2 * gpio_sub_n(ident)) & 0x3);
d2b11a46 292}
2f6f4bcd 293#elif defined(BF527_FAMILY) || defined(BF518_FAMILY)
f556309e 294inline void portmux_setup(unsigned short per)
59003145 295{
f556309e 296 u16 pmux, ident = P_IDENT(per), function = P_FUNCT2MUX(per);
59003145
MH		 297 u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
298
299 pmux = *port_mux[gpio_bank(ident)];
300 pmux &= ~(3 << offset);
301 pmux |= (function & 3) << offset;
302 *port_mux[gpio_bank(ident)] = pmux;
303 SSYNC();
304}
c58c2140
MH		 305#else
306# define portmux_setup(...) do { } while (0)
307#endif
1394f032 308
a161bb05 309static int __init bfin_gpio_init(void)
1394f032 310{
c58c2140 311 printk(KERN_INFO "Blackfin GPIO Controller\n");
1394f032
BW		 312
313 return 0;
314}
1394f032
BW		 315arch_initcall(bfin_gpio_init);
316
317
d2b11a46 318#ifndef BF548_FAMILY
1394f032
BW		 319/***********************************************************
320*
321* FUNCTIONS: Blackfin General Purpose Ports Access Functions
322*
323* INPUTS/OUTPUTS:
324* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
325*
326*
327* DESCRIPTION: These functions abstract direct register access
328* to Blackfin processor General Purpose
329* Ports Regsiters
330*
331* CAUTION: These functions do not belong to the GPIO Driver API
332*************************************************************
333* MODIFICATION HISTORY :
334**************************************************************/
335
336/* Set a specific bit */
337
338#define SET_GPIO(name) \
a2c8cfef 339void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
1394f032
BW		 340{ \
341 unsigned long flags; \
6a01f230 342 local_irq_save_hw(flags); \
1394f032 343 if (arg) \
f556309e 344 gpio_array[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
1394f032 345 else \
f556309e 346 gpio_array[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \
2b39331a 347 AWA_DUMMY_READ(name); \
6a01f230 348 local_irq_restore_hw(flags); \
1394f032
BW		 349} \
350EXPORT_SYMBOL(set_gpio_ ## name);
351
f556309e
MF		 352SET_GPIO(dir) /* set_gpio_dir() */
353SET_GPIO(inen) /* set_gpio_inen() */
354SET_GPIO(polar) /* set_gpio_polar() */
355SET_GPIO(edge) /* set_gpio_edge() */
356SET_GPIO(both) /* set_gpio_both() */
1394f032
BW		 357
358
2b39331a 359#define SET_GPIO_SC(name) \
a2c8cfef 360void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
2b39331a
MH		 361{ \
362 unsigned long flags; \
f556309e
MF		 363 if (ANOMALY_05000311 || ANOMALY_05000323) \
364 local_irq_save_hw(flags); \
1394f032 365 if (arg) \
f556309e 366 gpio_array[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
1394f032 367 else \
f556309e
MF		 368 gpio_array[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
369 if (ANOMALY_05000311 || ANOMALY_05000323) { \
370 AWA_DUMMY_READ(name); \
371 local_irq_restore_hw(flags); \
372 } \
1394f032
BW		 373} \
374EXPORT_SYMBOL(set_gpio_ ## name);
375
376SET_GPIO_SC(maska)
377SET_GPIO_SC(maskb)
1394f032 378SET_GPIO_SC(data)
1394f032 379
a2c8cfef 380void set_gpio_toggle(unsigned gpio)
1394f032
BW		 381{
382 unsigned long flags;
f556309e
MF		 383 if (ANOMALY_05000311 || ANOMALY_05000323)
384 local_irq_save_hw(flags);
385 gpio_array[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
386 if (ANOMALY_05000311 || ANOMALY_05000323) {
387 AWA_DUMMY_READ(toggle);
388 local_irq_restore_hw(flags);
389 }
1394f032 390}
1394f032
BW		 391EXPORT_SYMBOL(set_gpio_toggle);
392
393
394/*Set current PORT date (16-bit word)*/
395
396#define SET_GPIO_P(name) \
a2c8cfef 397void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
1394f032 398{ \
2b39331a 399 unsigned long flags; \
f556309e
MF		 400 if (ANOMALY_05000311 || ANOMALY_05000323) \
401 local_irq_save_hw(flags); \
402 gpio_array[gpio_bank(gpio)]->name = arg; \
403 if (ANOMALY_05000311 || ANOMALY_05000323) { \
404 AWA_DUMMY_READ(name); \
405 local_irq_restore_hw(flags); \
406 } \
2b39331a
MH		 407} \
408EXPORT_SYMBOL(set_gpiop_ ## name);
1394f032 409
2b39331a 410SET_GPIO_P(data)
1394f032
BW		 411SET_GPIO_P(dir)
412SET_GPIO_P(inen)
413SET_GPIO_P(polar)
414SET_GPIO_P(edge)
415SET_GPIO_P(both)
416SET_GPIO_P(maska)
417SET_GPIO_P(maskb)
418
1394f032 419/* Get a specific bit */
2b39331a 420#define GET_GPIO(name) \
a2c8cfef 421unsigned short get_gpio_ ## name(unsigned gpio) \
2b39331a
MH		 422{ \
423 unsigned long flags; \
424 unsigned short ret; \
f556309e
MF		 425 if (ANOMALY_05000311 || ANOMALY_05000323) \
426 local_irq_save_hw(flags); \
427 ret = 0x01 & (gpio_array[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \
428 if (ANOMALY_05000311 || ANOMALY_05000323) { \
429 AWA_DUMMY_READ(name); \
430 local_irq_restore_hw(flags); \
431 } \
2b39331a
MH		 432 return ret; \
433} \
434EXPORT_SYMBOL(get_gpio_ ## name);
1394f032 435
2b39331a 436GET_GPIO(data)
1394f032
BW		 437GET_GPIO(dir)
438GET_GPIO(inen)
439GET_GPIO(polar)
440GET_GPIO(edge)
441GET_GPIO(both)
442GET_GPIO(maska)
443GET_GPIO(maskb)
444
1394f032
BW		 445/*Get current PORT date (16-bit word)*/
446
2b39331a 447#define GET_GPIO_P(name) \
a2c8cfef 448unsigned short get_gpiop_ ## name(unsigned gpio) \
2b39331a
MH		 449{ \
450 unsigned long flags; \
451 unsigned short ret; \
f556309e
MF		 452 if (ANOMALY_05000311 || ANOMALY_05000323) \
453 local_irq_save_hw(flags); \
454 ret = (gpio_array[gpio_bank(gpio)]->name); \
455 if (ANOMALY_05000311 || ANOMALY_05000323) { \
456 AWA_DUMMY_READ(name); \
457 local_irq_restore_hw(flags); \
458 } \
2b39331a
MH		 459 return ret; \
460} \
461EXPORT_SYMBOL(get_gpiop_ ## name);
1394f032 462
2b39331a 463GET_GPIO_P(data)
1394f032
BW		 464GET_GPIO_P(dir)
465GET_GPIO_P(inen)
466GET_GPIO_P(polar)
467GET_GPIO_P(edge)
468GET_GPIO_P(both)
469GET_GPIO_P(maska)
470GET_GPIO_P(maskb)
471
1394f032
BW		 472
473#ifdef CONFIG_PM
f556309e
MF		 474
475static unsigned short wakeup_map[GPIO_BANK_NUM];
476static unsigned char wakeup_flags_map[MAX_BLACKFIN_GPIOS];
477
478static const unsigned int sic_iwr_irqs[] = {
479#if defined(BF533_FAMILY)
480 IRQ_PROG_INTB
481#elif defined(BF537_FAMILY)
482 IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX
483#elif defined(BF538_FAMILY)
484 IRQ_PORTF_INTB
485#elif defined(BF527_FAMILY) || defined(BF518_FAMILY)
486 IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB
487#elif defined(BF561_FAMILY)
488 IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB
489#else
490# error no SIC_IWR defined
491#endif
492};
493
1394f032
BW		 494/***********************************************************
495*
496* FUNCTIONS: Blackfin PM Setup API
497*
498* INPUTS/OUTPUTS:
499* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
500* type -
501* PM_WAKE_RISING
502* PM_WAKE_FALLING
503* PM_WAKE_HIGH
504* PM_WAKE_LOW
505* PM_WAKE_BOTH_EDGES
506*
507* DESCRIPTION: Blackfin PM Driver API
508*
509* CAUTION:
510*************************************************************
511* MODIFICATION HISTORY :
512**************************************************************/
a2c8cfef 513int gpio_pm_wakeup_request(unsigned gpio, unsigned char type)
1394f032
BW		 514{
515 unsigned long flags;
516
517 if ((check_gpio(gpio) < 0) || !type)
518 return -EINVAL;
519
6a01f230 520 local_irq_save_hw(flags);
1394f032
BW		 521 wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio);
522 wakeup_flags_map[gpio] = type;
6a01f230 523 local_irq_restore_hw(flags);
1394f032
BW		 524
525 return 0;
526}
527EXPORT_SYMBOL(gpio_pm_wakeup_request);
528
a2c8cfef 529void gpio_pm_wakeup_free(unsigned gpio)
1394f032
BW		 530{
531 unsigned long flags;
532
533 if (check_gpio(gpio) < 0)
534 return;
535
6a01f230 536 local_irq_save_hw(flags);
1394f032
BW		 537
538 wakeup_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
539
6a01f230 540 local_irq_restore_hw(flags);
1394f032
BW		 541}
542EXPORT_SYMBOL(gpio_pm_wakeup_free);
543
a2c8cfef 544static int bfin_gpio_wakeup_type(unsigned gpio, unsigned char type)
1394f032
BW		 545{
546 port_setup(gpio, GPIO_USAGE);
547 set_gpio_dir(gpio, 0);
548 set_gpio_inen(gpio, 1);
549
550 if (type & (PM_WAKE_RISING | PM_WAKE_FALLING))
551 set_gpio_edge(gpio, 1);
552 else
553 set_gpio_edge(gpio, 0);
554
555 if ((type & (PM_WAKE_BOTH_EDGES)) == (PM_WAKE_BOTH_EDGES))
556 set_gpio_both(gpio, 1);
557 else
558 set_gpio_both(gpio, 0);
559
560 if ((type & (PM_WAKE_FALLING | PM_WAKE_LOW)))
561 set_gpio_polar(gpio, 1);
562 else
563 set_gpio_polar(gpio, 0);
564
565 SSYNC();
566
567 return 0;
568}
569
1efc80b5 570u32 bfin_pm_standby_setup(void)
1394f032 571{
1394f032
BW		 572 u16 bank, mask, i, gpio;
573
1f83b8f1 574 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
1394f032
BW		 575 mask = wakeup_map[gpio_bank(i)];
576 bank = gpio_bank(i);
577
f556309e
MF		 578 gpio_bank_saved[bank].maskb = gpio_array[bank]->maskb;
579 gpio_array[bank]->maskb = 0;
1394f032
BW		 580
581 if (mask) {
2f6f4bcd 582#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
1394f032
BW		 583 gpio_bank_saved[bank].fer = *port_fer[bank];
584#endif
f556309e
MF		 585 gpio_bank_saved[bank].inen = gpio_array[bank]->inen;
586 gpio_bank_saved[bank].polar = gpio_array[bank]->polar;
587 gpio_bank_saved[bank].dir = gpio_array[bank]->dir;
588 gpio_bank_saved[bank].edge = gpio_array[bank]->edge;
589 gpio_bank_saved[bank].both = gpio_array[bank]->both;
c58c2140
MH		 590 gpio_bank_saved[bank].reserved =
591 reserved_gpio_map[bank];
1394f032
BW		 592
593 gpio = i;
594
595 while (mask) {
cfefe3c6
MH		 596 if ((mask & 1) && (wakeup_flags_map[gpio] !=
597 PM_WAKE_IGNORE)) {
c58c2140 598 reserved_gpio_map[gpio_bank(gpio)] |=
581d62ab
MH		 599 gpio_bit(gpio);
600 bfin_gpio_wakeup_type(gpio,
601 wakeup_flags_map[gpio]);
1394f032
BW		 602 set_gpio_data(gpio, 0); /*Clear*/
603 }
604 gpio++;
605 mask >>= 1;
606 }
607
cfefe3c6 608 bfin_internal_set_wake(sic_iwr_irqs[bank], 1);
f556309e 609 gpio_array[bank]->maskb_set = wakeup_map[gpio_bank(i)];
1394f032
BW		 610 }
611 }
612
2b39331a
MH		 613 AWA_DUMMY_READ(maskb_set);
614
cfefe3c6 615 return 0;
1394f032
BW		 616}
617
1efc80b5 618void bfin_pm_standby_restore(void)
1394f032
BW		 619{
620 u16 bank, mask, i;
621
1f83b8f1 622 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
1394f032
BW		 623 mask = wakeup_map[gpio_bank(i)];
624 bank = gpio_bank(i);
625
626 if (mask) {
2f6f4bcd 627#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
1394f032
BW		 628 *port_fer[bank] = gpio_bank_saved[bank].fer;
629#endif
f556309e
MF		 630 gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
631 gpio_array[bank]->dir = gpio_bank_saved[bank].dir;
632 gpio_array[bank]->polar = gpio_bank_saved[bank].polar;
633 gpio_array[bank]->edge = gpio_bank_saved[bank].edge;
634 gpio_array[bank]->both = gpio_bank_saved[bank].both;
581d62ab 635
c58c2140
MH		 636 reserved_gpio_map[bank] =
637 gpio_bank_saved[bank].reserved;
cfefe3c6 638 bfin_internal_set_wake(sic_iwr_irqs[bank], 0);
1394f032
BW		 639 }
640
f556309e 641 gpio_array[bank]->maskb = gpio_bank_saved[bank].maskb;
1394f032 642 }
2b39331a 643 AWA_DUMMY_READ(maskb);
1394f032
BW		 644}
645
1efc80b5
MH		 646void bfin_gpio_pm_hibernate_suspend(void)
647{
648 int i, bank;
649
650 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
651 bank = gpio_bank(i);
652
2f6f4bcd 653#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
f556309e 654 gpio_bank_saved[bank].fer = *port_fer[bank];
2f6f4bcd 655#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
f556309e 656 gpio_bank_saved[bank].mux = *port_mux[bank];
1efc80b5 657#else
f556309e
MF		 658 if (bank == 0)
659 gpio_bank_saved[bank].mux = bfin_read_PORT_MUX();
1efc80b5
MH		 660#endif
661#endif
f556309e
MF		 662 gpio_bank_saved[bank].data = gpio_array[bank]->data;
663 gpio_bank_saved[bank].inen = gpio_array[bank]->inen;
664 gpio_bank_saved[bank].polar = gpio_array[bank]->polar;
665 gpio_bank_saved[bank].dir = gpio_array[bank]->dir;
666 gpio_bank_saved[bank].edge = gpio_array[bank]->edge;
667 gpio_bank_saved[bank].both = gpio_array[bank]->both;
668 gpio_bank_saved[bank].maska = gpio_array[bank]->maska;
1efc80b5
MH		 669 }
670
671 AWA_DUMMY_READ(maska);
672}
673
674void bfin_gpio_pm_hibernate_restore(void)
675{
676 int i, bank;
677
678 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
f556309e 679 bank = gpio_bank(i);
1efc80b5 680
2f6f4bcd
BW		 681#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
682#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
f556309e 683 *port_mux[bank] = gpio_bank_saved[bank].mux;
1efc80b5 684#else
f556309e
MF		 685 if (bank == 0)
686 bfin_write_PORT_MUX(gpio_bank_saved[bank].mux);
1efc80b5 687#endif
f556309e 688 *port_fer[bank] = gpio_bank_saved[bank].fer;
1efc80b5 689#endif
f556309e
MF		 690 gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
691 gpio_array[bank]->dir = gpio_bank_saved[bank].dir;
692 gpio_array[bank]->polar = gpio_bank_saved[bank].polar;
693 gpio_array[bank]->edge = gpio_bank_saved[bank].edge;
694 gpio_array[bank]->both = gpio_bank_saved[bank].both;
1efc80b5 695
f556309e
MF		 696 gpio_array[bank]->data_set = gpio_bank_saved[bank].data
697 | gpio_bank_saved[bank].dir;
1efc80b5 698
f556309e 699 gpio_array[bank]->maska = gpio_bank_saved[bank].maska;
1efc80b5
MH		 700 }
701 AWA_DUMMY_READ(maska);
702}
703
704
1394f032 705#endif
fac3cf43 706#else /* BF548_FAMILY */
1efc80b5
MH		 707#ifdef CONFIG_PM
708
709u32 bfin_pm_standby_setup(void)
710{
711 return 0;
712}
713
714void bfin_pm_standby_restore(void)
715{
716
717}
718
719void bfin_gpio_pm_hibernate_suspend(void)
720{
721 int i, bank;
722
723 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
724 bank = gpio_bank(i);
725
f556309e
MF		 726 gpio_bank_saved[bank].fer = gpio_array[bank]->port_fer;
727 gpio_bank_saved[bank].mux = gpio_array[bank]->port_mux;
728 gpio_bank_saved[bank].data = gpio_array[bank]->data;
729 gpio_bank_saved[bank].data = gpio_array[bank]->data;
730 gpio_bank_saved[bank].inen = gpio_array[bank]->inen;
731 gpio_bank_saved[bank].dir = gpio_array[bank]->dir_set;
1efc80b5
MH		 732 }
733}
734
735void bfin_gpio_pm_hibernate_restore(void)
736{
737 int i, bank;
738
739 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
f556309e
MF		 740 bank = gpio_bank(i);
741
742 gpio_array[bank]->port_mux = gpio_bank_saved[bank].mux;
743 gpio_array[bank]->port_fer = gpio_bank_saved[bank].fer;
744 gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
745 gpio_array[bank]->dir_set = gpio_bank_saved[bank].dir;
746 gpio_array[bank]->data_set = gpio_bank_saved[bank].data
747 | gpio_bank_saved[bank].dir;
1efc80b5
MH		 748 }
749}
750#endif
fac3cf43 751
a2c8cfef 752unsigned short get_gpio_dir(unsigned gpio)
fac3cf43 753{
f556309e 754 return (0x01 & (gpio_array[gpio_bank(gpio)]->dir_clear >> gpio_sub_n(gpio)));
fac3cf43
MH		 755}
756EXPORT_SYMBOL(get_gpio_dir);
757
d2b11a46 758#endif /* BF548_FAMILY */
1394f032 759
d2b11a46
MH		 760/***********************************************************
761*
762* FUNCTIONS: Blackfin Peripheral Resource Allocation
763* and PortMux Setup
764*
765* INPUTS/OUTPUTS:
766* per Peripheral Identifier
767* label String
768*
769* DESCRIPTION: Blackfin Peripheral Resource Allocation and Setup API
770*
771* CAUTION:
772*************************************************************
773* MODIFICATION HISTORY :
774**************************************************************/
775
d2b11a46
MH		 776int peripheral_request(unsigned short per, const char *label)
777{
778 unsigned long flags;
779 unsigned short ident = P_IDENT(per);
780
781 /*
782 * Don't cares are pins with only one dedicated function
783 */
c58c2140 784
d2b11a46
MH		 785 if (per & P_DONTCARE)
786 return 0;
787
788 if (!(per & P_DEFINED))
789 return -ENODEV;
790
6a01f230 791 local_irq_save_hw(flags);
d2b11a46 792
6a87d29b
MF		 793 /* If a pin can be muxed as either GPIO or peripheral, make
794 * sure it is not already a GPIO pin when we request it.
795 */
796 if (unlikely(!check_gpio(ident) &&
797 reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
f85c4abd 798 dump_stack();
d2b11a46 799 printk(KERN_ERR
6c7ec0ec 800 "%s: Peripheral %d is already reserved as GPIO by %s !\n",
b85d858b 801 __func__, ident, get_label(ident));
6a01f230 802 local_irq_restore_hw(flags);
d2b11a46
MH		 803 return -EBUSY;
804 }
805
806 if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
807
d171c233
MF		 808 /*
809 * Pin functions like AMC address strobes my
810 * be requested and used by several drivers
811 */
d2b11a46 812
6c7ec0ec 813#ifdef BF548_FAMILY
f556309e 814 if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) {
6c7ec0ec
MF		 815#else
816 if (!(per & P_MAYSHARE)) {
817#endif
d171c233
MF		 818 /*
819 * Allow that the identical pin function can
820 * be requested from the same driver twice
821 */
d2b11a46 822
d171c233
MF		 823 if (cmp_label(ident, label) == 0)
824 goto anyway;
d2b11a46 825
f85c4abd 826 dump_stack();
d2b11a46
MH		 827 printk(KERN_ERR
828 "%s: Peripheral %d function %d is already reserved by %s !\n",
b85d858b 829 __func__, ident, P_FUNCT2MUX(per), get_label(ident));
6a01f230 830 local_irq_restore_hw(flags);
d2b11a46
MH		 831 return -EBUSY;
832 }
833 }
834
d171c233 835 anyway:
d2b11a46
MH		 836 reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
837
f556309e 838 portmux_setup(per);
c58c2140
MH		 839 port_setup(ident, PERIPHERAL_USAGE);
840
6a01f230 841 local_irq_restore_hw(flags);
c58c2140
MH		 842 set_label(ident, label);
843
844 return 0;
845}
846EXPORT_SYMBOL(peripheral_request);
847
68179371 848int peripheral_request_list(const unsigned short per[], const char *label)
c58c2140
MH		 849{
850 u16 cnt;
851 int ret;
852
853 for (cnt = 0; per[cnt] != 0; cnt++) {
314c98d5 854
c58c2140 855 ret = peripheral_request(per[cnt], label);
314c98d5
MH		 856
857 if (ret < 0) {
d171c233 858 for ( ; cnt > 0; cnt--)
314c98d5 859 peripheral_free(per[cnt - 1]);
d171c233
MF		 860
861 return ret;
314c98d5 862 }
c58c2140
MH		 863 }
864
865 return 0;
866}
867EXPORT_SYMBOL(peripheral_request_list);
868
869void peripheral_free(unsigned short per)
870{
871 unsigned long flags;
872 unsigned short ident = P_IDENT(per);
873
874 if (per & P_DONTCARE)
875 return;
876
877 if (!(per & P_DEFINED))
878 return;
879
6a01f230 880 local_irq_save_hw(flags);
c58c2140 881
d171c233 882 if (unlikely(!(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident)))) {
6a01f230 883 local_irq_restore_hw(flags);
c58c2140
MH		 884 return;
885 }
886
d171c233 887 if (!(per & P_MAYSHARE))
c58c2140 888 port_setup(ident, GPIO_USAGE);
c58c2140
MH		 889
890 reserved_peri_map[gpio_bank(ident)] &= ~gpio_bit(ident);
891
2acde902
MH		 892 set_label(ident, "free");
893
6a01f230 894 local_irq_restore_hw(flags);
c58c2140
MH		 895}
896EXPORT_SYMBOL(peripheral_free);
897
68179371 898void peripheral_free_list(const unsigned short per[])
c58c2140
MH		 899{
900 u16 cnt;
d171c233 901 for (cnt = 0; per[cnt] != 0; cnt++)
c58c2140 902 peripheral_free(per[cnt]);
c58c2140
MH		 903}
904EXPORT_SYMBOL(peripheral_free_list);
905
1394f032
BW		 906/***********************************************************
907*
908* FUNCTIONS: Blackfin GPIO Driver
909*
910* INPUTS/OUTPUTS:
d2b11a46
MH		 911* gpio PIO Number between 0 and MAX_BLACKFIN_GPIOS
912* label String
1394f032
BW		 913*
914* DESCRIPTION: Blackfin GPIO Driver API
915*
916* CAUTION:
917*************************************************************
918* MODIFICATION HISTORY :
919**************************************************************/
920
a4f0b32c 921int bfin_gpio_request(unsigned gpio, const char *label)
1394f032
BW		 922{
923 unsigned long flags;
924
925 if (check_gpio(gpio) < 0)
926 return -EINVAL;
927
6a01f230 928 local_irq_save_hw(flags);
1394f032 929
2acde902
MH		 930 /*
931 * Allow that the identical GPIO can
932 * be requested from the same driver twice
933 * Do nothing and return -
934 */
935
936 if (cmp_label(gpio, label) == 0) {
6a01f230 937 local_irq_restore_hw(flags);
2acde902
MH		 938 return 0;
939 }
940
c58c2140 941 if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
f85c4abd 942 dump_stack();
d2b11a46 943 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
9570ff4a 944 gpio, get_label(gpio));
6a01f230 945 local_irq_restore_hw(flags);
d2b11a46
MH		 946 return -EBUSY;
947 }
948 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
f85c4abd 949 dump_stack();
d2b11a46
MH		 950 printk(KERN_ERR
951 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
952 gpio, get_label(gpio));
6a01f230 953 local_irq_restore_hw(flags);
1394f032
BW		 954 return -EBUSY;
955 }
a2be3931 956 if (unlikely(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
9570ff4a
GY		 957 printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!"
958 " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio);
a2be3931
MH		 959 }
960#ifndef BF548_FAMILY
961 else { /* Reset POLAR setting when acquiring a gpio for the first time */
962 set_gpio_polar(gpio, 0);
963 }
964#endif
d2b11a46 965
c58c2140 966 reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
9570ff4a 967 set_label(gpio, label);
1394f032 968
6a01f230 969 local_irq_restore_hw(flags);
1394f032
BW		 970
971 port_setup(gpio, GPIO_USAGE);
972
973 return 0;
974}
a4f0b32c 975EXPORT_SYMBOL(bfin_gpio_request);
1394f032 976
a4f0b32c 977void bfin_gpio_free(unsigned gpio)
1394f032
BW		 978{
979 unsigned long flags;
980
981 if (check_gpio(gpio) < 0)
982 return;
983
45c4f2a0
UKK		 984 might_sleep();
985
6a01f230 986 local_irq_save_hw(flags);
1394f032 987
c58c2140 988 if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
1394f032 989 dump_stack();
f85c4abd 990 gpio_error(gpio);
6a01f230 991 local_irq_restore_hw(flags);
1394f032
BW		 992 return;
993 }
994
c58c2140 995 reserved_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
1394f032 996
2acde902
MH		 997 set_label(gpio, "free");
998
6a01f230 999 local_irq_restore_hw(flags);
1394f032 1000}
a4f0b32c 1001EXPORT_SYMBOL(bfin_gpio_free);
1394f032 1002
9570ff4a
GY		 1003int bfin_gpio_irq_request(unsigned gpio, const char *label)
1004{
1005 unsigned long flags;
1006
1007 if (check_gpio(gpio) < 0)
1008 return -EINVAL;
1009
6a01f230 1010 local_irq_save_hw(flags);
9570ff4a
GY		 1011
1012 if (unlikely(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1013 dump_stack();
1014 printk(KERN_ERR
1015 "bfin-gpio: GPIO %d is already reserved as gpio-irq !\n",
1016 gpio);
6a01f230 1017 local_irq_restore_hw(flags);
9570ff4a
GY		 1018 return -EBUSY;
1019 }
1020 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1021 dump_stack();
1022 printk(KERN_ERR
1023 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
1024 gpio, get_label(gpio));
6a01f230 1025 local_irq_restore_hw(flags);
9570ff4a
GY		 1026 return -EBUSY;
1027 }
1028 if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))
1029 printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved by %s! "
1030 "(Documentation/blackfin/bfin-gpio-notes.txt)\n",
1031 gpio, get_label(gpio));
1032
1033 reserved_gpio_irq_map[gpio_bank(gpio)] |= gpio_bit(gpio);
1034 set_label(gpio, label);
1035
6a01f230 1036 local_irq_restore_hw(flags);
9570ff4a
GY		 1037
1038 port_setup(gpio, GPIO_USAGE);
1039
1040 return 0;
1041}
1042
1043void bfin_gpio_irq_free(unsigned gpio)
1044{
1045 unsigned long flags;
1046
1047 if (check_gpio(gpio) < 0)
1048 return;
1049
6a01f230 1050 local_irq_save_hw(flags);
9570ff4a
GY		 1051
1052 if (unlikely(!(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
1053 dump_stack();
1054 gpio_error(gpio);
6a01f230 1055 local_irq_restore_hw(flags);
9570ff4a
GY		 1056 return;
1057 }
1058
1059 reserved_gpio_irq_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
1060
1061 set_label(gpio, "free");
1062
6a01f230 1063 local_irq_restore_hw(flags);
9570ff4a
GY		 1064}
1065
f556309e
MF		 1066static inline void __bfin_gpio_direction_input(unsigned gpio)
1067{
d2b11a46 1068#ifdef BF548_FAMILY
f556309e
MF		 1069 gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio);
1070#else
1071 gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
1072#endif
1073 gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
1074}
1075
a4f0b32c 1076int bfin_gpio_direction_input(unsigned gpio)
d2b11a46
MH		 1077{
1078 unsigned long flags;
1079
acbcd263
MH		 1080 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1081 gpio_error(gpio);
1082 return -EINVAL;
1083 }
1084
6a01f230 1085 local_irq_save_hw(flags);
f556309e
MF		 1086 __bfin_gpio_direction_input(gpio);
1087 AWA_DUMMY_READ(inen);
6a01f230 1088 local_irq_restore_hw(flags);
acbcd263
MH		 1089
1090 return 0;
d2b11a46 1091}
a4f0b32c 1092EXPORT_SYMBOL(bfin_gpio_direction_input);
d2b11a46 1093
f556309e 1094void bfin_gpio_irq_prepare(unsigned gpio)
d2b11a46 1095{
f556309e 1096#ifdef BF548_FAMILY
d2b11a46 1097 unsigned long flags;
f556309e 1098#endif
d2b11a46 1099
f556309e 1100 port_setup(gpio, GPIO_USAGE);
d2b11a46 1101
f556309e 1102#ifdef BF548_FAMILY
6a01f230 1103 local_irq_save_hw(flags);
f556309e 1104 __bfin_gpio_direction_input(gpio);
6a01f230 1105 local_irq_restore_hw(flags);
f556309e 1106#endif
d2b11a46 1107}
d2b11a46 1108
a4f0b32c 1109void bfin_gpio_set_value(unsigned gpio, int arg)
d2b11a46
MH		 1110{
1111 if (arg)
f556309e 1112 gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
d2b11a46 1113 else
f556309e 1114 gpio_array[gpio_bank(gpio)]->data_clear = gpio_bit(gpio);
d2b11a46 1115}
a4f0b32c 1116EXPORT_SYMBOL(bfin_gpio_set_value);
d2b11a46 1117
f556309e 1118int bfin_gpio_direction_output(unsigned gpio, int value)
affee2b2
MH		 1119{
1120 unsigned long flags;
1121
f556309e
MF		 1122 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1123 gpio_error(gpio);
1124 return -EINVAL;
1125 }
affee2b2 1126
6a01f230 1127 local_irq_save_hw(flags);
affee2b2 1128
f556309e
MF		 1129 gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
1130 gpio_set_value(gpio, value);
1131#ifdef BF548_FAMILY
1132 gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio);
d2b11a46 1133#else
f556309e
MF		 1134 gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
1135#endif
1136
1137 AWA_DUMMY_READ(dir);
1138 local_irq_restore_hw(flags);
1139
1140 return 0;
1141}
1142EXPORT_SYMBOL(bfin_gpio_direction_output);
d2b11a46 1143
a4f0b32c 1144int bfin_gpio_get_value(unsigned gpio)
803a8d2a 1145{
f556309e
MF		 1146#ifdef BF548_FAMILY
1147 return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio)));
1148#else
803a8d2a 1149 unsigned long flags;
803a8d2a
MH		 1150
1151 if (unlikely(get_gpio_edge(gpio))) {
f556309e 1152 int ret;
6a01f230 1153 local_irq_save_hw(flags);
803a8d2a
MH		 1154 set_gpio_edge(gpio, 0);
1155 ret = get_gpio_data(gpio);
1156 set_gpio_edge(gpio, 1);
6a01f230 1157 local_irq_restore_hw(flags);
803a8d2a
MH		 1158 return ret;
1159 } else
1160 return get_gpio_data(gpio);
f556309e 1161#endif
803a8d2a 1162}
a4f0b32c 1163EXPORT_SYMBOL(bfin_gpio_get_value);
803a8d2a 1164
168f1212
MF		 1165/* If we are booting from SPI and our board lacks a strong enough pull up,
1166 * the core can reset and execute the bootrom faster than the resistor can
1167 * pull the signal logically high. To work around this (common) error in
1168 * board design, we explicitly set the pin back to GPIO mode, force /CS
1169 * high, and wait for the electrons to do their thing.
1170 *
1171 * This function only makes sense to be called from reset code, but it
1172 * lives here as we need to force all the GPIO states w/out going through
1173 * BUG() checks and such.
1174 */
1175void bfin_gpio_reset_spi0_ssel1(void)
1176{
4d5f4ed3
MH		 1177 u16 gpio = P_IDENT(P_SPI0_SSEL1);
1178
1179 port_setup(gpio, GPIO_USAGE);
f556309e 1180 gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
a2c8cfef 1181 AWA_DUMMY_READ(data_set);
168f1212
MF		 1182 udelay(1);
1183}
d2b11a46 1184
1545a111
MF		 1185#if defined(CONFIG_PROC_FS)
1186static int gpio_proc_read(char *buf, char **start, off_t offset,
1187 int len, int *unused_i, void *unused_v)
1188{
9570ff4a 1189 int c, irq, gpio, outlen = 0;
1545a111
MF		 1190
1191 for (c = 0; c < MAX_RESOURCES; c++) {
9570ff4a
GY		 1192 irq = reserved_gpio_irq_map[gpio_bank(c)] & gpio_bit(c);
1193 gpio = reserved_gpio_map[gpio_bank(c)] & gpio_bit(c);
1194 if (!check_gpio(c) && (gpio || irq))
1195 len = sprintf(buf, "GPIO_%d: \t%s%s \t\tGPIO %s\n", c,
1196 get_label(c), (gpio && irq) ? " *" : "",
1197 get_gpio_dir(c) ? "OUTPUT" : "INPUT");
1545a111 1198 else if (reserved_peri_map[gpio_bank(c)] & gpio_bit(c))
8eb3e3bf 1199 len = sprintf(buf, "GPIO_%d: \t%s \t\tPeripheral\n", c, get_label(c));
1545a111
MF		 1200 else
1201 continue;
1202 buf += len;
1203 outlen += len;
1204 }
1205 return outlen;
1206}
1207
1208static __init int gpio_register_proc(void)
1209{
1210 struct proc_dir_entry *proc_gpio;
1211
1212 proc_gpio = create_proc_entry("gpio", S_IRUGO, NULL);
1213 if (proc_gpio)
1214 proc_gpio->read_proc = gpio_proc_read;
1215 return proc_gpio != NULL;
1216}
1545a111
MF		 1217__initcall(gpio_register_proc);
1218#endif
a4f0b32c
MH		 1219
1220#ifdef CONFIG_GPIOLIB
1221int bfin_gpiolib_direction_input(struct gpio_chip *chip, unsigned gpio)
1222{
1223 return bfin_gpio_direction_input(gpio);
1224}
1225
1226int bfin_gpiolib_direction_output(struct gpio_chip *chip, unsigned gpio, int level)
1227{
1228 return bfin_gpio_direction_output(gpio, level);
1229}
1230
1231int bfin_gpiolib_get_value(struct gpio_chip *chip, unsigned gpio)
1232{
1233 return bfin_gpio_get_value(gpio);
1234}
1235
1236void bfin_gpiolib_set_value(struct gpio_chip *chip, unsigned gpio, int value)
1237{
a4f0b32c 1238 return bfin_gpio_set_value(gpio, value);
a4f0b32c
MH		 1239}
1240
1241int bfin_gpiolib_gpio_request(struct gpio_chip *chip, unsigned gpio)
1242{
1243 return bfin_gpio_request(gpio, chip->label);
1244}
1245
1246void bfin_gpiolib_gpio_free(struct gpio_chip *chip, unsigned gpio)
1247{
1248 return bfin_gpio_free(gpio);
1249}
1250
1251static struct gpio_chip bfin_chip = {
1252 .label = "Blackfin-GPIOlib",
1253 .direction_input = bfin_gpiolib_direction_input,
1254 .get = bfin_gpiolib_get_value,
1255 .direction_output = bfin_gpiolib_direction_output,
1256 .set = bfin_gpiolib_set_value,
1257 .request = bfin_gpiolib_gpio_request,
1258 .free = bfin_gpiolib_gpio_free,
1259 .base = 0,
1260 .ngpio = MAX_BLACKFIN_GPIOS,
1261};
1262
1263static int __init bfin_gpiolib_setup(void)
1264{
1265 return gpiochip_add(&bfin_chip);
1266}
1267arch_initcall(bfin_gpiolib_setup);
1268#endif
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