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1/*
2 * File: arch/blackfin/kernel/bfin_gpio.c
3 * Based on:
4 * Author: Michael Hennerich (hennerich@blackfin.uclinux.org)
5 *
6 * Created:
7 * Description: GPIO Abstraction Layer
8 *
9 * Modified:
a2c8cfef 10 * Copyright 2008 Analog Devices Inc.
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11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30/*
d2b11a46 31* Number BF537/6/4 BF561 BF533/2/1 BF549/8/4/2
1394f032 32*
d2b11a46 33* GPIO_0 PF0 PF0 PF0 PA0...PJ13
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34* GPIO_1 PF1 PF1 PF1
35* GPIO_2 PF2 PF2 PF2
36* GPIO_3 PF3 PF3 PF3
37* GPIO_4 PF4 PF4 PF4
38* GPIO_5 PF5 PF5 PF5
39* GPIO_6 PF6 PF6 PF6
40* GPIO_7 PF7 PF7 PF7
41* GPIO_8 PF8 PF8 PF8
42* GPIO_9 PF9 PF9 PF9
43* GPIO_10 PF10 PF10 PF10
44* GPIO_11 PF11 PF11 PF11
45* GPIO_12 PF12 PF12 PF12
46* GPIO_13 PF13 PF13 PF13
47* GPIO_14 PF14 PF14 PF14
48* GPIO_15 PF15 PF15 PF15
49* GPIO_16 PG0 PF16
50* GPIO_17 PG1 PF17
51* GPIO_18 PG2 PF18
52* GPIO_19 PG3 PF19
53* GPIO_20 PG4 PF20
54* GPIO_21 PG5 PF21
55* GPIO_22 PG6 PF22
56* GPIO_23 PG7 PF23
57* GPIO_24 PG8 PF24
58* GPIO_25 PG9 PF25
59* GPIO_26 PG10 PF26
60* GPIO_27 PG11 PF27
61* GPIO_28 PG12 PF28
62* GPIO_29 PG13 PF29
63* GPIO_30 PG14 PF30
64* GPIO_31 PG15 PF31
65* GPIO_32 PH0 PF32
66* GPIO_33 PH1 PF33
67* GPIO_34 PH2 PF34
68* GPIO_35 PH3 PF35
69* GPIO_36 PH4 PF36
70* GPIO_37 PH5 PF37
71* GPIO_38 PH6 PF38
72* GPIO_39 PH7 PF39
73* GPIO_40 PH8 PF40
74* GPIO_41 PH9 PF41
75* GPIO_42 PH10 PF42
76* GPIO_43 PH11 PF43
77* GPIO_44 PH12 PF44
78* GPIO_45 PH13 PF45
79* GPIO_46 PH14 PF46
80* GPIO_47 PH15 PF47
81*/
82
168f1212 83#include <linux/delay.h>
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84#include <linux/module.h>
85#include <linux/err.h>
1545a111 86#include <linux/proc_fs.h>
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87#include <asm/blackfin.h>
88#include <asm/gpio.h>
c58c2140 89#include <asm/portmux.h>
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90#include <linux/irq.h>
91
2b39331a
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92#if ANOMALY_05000311 || ANOMALY_05000323
93enum {
94 AWA_data = SYSCR,
95 AWA_data_clear = SYSCR,
96 AWA_data_set = SYSCR,
97 AWA_toggle = SYSCR,
6ed83942
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98 AWA_maska = BFIN_UART_SCR,
99 AWA_maska_clear = BFIN_UART_SCR,
100 AWA_maska_set = BFIN_UART_SCR,
101 AWA_maska_toggle = BFIN_UART_SCR,
102 AWA_maskb = BFIN_UART_GCTL,
103 AWA_maskb_clear = BFIN_UART_GCTL,
104 AWA_maskb_set = BFIN_UART_GCTL,
105 AWA_maskb_toggle = BFIN_UART_GCTL,
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106 AWA_dir = SPORT1_STAT,
107 AWA_polar = SPORT1_STAT,
108 AWA_edge = SPORT1_STAT,
109 AWA_both = SPORT1_STAT,
110#if ANOMALY_05000311
111 AWA_inen = TIMER_ENABLE,
112#elif ANOMALY_05000323
113 AWA_inen = DMA1_1_CONFIG,
114#endif
115};
116 /* Anomaly Workaround */
117#define AWA_DUMMY_READ(name) bfin_read16(AWA_ ## name)
118#else
119#define AWA_DUMMY_READ(...) do { } while (0)
120#endif
121
dc26aec2 122#if defined(BF533_FAMILY) || defined(BF538_FAMILY)
397861cd 123static struct gpio_port_t *gpio_bankb[] = {
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124 (struct gpio_port_t *) FIO_FLAG_D,
125};
126#endif
127
2f6f4bcd 128#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
397861cd 129static struct gpio_port_t *gpio_bankb[] = {
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130 (struct gpio_port_t *) PORTFIO,
131 (struct gpio_port_t *) PORTGIO,
132 (struct gpio_port_t *) PORTHIO,
133};
134
397861cd 135static unsigned short *port_fer[] = {
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136 (unsigned short *) PORTF_FER,
137 (unsigned short *) PORTG_FER,
138 (unsigned short *) PORTH_FER,
139};
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140#endif
141
2f6f4bcd 142#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
397861cd 143static unsigned short *port_mux[] = {
59003145
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144 (unsigned short *) PORTF_MUX,
145 (unsigned short *) PORTG_MUX,
146 (unsigned short *) PORTH_MUX,
147};
148
149static const
150u8 pmux_offset[][16] =
151 {{ 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 4, 6, 8, 8, 10, 10 }, /* PORTF */
152 { 0, 0, 0, 0, 0, 2, 2, 4, 4, 6, 8, 10, 10, 10, 12, 12 }, /* PORTG */
153 { 0, 0, 0, 0, 0, 0, 0, 0, 2, 4, 4, 4, 4, 4, 4, 4 }, /* PORTH */
154 };
155#endif
156
1394f032 157#ifdef BF561_FAMILY
397861cd 158static struct gpio_port_t *gpio_bankb[] = {
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159 (struct gpio_port_t *) FIO0_FLAG_D,
160 (struct gpio_port_t *) FIO1_FLAG_D,
161 (struct gpio_port_t *) FIO2_FLAG_D,
162};
163#endif
164
d2b11a46 165#ifdef BF548_FAMILY
397861cd 166static struct gpio_port_t *gpio_array[] = {
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167 (struct gpio_port_t *)PORTA_FER,
168 (struct gpio_port_t *)PORTB_FER,
169 (struct gpio_port_t *)PORTC_FER,
170 (struct gpio_port_t *)PORTD_FER,
171 (struct gpio_port_t *)PORTE_FER,
172 (struct gpio_port_t *)PORTF_FER,
173 (struct gpio_port_t *)PORTG_FER,
174 (struct gpio_port_t *)PORTH_FER,
175 (struct gpio_port_t *)PORTI_FER,
176 (struct gpio_port_t *)PORTJ_FER,
177};
178#endif
179
397861cd 180static unsigned short reserved_gpio_map[GPIO_BANK_NUM];
fac3cf43 181static unsigned short reserved_peri_map[gpio_bank(MAX_RESOURCES)];
9570ff4a 182static unsigned short reserved_gpio_irq_map[GPIO_BANK_NUM];
c58c2140 183
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184#define RESOURCE_LABEL_SIZE 16
185
fac3cf43 186static struct str_ident {
8c613623 187 char name[RESOURCE_LABEL_SIZE];
fac3cf43 188} str_ident[MAX_RESOURCES];
1394f032 189
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190#if defined(CONFIG_PM)
191#if defined(CONFIG_BF54x)
397861cd 192static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM];
1efc80b5 193#else
397861cd 194static unsigned short wakeup_map[GPIO_BANK_NUM];
1394f032 195static unsigned char wakeup_flags_map[MAX_BLACKFIN_GPIOS];
397861cd 196static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM];
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197
198#ifdef BF533_FAMILY
397861cd 199static unsigned int sic_iwr_irqs[] = {IRQ_PROG_INTB};
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200#endif
201
202#ifdef BF537_FAMILY
397861cd 203static unsigned int sic_iwr_irqs[] = {IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX};
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204#endif
205
dc26aec2 206#ifdef BF538_FAMILY
397861cd 207static unsigned int sic_iwr_irqs[] = {IRQ_PORTF_INTB};
dc26aec2
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208#endif
209
2f6f4bcd 210#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
397861cd 211static unsigned int sic_iwr_irqs[] = {IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB};
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212#endif
213
1394f032 214#ifdef BF561_FAMILY
397861cd 215static unsigned int sic_iwr_irqs[] = {IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB};
1394f032 216#endif
1efc80b5 217#endif
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218#endif /* CONFIG_PM */
219
a2c8cfef 220inline int check_gpio(unsigned gpio)
d2b11a46 221{
27228b2e 222#if defined(BF548_FAMILY)
d2b11a46
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223 if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
224 || gpio == GPIO_PH14 || gpio == GPIO_PH15
27228b2e 225 || gpio == GPIO_PJ14 || gpio == GPIO_PJ15)
d2b11a46 226 return -EINVAL;
27228b2e 227#endif
e7613aab 228 if (gpio >= MAX_BLACKFIN_GPIOS)
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229 return -EINVAL;
230 return 0;
231}
232
74c04503 233static void gpio_error(unsigned gpio)
acbcd263
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234{
235 printk(KERN_ERR "bfin-gpio: GPIO %d wasn't requested!\n", gpio);
236}
237
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238static void set_label(unsigned short ident, const char *label)
239{
e9fae189 240 if (label) {
8c613623 241 strncpy(str_ident[ident].name, label,
c58c2140 242 RESOURCE_LABEL_SIZE);
8c613623 243 str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0;
c58c2140
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244 }
245}
246
247static char *get_label(unsigned short ident)
248{
8c613623 249 return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN");
c58c2140
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250}
251
252static int cmp_label(unsigned short ident, const char *label)
253{
fac3cf43
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254 if (label == NULL) {
255 dump_stack();
256 printk(KERN_ERR "Please provide none-null label\n");
257 }
258
e9fae189 259 if (label)
1f7d373f 260 return strcmp(str_ident[ident].name, label);
c58c2140
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261 else
262 return -EINVAL;
263}
264
a2c8cfef 265static void port_setup(unsigned gpio, unsigned short usage)
1394f032 266{
a2d03a1d
MF
267 if (check_gpio(gpio))
268 return;
269
270#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
271 if (usage == GPIO_USAGE)
272 *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
273 else
274 *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
275 SSYNC();
d2b11a46 276#elif defined(BF548_FAMILY)
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277 if (usage == GPIO_USAGE)
278 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
279 else
280 gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
281 SSYNC();
1394f032 282#endif
a2d03a1d 283}
1394f032 284
c58c2140 285#ifdef BF537_FAMILY
8c613623
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286static struct {
287 unsigned short res;
288 unsigned short offset;
289} port_mux_lut[] = {
290 {.res = P_PPI0_D13, .offset = 11},
291 {.res = P_PPI0_D14, .offset = 11},
292 {.res = P_PPI0_D15, .offset = 11},
293 {.res = P_SPORT1_TFS, .offset = 11},
294 {.res = P_SPORT1_TSCLK, .offset = 11},
295 {.res = P_SPORT1_DTPRI, .offset = 11},
296 {.res = P_PPI0_D10, .offset = 10},
297 {.res = P_PPI0_D11, .offset = 10},
298 {.res = P_PPI0_D12, .offset = 10},
299 {.res = P_SPORT1_RSCLK, .offset = 10},
300 {.res = P_SPORT1_RFS, .offset = 10},
301 {.res = P_SPORT1_DRPRI, .offset = 10},
302 {.res = P_PPI0_D8, .offset = 9},
303 {.res = P_PPI0_D9, .offset = 9},
304 {.res = P_SPORT1_DRSEC, .offset = 9},
305 {.res = P_SPORT1_DTSEC, .offset = 9},
306 {.res = P_TMR2, .offset = 8},
307 {.res = P_PPI0_FS3, .offset = 8},
308 {.res = P_TMR3, .offset = 7},
309 {.res = P_SPI0_SSEL4, .offset = 7},
310 {.res = P_TMR4, .offset = 6},
311 {.res = P_SPI0_SSEL5, .offset = 6},
312 {.res = P_TMR5, .offset = 5},
313 {.res = P_SPI0_SSEL6, .offset = 5},
314 {.res = P_UART1_RX, .offset = 4},
315 {.res = P_UART1_TX, .offset = 4},
316 {.res = P_TMR6, .offset = 4},
317 {.res = P_TMR7, .offset = 4},
318 {.res = P_UART0_RX, .offset = 3},
319 {.res = P_UART0_TX, .offset = 3},
320 {.res = P_DMAR0, .offset = 3},
321 {.res = P_DMAR1, .offset = 3},
322 {.res = P_SPORT0_DTSEC, .offset = 1},
323 {.res = P_SPORT0_DRSEC, .offset = 1},
324 {.res = P_CAN0_RX, .offset = 1},
325 {.res = P_CAN0_TX, .offset = 1},
326 {.res = P_SPI0_SSEL7, .offset = 1},
327 {.res = P_SPORT0_TFS, .offset = 0},
328 {.res = P_SPORT0_DTPRI, .offset = 0},
329 {.res = P_SPI0_SSEL2, .offset = 0},
330 {.res = P_SPI0_SSEL3, .offset = 0},
c58c2140
MH
331};
332
333static void portmux_setup(unsigned short per, unsigned short function)
334{
8c613623 335 u16 y, offset, muxreg;
c58c2140 336
8c613623
MH
337 for (y = 0; y < ARRAY_SIZE(port_mux_lut); y++) {
338 if (port_mux_lut[y].res == per) {
c58c2140
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339
340 /* SET PORTMUX REG */
341
8c613623 342 offset = port_mux_lut[y].offset;
c58c2140
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343 muxreg = bfin_read_PORT_MUX();
344
d171c233 345 if (offset != 1)
c58c2140 346 muxreg &= ~(1 << offset);
d171c233 347 else
c58c2140 348 muxreg &= ~(3 << 1);
c58c2140
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349
350 muxreg |= (function << offset);
351 bfin_write_PORT_MUX(muxreg);
352 }
353 }
354}
d2b11a46
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355#elif defined(BF548_FAMILY)
356inline void portmux_setup(unsigned short portno, unsigned short function)
357{
358 u32 pmux;
359
360 pmux = gpio_array[gpio_bank(portno)]->port_mux;
361
362 pmux &= ~(0x3 << (2 * gpio_sub_n(portno)));
363 pmux |= (function & 0x3) << (2 * gpio_sub_n(portno));
364
365 gpio_array[gpio_bank(portno)]->port_mux = pmux;
366}
367
368inline u16 get_portmux(unsigned short portno)
369{
370 u32 pmux;
c58c2140 371
d2b11a46
MH
372 pmux = gpio_array[gpio_bank(portno)]->port_mux;
373
374 return (pmux >> (2 * gpio_sub_n(portno)) & 0x3);
375}
2f6f4bcd 376#elif defined(BF527_FAMILY) || defined(BF518_FAMILY)
59003145
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377inline void portmux_setup(unsigned short portno, unsigned short function)
378{
379 u16 pmux, ident = P_IDENT(portno);
380 u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
381
382 pmux = *port_mux[gpio_bank(ident)];
383 pmux &= ~(3 << offset);
384 pmux |= (function & 3) << offset;
385 *port_mux[gpio_bank(ident)] = pmux;
386 SSYNC();
387}
c58c2140
MH
388#else
389# define portmux_setup(...) do { } while (0)
390#endif
1394f032 391
a161bb05 392static int __init bfin_gpio_init(void)
1394f032 393{
c58c2140 394 printk(KERN_INFO "Blackfin GPIO Controller\n");
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395
396 return 0;
397}
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398arch_initcall(bfin_gpio_init);
399
400
d2b11a46 401#ifndef BF548_FAMILY
1394f032
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402/***********************************************************
403*
404* FUNCTIONS: Blackfin General Purpose Ports Access Functions
405*
406* INPUTS/OUTPUTS:
407* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
408*
409*
410* DESCRIPTION: These functions abstract direct register access
411* to Blackfin processor General Purpose
412* Ports Regsiters
413*
414* CAUTION: These functions do not belong to the GPIO Driver API
415*************************************************************
416* MODIFICATION HISTORY :
417**************************************************************/
418
419/* Set a specific bit */
420
421#define SET_GPIO(name) \
a2c8cfef 422void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
1394f032
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423{ \
424 unsigned long flags; \
6a01f230 425 local_irq_save_hw(flags); \
1394f032
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426 if (arg) \
427 gpio_bankb[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
428 else \
429 gpio_bankb[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \
2b39331a 430 AWA_DUMMY_READ(name); \
6a01f230 431 local_irq_restore_hw(flags); \
1394f032
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432} \
433EXPORT_SYMBOL(set_gpio_ ## name);
434
435SET_GPIO(dir)
436SET_GPIO(inen)
437SET_GPIO(polar)
438SET_GPIO(edge)
439SET_GPIO(both)
440
441
2b39331a
MH
442#if ANOMALY_05000311 || ANOMALY_05000323
443#define SET_GPIO_SC(name) \
a2c8cfef 444void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
2b39331a
MH
445{ \
446 unsigned long flags; \
6a01f230 447 local_irq_save_hw(flags); \
2b39331a
MH
448 if (arg) \
449 gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
450 else \
451 gpio_bankb[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
452 AWA_DUMMY_READ(name); \
6a01f230 453 local_irq_restore_hw(flags); \
2b39331a
MH
454} \
455EXPORT_SYMBOL(set_gpio_ ## name);
456#else
1394f032 457#define SET_GPIO_SC(name) \
a2c8cfef 458void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
1394f032 459{ \
1394f032
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460 if (arg) \
461 gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
462 else \
463 gpio_bankb[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
464} \
465EXPORT_SYMBOL(set_gpio_ ## name);
2b39331a 466#endif
1394f032
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467
468SET_GPIO_SC(maska)
469SET_GPIO_SC(maskb)
1394f032 470SET_GPIO_SC(data)
1394f032 471
2b39331a 472#if ANOMALY_05000311 || ANOMALY_05000323
a2c8cfef 473void set_gpio_toggle(unsigned gpio)
1394f032
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474{
475 unsigned long flags;
6a01f230 476 local_irq_save_hw(flags);
1394f032 477 gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
2b39331a 478 AWA_DUMMY_READ(toggle);
6a01f230 479 local_irq_restore_hw(flags);
1394f032
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480}
481#else
a2c8cfef 482void set_gpio_toggle(unsigned gpio)
1394f032 483{
1394f032
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484 gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
485}
486#endif
487EXPORT_SYMBOL(set_gpio_toggle);
488
489
490/*Set current PORT date (16-bit word)*/
491
2b39331a 492#if ANOMALY_05000311 || ANOMALY_05000323
1394f032 493#define SET_GPIO_P(name) \
a2c8cfef 494void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
1394f032 495{ \
2b39331a 496 unsigned long flags; \
6a01f230 497 local_irq_save_hw(flags); \
1394f032 498 gpio_bankb[gpio_bank(gpio)]->name = arg; \
2b39331a 499 AWA_DUMMY_READ(name); \
6a01f230 500 local_irq_restore_hw(flags); \
1394f032
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501} \
502EXPORT_SYMBOL(set_gpiop_ ## name);
2b39331a
MH
503#else
504#define SET_GPIO_P(name) \
a2c8cfef 505void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
2b39331a
MH
506{ \
507 gpio_bankb[gpio_bank(gpio)]->name = arg; \
508} \
509EXPORT_SYMBOL(set_gpiop_ ## name);
510#endif
1394f032 511
2b39331a 512SET_GPIO_P(data)
1394f032
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513SET_GPIO_P(dir)
514SET_GPIO_P(inen)
515SET_GPIO_P(polar)
516SET_GPIO_P(edge)
517SET_GPIO_P(both)
518SET_GPIO_P(maska)
519SET_GPIO_P(maskb)
520
1394f032 521/* Get a specific bit */
2b39331a
MH
522#if ANOMALY_05000311 || ANOMALY_05000323
523#define GET_GPIO(name) \
a2c8cfef 524unsigned short get_gpio_ ## name(unsigned gpio) \
2b39331a
MH
525{ \
526 unsigned long flags; \
527 unsigned short ret; \
6a01f230 528 local_irq_save_hw(flags); \
2b39331a
MH
529 ret = 0x01 & (gpio_bankb[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \
530 AWA_DUMMY_READ(name); \
6a01f230 531 local_irq_restore_hw(flags); \
2b39331a
MH
532 return ret; \
533} \
534EXPORT_SYMBOL(get_gpio_ ## name);
535#else
1394f032 536#define GET_GPIO(name) \
a2c8cfef 537unsigned short get_gpio_ ## name(unsigned gpio) \
1394f032
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538{ \
539 return (0x01 & (gpio_bankb[gpio_bank(gpio)]->name >> gpio_sub_n(gpio))); \
540} \
541EXPORT_SYMBOL(get_gpio_ ## name);
2b39331a 542#endif
1394f032 543
2b39331a 544GET_GPIO(data)
1394f032
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545GET_GPIO(dir)
546GET_GPIO(inen)
547GET_GPIO(polar)
548GET_GPIO(edge)
549GET_GPIO(both)
550GET_GPIO(maska)
551GET_GPIO(maskb)
552
1394f032
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553/*Get current PORT date (16-bit word)*/
554
2b39331a
MH
555#if ANOMALY_05000311 || ANOMALY_05000323
556#define GET_GPIO_P(name) \
a2c8cfef 557unsigned short get_gpiop_ ## name(unsigned gpio) \
2b39331a
MH
558{ \
559 unsigned long flags; \
560 unsigned short ret; \
6a01f230 561 local_irq_save_hw(flags); \
2b39331a
MH
562 ret = (gpio_bankb[gpio_bank(gpio)]->name); \
563 AWA_DUMMY_READ(name); \
6a01f230 564 local_irq_restore_hw(flags); \
2b39331a
MH
565 return ret; \
566} \
567EXPORT_SYMBOL(get_gpiop_ ## name);
568#else
1394f032 569#define GET_GPIO_P(name) \
a2c8cfef 570unsigned short get_gpiop_ ## name(unsigned gpio) \
1394f032
BW
571{ \
572 return (gpio_bankb[gpio_bank(gpio)]->name);\
573} \
574EXPORT_SYMBOL(get_gpiop_ ## name);
2b39331a 575#endif
1394f032 576
2b39331a 577GET_GPIO_P(data)
1394f032
BW
578GET_GPIO_P(dir)
579GET_GPIO_P(inen)
580GET_GPIO_P(polar)
581GET_GPIO_P(edge)
582GET_GPIO_P(both)
583GET_GPIO_P(maska)
584GET_GPIO_P(maskb)
585
1394f032
BW
586
587#ifdef CONFIG_PM
588/***********************************************************
589*
590* FUNCTIONS: Blackfin PM Setup API
591*
592* INPUTS/OUTPUTS:
593* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
594* type -
595* PM_WAKE_RISING
596* PM_WAKE_FALLING
597* PM_WAKE_HIGH
598* PM_WAKE_LOW
599* PM_WAKE_BOTH_EDGES
600*
601* DESCRIPTION: Blackfin PM Driver API
602*
603* CAUTION:
604*************************************************************
605* MODIFICATION HISTORY :
606**************************************************************/
a2c8cfef 607int gpio_pm_wakeup_request(unsigned gpio, unsigned char type)
1394f032
BW
608{
609 unsigned long flags;
610
611 if ((check_gpio(gpio) < 0) || !type)
612 return -EINVAL;
613
6a01f230 614 local_irq_save_hw(flags);
1394f032
BW
615 wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio);
616 wakeup_flags_map[gpio] = type;
6a01f230 617 local_irq_restore_hw(flags);
1394f032
BW
618
619 return 0;
620}
621EXPORT_SYMBOL(gpio_pm_wakeup_request);
622
a2c8cfef 623void gpio_pm_wakeup_free(unsigned gpio)
1394f032
BW
624{
625 unsigned long flags;
626
627 if (check_gpio(gpio) < 0)
628 return;
629
6a01f230 630 local_irq_save_hw(flags);
1394f032
BW
631
632 wakeup_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
633
6a01f230 634 local_irq_restore_hw(flags);
1394f032
BW
635}
636EXPORT_SYMBOL(gpio_pm_wakeup_free);
637
a2c8cfef 638static int bfin_gpio_wakeup_type(unsigned gpio, unsigned char type)
1394f032
BW
639{
640 port_setup(gpio, GPIO_USAGE);
641 set_gpio_dir(gpio, 0);
642 set_gpio_inen(gpio, 1);
643
644 if (type & (PM_WAKE_RISING | PM_WAKE_FALLING))
645 set_gpio_edge(gpio, 1);
646 else
647 set_gpio_edge(gpio, 0);
648
649 if ((type & (PM_WAKE_BOTH_EDGES)) == (PM_WAKE_BOTH_EDGES))
650 set_gpio_both(gpio, 1);
651 else
652 set_gpio_both(gpio, 0);
653
654 if ((type & (PM_WAKE_FALLING | PM_WAKE_LOW)))
655 set_gpio_polar(gpio, 1);
656 else
657 set_gpio_polar(gpio, 0);
658
659 SSYNC();
660
661 return 0;
662}
663
1efc80b5 664u32 bfin_pm_standby_setup(void)
1394f032 665{
1394f032
BW
666 u16 bank, mask, i, gpio;
667
1f83b8f1 668 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
1394f032
BW
669 mask = wakeup_map[gpio_bank(i)];
670 bank = gpio_bank(i);
671
672 gpio_bank_saved[bank].maskb = gpio_bankb[bank]->maskb;
673 gpio_bankb[bank]->maskb = 0;
674
675 if (mask) {
2f6f4bcd 676#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
1394f032
BW
677 gpio_bank_saved[bank].fer = *port_fer[bank];
678#endif
679 gpio_bank_saved[bank].inen = gpio_bankb[bank]->inen;
680 gpio_bank_saved[bank].polar = gpio_bankb[bank]->polar;
681 gpio_bank_saved[bank].dir = gpio_bankb[bank]->dir;
682 gpio_bank_saved[bank].edge = gpio_bankb[bank]->edge;
683 gpio_bank_saved[bank].both = gpio_bankb[bank]->both;
c58c2140
MH
684 gpio_bank_saved[bank].reserved =
685 reserved_gpio_map[bank];
1394f032
BW
686
687 gpio = i;
688
689 while (mask) {
cfefe3c6
MH
690 if ((mask & 1) && (wakeup_flags_map[gpio] !=
691 PM_WAKE_IGNORE)) {
c58c2140 692 reserved_gpio_map[gpio_bank(gpio)] |=
581d62ab
MH
693 gpio_bit(gpio);
694 bfin_gpio_wakeup_type(gpio,
695 wakeup_flags_map[gpio]);
1394f032
BW
696 set_gpio_data(gpio, 0); /*Clear*/
697 }
698 gpio++;
699 mask >>= 1;
700 }
701
cfefe3c6 702 bfin_internal_set_wake(sic_iwr_irqs[bank], 1);
1394f032
BW
703 gpio_bankb[bank]->maskb_set = wakeup_map[gpio_bank(i)];
704 }
705 }
706
2b39331a
MH
707 AWA_DUMMY_READ(maskb_set);
708
cfefe3c6 709 return 0;
1394f032
BW
710}
711
1efc80b5 712void bfin_pm_standby_restore(void)
1394f032
BW
713{
714 u16 bank, mask, i;
715
1f83b8f1 716 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
1394f032
BW
717 mask = wakeup_map[gpio_bank(i)];
718 bank = gpio_bank(i);
719
720 if (mask) {
2f6f4bcd 721#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
1394f032
BW
722 *port_fer[bank] = gpio_bank_saved[bank].fer;
723#endif
724 gpio_bankb[bank]->inen = gpio_bank_saved[bank].inen;
725 gpio_bankb[bank]->dir = gpio_bank_saved[bank].dir;
726 gpio_bankb[bank]->polar = gpio_bank_saved[bank].polar;
727 gpio_bankb[bank]->edge = gpio_bank_saved[bank].edge;
728 gpio_bankb[bank]->both = gpio_bank_saved[bank].both;
581d62ab 729
c58c2140
MH
730 reserved_gpio_map[bank] =
731 gpio_bank_saved[bank].reserved;
cfefe3c6 732 bfin_internal_set_wake(sic_iwr_irqs[bank], 0);
1394f032
BW
733 }
734
735 gpio_bankb[bank]->maskb = gpio_bank_saved[bank].maskb;
736 }
2b39331a 737 AWA_DUMMY_READ(maskb);
1394f032
BW
738}
739
1efc80b5
MH
740void bfin_gpio_pm_hibernate_suspend(void)
741{
742 int i, bank;
743
744 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
745 bank = gpio_bank(i);
746
2f6f4bcd 747#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
1efc80b5 748 gpio_bank_saved[bank].fer = *port_fer[bank];
2f6f4bcd 749#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
1efc80b5
MH
750 gpio_bank_saved[bank].mux = *port_mux[bank];
751#else
752 if (bank == 0)
753 gpio_bank_saved[bank].mux = bfin_read_PORT_MUX();
754#endif
755#endif
756 gpio_bank_saved[bank].data = gpio_bankb[bank]->data;
757 gpio_bank_saved[bank].inen = gpio_bankb[bank]->inen;
758 gpio_bank_saved[bank].polar = gpio_bankb[bank]->polar;
759 gpio_bank_saved[bank].dir = gpio_bankb[bank]->dir;
760 gpio_bank_saved[bank].edge = gpio_bankb[bank]->edge;
761 gpio_bank_saved[bank].both = gpio_bankb[bank]->both;
762 gpio_bank_saved[bank].maska = gpio_bankb[bank]->maska;
763 }
764
765 AWA_DUMMY_READ(maska);
766}
767
768void bfin_gpio_pm_hibernate_restore(void)
769{
770 int i, bank;
771
772 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
773 bank = gpio_bank(i);
774
2f6f4bcd
BW
775#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
776#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
1efc80b5
MH
777 *port_mux[bank] = gpio_bank_saved[bank].mux;
778#else
779 if (bank == 0)
780 bfin_write_PORT_MUX(gpio_bank_saved[bank].mux);
781#endif
782 *port_fer[bank] = gpio_bank_saved[bank].fer;
783#endif
784 gpio_bankb[bank]->inen = gpio_bank_saved[bank].inen;
785 gpio_bankb[bank]->dir = gpio_bank_saved[bank].dir;
786 gpio_bankb[bank]->polar = gpio_bank_saved[bank].polar;
787 gpio_bankb[bank]->edge = gpio_bank_saved[bank].edge;
788 gpio_bankb[bank]->both = gpio_bank_saved[bank].both;
789
790 gpio_bankb[bank]->data_set = gpio_bank_saved[bank].data
791 | gpio_bank_saved[bank].dir;
792
793 gpio_bankb[bank]->maska = gpio_bank_saved[bank].maska;
794 }
795 AWA_DUMMY_READ(maska);
796}
797
798
1394f032 799#endif
fac3cf43 800#else /* BF548_FAMILY */
1efc80b5
MH
801#ifdef CONFIG_PM
802
803u32 bfin_pm_standby_setup(void)
804{
805 return 0;
806}
807
808void bfin_pm_standby_restore(void)
809{
810
811}
812
813void bfin_gpio_pm_hibernate_suspend(void)
814{
815 int i, bank;
816
817 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
818 bank = gpio_bank(i);
819
820 gpio_bank_saved[bank].fer = gpio_array[bank]->port_fer;
821 gpio_bank_saved[bank].mux = gpio_array[bank]->port_mux;
822 gpio_bank_saved[bank].data = gpio_array[bank]->port_data;
823 gpio_bank_saved[bank].data = gpio_array[bank]->port_data;
824 gpio_bank_saved[bank].inen = gpio_array[bank]->port_inen;
825 gpio_bank_saved[bank].dir = gpio_array[bank]->port_dir_set;
826 }
827}
828
829void bfin_gpio_pm_hibernate_restore(void)
830{
831 int i, bank;
832
833 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
834 bank = gpio_bank(i);
835
836 gpio_array[bank]->port_mux = gpio_bank_saved[bank].mux;
837 gpio_array[bank]->port_fer = gpio_bank_saved[bank].fer;
838 gpio_array[bank]->port_inen = gpio_bank_saved[bank].inen;
839 gpio_array[bank]->port_dir_set = gpio_bank_saved[bank].dir;
840 gpio_array[bank]->port_set = gpio_bank_saved[bank].data
841 | gpio_bank_saved[bank].dir;
842 }
843}
844#endif
fac3cf43 845
a2c8cfef 846unsigned short get_gpio_dir(unsigned gpio)
fac3cf43
MH
847{
848 return (0x01 & (gpio_array[gpio_bank(gpio)]->port_dir_clear >> gpio_sub_n(gpio)));
849}
850EXPORT_SYMBOL(get_gpio_dir);
851
d2b11a46 852#endif /* BF548_FAMILY */
1394f032 853
d2b11a46
MH
854/***********************************************************
855*
856* FUNCTIONS: Blackfin Peripheral Resource Allocation
857* and PortMux Setup
858*
859* INPUTS/OUTPUTS:
860* per Peripheral Identifier
861* label String
862*
863* DESCRIPTION: Blackfin Peripheral Resource Allocation and Setup API
864*
865* CAUTION:
866*************************************************************
867* MODIFICATION HISTORY :
868**************************************************************/
869
d2b11a46
MH
870int peripheral_request(unsigned short per, const char *label)
871{
872 unsigned long flags;
873 unsigned short ident = P_IDENT(per);
874
875 /*
876 * Don't cares are pins with only one dedicated function
877 */
c58c2140 878
d2b11a46
MH
879 if (per & P_DONTCARE)
880 return 0;
881
882 if (!(per & P_DEFINED))
883 return -ENODEV;
884
6a01f230 885 local_irq_save_hw(flags);
d2b11a46 886
6a87d29b
MF
887 /* If a pin can be muxed as either GPIO or peripheral, make
888 * sure it is not already a GPIO pin when we request it.
889 */
890 if (unlikely(!check_gpio(ident) &&
891 reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
f85c4abd 892 dump_stack();
d2b11a46 893 printk(KERN_ERR
6c7ec0ec 894 "%s: Peripheral %d is already reserved as GPIO by %s !\n",
b85d858b 895 __func__, ident, get_label(ident));
6a01f230 896 local_irq_restore_hw(flags);
d2b11a46
MH
897 return -EBUSY;
898 }
899
900 if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
901
d171c233
MF
902 /*
903 * Pin functions like AMC address strobes my
904 * be requested and used by several drivers
905 */
d2b11a46 906
6c7ec0ec
MF
907#ifdef BF548_FAMILY
908 u16 funct = get_portmux(ident);
d2b11a46 909
6c7ec0ec
MF
910 if (!((per & P_MAYSHARE) && (funct == P_FUNCT2MUX(per)))) {
911#else
912 if (!(per & P_MAYSHARE)) {
913#endif
d171c233
MF
914 /*
915 * Allow that the identical pin function can
916 * be requested from the same driver twice
917 */
d2b11a46 918
d171c233
MF
919 if (cmp_label(ident, label) == 0)
920 goto anyway;
d2b11a46 921
f85c4abd 922 dump_stack();
d2b11a46
MH
923 printk(KERN_ERR
924 "%s: Peripheral %d function %d is already reserved by %s !\n",
b85d858b 925 __func__, ident, P_FUNCT2MUX(per), get_label(ident));
6a01f230 926 local_irq_restore_hw(flags);
d2b11a46
MH
927 return -EBUSY;
928 }
929 }
930
d171c233 931 anyway:
d2b11a46
MH
932 reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
933
6c7ec0ec 934#ifdef BF548_FAMILY
d2b11a46 935 portmux_setup(ident, P_FUNCT2MUX(per));
d2b11a46 936#else
c58c2140 937 portmux_setup(per, P_FUNCT2MUX(per));
6c7ec0ec 938#endif
c58c2140
MH
939 port_setup(ident, PERIPHERAL_USAGE);
940
6a01f230 941 local_irq_restore_hw(flags);
c58c2140
MH
942 set_label(ident, label);
943
944 return 0;
945}
946EXPORT_SYMBOL(peripheral_request);
947
68179371 948int peripheral_request_list(const unsigned short per[], const char *label)
c58c2140
MH
949{
950 u16 cnt;
951 int ret;
952
953 for (cnt = 0; per[cnt] != 0; cnt++) {
314c98d5 954
c58c2140 955 ret = peripheral_request(per[cnt], label);
314c98d5
MH
956
957 if (ret < 0) {
d171c233 958 for ( ; cnt > 0; cnt--)
314c98d5 959 peripheral_free(per[cnt - 1]);
d171c233
MF
960
961 return ret;
314c98d5 962 }
c58c2140
MH
963 }
964
965 return 0;
966}
967EXPORT_SYMBOL(peripheral_request_list);
968
969void peripheral_free(unsigned short per)
970{
971 unsigned long flags;
972 unsigned short ident = P_IDENT(per);
973
974 if (per & P_DONTCARE)
975 return;
976
977 if (!(per & P_DEFINED))
978 return;
979
6a01f230 980 local_irq_save_hw(flags);
c58c2140 981
d171c233 982 if (unlikely(!(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident)))) {
6a01f230 983 local_irq_restore_hw(flags);
c58c2140
MH
984 return;
985 }
986
d171c233 987 if (!(per & P_MAYSHARE))
c58c2140 988 port_setup(ident, GPIO_USAGE);
c58c2140
MH
989
990 reserved_peri_map[gpio_bank(ident)] &= ~gpio_bit(ident);
991
2acde902
MH
992 set_label(ident, "free");
993
6a01f230 994 local_irq_restore_hw(flags);
c58c2140
MH
995}
996EXPORT_SYMBOL(peripheral_free);
997
68179371 998void peripheral_free_list(const unsigned short per[])
c58c2140
MH
999{
1000 u16 cnt;
d171c233 1001 for (cnt = 0; per[cnt] != 0; cnt++)
c58c2140 1002 peripheral_free(per[cnt]);
c58c2140
MH
1003}
1004EXPORT_SYMBOL(peripheral_free_list);
1005
1394f032
BW
1006/***********************************************************
1007*
1008* FUNCTIONS: Blackfin GPIO Driver
1009*
1010* INPUTS/OUTPUTS:
d2b11a46
MH
1011* gpio PIO Number between 0 and MAX_BLACKFIN_GPIOS
1012* label String
1394f032
BW
1013*
1014* DESCRIPTION: Blackfin GPIO Driver API
1015*
1016* CAUTION:
1017*************************************************************
1018* MODIFICATION HISTORY :
1019**************************************************************/
1020
a4f0b32c 1021int bfin_gpio_request(unsigned gpio, const char *label)
1394f032
BW
1022{
1023 unsigned long flags;
1024
1025 if (check_gpio(gpio) < 0)
1026 return -EINVAL;
1027
6a01f230 1028 local_irq_save_hw(flags);
1394f032 1029
2acde902
MH
1030 /*
1031 * Allow that the identical GPIO can
1032 * be requested from the same driver twice
1033 * Do nothing and return -
1034 */
1035
1036 if (cmp_label(gpio, label) == 0) {
6a01f230 1037 local_irq_restore_hw(flags);
2acde902
MH
1038 return 0;
1039 }
1040
c58c2140 1041 if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
f85c4abd 1042 dump_stack();
d2b11a46 1043 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
9570ff4a 1044 gpio, get_label(gpio));
6a01f230 1045 local_irq_restore_hw(flags);
d2b11a46
MH
1046 return -EBUSY;
1047 }
1048 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
f85c4abd 1049 dump_stack();
d2b11a46
MH
1050 printk(KERN_ERR
1051 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
1052 gpio, get_label(gpio));
6a01f230 1053 local_irq_restore_hw(flags);
1394f032
BW
1054 return -EBUSY;
1055 }
a2be3931 1056 if (unlikely(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
9570ff4a
GY
1057 printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!"
1058 " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio);
a2be3931
MH
1059 }
1060#ifndef BF548_FAMILY
1061 else { /* Reset POLAR setting when acquiring a gpio for the first time */
1062 set_gpio_polar(gpio, 0);
1063 }
1064#endif
d2b11a46 1065
c58c2140 1066 reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
9570ff4a 1067 set_label(gpio, label);
1394f032 1068
6a01f230 1069 local_irq_restore_hw(flags);
1394f032
BW
1070
1071 port_setup(gpio, GPIO_USAGE);
1072
1073 return 0;
1074}
a4f0b32c 1075EXPORT_SYMBOL(bfin_gpio_request);
1394f032 1076
a4f0b32c 1077void bfin_gpio_free(unsigned gpio)
1394f032
BW
1078{
1079 unsigned long flags;
1080
1081 if (check_gpio(gpio) < 0)
1082 return;
1083
45c4f2a0
UKK
1084 might_sleep();
1085
6a01f230 1086 local_irq_save_hw(flags);
1394f032 1087
c58c2140 1088 if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
1394f032 1089 dump_stack();
f85c4abd 1090 gpio_error(gpio);
6a01f230 1091 local_irq_restore_hw(flags);
1394f032
BW
1092 return;
1093 }
1094
c58c2140 1095 reserved_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
1394f032 1096
2acde902
MH
1097 set_label(gpio, "free");
1098
6a01f230 1099 local_irq_restore_hw(flags);
1394f032 1100}
a4f0b32c 1101EXPORT_SYMBOL(bfin_gpio_free);
1394f032 1102
9570ff4a
GY
1103int bfin_gpio_irq_request(unsigned gpio, const char *label)
1104{
1105 unsigned long flags;
1106
1107 if (check_gpio(gpio) < 0)
1108 return -EINVAL;
1109
6a01f230 1110 local_irq_save_hw(flags);
9570ff4a
GY
1111
1112 if (unlikely(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1113 dump_stack();
1114 printk(KERN_ERR
1115 "bfin-gpio: GPIO %d is already reserved as gpio-irq !\n",
1116 gpio);
6a01f230 1117 local_irq_restore_hw(flags);
9570ff4a
GY
1118 return -EBUSY;
1119 }
1120 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1121 dump_stack();
1122 printk(KERN_ERR
1123 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
1124 gpio, get_label(gpio));
6a01f230 1125 local_irq_restore_hw(flags);
9570ff4a
GY
1126 return -EBUSY;
1127 }
1128 if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))
1129 printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved by %s! "
1130 "(Documentation/blackfin/bfin-gpio-notes.txt)\n",
1131 gpio, get_label(gpio));
1132
1133 reserved_gpio_irq_map[gpio_bank(gpio)] |= gpio_bit(gpio);
1134 set_label(gpio, label);
1135
6a01f230 1136 local_irq_restore_hw(flags);
9570ff4a
GY
1137
1138 port_setup(gpio, GPIO_USAGE);
1139
1140 return 0;
1141}
1142
1143void bfin_gpio_irq_free(unsigned gpio)
1144{
1145 unsigned long flags;
1146
1147 if (check_gpio(gpio) < 0)
1148 return;
1149
6a01f230 1150 local_irq_save_hw(flags);
9570ff4a
GY
1151
1152 if (unlikely(!(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
1153 dump_stack();
1154 gpio_error(gpio);
6a01f230 1155 local_irq_restore_hw(flags);
9570ff4a
GY
1156 return;
1157 }
1158
1159 reserved_gpio_irq_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
1160
1161 set_label(gpio, "free");
1162
6a01f230 1163 local_irq_restore_hw(flags);
9570ff4a
GY
1164}
1165
acbcd263 1166
d2b11a46 1167#ifdef BF548_FAMILY
a4f0b32c 1168int bfin_gpio_direction_input(unsigned gpio)
d2b11a46
MH
1169{
1170 unsigned long flags;
1171
acbcd263
MH
1172 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1173 gpio_error(gpio);
1174 return -EINVAL;
1175 }
1176
6a01f230 1177 local_irq_save_hw(flags);
d2b11a46
MH
1178 gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
1179 gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
6a01f230 1180 local_irq_restore_hw(flags);
acbcd263
MH
1181
1182 return 0;
d2b11a46 1183}
a4f0b32c 1184EXPORT_SYMBOL(bfin_gpio_direction_input);
d2b11a46 1185
a4f0b32c 1186int bfin_gpio_direction_output(unsigned gpio, int value)
d2b11a46
MH
1187{
1188 unsigned long flags;
1189
acbcd263
MH
1190 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1191 gpio_error(gpio);
1192 return -EINVAL;
1193 }
d2b11a46 1194
6a01f230 1195 local_irq_save_hw(flags);
d2b11a46 1196 gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio);
acbcd263 1197 gpio_set_value(gpio, value);
d2b11a46 1198 gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio);
6a01f230 1199 local_irq_restore_hw(flags);
acbcd263
MH
1200
1201 return 0;
d2b11a46 1202}
a4f0b32c 1203EXPORT_SYMBOL(bfin_gpio_direction_output);
d2b11a46 1204
a4f0b32c 1205void bfin_gpio_set_value(unsigned gpio, int arg)
d2b11a46
MH
1206{
1207 if (arg)
1208 gpio_array[gpio_bank(gpio)]->port_set = gpio_bit(gpio);
1209 else
1210 gpio_array[gpio_bank(gpio)]->port_clear = gpio_bit(gpio);
d2b11a46 1211}
a4f0b32c 1212EXPORT_SYMBOL(bfin_gpio_set_value);
d2b11a46 1213
a4f0b32c 1214int bfin_gpio_get_value(unsigned gpio)
d2b11a46
MH
1215{
1216 return (1 & (gpio_array[gpio_bank(gpio)]->port_data >> gpio_sub_n(gpio)));
1217}
a4f0b32c 1218EXPORT_SYMBOL(bfin_gpio_get_value);
d2b11a46 1219
affee2b2
MH
1220void bfin_gpio_irq_prepare(unsigned gpio)
1221{
1222 unsigned long flags;
1223
1224 port_setup(gpio, GPIO_USAGE);
1225
6a01f230 1226 local_irq_save_hw(flags);
affee2b2
MH
1227 gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
1228 gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
6a01f230 1229 local_irq_restore_hw(flags);
affee2b2
MH
1230}
1231
d2b11a46
MH
1232#else
1233
a4f0b32c 1234int bfin_gpio_get_value(unsigned gpio)
803a8d2a
MH
1235{
1236 unsigned long flags;
1237 int ret;
1238
1239 if (unlikely(get_gpio_edge(gpio))) {
6a01f230 1240 local_irq_save_hw(flags);
803a8d2a
MH
1241 set_gpio_edge(gpio, 0);
1242 ret = get_gpio_data(gpio);
1243 set_gpio_edge(gpio, 1);
6a01f230 1244 local_irq_restore_hw(flags);
803a8d2a
MH
1245
1246 return ret;
1247 } else
1248 return get_gpio_data(gpio);
1249}
a4f0b32c 1250EXPORT_SYMBOL(bfin_gpio_get_value);
803a8d2a
MH
1251
1252
a4f0b32c 1253int bfin_gpio_direction_input(unsigned gpio)
1394f032
BW
1254{
1255 unsigned long flags;
1256
acbcd263
MH
1257 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1258 gpio_error(gpio);
1259 return -EINVAL;
1260 }
1394f032 1261
6a01f230 1262 local_irq_save_hw(flags);
1394f032
BW
1263 gpio_bankb[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
1264 gpio_bankb[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
2b39331a 1265 AWA_DUMMY_READ(inen);
6a01f230 1266 local_irq_restore_hw(flags);
acbcd263
MH
1267
1268 return 0;
1394f032 1269}
a4f0b32c 1270EXPORT_SYMBOL(bfin_gpio_direction_input);
1394f032 1271
a4f0b32c 1272int bfin_gpio_direction_output(unsigned gpio, int value)
1394f032
BW
1273{
1274 unsigned long flags;
1275
acbcd263
MH
1276 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1277 gpio_error(gpio);
1278 return -EINVAL;
1279 }
1394f032 1280
6a01f230 1281 local_irq_save_hw(flags);
1394f032 1282 gpio_bankb[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
a2c8cfef
MH
1283
1284 if (value)
1285 gpio_bankb[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
1286 else
1287 gpio_bankb[gpio_bank(gpio)]->data_clear = gpio_bit(gpio);
1288
1394f032 1289 gpio_bankb[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
2b39331a 1290 AWA_DUMMY_READ(dir);
6a01f230 1291 local_irq_restore_hw(flags);
acbcd263
MH
1292
1293 return 0;
1394f032 1294}
a4f0b32c 1295EXPORT_SYMBOL(bfin_gpio_direction_output);
168f1212
MF
1296
1297/* If we are booting from SPI and our board lacks a strong enough pull up,
1298 * the core can reset and execute the bootrom faster than the resistor can
1299 * pull the signal logically high. To work around this (common) error in
1300 * board design, we explicitly set the pin back to GPIO mode, force /CS
1301 * high, and wait for the electrons to do their thing.
1302 *
1303 * This function only makes sense to be called from reset code, but it
1304 * lives here as we need to force all the GPIO states w/out going through
1305 * BUG() checks and such.
1306 */
1307void bfin_gpio_reset_spi0_ssel1(void)
1308{
4d5f4ed3
MH
1309 u16 gpio = P_IDENT(P_SPI0_SSEL1);
1310
1311 port_setup(gpio, GPIO_USAGE);
1312 gpio_bankb[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
a2c8cfef 1313 AWA_DUMMY_READ(data_set);
168f1212
MF
1314 udelay(1);
1315}
d2b11a46 1316
affee2b2
MH
1317void bfin_gpio_irq_prepare(unsigned gpio)
1318{
1319 port_setup(gpio, GPIO_USAGE);
1320}
1321
d2b11a46 1322#endif /*BF548_FAMILY */
1545a111
MF
1323
1324#if defined(CONFIG_PROC_FS)
1325static int gpio_proc_read(char *buf, char **start, off_t offset,
1326 int len, int *unused_i, void *unused_v)
1327{
9570ff4a 1328 int c, irq, gpio, outlen = 0;
1545a111
MF
1329
1330 for (c = 0; c < MAX_RESOURCES; c++) {
9570ff4a
GY
1331 irq = reserved_gpio_irq_map[gpio_bank(c)] & gpio_bit(c);
1332 gpio = reserved_gpio_map[gpio_bank(c)] & gpio_bit(c);
1333 if (!check_gpio(c) && (gpio || irq))
1334 len = sprintf(buf, "GPIO_%d: \t%s%s \t\tGPIO %s\n", c,
1335 get_label(c), (gpio && irq) ? " *" : "",
1336 get_gpio_dir(c) ? "OUTPUT" : "INPUT");
1545a111 1337 else if (reserved_peri_map[gpio_bank(c)] & gpio_bit(c))
8eb3e3bf 1338 len = sprintf(buf, "GPIO_%d: \t%s \t\tPeripheral\n", c, get_label(c));
1545a111
MF
1339 else
1340 continue;
1341 buf += len;
1342 outlen += len;
1343 }
1344 return outlen;
1345}
1346
1347static __init int gpio_register_proc(void)
1348{
1349 struct proc_dir_entry *proc_gpio;
1350
1351 proc_gpio = create_proc_entry("gpio", S_IRUGO, NULL);
1352 if (proc_gpio)
1353 proc_gpio->read_proc = gpio_proc_read;
1354 return proc_gpio != NULL;
1355}
1545a111
MF
1356__initcall(gpio_register_proc);
1357#endif
a4f0b32c
MH
1358
1359#ifdef CONFIG_GPIOLIB
1360int bfin_gpiolib_direction_input(struct gpio_chip *chip, unsigned gpio)
1361{
1362 return bfin_gpio_direction_input(gpio);
1363}
1364
1365int bfin_gpiolib_direction_output(struct gpio_chip *chip, unsigned gpio, int level)
1366{
1367 return bfin_gpio_direction_output(gpio, level);
1368}
1369
1370int bfin_gpiolib_get_value(struct gpio_chip *chip, unsigned gpio)
1371{
1372 return bfin_gpio_get_value(gpio);
1373}
1374
1375void bfin_gpiolib_set_value(struct gpio_chip *chip, unsigned gpio, int value)
1376{
1377#ifdef BF548_FAMILY
1378 return bfin_gpio_set_value(gpio, value);
1379#else
1380 return set_gpio_data(gpio, value);
1381#endif
1382}
1383
1384int bfin_gpiolib_gpio_request(struct gpio_chip *chip, unsigned gpio)
1385{
1386 return bfin_gpio_request(gpio, chip->label);
1387}
1388
1389void bfin_gpiolib_gpio_free(struct gpio_chip *chip, unsigned gpio)
1390{
1391 return bfin_gpio_free(gpio);
1392}
1393
1394static struct gpio_chip bfin_chip = {
1395 .label = "Blackfin-GPIOlib",
1396 .direction_input = bfin_gpiolib_direction_input,
1397 .get = bfin_gpiolib_get_value,
1398 .direction_output = bfin_gpiolib_direction_output,
1399 .set = bfin_gpiolib_set_value,
1400 .request = bfin_gpiolib_gpio_request,
1401 .free = bfin_gpiolib_gpio_free,
1402 .base = 0,
1403 .ngpio = MAX_BLACKFIN_GPIOS,
1404};
1405
1406static int __init bfin_gpiolib_setup(void)
1407{
1408 return gpiochip_add(&bfin_chip);
1409}
1410arch_initcall(bfin_gpiolib_setup);
1411#endif