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Blackfin arch: Cleanup and unify Blackfin IRQ and GPIO IRQ handling
[mirror_ubuntu-artful-kernel.git] / arch / blackfin / kernel / bfin_gpio.c
CommitLineData
1394f032
BW		 1/*
2 * File: arch/blackfin/kernel/bfin_gpio.c
3 * Based on:
4 * Author: Michael Hennerich (hennerich@blackfin.uclinux.org)
5 *
6 * Created:
7 * Description: GPIO Abstraction Layer
8 *
9 * Modified:
a2c8cfef 10 * Copyright 2008 Analog Devices Inc.
1394f032
BW		 11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30/*
d2b11a46 31* Number BF537/6/4 BF561 BF533/2/1 BF549/8/4/2
1394f032 32*
d2b11a46 33* GPIO_0 PF0 PF0 PF0 PA0...PJ13
1394f032
BW		 34* GPIO_1 PF1 PF1 PF1
35* GPIO_2 PF2 PF2 PF2
36* GPIO_3 PF3 PF3 PF3
37* GPIO_4 PF4 PF4 PF4
38* GPIO_5 PF5 PF5 PF5
39* GPIO_6 PF6 PF6 PF6
40* GPIO_7 PF7 PF7 PF7
41* GPIO_8 PF8 PF8 PF8
42* GPIO_9 PF9 PF9 PF9
43* GPIO_10 PF10 PF10 PF10
44* GPIO_11 PF11 PF11 PF11
45* GPIO_12 PF12 PF12 PF12
46* GPIO_13 PF13 PF13 PF13
47* GPIO_14 PF14 PF14 PF14
48* GPIO_15 PF15 PF15 PF15
49* GPIO_16 PG0 PF16
50* GPIO_17 PG1 PF17
51* GPIO_18 PG2 PF18
52* GPIO_19 PG3 PF19
53* GPIO_20 PG4 PF20
54* GPIO_21 PG5 PF21
55* GPIO_22 PG6 PF22
56* GPIO_23 PG7 PF23
57* GPIO_24 PG8 PF24
58* GPIO_25 PG9 PF25
59* GPIO_26 PG10 PF26
60* GPIO_27 PG11 PF27
61* GPIO_28 PG12 PF28
62* GPIO_29 PG13 PF29
63* GPIO_30 PG14 PF30
64* GPIO_31 PG15 PF31
65* GPIO_32 PH0 PF32
66* GPIO_33 PH1 PF33
67* GPIO_34 PH2 PF34
68* GPIO_35 PH3 PF35
69* GPIO_36 PH4 PF36
70* GPIO_37 PH5 PF37
71* GPIO_38 PH6 PF38
72* GPIO_39 PH7 PF39
73* GPIO_40 PH8 PF40
74* GPIO_41 PH9 PF41
75* GPIO_42 PH10 PF42
76* GPIO_43 PH11 PF43
77* GPIO_44 PH12 PF44
78* GPIO_45 PH13 PF45
79* GPIO_46 PH14 PF46
80* GPIO_47 PH15 PF47
81*/
82
168f1212 83#include <linux/delay.h>
1394f032
BW		 84#include <linux/module.h>
85#include <linux/err.h>
1545a111 86#include <linux/proc_fs.h>
1394f032
BW		 87#include <asm/blackfin.h>
88#include <asm/gpio.h>
c58c2140 89#include <asm/portmux.h>
1394f032
BW		 90#include <linux/irq.h>
91
2b39331a
MH		 92#if ANOMALY_05000311 || ANOMALY_05000323
93enum {
94 AWA_data = SYSCR,
95 AWA_data_clear = SYSCR,
96 AWA_data_set = SYSCR,
97 AWA_toggle = SYSCR,
6ed83942
GY		 98 AWA_maska = BFIN_UART_SCR,
99 AWA_maska_clear = BFIN_UART_SCR,
100 AWA_maska_set = BFIN_UART_SCR,
101 AWA_maska_toggle = BFIN_UART_SCR,
102 AWA_maskb = BFIN_UART_GCTL,
103 AWA_maskb_clear = BFIN_UART_GCTL,
104 AWA_maskb_set = BFIN_UART_GCTL,
105 AWA_maskb_toggle = BFIN_UART_GCTL,
2b39331a
MH		 106 AWA_dir = SPORT1_STAT,
107 AWA_polar = SPORT1_STAT,
108 AWA_edge = SPORT1_STAT,
109 AWA_both = SPORT1_STAT,
110#if ANOMALY_05000311
111 AWA_inen = TIMER_ENABLE,
112#elif ANOMALY_05000323
113 AWA_inen = DMA1_1_CONFIG,
114#endif
115};
116 /* Anomaly Workaround */
117#define AWA_DUMMY_READ(name) bfin_read16(AWA_ ## name)
118#else
119#define AWA_DUMMY_READ(...) do { } while (0)
120#endif
121
dc26aec2 122#if defined(BF533_FAMILY) || defined(BF538_FAMILY)
397861cd 123static struct gpio_port_t *gpio_bankb[] = {
1394f032
BW		 124 (struct gpio_port_t *) FIO_FLAG_D,
125};
126#endif
127
2f6f4bcd 128#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
397861cd 129static struct gpio_port_t *gpio_bankb[] = {
1394f032
BW		 130 (struct gpio_port_t *) PORTFIO,
131 (struct gpio_port_t *) PORTGIO,
132 (struct gpio_port_t *) PORTHIO,
133};
134
397861cd 135static unsigned short *port_fer[] = {
1394f032
BW		 136 (unsigned short *) PORTF_FER,
137 (unsigned short *) PORTG_FER,
138 (unsigned short *) PORTH_FER,
139};
1394f032
BW		 140#endif
141
2f6f4bcd 142#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
397861cd 143static unsigned short *port_mux[] = {
59003145
MH		 144 (unsigned short *) PORTF_MUX,
145 (unsigned short *) PORTG_MUX,
146 (unsigned short *) PORTH_MUX,
147};
148
149static const
150u8 pmux_offset[][16] =
151 {{ 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 4, 6, 8, 8, 10, 10 }, /* PORTF */
152 { 0, 0, 0, 0, 0, 2, 2, 4, 4, 6, 8, 10, 10, 10, 12, 12 }, /* PORTG */
153 { 0, 0, 0, 0, 0, 0, 0, 0, 2, 4, 4, 4, 4, 4, 4, 4 }, /* PORTH */
154 };
155#endif
156
1394f032 157#ifdef BF561_FAMILY
397861cd 158static struct gpio_port_t *gpio_bankb[] = {
1394f032
BW		 159 (struct gpio_port_t *) FIO0_FLAG_D,
160 (struct gpio_port_t *) FIO1_FLAG_D,
161 (struct gpio_port_t *) FIO2_FLAG_D,
162};
163#endif
164
d2b11a46 165#ifdef BF548_FAMILY
397861cd 166static struct gpio_port_t *gpio_array[] = {
d2b11a46
MH		 167 (struct gpio_port_t *)PORTA_FER,
168 (struct gpio_port_t *)PORTB_FER,
169 (struct gpio_port_t *)PORTC_FER,
170 (struct gpio_port_t *)PORTD_FER,
171 (struct gpio_port_t *)PORTE_FER,
172 (struct gpio_port_t *)PORTF_FER,
173 (struct gpio_port_t *)PORTG_FER,
174 (struct gpio_port_t *)PORTH_FER,
175 (struct gpio_port_t *)PORTI_FER,
176 (struct gpio_port_t *)PORTJ_FER,
177};
178#endif
179
397861cd 180static unsigned short reserved_gpio_map[GPIO_BANK_NUM];
fac3cf43 181static unsigned short reserved_peri_map[gpio_bank(MAX_RESOURCES)];
c58c2140 182
8c613623
MH		 183#define RESOURCE_LABEL_SIZE 16
184
fac3cf43 185static struct str_ident {
8c613623 186 char name[RESOURCE_LABEL_SIZE];
fac3cf43 187} str_ident[MAX_RESOURCES];
1394f032 188
1efc80b5
MH		 189#if defined(CONFIG_PM)
190#if defined(CONFIG_BF54x)
397861cd 191static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM];
1efc80b5 192#else
397861cd 193static unsigned short wakeup_map[GPIO_BANK_NUM];
1394f032 194static unsigned char wakeup_flags_map[MAX_BLACKFIN_GPIOS];
397861cd 195static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM];
1394f032
BW		 196
197#ifdef BF533_FAMILY
397861cd 198static unsigned int sic_iwr_irqs[] = {IRQ_PROG_INTB};
1394f032
BW		 199#endif
200
201#ifdef BF537_FAMILY
397861cd 202static unsigned int sic_iwr_irqs[] = {IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX};
1394f032
BW		 203#endif
204
dc26aec2 205#ifdef BF538_FAMILY
397861cd 206static unsigned int sic_iwr_irqs[] = {IRQ_PORTF_INTB};
dc26aec2
MH		 207#endif
208
2f6f4bcd 209#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
397861cd 210static unsigned int sic_iwr_irqs[] = {IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB};
59003145
MH		 211#endif
212
1394f032 213#ifdef BF561_FAMILY
397861cd 214static unsigned int sic_iwr_irqs[] = {IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB};
1394f032 215#endif
1efc80b5 216#endif
1394f032
BW		 217#endif /* CONFIG_PM */
218
a2c8cfef 219inline int check_gpio(unsigned gpio)
d2b11a46 220{
27228b2e 221#if defined(BF548_FAMILY)
d2b11a46
MH		 222 if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
223 || gpio == GPIO_PH14 || gpio == GPIO_PH15
27228b2e 224 || gpio == GPIO_PJ14 || gpio == GPIO_PJ15)
d2b11a46 225 return -EINVAL;
27228b2e 226#endif
e7613aab 227 if (gpio >= MAX_BLACKFIN_GPIOS)
1394f032
BW		 228 return -EINVAL;
229 return 0;
230}
231
74c04503 232static void gpio_error(unsigned gpio)
acbcd263
MH		 233{
234 printk(KERN_ERR "bfin-gpio: GPIO %d wasn't requested!\n", gpio);
235}
236
c58c2140
MH		 237static void set_label(unsigned short ident, const char *label)
238{
e9fae189 239 if (label) {
8c613623 240 strncpy(str_ident[ident].name, label,
c58c2140 241 RESOURCE_LABEL_SIZE);
8c613623 242 str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0;
c58c2140
MH		 243 }
244}
245
246static char *get_label(unsigned short ident)
247{
8c613623 248 return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN");
c58c2140
MH		 249}
250
251static int cmp_label(unsigned short ident, const char *label)
252{
fac3cf43
MH		 253 if (label == NULL) {
254 dump_stack();
255 printk(KERN_ERR "Please provide none-null label\n");
256 }
257
e9fae189 258 if (label)
1f7d373f 259 return strcmp(str_ident[ident].name, label);
c58c2140
MH		 260 else
261 return -EINVAL;
262}
263
a2c8cfef 264static void port_setup(unsigned gpio, unsigned short usage)
1394f032 265{
a2d03a1d
MF		 266 if (check_gpio(gpio))
267 return;
268
269#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
270 if (usage == GPIO_USAGE)
271 *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
272 else
273 *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
274 SSYNC();
d2b11a46 275#elif defined(BF548_FAMILY)
d2b11a46
MH		 276 if (usage == GPIO_USAGE)
277 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
278 else
279 gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
280 SSYNC();
1394f032 281#endif
a2d03a1d 282}
1394f032 283
c58c2140 284#ifdef BF537_FAMILY
8c613623
MH		 285static struct {
286 unsigned short res;
287 unsigned short offset;
288} port_mux_lut[] = {
289 {.res = P_PPI0_D13, .offset = 11},
290 {.res = P_PPI0_D14, .offset = 11},
291 {.res = P_PPI0_D15, .offset = 11},
292 {.res = P_SPORT1_TFS, .offset = 11},
293 {.res = P_SPORT1_TSCLK, .offset = 11},
294 {.res = P_SPORT1_DTPRI, .offset = 11},
295 {.res = P_PPI0_D10, .offset = 10},
296 {.res = P_PPI0_D11, .offset = 10},
297 {.res = P_PPI0_D12, .offset = 10},
298 {.res = P_SPORT1_RSCLK, .offset = 10},
299 {.res = P_SPORT1_RFS, .offset = 10},
300 {.res = P_SPORT1_DRPRI, .offset = 10},
301 {.res = P_PPI0_D8, .offset = 9},
302 {.res = P_PPI0_D9, .offset = 9},
303 {.res = P_SPORT1_DRSEC, .offset = 9},
304 {.res = P_SPORT1_DTSEC, .offset = 9},
305 {.res = P_TMR2, .offset = 8},
306 {.res = P_PPI0_FS3, .offset = 8},
307 {.res = P_TMR3, .offset = 7},
308 {.res = P_SPI0_SSEL4, .offset = 7},
309 {.res = P_TMR4, .offset = 6},
310 {.res = P_SPI0_SSEL5, .offset = 6},
311 {.res = P_TMR5, .offset = 5},
312 {.res = P_SPI0_SSEL6, .offset = 5},
313 {.res = P_UART1_RX, .offset = 4},
314 {.res = P_UART1_TX, .offset = 4},
315 {.res = P_TMR6, .offset = 4},
316 {.res = P_TMR7, .offset = 4},
317 {.res = P_UART0_RX, .offset = 3},
318 {.res = P_UART0_TX, .offset = 3},
319 {.res = P_DMAR0, .offset = 3},
320 {.res = P_DMAR1, .offset = 3},
321 {.res = P_SPORT0_DTSEC, .offset = 1},
322 {.res = P_SPORT0_DRSEC, .offset = 1},
323 {.res = P_CAN0_RX, .offset = 1},
324 {.res = P_CAN0_TX, .offset = 1},
325 {.res = P_SPI0_SSEL7, .offset = 1},
326 {.res = P_SPORT0_TFS, .offset = 0},
327 {.res = P_SPORT0_DTPRI, .offset = 0},
328 {.res = P_SPI0_SSEL2, .offset = 0},
329 {.res = P_SPI0_SSEL3, .offset = 0},
c58c2140
MH		 330};
331
332static void portmux_setup(unsigned short per, unsigned short function)
333{
8c613623 334 u16 y, offset, muxreg;
c58c2140 335
8c613623
MH		 336 for (y = 0; y < ARRAY_SIZE(port_mux_lut); y++) {
337 if (port_mux_lut[y].res == per) {
c58c2140
MH		 338
339 /* SET PORTMUX REG */
340
8c613623 341 offset = port_mux_lut[y].offset;
c58c2140
MH		 342 muxreg = bfin_read_PORT_MUX();
343
d171c233 344 if (offset != 1)
c58c2140 345 muxreg &= ~(1 << offset);
d171c233 346 else
c58c2140 347 muxreg &= ~(3 << 1);
c58c2140
MH		 348
349 muxreg |= (function << offset);
350 bfin_write_PORT_MUX(muxreg);
351 }
352 }
353}
d2b11a46
MH		 354#elif defined(BF548_FAMILY)
355inline void portmux_setup(unsigned short portno, unsigned short function)
356{
357 u32 pmux;
358
359 pmux = gpio_array[gpio_bank(portno)]->port_mux;
360
361 pmux &= ~(0x3 << (2 * gpio_sub_n(portno)));
362 pmux |= (function & 0x3) << (2 * gpio_sub_n(portno));
363
364 gpio_array[gpio_bank(portno)]->port_mux = pmux;
365}
366
367inline u16 get_portmux(unsigned short portno)
368{
369 u32 pmux;
c58c2140 370
d2b11a46
MH		 371 pmux = gpio_array[gpio_bank(portno)]->port_mux;
372
373 return (pmux >> (2 * gpio_sub_n(portno)) & 0x3);
374}
2f6f4bcd 375#elif defined(BF527_FAMILY) || defined(BF518_FAMILY)
59003145
MH		 376inline void portmux_setup(unsigned short portno, unsigned short function)
377{
378 u16 pmux, ident = P_IDENT(portno);
379 u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
380
381 pmux = *port_mux[gpio_bank(ident)];
382 pmux &= ~(3 << offset);
383 pmux |= (function & 3) << offset;
384 *port_mux[gpio_bank(ident)] = pmux;
385 SSYNC();
386}
c58c2140
MH		 387#else
388# define portmux_setup(...) do { } while (0)
389#endif
1394f032 390
a161bb05 391static int __init bfin_gpio_init(void)
1394f032 392{
c58c2140 393 printk(KERN_INFO "Blackfin GPIO Controller\n");
1394f032
BW		 394
395 return 0;
396}
1394f032
BW		 397arch_initcall(bfin_gpio_init);
398
399
d2b11a46 400#ifndef BF548_FAMILY
1394f032
BW		 401/***********************************************************
402*
403* FUNCTIONS: Blackfin General Purpose Ports Access Functions
404*
405* INPUTS/OUTPUTS:
406* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
407*
408*
409* DESCRIPTION: These functions abstract direct register access
410* to Blackfin processor General Purpose
411* Ports Regsiters
412*
413* CAUTION: These functions do not belong to the GPIO Driver API
414*************************************************************
415* MODIFICATION HISTORY :
416**************************************************************/
417
418/* Set a specific bit */
419
420#define SET_GPIO(name) \
a2c8cfef 421void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
1394f032
BW		 422{ \
423 unsigned long flags; \
1394f032
BW		 424 local_irq_save(flags); \
425 if (arg) \
426 gpio_bankb[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
427 else \
428 gpio_bankb[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \
2b39331a 429 AWA_DUMMY_READ(name); \
1394f032
BW		 430 local_irq_restore(flags); \
431} \
432EXPORT_SYMBOL(set_gpio_ ## name);
433
434SET_GPIO(dir)
435SET_GPIO(inen)
436SET_GPIO(polar)
437SET_GPIO(edge)
438SET_GPIO(both)
439
440
2b39331a
MH		 441#if ANOMALY_05000311 || ANOMALY_05000323
442#define SET_GPIO_SC(name) \
a2c8cfef 443void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
2b39331a
MH		 444{ \
445 unsigned long flags; \
2b39331a
MH		 446 local_irq_save(flags); \
447 if (arg) \
448 gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
449 else \
450 gpio_bankb[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
451 AWA_DUMMY_READ(name); \
452 local_irq_restore(flags); \
453} \
454EXPORT_SYMBOL(set_gpio_ ## name);
455#else
1394f032 456#define SET_GPIO_SC(name) \
a2c8cfef 457void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
1394f032 458{ \
1394f032
BW		 459 if (arg) \
460 gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
461 else \
462 gpio_bankb[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
463} \
464EXPORT_SYMBOL(set_gpio_ ## name);
2b39331a 465#endif
1394f032
BW		 466
467SET_GPIO_SC(maska)
468SET_GPIO_SC(maskb)
1394f032 469SET_GPIO_SC(data)
1394f032 470
2b39331a 471#if ANOMALY_05000311 || ANOMALY_05000323
a2c8cfef 472void set_gpio_toggle(unsigned gpio)
1394f032
BW		 473{
474 unsigned long flags;
1394f032
BW		 475 local_irq_save(flags);
476 gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
2b39331a 477 AWA_DUMMY_READ(toggle);
1394f032
BW		 478 local_irq_restore(flags);
479}
480#else
a2c8cfef 481void set_gpio_toggle(unsigned gpio)
1394f032 482{
1394f032
BW		 483 gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
484}
485#endif
486EXPORT_SYMBOL(set_gpio_toggle);
487
488
489/*Set current PORT date (16-bit word)*/
490
2b39331a 491#if ANOMALY_05000311 || ANOMALY_05000323
1394f032 492#define SET_GPIO_P(name) \
a2c8cfef 493void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
1394f032 494{ \
2b39331a
MH		 495 unsigned long flags; \
496 local_irq_save(flags); \
1394f032 497 gpio_bankb[gpio_bank(gpio)]->name = arg; \
2b39331a
MH		 498 AWA_DUMMY_READ(name); \
499 local_irq_restore(flags); \
1394f032
BW		 500} \
501EXPORT_SYMBOL(set_gpiop_ ## name);
2b39331a
MH		 502#else
503#define SET_GPIO_P(name) \
a2c8cfef 504void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
2b39331a
MH		 505{ \
506 gpio_bankb[gpio_bank(gpio)]->name = arg; \
507} \
508EXPORT_SYMBOL(set_gpiop_ ## name);
509#endif
1394f032 510
2b39331a 511SET_GPIO_P(data)
1394f032
BW		 512SET_GPIO_P(dir)
513SET_GPIO_P(inen)
514SET_GPIO_P(polar)
515SET_GPIO_P(edge)
516SET_GPIO_P(both)
517SET_GPIO_P(maska)
518SET_GPIO_P(maskb)
519
1394f032 520/* Get a specific bit */
2b39331a
MH		 521#if ANOMALY_05000311 || ANOMALY_05000323
522#define GET_GPIO(name) \
a2c8cfef 523unsigned short get_gpio_ ## name(unsigned gpio) \
2b39331a
MH		 524{ \
525 unsigned long flags; \
526 unsigned short ret; \
527 local_irq_save(flags); \
528 ret = 0x01 & (gpio_bankb[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \
529 AWA_DUMMY_READ(name); \
530 local_irq_restore(flags); \
531 return ret; \
532} \
533EXPORT_SYMBOL(get_gpio_ ## name);
534#else
1394f032 535#define GET_GPIO(name) \
a2c8cfef 536unsigned short get_gpio_ ## name(unsigned gpio) \
1394f032
BW		 537{ \
538 return (0x01 & (gpio_bankb[gpio_bank(gpio)]->name >> gpio_sub_n(gpio))); \
539} \
540EXPORT_SYMBOL(get_gpio_ ## name);
2b39331a 541#endif
1394f032 542
2b39331a 543GET_GPIO(data)
1394f032
BW		 544GET_GPIO(dir)
545GET_GPIO(inen)
546GET_GPIO(polar)
547GET_GPIO(edge)
548GET_GPIO(both)
549GET_GPIO(maska)
550GET_GPIO(maskb)
551
1394f032
BW		 552/*Get current PORT date (16-bit word)*/
553
2b39331a
MH		 554#if ANOMALY_05000311 || ANOMALY_05000323
555#define GET_GPIO_P(name) \
a2c8cfef 556unsigned short get_gpiop_ ## name(unsigned gpio) \
2b39331a
MH		 557{ \
558 unsigned long flags; \
559 unsigned short ret; \
560 local_irq_save(flags); \
561 ret = (gpio_bankb[gpio_bank(gpio)]->name); \
562 AWA_DUMMY_READ(name); \
563 local_irq_restore(flags); \
564 return ret; \
565} \
566EXPORT_SYMBOL(get_gpiop_ ## name);
567#else
1394f032 568#define GET_GPIO_P(name) \
a2c8cfef 569unsigned short get_gpiop_ ## name(unsigned gpio) \
1394f032
BW		 570{ \
571 return (gpio_bankb[gpio_bank(gpio)]->name);\
572} \
573EXPORT_SYMBOL(get_gpiop_ ## name);
2b39331a 574#endif
1394f032 575
2b39331a 576GET_GPIO_P(data)
1394f032
BW		 577GET_GPIO_P(dir)
578GET_GPIO_P(inen)
579GET_GPIO_P(polar)
580GET_GPIO_P(edge)
581GET_GPIO_P(both)
582GET_GPIO_P(maska)
583GET_GPIO_P(maskb)
584
1394f032
BW		 585
586#ifdef CONFIG_PM
587/***********************************************************
588*
589* FUNCTIONS: Blackfin PM Setup API
590*
591* INPUTS/OUTPUTS:
592* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
593* type -
594* PM_WAKE_RISING
595* PM_WAKE_FALLING
596* PM_WAKE_HIGH
597* PM_WAKE_LOW
598* PM_WAKE_BOTH_EDGES
599*
600* DESCRIPTION: Blackfin PM Driver API
601*
602* CAUTION:
603*************************************************************
604* MODIFICATION HISTORY :
605**************************************************************/
a2c8cfef 606int gpio_pm_wakeup_request(unsigned gpio, unsigned char type)
1394f032
BW		 607{
608 unsigned long flags;
609
610 if ((check_gpio(gpio) < 0) || !type)
611 return -EINVAL;
612
613 local_irq_save(flags);
1394f032
BW		 614 wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio);
615 wakeup_flags_map[gpio] = type;
616 local_irq_restore(flags);
617
618 return 0;
619}
620EXPORT_SYMBOL(gpio_pm_wakeup_request);
621
a2c8cfef 622void gpio_pm_wakeup_free(unsigned gpio)
1394f032
BW		 623{
624 unsigned long flags;
625
626 if (check_gpio(gpio) < 0)
627 return;
628
629 local_irq_save(flags);
630
631 wakeup_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
632
633 local_irq_restore(flags);
634}
635EXPORT_SYMBOL(gpio_pm_wakeup_free);
636
a2c8cfef 637static int bfin_gpio_wakeup_type(unsigned gpio, unsigned char type)
1394f032
BW		 638{
639 port_setup(gpio, GPIO_USAGE);
640 set_gpio_dir(gpio, 0);
641 set_gpio_inen(gpio, 1);
642
643 if (type & (PM_WAKE_RISING | PM_WAKE_FALLING))
644 set_gpio_edge(gpio, 1);
645 else
646 set_gpio_edge(gpio, 0);
647
648 if ((type & (PM_WAKE_BOTH_EDGES)) == (PM_WAKE_BOTH_EDGES))
649 set_gpio_both(gpio, 1);
650 else
651 set_gpio_both(gpio, 0);
652
653 if ((type & (PM_WAKE_FALLING | PM_WAKE_LOW)))
654 set_gpio_polar(gpio, 1);
655 else
656 set_gpio_polar(gpio, 0);
657
658 SSYNC();
659
660 return 0;
661}
662
1efc80b5 663u32 bfin_pm_standby_setup(void)
1394f032 664{
1394f032
BW		 665 u16 bank, mask, i, gpio;
666
1f83b8f1 667 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
1394f032
BW		 668 mask = wakeup_map[gpio_bank(i)];
669 bank = gpio_bank(i);
670
671 gpio_bank_saved[bank].maskb = gpio_bankb[bank]->maskb;
672 gpio_bankb[bank]->maskb = 0;
673
674 if (mask) {
2f6f4bcd 675#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
1394f032
BW		 676 gpio_bank_saved[bank].fer = *port_fer[bank];
677#endif
678 gpio_bank_saved[bank].inen = gpio_bankb[bank]->inen;
679 gpio_bank_saved[bank].polar = gpio_bankb[bank]->polar;
680 gpio_bank_saved[bank].dir = gpio_bankb[bank]->dir;
681 gpio_bank_saved[bank].edge = gpio_bankb[bank]->edge;
682 gpio_bank_saved[bank].both = gpio_bankb[bank]->both;
c58c2140
MH		 683 gpio_bank_saved[bank].reserved =
684 reserved_gpio_map[bank];
1394f032
BW		 685
686 gpio = i;
687
688 while (mask) {
cfefe3c6
MH		 689 if ((mask & 1) && (wakeup_flags_map[gpio] !=
690 PM_WAKE_IGNORE)) {
c58c2140 691 reserved_gpio_map[gpio_bank(gpio)] |=
581d62ab
MH		 692 gpio_bit(gpio);
693 bfin_gpio_wakeup_type(gpio,
694 wakeup_flags_map[gpio]);
1394f032
BW		 695 set_gpio_data(gpio, 0); /*Clear*/
696 }
697 gpio++;
698 mask >>= 1;
699 }
700
cfefe3c6 701 bfin_internal_set_wake(sic_iwr_irqs[bank], 1);
1394f032
BW		 702 gpio_bankb[bank]->maskb_set = wakeup_map[gpio_bank(i)];
703 }
704 }
705
2b39331a
MH		 706 AWA_DUMMY_READ(maskb_set);
707
cfefe3c6 708 return 0;
1394f032
BW		 709}
710
1efc80b5 711void bfin_pm_standby_restore(void)
1394f032
BW		 712{
713 u16 bank, mask, i;
714
1f83b8f1 715 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
1394f032
BW		 716 mask = wakeup_map[gpio_bank(i)];
717 bank = gpio_bank(i);
718
719 if (mask) {
2f6f4bcd 720#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
1394f032
BW		 721 *port_fer[bank] = gpio_bank_saved[bank].fer;
722#endif
723 gpio_bankb[bank]->inen = gpio_bank_saved[bank].inen;
724 gpio_bankb[bank]->dir = gpio_bank_saved[bank].dir;
725 gpio_bankb[bank]->polar = gpio_bank_saved[bank].polar;
726 gpio_bankb[bank]->edge = gpio_bank_saved[bank].edge;
727 gpio_bankb[bank]->both = gpio_bank_saved[bank].both;
581d62ab 728
c58c2140
MH		 729 reserved_gpio_map[bank] =
730 gpio_bank_saved[bank].reserved;
cfefe3c6 731 bfin_internal_set_wake(sic_iwr_irqs[bank], 0);
1394f032
BW		 732 }
733
734 gpio_bankb[bank]->maskb = gpio_bank_saved[bank].maskb;
735 }
2b39331a 736 AWA_DUMMY_READ(maskb);
1394f032
BW		 737}
738
1efc80b5
MH		 739void bfin_gpio_pm_hibernate_suspend(void)
740{
741 int i, bank;
742
743 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
744 bank = gpio_bank(i);
745
2f6f4bcd 746#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
1efc80b5 747 gpio_bank_saved[bank].fer = *port_fer[bank];
2f6f4bcd 748#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
1efc80b5
MH		 749 gpio_bank_saved[bank].mux = *port_mux[bank];
750#else
751 if (bank == 0)
752 gpio_bank_saved[bank].mux = bfin_read_PORT_MUX();
753#endif
754#endif
755 gpio_bank_saved[bank].data = gpio_bankb[bank]->data;
756 gpio_bank_saved[bank].inen = gpio_bankb[bank]->inen;
757 gpio_bank_saved[bank].polar = gpio_bankb[bank]->polar;
758 gpio_bank_saved[bank].dir = gpio_bankb[bank]->dir;
759 gpio_bank_saved[bank].edge = gpio_bankb[bank]->edge;
760 gpio_bank_saved[bank].both = gpio_bankb[bank]->both;
761 gpio_bank_saved[bank].maska = gpio_bankb[bank]->maska;
762 }
763
764 AWA_DUMMY_READ(maska);
765}
766
767void bfin_gpio_pm_hibernate_restore(void)
768{
769 int i, bank;
770
771 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
772 bank = gpio_bank(i);
773
2f6f4bcd
BW		 774#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
775#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
1efc80b5
MH		 776 *port_mux[bank] = gpio_bank_saved[bank].mux;
777#else
778 if (bank == 0)
779 bfin_write_PORT_MUX(gpio_bank_saved[bank].mux);
780#endif
781 *port_fer[bank] = gpio_bank_saved[bank].fer;
782#endif
783 gpio_bankb[bank]->inen = gpio_bank_saved[bank].inen;
784 gpio_bankb[bank]->dir = gpio_bank_saved[bank].dir;
785 gpio_bankb[bank]->polar = gpio_bank_saved[bank].polar;
786 gpio_bankb[bank]->edge = gpio_bank_saved[bank].edge;
787 gpio_bankb[bank]->both = gpio_bank_saved[bank].both;
788
789 gpio_bankb[bank]->data_set = gpio_bank_saved[bank].data
790 | gpio_bank_saved[bank].dir;
791
792 gpio_bankb[bank]->maska = gpio_bank_saved[bank].maska;
793 }
794 AWA_DUMMY_READ(maska);
795}
796
797
1394f032 798#endif
fac3cf43 799#else /* BF548_FAMILY */
1efc80b5
MH		 800#ifdef CONFIG_PM
801
802u32 bfin_pm_standby_setup(void)
803{
804 return 0;
805}
806
807void bfin_pm_standby_restore(void)
808{
809
810}
811
812void bfin_gpio_pm_hibernate_suspend(void)
813{
814 int i, bank;
815
816 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
817 bank = gpio_bank(i);
818
819 gpio_bank_saved[bank].fer = gpio_array[bank]->port_fer;
820 gpio_bank_saved[bank].mux = gpio_array[bank]->port_mux;
821 gpio_bank_saved[bank].data = gpio_array[bank]->port_data;
822 gpio_bank_saved[bank].data = gpio_array[bank]->port_data;
823 gpio_bank_saved[bank].inen = gpio_array[bank]->port_inen;
824 gpio_bank_saved[bank].dir = gpio_array[bank]->port_dir_set;
825 }
826}
827
828void bfin_gpio_pm_hibernate_restore(void)
829{
830 int i, bank;
831
832 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
833 bank = gpio_bank(i);
834
835 gpio_array[bank]->port_mux = gpio_bank_saved[bank].mux;
836 gpio_array[bank]->port_fer = gpio_bank_saved[bank].fer;
837 gpio_array[bank]->port_inen = gpio_bank_saved[bank].inen;
838 gpio_array[bank]->port_dir_set = gpio_bank_saved[bank].dir;
839 gpio_array[bank]->port_set = gpio_bank_saved[bank].data
840 | gpio_bank_saved[bank].dir;
841 }
842}
843#endif
fac3cf43 844
a2c8cfef 845unsigned short get_gpio_dir(unsigned gpio)
fac3cf43
MH		 846{
847 return (0x01 & (gpio_array[gpio_bank(gpio)]->port_dir_clear >> gpio_sub_n(gpio)));
848}
849EXPORT_SYMBOL(get_gpio_dir);
850
d2b11a46 851#endif /* BF548_FAMILY */
1394f032 852
d2b11a46
MH		 853/***********************************************************
854*
855* FUNCTIONS: Blackfin Peripheral Resource Allocation
856* and PortMux Setup
857*
858* INPUTS/OUTPUTS:
859* per Peripheral Identifier
860* label String
861*
862* DESCRIPTION: Blackfin Peripheral Resource Allocation and Setup API
863*
864* CAUTION:
865*************************************************************
866* MODIFICATION HISTORY :
867**************************************************************/
868
d2b11a46
MH		 869int peripheral_request(unsigned short per, const char *label)
870{
871 unsigned long flags;
872 unsigned short ident = P_IDENT(per);
873
874 /*
875 * Don't cares are pins with only one dedicated function
876 */
c58c2140 877
d2b11a46
MH		 878 if (per & P_DONTCARE)
879 return 0;
880
881 if (!(per & P_DEFINED))
882 return -ENODEV;
883
d2b11a46
MH		 884 local_irq_save(flags);
885
6a87d29b
MF		 886 /* If a pin can be muxed as either GPIO or peripheral, make
887 * sure it is not already a GPIO pin when we request it.
888 */
889 if (unlikely(!check_gpio(ident) &&
890 reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
f85c4abd 891 dump_stack();
d2b11a46 892 printk(KERN_ERR
6c7ec0ec 893 "%s: Peripheral %d is already reserved as GPIO by %s !\n",
b85d858b 894 __func__, ident, get_label(ident));
d2b11a46
MH		 895 local_irq_restore(flags);
896 return -EBUSY;
897 }
898
899 if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
900
d171c233
MF		 901 /*
902 * Pin functions like AMC address strobes my
903 * be requested and used by several drivers
904 */
d2b11a46 905
6c7ec0ec
MF		 906#ifdef BF548_FAMILY
907 u16 funct = get_portmux(ident);
d2b11a46 908
6c7ec0ec
MF		 909 if (!((per & P_MAYSHARE) && (funct == P_FUNCT2MUX(per)))) {
910#else
911 if (!(per & P_MAYSHARE)) {
912#endif
d171c233
MF		 913 /*
914 * Allow that the identical pin function can
915 * be requested from the same driver twice
916 */
d2b11a46 917
d171c233
MF		 918 if (cmp_label(ident, label) == 0)
919 goto anyway;
d2b11a46 920
f85c4abd 921 dump_stack();
d2b11a46
MH		 922 printk(KERN_ERR
923 "%s: Peripheral %d function %d is already reserved by %s !\n",
b85d858b 924 __func__, ident, P_FUNCT2MUX(per), get_label(ident));
d2b11a46
MH		 925 local_irq_restore(flags);
926 return -EBUSY;
927 }
928 }
929
d171c233 930 anyway:
d2b11a46
MH		 931 reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
932
6c7ec0ec 933#ifdef BF548_FAMILY
d2b11a46 934 portmux_setup(ident, P_FUNCT2MUX(per));
d2b11a46 935#else
c58c2140 936 portmux_setup(per, P_FUNCT2MUX(per));
6c7ec0ec 937#endif
c58c2140
MH		 938 port_setup(ident, PERIPHERAL_USAGE);
939
c58c2140
MH		 940 local_irq_restore(flags);
941 set_label(ident, label);
942
943 return 0;
944}
945EXPORT_SYMBOL(peripheral_request);
946
68179371 947int peripheral_request_list(const unsigned short per[], const char *label)
c58c2140
MH		 948{
949 u16 cnt;
950 int ret;
951
952 for (cnt = 0; per[cnt] != 0; cnt++) {
314c98d5 953
c58c2140 954 ret = peripheral_request(per[cnt], label);
314c98d5
MH		 955
956 if (ret < 0) {
d171c233 957 for ( ; cnt > 0; cnt--)
314c98d5 958 peripheral_free(per[cnt - 1]);
d171c233
MF		 959
960 return ret;
314c98d5 961 }
c58c2140
MH		 962 }
963
964 return 0;
965}
966EXPORT_SYMBOL(peripheral_request_list);
967
968void peripheral_free(unsigned short per)
969{
970 unsigned long flags;
971 unsigned short ident = P_IDENT(per);
972
973 if (per & P_DONTCARE)
974 return;
975
976 if (!(per & P_DEFINED))
977 return;
978
979 if (check_gpio(ident) < 0)
980 return;
981
982 local_irq_save(flags);
983
d171c233 984 if (unlikely(!(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident)))) {
c58c2140
MH		 985 local_irq_restore(flags);
986 return;
987 }
988
d171c233 989 if (!(per & P_MAYSHARE))
c58c2140 990 port_setup(ident, GPIO_USAGE);
c58c2140
MH		 991
992 reserved_peri_map[gpio_bank(ident)] &= ~gpio_bit(ident);
993
2acde902
MH		 994 set_label(ident, "free");
995
c58c2140
MH		 996 local_irq_restore(flags);
997}
998EXPORT_SYMBOL(peripheral_free);
999
68179371 1000void peripheral_free_list(const unsigned short per[])
c58c2140
MH		 1001{
1002 u16 cnt;
d171c233 1003 for (cnt = 0; per[cnt] != 0; cnt++)
c58c2140 1004 peripheral_free(per[cnt]);
c58c2140
MH		 1005}
1006EXPORT_SYMBOL(peripheral_free_list);
1007
1394f032
BW		 1008/***********************************************************
1009*
1010* FUNCTIONS: Blackfin GPIO Driver
1011*
1012* INPUTS/OUTPUTS:
d2b11a46
MH		 1013* gpio PIO Number between 0 and MAX_BLACKFIN_GPIOS
1014* label String
1394f032
BW		 1015*
1016* DESCRIPTION: Blackfin GPIO Driver API
1017*
1018* CAUTION:
1019*************************************************************
1020* MODIFICATION HISTORY :
1021**************************************************************/
1022
acbcd263 1023int gpio_request(unsigned gpio, const char *label)
1394f032
BW		 1024{
1025 unsigned long flags;
1026
1027 if (check_gpio(gpio) < 0)
1028 return -EINVAL;
1029
1030 local_irq_save(flags);
1031
2acde902
MH		 1032 /*
1033 * Allow that the identical GPIO can
1034 * be requested from the same driver twice
1035 * Do nothing and return -
1036 */
1037
1038 if (cmp_label(gpio, label) == 0) {
1039 local_irq_restore(flags);
1040 return 0;
1041 }
1042
c58c2140 1043 if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
f85c4abd 1044 dump_stack();
d2b11a46
MH		 1045 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
1046 gpio, get_label(gpio));
d2b11a46
MH		 1047 local_irq_restore(flags);
1048 return -EBUSY;
1049 }
1050 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
f85c4abd 1051 dump_stack();
d2b11a46
MH		 1052 printk(KERN_ERR
1053 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
1054 gpio, get_label(gpio));
1394f032
BW		 1055 local_irq_restore(flags);
1056 return -EBUSY;
1057 }
d2b11a46 1058
c58c2140 1059 reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
1394f032
BW		 1060
1061 local_irq_restore(flags);
1062
1063 port_setup(gpio, GPIO_USAGE);
d2b11a46 1064 set_label(gpio, label);
1394f032
BW		 1065
1066 return 0;
1067}
1068EXPORT_SYMBOL(gpio_request);
1069
acbcd263 1070void gpio_free(unsigned gpio)
1394f032
BW		 1071{
1072 unsigned long flags;
1073
1074 if (check_gpio(gpio) < 0)
1075 return;
1076
1077 local_irq_save(flags);
1078
c58c2140 1079 if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
1394f032 1080 dump_stack();
f85c4abd 1081 gpio_error(gpio);
1394f032
BW		 1082 local_irq_restore(flags);
1083 return;
1084 }
1085
c58c2140 1086 reserved_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
1394f032 1087
2acde902
MH		 1088 set_label(gpio, "free");
1089
1394f032
BW		 1090 local_irq_restore(flags);
1091}
1092EXPORT_SYMBOL(gpio_free);
1093
acbcd263 1094
d2b11a46 1095#ifdef BF548_FAMILY
acbcd263 1096int gpio_direction_input(unsigned gpio)
d2b11a46
MH		 1097{
1098 unsigned long flags;
1099
acbcd263
MH		 1100 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1101 gpio_error(gpio);
1102 return -EINVAL;
1103 }
1104
d2b11a46
MH		 1105 local_irq_save(flags);
1106 gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
1107 gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
1108 local_irq_restore(flags);
acbcd263
MH		 1109
1110 return 0;
d2b11a46
MH		 1111}
1112EXPORT_SYMBOL(gpio_direction_input);
1113
acbcd263 1114int gpio_direction_output(unsigned gpio, int value)
d2b11a46
MH		 1115{
1116 unsigned long flags;
1117
acbcd263
MH		 1118 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1119 gpio_error(gpio);
1120 return -EINVAL;
1121 }
d2b11a46
MH		 1122
1123 local_irq_save(flags);
1124 gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio);
acbcd263 1125 gpio_set_value(gpio, value);
d2b11a46
MH		 1126 gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio);
1127 local_irq_restore(flags);
acbcd263
MH		 1128
1129 return 0;
d2b11a46
MH		 1130}
1131EXPORT_SYMBOL(gpio_direction_output);
1132
acbcd263 1133void gpio_set_value(unsigned gpio, int arg)
d2b11a46
MH		 1134{
1135 if (arg)
1136 gpio_array[gpio_bank(gpio)]->port_set = gpio_bit(gpio);
1137 else
1138 gpio_array[gpio_bank(gpio)]->port_clear = gpio_bit(gpio);
d2b11a46
MH		 1139}
1140EXPORT_SYMBOL(gpio_set_value);
1141
acbcd263 1142int gpio_get_value(unsigned gpio)
d2b11a46
MH		 1143{
1144 return (1 & (gpio_array[gpio_bank(gpio)]->port_data >> gpio_sub_n(gpio)));
1145}
1146EXPORT_SYMBOL(gpio_get_value);
1147
affee2b2
MH		 1148void bfin_gpio_irq_prepare(unsigned gpio)
1149{
1150 unsigned long flags;
1151
1152 port_setup(gpio, GPIO_USAGE);
1153
1154 local_irq_save(flags);
1155 gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
1156 gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
1157 local_irq_restore(flags);
1158}
1159
d2b11a46
MH		 1160#else
1161
803a8d2a
MH		 1162int gpio_get_value(unsigned gpio)
1163{
1164 unsigned long flags;
1165 int ret;
1166
1167 if (unlikely(get_gpio_edge(gpio))) {
1168 local_irq_save(flags);
1169 set_gpio_edge(gpio, 0);
1170 ret = get_gpio_data(gpio);
1171 set_gpio_edge(gpio, 1);
1172 local_irq_restore(flags);
1173
1174 return ret;
1175 } else
1176 return get_gpio_data(gpio);
1177}
1178EXPORT_SYMBOL(gpio_get_value);
1179
1180
acbcd263 1181int gpio_direction_input(unsigned gpio)
1394f032
BW		 1182{
1183 unsigned long flags;
1184
acbcd263
MH		 1185 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1186 gpio_error(gpio);
1187 return -EINVAL;
1188 }
1394f032
BW		 1189
1190 local_irq_save(flags);
1191 gpio_bankb[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
1192 gpio_bankb[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
2b39331a 1193 AWA_DUMMY_READ(inen);
1394f032 1194 local_irq_restore(flags);
acbcd263
MH		 1195
1196 return 0;
1394f032
BW		 1197}
1198EXPORT_SYMBOL(gpio_direction_input);
1199
acbcd263 1200int gpio_direction_output(unsigned gpio, int value)
1394f032
BW		 1201{
1202 unsigned long flags;
1203
acbcd263
MH		 1204 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1205 gpio_error(gpio);
1206 return -EINVAL;
1207 }
1394f032
BW		 1208
1209 local_irq_save(flags);
1210 gpio_bankb[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
a2c8cfef
MH		 1211
1212 if (value)
1213 gpio_bankb[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
1214 else
1215 gpio_bankb[gpio_bank(gpio)]->data_clear = gpio_bit(gpio);
1216
1394f032 1217 gpio_bankb[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
2b39331a 1218 AWA_DUMMY_READ(dir);
1394f032 1219 local_irq_restore(flags);
acbcd263
MH		 1220
1221 return 0;
1394f032
BW		 1222}
1223EXPORT_SYMBOL(gpio_direction_output);
168f1212
MF		 1224
1225/* If we are booting from SPI and our board lacks a strong enough pull up,
1226 * the core can reset and execute the bootrom faster than the resistor can
1227 * pull the signal logically high. To work around this (common) error in
1228 * board design, we explicitly set the pin back to GPIO mode, force /CS
1229 * high, and wait for the electrons to do their thing.
1230 *
1231 * This function only makes sense to be called from reset code, but it
1232 * lives here as we need to force all the GPIO states w/out going through
1233 * BUG() checks and such.
1234 */
1235void bfin_gpio_reset_spi0_ssel1(void)
1236{
4d5f4ed3
MH		 1237 u16 gpio = P_IDENT(P_SPI0_SSEL1);
1238
1239 port_setup(gpio, GPIO_USAGE);
1240 gpio_bankb[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
a2c8cfef 1241 AWA_DUMMY_READ(data_set);
168f1212
MF		 1242 udelay(1);
1243}
d2b11a46 1244
affee2b2
MH		 1245void bfin_gpio_irq_prepare(unsigned gpio)
1246{
1247 port_setup(gpio, GPIO_USAGE);
1248}
1249
d2b11a46 1250#endif /*BF548_FAMILY */
1545a111
MF		 1251
1252#if defined(CONFIG_PROC_FS)
1253static int gpio_proc_read(char *buf, char **start, off_t offset,
1254 int len, int *unused_i, void *unused_v)
1255{
1256 int c, outlen = 0;
1257
1258 for (c = 0; c < MAX_RESOURCES; c++) {
1259 if (!check_gpio(c) && (reserved_gpio_map[gpio_bank(c)] & gpio_bit(c)))
fac3cf43 1260 len = sprintf(buf, "GPIO_%d: %s \t\tGPIO %s\n", c,
1545a111
MF		 1261 get_label(c), get_gpio_dir(c) ? "OUTPUT" : "INPUT");
1262 else if (reserved_peri_map[gpio_bank(c)] & gpio_bit(c))
fac3cf43 1263 len = sprintf(buf, "GPIO_%d: %s \t\tPeripheral\n", c, get_label(c));
1545a111
MF		 1264 else
1265 continue;
1266 buf += len;
1267 outlen += len;
1268 }
1269 return outlen;
1270}
1271
1272static __init int gpio_register_proc(void)
1273{
1274 struct proc_dir_entry *proc_gpio;
1275
1276 proc_gpio = create_proc_entry("gpio", S_IRUGO, NULL);
1277 if (proc_gpio)
1278 proc_gpio->read_proc = gpio_proc_read;
1279 return proc_gpio != NULL;
1280}
1545a111
MF		 1281__initcall(gpio_register_proc);
1282#endif
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