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Blackfin arch: add RSI's definitions to bf514 and bf516
[mirror_ubuntu-artful-kernel.git] / arch / blackfin / kernel / bfin_gpio.c
CommitLineData
1394f032
BW		 1/*
2 * File: arch/blackfin/kernel/bfin_gpio.c
3 * Based on:
4 * Author: Michael Hennerich (hennerich@blackfin.uclinux.org)
5 *
6 * Created:
7 * Description: GPIO Abstraction Layer
8 *
9 * Modified:
a2c8cfef 10 * Copyright 2008 Analog Devices Inc.
1394f032
BW		 11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
168f1212 30#include <linux/delay.h>
1394f032
BW		 31#include <linux/module.h>
32#include <linux/err.h>
1545a111 33#include <linux/proc_fs.h>
1394f032
BW		 34#include <asm/blackfin.h>
35#include <asm/gpio.h>
c58c2140 36#include <asm/portmux.h>
1394f032
BW		 37#include <linux/irq.h>
38
2b39331a
MH		 39#if ANOMALY_05000311 || ANOMALY_05000323
40enum {
41 AWA_data = SYSCR,
42 AWA_data_clear = SYSCR,
43 AWA_data_set = SYSCR,
44 AWA_toggle = SYSCR,
6ed83942
GY		 45 AWA_maska = BFIN_UART_SCR,
46 AWA_maska_clear = BFIN_UART_SCR,
47 AWA_maska_set = BFIN_UART_SCR,
48 AWA_maska_toggle = BFIN_UART_SCR,
49 AWA_maskb = BFIN_UART_GCTL,
50 AWA_maskb_clear = BFIN_UART_GCTL,
51 AWA_maskb_set = BFIN_UART_GCTL,
52 AWA_maskb_toggle = BFIN_UART_GCTL,
2b39331a
MH		 53 AWA_dir = SPORT1_STAT,
54 AWA_polar = SPORT1_STAT,
55 AWA_edge = SPORT1_STAT,
56 AWA_both = SPORT1_STAT,
57#if ANOMALY_05000311
58 AWA_inen = TIMER_ENABLE,
59#elif ANOMALY_05000323
60 AWA_inen = DMA1_1_CONFIG,
61#endif
62};
63 /* Anomaly Workaround */
64#define AWA_DUMMY_READ(name) bfin_read16(AWA_ ## name)
65#else
66#define AWA_DUMMY_READ(...) do { } while (0)
67#endif
68
f556309e 69static struct gpio_port_t * const gpio_array[] = {
dc26aec2 70#if defined(BF533_FAMILY) || defined(BF538_FAMILY)
1394f032 71 (struct gpio_port_t *) FIO_FLAG_D,
269647dc 72#elif defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
1394f032
BW		 73 (struct gpio_port_t *) PORTFIO,
74 (struct gpio_port_t *) PORTGIO,
75 (struct gpio_port_t *) PORTHIO,
f556309e
MF		 76#elif defined(BF561_FAMILY)
77 (struct gpio_port_t *) FIO0_FLAG_D,
78 (struct gpio_port_t *) FIO1_FLAG_D,
79 (struct gpio_port_t *) FIO2_FLAG_D,
269647dc 80#elif defined(CONFIG_BF54x)
f556309e
MF		 81 (struct gpio_port_t *)PORTA_FER,
82 (struct gpio_port_t *)PORTB_FER,
83 (struct gpio_port_t *)PORTC_FER,
84 (struct gpio_port_t *)PORTD_FER,
85 (struct gpio_port_t *)PORTE_FER,
86 (struct gpio_port_t *)PORTF_FER,
87 (struct gpio_port_t *)PORTG_FER,
88 (struct gpio_port_t *)PORTH_FER,
89 (struct gpio_port_t *)PORTI_FER,
90 (struct gpio_port_t *)PORTJ_FER,
91#else
92# error no gpio arrays defined
93#endif
1394f032
BW		 94};
95
269647dc 96#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
f556309e 97static unsigned short * const port_fer[] = {
1394f032
BW		 98 (unsigned short *) PORTF_FER,
99 (unsigned short *) PORTG_FER,
100 (unsigned short *) PORTH_FER,
101};
1394f032 102
f556309e
MF		 103# if !defined(BF537_FAMILY)
104static unsigned short * const port_mux[] = {
59003145
MH		 105 (unsigned short *) PORTF_MUX,
106 (unsigned short *) PORTG_MUX,
107 (unsigned short *) PORTH_MUX,
108};
109
110static const
0ce5eaf8 111u8 pmux_offset[][16] = {
269647dc 112# if defined(CONFIG_BF52x)
0ce5eaf8
GY		 113 { 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 4, 6, 8, 8, 10, 10 }, /* PORTF */
114 { 0, 0, 0, 0, 0, 2, 2, 4, 4, 6, 8, 10, 10, 10, 12, 12 }, /* PORTG */
115 { 0, 0, 0, 0, 0, 0, 0, 0, 2, 4, 4, 4, 4, 4, 4, 4 }, /* PORTH */
269647dc 116# elif defined(CONFIG_BF51x)
0ce5eaf8
GY		 117 { 0, 2, 2, 2, 2, 2, 2, 4, 6, 6, 6, 8, 8, 8, 8, 10 }, /* PORTF */
118 { 0, 0, 0, 2, 4, 6, 6, 6, 8, 10, 10, 12, 14, 14, 14, 14 }, /* PORTG */
119 { 0, 0, 0, 0, 2, 2, 4, 6, 10, 10, 10, 10, 10, 10, 10, 10 }, /* PORTH */
120# endif
121};
f556309e 122# endif
0ce5eaf8 123
d2b11a46
MH		 124#endif
125
397861cd 126static unsigned short reserved_gpio_map[GPIO_BANK_NUM];
fac3cf43 127static unsigned short reserved_peri_map[gpio_bank(MAX_RESOURCES)];
9570ff4a 128static unsigned short reserved_gpio_irq_map[GPIO_BANK_NUM];
c58c2140 129
8c613623
MH		 130#define RESOURCE_LABEL_SIZE 16
131
fac3cf43 132static struct str_ident {
8c613623 133 char name[RESOURCE_LABEL_SIZE];
fac3cf43 134} str_ident[MAX_RESOURCES];
1394f032 135
1efc80b5 136#if defined(CONFIG_PM)
397861cd 137static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM];
59003145
MH		 138#endif
139
a2c8cfef 140inline int check_gpio(unsigned gpio)
d2b11a46 141{
269647dc 142#if defined(CONFIG_BF54x)
d2b11a46
MH		 143 if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
144 || gpio == GPIO_PH14 || gpio == GPIO_PH15
27228b2e 145 || gpio == GPIO_PJ14 || gpio == GPIO_PJ15)
d2b11a46 146 return -EINVAL;
27228b2e 147#endif
e7613aab 148 if (gpio >= MAX_BLACKFIN_GPIOS)
1394f032
BW		 149 return -EINVAL;
150 return 0;
151}
152
74c04503 153static void gpio_error(unsigned gpio)
acbcd263
MH		 154{
155 printk(KERN_ERR "bfin-gpio: GPIO %d wasn't requested!\n", gpio);
156}
157
c58c2140
MH		 158static void set_label(unsigned short ident, const char *label)
159{
e9fae189 160 if (label) {
8c613623 161 strncpy(str_ident[ident].name, label,
c58c2140 162 RESOURCE_LABEL_SIZE);
8c613623 163 str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0;
c58c2140
MH		 164 }
165}
166
167static char *get_label(unsigned short ident)
168{
8c613623 169 return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN");
c58c2140
MH		 170}
171
172static int cmp_label(unsigned short ident, const char *label)
173{
fac3cf43
MH		 174 if (label == NULL) {
175 dump_stack();
176 printk(KERN_ERR "Please provide none-null label\n");
177 }
178
e9fae189 179 if (label)
1f7d373f 180 return strcmp(str_ident[ident].name, label);
c58c2140
MH		 181 else
182 return -EINVAL;
183}
184
a2c8cfef 185static void port_setup(unsigned gpio, unsigned short usage)
1394f032 186{
a2d03a1d
MF		 187 if (check_gpio(gpio))
188 return;
189
269647dc 190#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
a2d03a1d
MF		 191 if (usage == GPIO_USAGE)
192 *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
193 else
194 *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
195 SSYNC();
269647dc 196#elif defined(CONFIG_BF54x)
d2b11a46
MH		 197 if (usage == GPIO_USAGE)
198 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
199 else
200 gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
201 SSYNC();
1394f032 202#endif
a2d03a1d 203}
1394f032 204
c58c2140 205#ifdef BF537_FAMILY
8c613623
MH		 206static struct {
207 unsigned short res;
208 unsigned short offset;
209} port_mux_lut[] = {
210 {.res = P_PPI0_D13, .offset = 11},
211 {.res = P_PPI0_D14, .offset = 11},
212 {.res = P_PPI0_D15, .offset = 11},
213 {.res = P_SPORT1_TFS, .offset = 11},
214 {.res = P_SPORT1_TSCLK, .offset = 11},
215 {.res = P_SPORT1_DTPRI, .offset = 11},
216 {.res = P_PPI0_D10, .offset = 10},
217 {.res = P_PPI0_D11, .offset = 10},
218 {.res = P_PPI0_D12, .offset = 10},
219 {.res = P_SPORT1_RSCLK, .offset = 10},
220 {.res = P_SPORT1_RFS, .offset = 10},
221 {.res = P_SPORT1_DRPRI, .offset = 10},
222 {.res = P_PPI0_D8, .offset = 9},
223 {.res = P_PPI0_D9, .offset = 9},
224 {.res = P_SPORT1_DRSEC, .offset = 9},
225 {.res = P_SPORT1_DTSEC, .offset = 9},
226 {.res = P_TMR2, .offset = 8},
227 {.res = P_PPI0_FS3, .offset = 8},
228 {.res = P_TMR3, .offset = 7},
229 {.res = P_SPI0_SSEL4, .offset = 7},
230 {.res = P_TMR4, .offset = 6},
231 {.res = P_SPI0_SSEL5, .offset = 6},
232 {.res = P_TMR5, .offset = 5},
233 {.res = P_SPI0_SSEL6, .offset = 5},
234 {.res = P_UART1_RX, .offset = 4},
235 {.res = P_UART1_TX, .offset = 4},
236 {.res = P_TMR6, .offset = 4},
237 {.res = P_TMR7, .offset = 4},
238 {.res = P_UART0_RX, .offset = 3},
239 {.res = P_UART0_TX, .offset = 3},
240 {.res = P_DMAR0, .offset = 3},
241 {.res = P_DMAR1, .offset = 3},
242 {.res = P_SPORT0_DTSEC, .offset = 1},
243 {.res = P_SPORT0_DRSEC, .offset = 1},
244 {.res = P_CAN0_RX, .offset = 1},
245 {.res = P_CAN0_TX, .offset = 1},
246 {.res = P_SPI0_SSEL7, .offset = 1},
247 {.res = P_SPORT0_TFS, .offset = 0},
248 {.res = P_SPORT0_DTPRI, .offset = 0},
249 {.res = P_SPI0_SSEL2, .offset = 0},
250 {.res = P_SPI0_SSEL3, .offset = 0},
c58c2140
MH		 251};
252
f556309e 253static void portmux_setup(unsigned short per)
c58c2140 254{
8c613623 255 u16 y, offset, muxreg;
f556309e 256 u16 function = P_FUNCT2MUX(per);
c58c2140 257
8c613623
MH		 258 for (y = 0; y < ARRAY_SIZE(port_mux_lut); y++) {
259 if (port_mux_lut[y].res == per) {
c58c2140
MH		 260
261 /* SET PORTMUX REG */
262
8c613623 263 offset = port_mux_lut[y].offset;
c58c2140
MH		 264 muxreg = bfin_read_PORT_MUX();
265
d171c233 266 if (offset != 1)
c58c2140 267 muxreg &= ~(1 << offset);
d171c233 268 else
c58c2140 269 muxreg &= ~(3 << 1);
c58c2140
MH		 270
271 muxreg |= (function << offset);
272 bfin_write_PORT_MUX(muxreg);
273 }
274 }
275}
269647dc 276#elif defined(CONFIG_BF54x)
f556309e 277inline void portmux_setup(unsigned short per)
d2b11a46
MH		 278{
279 u32 pmux;
f556309e
MF		 280 u16 ident = P_IDENT(per);
281 u16 function = P_FUNCT2MUX(per);
d2b11a46 282
f556309e 283 pmux = gpio_array[gpio_bank(ident)]->port_mux;
d2b11a46 284
f556309e
MF		 285 pmux &= ~(0x3 << (2 * gpio_sub_n(ident)));
286 pmux |= (function & 0x3) << (2 * gpio_sub_n(ident));
d2b11a46 287
f556309e 288 gpio_array[gpio_bank(ident)]->port_mux = pmux;
d2b11a46
MH		 289}
290
f556309e 291inline u16 get_portmux(unsigned short per)
d2b11a46
MH		 292{
293 u32 pmux;
f556309e 294 u16 ident = P_IDENT(per);
c58c2140 295
f556309e 296 pmux = gpio_array[gpio_bank(ident)]->port_mux;
d2b11a46 297
f556309e 298 return (pmux >> (2 * gpio_sub_n(ident)) & 0x3);
d2b11a46 299}
269647dc 300#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
f556309e 301inline void portmux_setup(unsigned short per)
59003145 302{
f556309e 303 u16 pmux, ident = P_IDENT(per), function = P_FUNCT2MUX(per);
59003145
MH		 304 u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
305
306 pmux = *port_mux[gpio_bank(ident)];
307 pmux &= ~(3 << offset);
308 pmux |= (function & 3) << offset;
309 *port_mux[gpio_bank(ident)] = pmux;
310 SSYNC();
311}
c58c2140
MH		 312#else
313# define portmux_setup(...) do { } while (0)
314#endif
1394f032 315
a161bb05 316static int __init bfin_gpio_init(void)
1394f032 317{
c58c2140 318 printk(KERN_INFO "Blackfin GPIO Controller\n");
1394f032
BW		 319
320 return 0;
321}
1394f032
BW		 322arch_initcall(bfin_gpio_init);
323
324
269647dc 325#ifndef CONFIG_BF54x
1394f032
BW		 326/***********************************************************
327*
328* FUNCTIONS: Blackfin General Purpose Ports Access Functions
329*
330* INPUTS/OUTPUTS:
331* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
332*
333*
334* DESCRIPTION: These functions abstract direct register access
335* to Blackfin processor General Purpose
336* Ports Regsiters
337*
338* CAUTION: These functions do not belong to the GPIO Driver API
339*************************************************************
340* MODIFICATION HISTORY :
341**************************************************************/
342
343/* Set a specific bit */
344
345#define SET_GPIO(name) \
a2c8cfef 346void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
1394f032
BW		 347{ \
348 unsigned long flags; \
6a01f230 349 local_irq_save_hw(flags); \
1394f032 350 if (arg) \
f556309e 351 gpio_array[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
1394f032 352 else \
f556309e 353 gpio_array[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \
2b39331a 354 AWA_DUMMY_READ(name); \
6a01f230 355 local_irq_restore_hw(flags); \
1394f032
BW		 356} \
357EXPORT_SYMBOL(set_gpio_ ## name);
358
f556309e
MF		 359SET_GPIO(dir) /* set_gpio_dir() */
360SET_GPIO(inen) /* set_gpio_inen() */
361SET_GPIO(polar) /* set_gpio_polar() */
362SET_GPIO(edge) /* set_gpio_edge() */
363SET_GPIO(both) /* set_gpio_both() */
1394f032
BW		 364
365
2b39331a 366#define SET_GPIO_SC(name) \
a2c8cfef 367void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
2b39331a
MH		 368{ \
369 unsigned long flags; \
f556309e
MF		 370 if (ANOMALY_05000311 || ANOMALY_05000323) \
371 local_irq_save_hw(flags); \
1394f032 372 if (arg) \
f556309e 373 gpio_array[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
1394f032 374 else \
f556309e
MF		 375 gpio_array[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
376 if (ANOMALY_05000311 || ANOMALY_05000323) { \
377 AWA_DUMMY_READ(name); \
378 local_irq_restore_hw(flags); \
379 } \
1394f032
BW		 380} \
381EXPORT_SYMBOL(set_gpio_ ## name);
382
383SET_GPIO_SC(maska)
384SET_GPIO_SC(maskb)
1394f032 385SET_GPIO_SC(data)
1394f032 386
a2c8cfef 387void set_gpio_toggle(unsigned gpio)
1394f032
BW		 388{
389 unsigned long flags;
f556309e
MF		 390 if (ANOMALY_05000311 || ANOMALY_05000323)
391 local_irq_save_hw(flags);
392 gpio_array[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
393 if (ANOMALY_05000311 || ANOMALY_05000323) {
394 AWA_DUMMY_READ(toggle);
395 local_irq_restore_hw(flags);
396 }
1394f032 397}
1394f032
BW		 398EXPORT_SYMBOL(set_gpio_toggle);
399
400
401/*Set current PORT date (16-bit word)*/
402
403#define SET_GPIO_P(name) \
a2c8cfef 404void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
1394f032 405{ \
2b39331a 406 unsigned long flags; \
f556309e
MF		 407 if (ANOMALY_05000311 || ANOMALY_05000323) \
408 local_irq_save_hw(flags); \
409 gpio_array[gpio_bank(gpio)]->name = arg; \
410 if (ANOMALY_05000311 || ANOMALY_05000323) { \
411 AWA_DUMMY_READ(name); \
412 local_irq_restore_hw(flags); \
413 } \
2b39331a
MH		 414} \
415EXPORT_SYMBOL(set_gpiop_ ## name);
1394f032 416
2b39331a 417SET_GPIO_P(data)
1394f032
BW		 418SET_GPIO_P(dir)
419SET_GPIO_P(inen)
420SET_GPIO_P(polar)
421SET_GPIO_P(edge)
422SET_GPIO_P(both)
423SET_GPIO_P(maska)
424SET_GPIO_P(maskb)
425
1394f032 426/* Get a specific bit */
2b39331a 427#define GET_GPIO(name) \
a2c8cfef 428unsigned short get_gpio_ ## name(unsigned gpio) \
2b39331a
MH		 429{ \
430 unsigned long flags; \
431 unsigned short ret; \
f556309e
MF		 432 if (ANOMALY_05000311 || ANOMALY_05000323) \
433 local_irq_save_hw(flags); \
434 ret = 0x01 & (gpio_array[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \
435 if (ANOMALY_05000311 || ANOMALY_05000323) { \
436 AWA_DUMMY_READ(name); \
437 local_irq_restore_hw(flags); \
438 } \
2b39331a
MH		 439 return ret; \
440} \
441EXPORT_SYMBOL(get_gpio_ ## name);
1394f032 442
2b39331a 443GET_GPIO(data)
1394f032
BW		 444GET_GPIO(dir)
445GET_GPIO(inen)
446GET_GPIO(polar)
447GET_GPIO(edge)
448GET_GPIO(both)
449GET_GPIO(maska)
450GET_GPIO(maskb)
451
1394f032
BW		 452/*Get current PORT date (16-bit word)*/
453
2b39331a 454#define GET_GPIO_P(name) \
a2c8cfef 455unsigned short get_gpiop_ ## name(unsigned gpio) \
2b39331a
MH		 456{ \
457 unsigned long flags; \
458 unsigned short ret; \
f556309e
MF		 459 if (ANOMALY_05000311 || ANOMALY_05000323) \
460 local_irq_save_hw(flags); \
461 ret = (gpio_array[gpio_bank(gpio)]->name); \
462 if (ANOMALY_05000311 || ANOMALY_05000323) { \
463 AWA_DUMMY_READ(name); \
464 local_irq_restore_hw(flags); \
465 } \
2b39331a
MH		 466 return ret; \
467} \
468EXPORT_SYMBOL(get_gpiop_ ## name);
1394f032 469
2b39331a 470GET_GPIO_P(data)
1394f032
BW		 471GET_GPIO_P(dir)
472GET_GPIO_P(inen)
473GET_GPIO_P(polar)
474GET_GPIO_P(edge)
475GET_GPIO_P(both)
476GET_GPIO_P(maska)
477GET_GPIO_P(maskb)
478
1394f032
BW		 479
480#ifdef CONFIG_PM
f556309e
MF		 481
482static unsigned short wakeup_map[GPIO_BANK_NUM];
483static unsigned char wakeup_flags_map[MAX_BLACKFIN_GPIOS];
484
485static const unsigned int sic_iwr_irqs[] = {
486#if defined(BF533_FAMILY)
487 IRQ_PROG_INTB
488#elif defined(BF537_FAMILY)
489 IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX
490#elif defined(BF538_FAMILY)
491 IRQ_PORTF_INTB
269647dc 492#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
f556309e
MF		 493 IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB
494#elif defined(BF561_FAMILY)
495 IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB
496#else
497# error no SIC_IWR defined
498#endif
499};
500
1394f032
BW		 501/***********************************************************
502*
503* FUNCTIONS: Blackfin PM Setup API
504*
505* INPUTS/OUTPUTS:
506* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
507* type -
508* PM_WAKE_RISING
509* PM_WAKE_FALLING
510* PM_WAKE_HIGH
511* PM_WAKE_LOW
512* PM_WAKE_BOTH_EDGES
513*
514* DESCRIPTION: Blackfin PM Driver API
515*
516* CAUTION:
517*************************************************************
518* MODIFICATION HISTORY :
519**************************************************************/
a2c8cfef 520int gpio_pm_wakeup_request(unsigned gpio, unsigned char type)
1394f032
BW		 521{
522 unsigned long flags;
523
524 if ((check_gpio(gpio) < 0) || !type)
525 return -EINVAL;
526
6a01f230 527 local_irq_save_hw(flags);
1394f032
BW		 528 wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio);
529 wakeup_flags_map[gpio] = type;
6a01f230 530 local_irq_restore_hw(flags);
1394f032
BW		 531
532 return 0;
533}
534EXPORT_SYMBOL(gpio_pm_wakeup_request);
535
a2c8cfef 536void gpio_pm_wakeup_free(unsigned gpio)
1394f032
BW		 537{
538 unsigned long flags;
539
540 if (check_gpio(gpio) < 0)
541 return;
542
6a01f230 543 local_irq_save_hw(flags);
1394f032
BW		 544
545 wakeup_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
546
6a01f230 547 local_irq_restore_hw(flags);
1394f032
BW		 548}
549EXPORT_SYMBOL(gpio_pm_wakeup_free);
550
a2c8cfef 551static int bfin_gpio_wakeup_type(unsigned gpio, unsigned char type)
1394f032
BW		 552{
553 port_setup(gpio, GPIO_USAGE);
554 set_gpio_dir(gpio, 0);
555 set_gpio_inen(gpio, 1);
556
557 if (type & (PM_WAKE_RISING | PM_WAKE_FALLING))
558 set_gpio_edge(gpio, 1);
559 else
560 set_gpio_edge(gpio, 0);
561
562 if ((type & (PM_WAKE_BOTH_EDGES)) == (PM_WAKE_BOTH_EDGES))
563 set_gpio_both(gpio, 1);
564 else
565 set_gpio_both(gpio, 0);
566
567 if ((type & (PM_WAKE_FALLING | PM_WAKE_LOW)))
568 set_gpio_polar(gpio, 1);
569 else
570 set_gpio_polar(gpio, 0);
571
572 SSYNC();
573
574 return 0;
575}
576
1efc80b5 577u32 bfin_pm_standby_setup(void)
1394f032 578{
1394f032
BW		 579 u16 bank, mask, i, gpio;
580
1f83b8f1 581 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
1394f032
BW		 582 mask = wakeup_map[gpio_bank(i)];
583 bank = gpio_bank(i);
584
f556309e
MF		 585 gpio_bank_saved[bank].maskb = gpio_array[bank]->maskb;
586 gpio_array[bank]->maskb = 0;
1394f032
BW		 587
588 if (mask) {
269647dc 589#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
1394f032
BW		 590 gpio_bank_saved[bank].fer = *port_fer[bank];
591#endif
f556309e
MF		 592 gpio_bank_saved[bank].inen = gpio_array[bank]->inen;
593 gpio_bank_saved[bank].polar = gpio_array[bank]->polar;
594 gpio_bank_saved[bank].dir = gpio_array[bank]->dir;
595 gpio_bank_saved[bank].edge = gpio_array[bank]->edge;
596 gpio_bank_saved[bank].both = gpio_array[bank]->both;
c58c2140
MH		 597 gpio_bank_saved[bank].reserved =
598 reserved_gpio_map[bank];
1394f032
BW		 599
600 gpio = i;
601
602 while (mask) {
cfefe3c6
MH		 603 if ((mask & 1) && (wakeup_flags_map[gpio] !=
604 PM_WAKE_IGNORE)) {
c58c2140 605 reserved_gpio_map[gpio_bank(gpio)] |=
581d62ab
MH		 606 gpio_bit(gpio);
607 bfin_gpio_wakeup_type(gpio,
608 wakeup_flags_map[gpio]);
1394f032
BW		 609 set_gpio_data(gpio, 0); /*Clear*/
610 }
611 gpio++;
612 mask >>= 1;
613 }
614
cfefe3c6 615 bfin_internal_set_wake(sic_iwr_irqs[bank], 1);
f556309e 616 gpio_array[bank]->maskb_set = wakeup_map[gpio_bank(i)];
1394f032
BW		 617 }
618 }
619
2b39331a
MH		 620 AWA_DUMMY_READ(maskb_set);
621
cfefe3c6 622 return 0;
1394f032
BW		 623}
624
1efc80b5 625void bfin_pm_standby_restore(void)
1394f032
BW		 626{
627 u16 bank, mask, i;
628
1f83b8f1 629 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
1394f032
BW		 630 mask = wakeup_map[gpio_bank(i)];
631 bank = gpio_bank(i);
632
633 if (mask) {
269647dc 634#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
1394f032
BW		 635 *port_fer[bank] = gpio_bank_saved[bank].fer;
636#endif
f556309e
MF		 637 gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
638 gpio_array[bank]->dir = gpio_bank_saved[bank].dir;
639 gpio_array[bank]->polar = gpio_bank_saved[bank].polar;
640 gpio_array[bank]->edge = gpio_bank_saved[bank].edge;
641 gpio_array[bank]->both = gpio_bank_saved[bank].both;
581d62ab 642
c58c2140
MH		 643 reserved_gpio_map[bank] =
644 gpio_bank_saved[bank].reserved;
cfefe3c6 645 bfin_internal_set_wake(sic_iwr_irqs[bank], 0);
1394f032
BW		 646 }
647
f556309e 648 gpio_array[bank]->maskb = gpio_bank_saved[bank].maskb;
1394f032 649 }
2b39331a 650 AWA_DUMMY_READ(maskb);
1394f032
BW		 651}
652
1efc80b5
MH		 653void bfin_gpio_pm_hibernate_suspend(void)
654{
655 int i, bank;
656
657 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
658 bank = gpio_bank(i);
659
269647dc 660#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
f556309e 661 gpio_bank_saved[bank].fer = *port_fer[bank];
269647dc 662#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
f556309e 663 gpio_bank_saved[bank].mux = *port_mux[bank];
1efc80b5 664#else
f556309e
MF		 665 if (bank == 0)
666 gpio_bank_saved[bank].mux = bfin_read_PORT_MUX();
1efc80b5
MH		 667#endif
668#endif
f556309e
MF		 669 gpio_bank_saved[bank].data = gpio_array[bank]->data;
670 gpio_bank_saved[bank].inen = gpio_array[bank]->inen;
671 gpio_bank_saved[bank].polar = gpio_array[bank]->polar;
672 gpio_bank_saved[bank].dir = gpio_array[bank]->dir;
673 gpio_bank_saved[bank].edge = gpio_array[bank]->edge;
674 gpio_bank_saved[bank].both = gpio_array[bank]->both;
675 gpio_bank_saved[bank].maska = gpio_array[bank]->maska;
1efc80b5
MH		 676 }
677
678 AWA_DUMMY_READ(maska);
679}
680
681void bfin_gpio_pm_hibernate_restore(void)
682{
683 int i, bank;
684
685 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
f556309e 686 bank = gpio_bank(i);
1efc80b5 687
269647dc
MF		 688#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
689#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
f556309e 690 *port_mux[bank] = gpio_bank_saved[bank].mux;
1efc80b5 691#else
f556309e
MF		 692 if (bank == 0)
693 bfin_write_PORT_MUX(gpio_bank_saved[bank].mux);
1efc80b5 694#endif
f556309e 695 *port_fer[bank] = gpio_bank_saved[bank].fer;
1efc80b5 696#endif
f556309e
MF		 697 gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
698 gpio_array[bank]->dir = gpio_bank_saved[bank].dir;
699 gpio_array[bank]->polar = gpio_bank_saved[bank].polar;
700 gpio_array[bank]->edge = gpio_bank_saved[bank].edge;
701 gpio_array[bank]->both = gpio_bank_saved[bank].both;
1efc80b5 702
f556309e
MF		 703 gpio_array[bank]->data_set = gpio_bank_saved[bank].data
704 | gpio_bank_saved[bank].dir;
1efc80b5 705
f556309e 706 gpio_array[bank]->maska = gpio_bank_saved[bank].maska;
1efc80b5
MH		 707 }
708 AWA_DUMMY_READ(maska);
709}
710
711
1394f032 712#endif
269647dc 713#else /* CONFIG_BF54x */
1efc80b5
MH		 714#ifdef CONFIG_PM
715
716u32 bfin_pm_standby_setup(void)
717{
718 return 0;
719}
720
721void bfin_pm_standby_restore(void)
722{
723
724}
725
726void bfin_gpio_pm_hibernate_suspend(void)
727{
728 int i, bank;
729
730 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
731 bank = gpio_bank(i);
732
f556309e
MF		 733 gpio_bank_saved[bank].fer = gpio_array[bank]->port_fer;
734 gpio_bank_saved[bank].mux = gpio_array[bank]->port_mux;
735 gpio_bank_saved[bank].data = gpio_array[bank]->data;
736 gpio_bank_saved[bank].data = gpio_array[bank]->data;
737 gpio_bank_saved[bank].inen = gpio_array[bank]->inen;
738 gpio_bank_saved[bank].dir = gpio_array[bank]->dir_set;
1efc80b5
MH		 739 }
740}
741
742void bfin_gpio_pm_hibernate_restore(void)
743{
744 int i, bank;
745
746 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
f556309e
MF		 747 bank = gpio_bank(i);
748
749 gpio_array[bank]->port_mux = gpio_bank_saved[bank].mux;
750 gpio_array[bank]->port_fer = gpio_bank_saved[bank].fer;
751 gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
752 gpio_array[bank]->dir_set = gpio_bank_saved[bank].dir;
753 gpio_array[bank]->data_set = gpio_bank_saved[bank].data
754 | gpio_bank_saved[bank].dir;
1efc80b5
MH		 755 }
756}
757#endif
fac3cf43 758
a2c8cfef 759unsigned short get_gpio_dir(unsigned gpio)
fac3cf43 760{
f556309e 761 return (0x01 & (gpio_array[gpio_bank(gpio)]->dir_clear >> gpio_sub_n(gpio)));
fac3cf43
MH		 762}
763EXPORT_SYMBOL(get_gpio_dir);
764
269647dc 765#endif /* CONFIG_BF54x */
1394f032 766
d2b11a46
MH		 767/***********************************************************
768*
769* FUNCTIONS: Blackfin Peripheral Resource Allocation
770* and PortMux Setup
771*
772* INPUTS/OUTPUTS:
773* per Peripheral Identifier
774* label String
775*
776* DESCRIPTION: Blackfin Peripheral Resource Allocation and Setup API
777*
778* CAUTION:
779*************************************************************
780* MODIFICATION HISTORY :
781**************************************************************/
782
d2b11a46
MH		 783int peripheral_request(unsigned short per, const char *label)
784{
785 unsigned long flags;
786 unsigned short ident = P_IDENT(per);
787
788 /*
789 * Don't cares are pins with only one dedicated function
790 */
c58c2140 791
d2b11a46
MH		 792 if (per & P_DONTCARE)
793 return 0;
794
795 if (!(per & P_DEFINED))
796 return -ENODEV;
797
6a01f230 798 local_irq_save_hw(flags);
d2b11a46 799
6a87d29b
MF		 800 /* If a pin can be muxed as either GPIO or peripheral, make
801 * sure it is not already a GPIO pin when we request it.
802 */
803 if (unlikely(!check_gpio(ident) &&
804 reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
f85c4abd 805 dump_stack();
d2b11a46 806 printk(KERN_ERR
6c7ec0ec 807 "%s: Peripheral %d is already reserved as GPIO by %s !\n",
b85d858b 808 __func__, ident, get_label(ident));
6a01f230 809 local_irq_restore_hw(flags);
d2b11a46
MH		 810 return -EBUSY;
811 }
812
813 if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
814
d171c233
MF		 815 /*
816 * Pin functions like AMC address strobes my
817 * be requested and used by several drivers
818 */
d2b11a46 819
269647dc 820#ifdef CONFIG_BF54x
f556309e 821 if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) {
6c7ec0ec
MF		 822#else
823 if (!(per & P_MAYSHARE)) {
824#endif
d171c233
MF		 825 /*
826 * Allow that the identical pin function can
827 * be requested from the same driver twice
828 */
d2b11a46 829
d171c233
MF		 830 if (cmp_label(ident, label) == 0)
831 goto anyway;
d2b11a46 832
f85c4abd 833 dump_stack();
d2b11a46
MH		 834 printk(KERN_ERR
835 "%s: Peripheral %d function %d is already reserved by %s !\n",
b85d858b 836 __func__, ident, P_FUNCT2MUX(per), get_label(ident));
6a01f230 837 local_irq_restore_hw(flags);
d2b11a46
MH		 838 return -EBUSY;
839 }
840 }
841
d171c233 842 anyway:
d2b11a46
MH		 843 reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
844
f556309e 845 portmux_setup(per);
c58c2140
MH		 846 port_setup(ident, PERIPHERAL_USAGE);
847
6a01f230 848 local_irq_restore_hw(flags);
c58c2140
MH		 849 set_label(ident, label);
850
851 return 0;
852}
853EXPORT_SYMBOL(peripheral_request);
854
68179371 855int peripheral_request_list(const unsigned short per[], const char *label)
c58c2140
MH		 856{
857 u16 cnt;
858 int ret;
859
860 for (cnt = 0; per[cnt] != 0; cnt++) {
314c98d5 861
c58c2140 862 ret = peripheral_request(per[cnt], label);
314c98d5
MH		 863
864 if (ret < 0) {
d171c233 865 for ( ; cnt > 0; cnt--)
314c98d5 866 peripheral_free(per[cnt - 1]);
d171c233
MF		 867
868 return ret;
314c98d5 869 }
c58c2140
MH		 870 }
871
872 return 0;
873}
874EXPORT_SYMBOL(peripheral_request_list);
875
876void peripheral_free(unsigned short per)
877{
878 unsigned long flags;
879 unsigned short ident = P_IDENT(per);
880
881 if (per & P_DONTCARE)
882 return;
883
884 if (!(per & P_DEFINED))
885 return;
886
6a01f230 887 local_irq_save_hw(flags);
c58c2140 888
d171c233 889 if (unlikely(!(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident)))) {
6a01f230 890 local_irq_restore_hw(flags);
c58c2140
MH		 891 return;
892 }
893
d171c233 894 if (!(per & P_MAYSHARE))
c58c2140 895 port_setup(ident, GPIO_USAGE);
c58c2140
MH		 896
897 reserved_peri_map[gpio_bank(ident)] &= ~gpio_bit(ident);
898
2acde902
MH		 899 set_label(ident, "free");
900
6a01f230 901 local_irq_restore_hw(flags);
c58c2140
MH		 902}
903EXPORT_SYMBOL(peripheral_free);
904
68179371 905void peripheral_free_list(const unsigned short per[])
c58c2140
MH		 906{
907 u16 cnt;
d171c233 908 for (cnt = 0; per[cnt] != 0; cnt++)
c58c2140 909 peripheral_free(per[cnt]);
c58c2140
MH		 910}
911EXPORT_SYMBOL(peripheral_free_list);
912
1394f032
BW		 913/***********************************************************
914*
915* FUNCTIONS: Blackfin GPIO Driver
916*
917* INPUTS/OUTPUTS:
d2b11a46
MH		 918* gpio PIO Number between 0 and MAX_BLACKFIN_GPIOS
919* label String
1394f032
BW		 920*
921* DESCRIPTION: Blackfin GPIO Driver API
922*
923* CAUTION:
924*************************************************************
925* MODIFICATION HISTORY :
926**************************************************************/
927
a4f0b32c 928int bfin_gpio_request(unsigned gpio, const char *label)
1394f032
BW		 929{
930 unsigned long flags;
931
932 if (check_gpio(gpio) < 0)
933 return -EINVAL;
934
6a01f230 935 local_irq_save_hw(flags);
1394f032 936
2acde902
MH		 937 /*
938 * Allow that the identical GPIO can
939 * be requested from the same driver twice
940 * Do nothing and return -
941 */
942
943 if (cmp_label(gpio, label) == 0) {
6a01f230 944 local_irq_restore_hw(flags);
2acde902
MH		 945 return 0;
946 }
947
c58c2140 948 if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
f85c4abd 949 dump_stack();
d2b11a46 950 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
9570ff4a 951 gpio, get_label(gpio));
6a01f230 952 local_irq_restore_hw(flags);
d2b11a46
MH		 953 return -EBUSY;
954 }
955 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
f85c4abd 956 dump_stack();
d2b11a46
MH		 957 printk(KERN_ERR
958 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
959 gpio, get_label(gpio));
6a01f230 960 local_irq_restore_hw(flags);
1394f032
BW		 961 return -EBUSY;
962 }
a2be3931 963 if (unlikely(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
9570ff4a
GY		 964 printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!"
965 " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio);
a2be3931 966 }
269647dc 967#ifndef CONFIG_BF54x
a2be3931
MH		 968 else { /* Reset POLAR setting when acquiring a gpio for the first time */
969 set_gpio_polar(gpio, 0);
970 }
971#endif
d2b11a46 972
c58c2140 973 reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
9570ff4a 974 set_label(gpio, label);
1394f032 975
6a01f230 976 local_irq_restore_hw(flags);
1394f032
BW		 977
978 port_setup(gpio, GPIO_USAGE);
979
980 return 0;
981}
a4f0b32c 982EXPORT_SYMBOL(bfin_gpio_request);
1394f032 983
a4f0b32c 984void bfin_gpio_free(unsigned gpio)
1394f032
BW		 985{
986 unsigned long flags;
987
988 if (check_gpio(gpio) < 0)
989 return;
990
45c4f2a0
UKK		 991 might_sleep();
992
6a01f230 993 local_irq_save_hw(flags);
1394f032 994
c58c2140 995 if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
1394f032 996 dump_stack();
f85c4abd 997 gpio_error(gpio);
6a01f230 998 local_irq_restore_hw(flags);
1394f032
BW		 999 return;
1000 }
1001
c58c2140 1002 reserved_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
1394f032 1003
2acde902
MH		 1004 set_label(gpio, "free");
1005
6a01f230 1006 local_irq_restore_hw(flags);
1394f032 1007}
a4f0b32c 1008EXPORT_SYMBOL(bfin_gpio_free);
1394f032 1009
9570ff4a
GY		 1010int bfin_gpio_irq_request(unsigned gpio, const char *label)
1011{
1012 unsigned long flags;
1013
1014 if (check_gpio(gpio) < 0)
1015 return -EINVAL;
1016
6a01f230 1017 local_irq_save_hw(flags);
9570ff4a
GY		 1018
1019 if (unlikely(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1020 dump_stack();
1021 printk(KERN_ERR
1022 "bfin-gpio: GPIO %d is already reserved as gpio-irq !\n",
1023 gpio);
6a01f230 1024 local_irq_restore_hw(flags);
9570ff4a
GY		 1025 return -EBUSY;
1026 }
1027 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1028 dump_stack();
1029 printk(KERN_ERR
1030 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
1031 gpio, get_label(gpio));
6a01f230 1032 local_irq_restore_hw(flags);
9570ff4a
GY		 1033 return -EBUSY;
1034 }
1035 if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))
1036 printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved by %s! "
1037 "(Documentation/blackfin/bfin-gpio-notes.txt)\n",
1038 gpio, get_label(gpio));
1039
1040 reserved_gpio_irq_map[gpio_bank(gpio)] |= gpio_bit(gpio);
1041 set_label(gpio, label);
1042
6a01f230 1043 local_irq_restore_hw(flags);
9570ff4a
GY		 1044
1045 port_setup(gpio, GPIO_USAGE);
1046
1047 return 0;
1048}
1049
1050void bfin_gpio_irq_free(unsigned gpio)
1051{
1052 unsigned long flags;
1053
1054 if (check_gpio(gpio) < 0)
1055 return;
1056
6a01f230 1057 local_irq_save_hw(flags);
9570ff4a
GY		 1058
1059 if (unlikely(!(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
1060 dump_stack();
1061 gpio_error(gpio);
6a01f230 1062 local_irq_restore_hw(flags);
9570ff4a
GY		 1063 return;
1064 }
1065
1066 reserved_gpio_irq_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
1067
1068 set_label(gpio, "free");
1069
6a01f230 1070 local_irq_restore_hw(flags);
9570ff4a
GY		 1071}
1072
f556309e
MF		 1073static inline void __bfin_gpio_direction_input(unsigned gpio)
1074{
269647dc 1075#ifdef CONFIG_BF54x
f556309e
MF		 1076 gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio);
1077#else
1078 gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
1079#endif
1080 gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
1081}
1082
a4f0b32c 1083int bfin_gpio_direction_input(unsigned gpio)
d2b11a46
MH		 1084{
1085 unsigned long flags;
1086
acbcd263
MH		 1087 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1088 gpio_error(gpio);
1089 return -EINVAL;
1090 }
1091
6a01f230 1092 local_irq_save_hw(flags);
f556309e
MF		 1093 __bfin_gpio_direction_input(gpio);
1094 AWA_DUMMY_READ(inen);
6a01f230 1095 local_irq_restore_hw(flags);
acbcd263
MH		 1096
1097 return 0;
d2b11a46 1098}
a4f0b32c 1099EXPORT_SYMBOL(bfin_gpio_direction_input);
d2b11a46 1100
f556309e 1101void bfin_gpio_irq_prepare(unsigned gpio)
d2b11a46 1102{
269647dc 1103#ifdef CONFIG_BF54x
d2b11a46 1104 unsigned long flags;
f556309e 1105#endif
d2b11a46 1106
f556309e 1107 port_setup(gpio, GPIO_USAGE);
d2b11a46 1108
269647dc 1109#ifdef CONFIG_BF54x
6a01f230 1110 local_irq_save_hw(flags);
f556309e 1111 __bfin_gpio_direction_input(gpio);
6a01f230 1112 local_irq_restore_hw(flags);
f556309e 1113#endif
d2b11a46 1114}
d2b11a46 1115
a4f0b32c 1116void bfin_gpio_set_value(unsigned gpio, int arg)
d2b11a46
MH		 1117{
1118 if (arg)
f556309e 1119 gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
d2b11a46 1120 else
f556309e 1121 gpio_array[gpio_bank(gpio)]->data_clear = gpio_bit(gpio);
d2b11a46 1122}
a4f0b32c 1123EXPORT_SYMBOL(bfin_gpio_set_value);
d2b11a46 1124
f556309e 1125int bfin_gpio_direction_output(unsigned gpio, int value)
affee2b2
MH		 1126{
1127 unsigned long flags;
1128
f556309e
MF		 1129 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1130 gpio_error(gpio);
1131 return -EINVAL;
1132 }
affee2b2 1133
6a01f230 1134 local_irq_save_hw(flags);
affee2b2 1135
f556309e
MF		 1136 gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
1137 gpio_set_value(gpio, value);
269647dc 1138#ifdef CONFIG_BF54x
f556309e 1139 gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio);
d2b11a46 1140#else
f556309e
MF		 1141 gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
1142#endif
1143
1144 AWA_DUMMY_READ(dir);
1145 local_irq_restore_hw(flags);
1146
1147 return 0;
1148}
1149EXPORT_SYMBOL(bfin_gpio_direction_output);
d2b11a46 1150
a4f0b32c 1151int bfin_gpio_get_value(unsigned gpio)
803a8d2a 1152{
269647dc 1153#ifdef CONFIG_BF54x
f556309e
MF		 1154 return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio)));
1155#else
803a8d2a 1156 unsigned long flags;
803a8d2a
MH		 1157
1158 if (unlikely(get_gpio_edge(gpio))) {
f556309e 1159 int ret;
6a01f230 1160 local_irq_save_hw(flags);
803a8d2a
MH		 1161 set_gpio_edge(gpio, 0);
1162 ret = get_gpio_data(gpio);
1163 set_gpio_edge(gpio, 1);
6a01f230 1164 local_irq_restore_hw(flags);
803a8d2a
MH		 1165 return ret;
1166 } else
1167 return get_gpio_data(gpio);
f556309e 1168#endif
803a8d2a 1169}
a4f0b32c 1170EXPORT_SYMBOL(bfin_gpio_get_value);
803a8d2a 1171
168f1212
MF		 1172/* If we are booting from SPI and our board lacks a strong enough pull up,
1173 * the core can reset and execute the bootrom faster than the resistor can
1174 * pull the signal logically high. To work around this (common) error in
1175 * board design, we explicitly set the pin back to GPIO mode, force /CS
1176 * high, and wait for the electrons to do their thing.
1177 *
1178 * This function only makes sense to be called from reset code, but it
1179 * lives here as we need to force all the GPIO states w/out going through
1180 * BUG() checks and such.
1181 */
b52dae31 1182void bfin_reset_boot_spi_cs(unsigned short pin)
168f1212 1183{
b52dae31 1184 unsigned short gpio = P_IDENT(pin);
4d5f4ed3 1185 port_setup(gpio, GPIO_USAGE);
f556309e 1186 gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
a2c8cfef 1187 AWA_DUMMY_READ(data_set);
168f1212
MF		 1188 udelay(1);
1189}
d2b11a46 1190
1545a111
MF		 1191#if defined(CONFIG_PROC_FS)
1192static int gpio_proc_read(char *buf, char **start, off_t offset,
1193 int len, int *unused_i, void *unused_v)
1194{
9570ff4a 1195 int c, irq, gpio, outlen = 0;
1545a111
MF		 1196
1197 for (c = 0; c < MAX_RESOURCES; c++) {
9570ff4a
GY		 1198 irq = reserved_gpio_irq_map[gpio_bank(c)] & gpio_bit(c);
1199 gpio = reserved_gpio_map[gpio_bank(c)] & gpio_bit(c);
1200 if (!check_gpio(c) && (gpio || irq))
1201 len = sprintf(buf, "GPIO_%d: \t%s%s \t\tGPIO %s\n", c,
1202 get_label(c), (gpio && irq) ? " *" : "",
1203 get_gpio_dir(c) ? "OUTPUT" : "INPUT");
1545a111 1204 else if (reserved_peri_map[gpio_bank(c)] & gpio_bit(c))
8eb3e3bf 1205 len = sprintf(buf, "GPIO_%d: \t%s \t\tPeripheral\n", c, get_label(c));
1545a111
MF		 1206 else
1207 continue;
1208 buf += len;
1209 outlen += len;
1210 }
1211 return outlen;
1212}
1213
1214static __init int gpio_register_proc(void)
1215{
1216 struct proc_dir_entry *proc_gpio;
1217
1218 proc_gpio = create_proc_entry("gpio", S_IRUGO, NULL);
1219 if (proc_gpio)
1220 proc_gpio->read_proc = gpio_proc_read;
1221 return proc_gpio != NULL;
1222}
1545a111
MF		 1223__initcall(gpio_register_proc);
1224#endif
a4f0b32c
MH		 1225
1226#ifdef CONFIG_GPIOLIB
1227int bfin_gpiolib_direction_input(struct gpio_chip *chip, unsigned gpio)
1228{
1229 return bfin_gpio_direction_input(gpio);
1230}
1231
1232int bfin_gpiolib_direction_output(struct gpio_chip *chip, unsigned gpio, int level)
1233{
1234 return bfin_gpio_direction_output(gpio, level);
1235}
1236
1237int bfin_gpiolib_get_value(struct gpio_chip *chip, unsigned gpio)
1238{
1239 return bfin_gpio_get_value(gpio);
1240}
1241
1242void bfin_gpiolib_set_value(struct gpio_chip *chip, unsigned gpio, int value)
1243{
a4f0b32c 1244 return bfin_gpio_set_value(gpio, value);
a4f0b32c
MH		 1245}
1246
1247int bfin_gpiolib_gpio_request(struct gpio_chip *chip, unsigned gpio)
1248{
1249 return bfin_gpio_request(gpio, chip->label);
1250}
1251
1252void bfin_gpiolib_gpio_free(struct gpio_chip *chip, unsigned gpio)
1253{
1254 return bfin_gpio_free(gpio);
1255}
1256
1257static struct gpio_chip bfin_chip = {
1258 .label = "Blackfin-GPIOlib",
1259 .direction_input = bfin_gpiolib_direction_input,
1260 .get = bfin_gpiolib_get_value,
1261 .direction_output = bfin_gpiolib_direction_output,
1262 .set = bfin_gpiolib_set_value,
1263 .request = bfin_gpiolib_gpio_request,
1264 .free = bfin_gpiolib_gpio_free,
1265 .base = 0,
1266 .ngpio = MAX_BLACKFIN_GPIOS,
1267};
1268
1269static int __init bfin_gpiolib_setup(void)
1270{
1271 return gpiochip_add(&bfin_chip);
1272}
1273arch_initcall(bfin_gpiolib_setup);
1274#endif
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