[mirror_ubuntu-zesty-kernel.git] / arch / blackfin / kernel / cplb-mpu / cplbmgr.c

/*
 * Blackfin CPLB exception handling for when MPU in on
 *
 * Copyright 2008-2009 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#include <linux/module.h>
#include <linux/mm.h>

#include <asm/blackfin.h>
#include <asm/cacheflush.h>
#include <asm/cplb.h>
#include <asm/cplbinit.h>
#include <asm/mmu_context.h>

/*
 * WARNING
 *
 * This file is compiled with certain -ffixed-reg options.  We have to
 * make sure not to call any functions here that could clobber these
 * registers.
 */

int page_mask_nelts;
int page_mask_order;
unsigned long *current_rwx_mask[NR_CPUS];

int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS];
int nr_icplb_supv_miss[NR_CPUS], nr_dcplb_prot[NR_CPUS];
int nr_cplb_flush[NR_CPUS];

/*
 * Given the contents of the status register, return the index of the
 * CPLB that caused the fault.
 */
static inline int faulting_cplb_index(int status)
{
	int signbits = __builtin_bfin_norm_fr1x32(status & 0xFFFF);
	return 30 - signbits;
}

/*
 * Given the contents of the status register and the DCPLB_DATA contents,
 * return true if a write access should be permitted.
 */
static inline int write_permitted(int status, unsigned long data)
{
	if (status & FAULT_USERSUPV)
		return !!(data & CPLB_SUPV_WR);
	else
		return !!(data & CPLB_USER_WR);
}

/* Counters to implement round-robin replacement.  */
static int icplb_rr_index[NR_CPUS], dcplb_rr_index[NR_CPUS];

/*
 * Find an ICPLB entry to be evicted and return its index.
 */
static int evict_one_icplb(unsigned int cpu)
{
	int i;
	for (i = first_switched_icplb; i < MAX_CPLBS; i++)
		if ((icplb_tbl[cpu][i].data & CPLB_VALID) == 0)
			return i;
	i = first_switched_icplb + icplb_rr_index[cpu];
	if (i >= MAX_CPLBS) {
		i -= MAX_CPLBS - first_switched_icplb;
		icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb;
	}
	icplb_rr_index[cpu]++;
	return i;
}

static int evict_one_dcplb(unsigned int cpu)
{
	int i;
	for (i = first_switched_dcplb; i < MAX_CPLBS; i++)
		if ((dcplb_tbl[cpu][i].data & CPLB_VALID) == 0)
			return i;
	i = first_switched_dcplb + dcplb_rr_index[cpu];
	if (i >= MAX_CPLBS) {
		i -= MAX_CPLBS - first_switched_dcplb;
		dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb;
	}
	dcplb_rr_index[cpu]++;
	return i;
}

static noinline int dcplb_miss(unsigned int cpu)
{
	unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
	int status = bfin_read_DCPLB_STATUS();
	unsigned long *mask;
	int idx;
	unsigned long d_data;

	nr_dcplb_miss[cpu]++;

	d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
	if (bfin_addr_dcacheable(addr)) {
		d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
		d_data |= CPLB_L1_AOW | CPLB_WT;
# endif
	}
#endif

	if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
		addr = L2_START;
		d_data = L2_DMEMORY;
	} else if (addr >= physical_mem_end) {
		if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE
		    && (status & FAULT_USERSUPV)) {
			addr &= ~0x3fffff;
			d_data &= ~PAGE_SIZE_4KB;
			d_data |= PAGE_SIZE_4MB;
		} else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
		    && (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) {
			addr &= ~(1 * 1024 * 1024 - 1);
			d_data &= ~PAGE_SIZE_4KB;
			d_data |= PAGE_SIZE_1MB;
		} else
			return CPLB_PROT_VIOL;
	} else if (addr >= _ramend) {
	    d_data |= CPLB_USER_RD | CPLB_USER_WR;
	} else {
		mask = current_rwx_mask[cpu];
		if (mask) {
			int page = addr >> PAGE_SHIFT;
			int idx = page >> 5;
			int bit = 1 << (page & 31);

			if (mask[idx] & bit)
				d_data |= CPLB_USER_RD;

			mask += page_mask_nelts;
			if (mask[idx] & bit)
				d_data |= CPLB_USER_WR;
		}
	}
	idx = evict_one_dcplb(cpu);

	addr &= PAGE_MASK;
	dcplb_tbl[cpu][idx].addr = addr;
	dcplb_tbl[cpu][idx].data = d_data;

	_disable_dcplb();
	bfin_write32(DCPLB_DATA0 + idx * 4, d_data);
	bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
	_enable_dcplb();

	return 0;
}

static noinline int icplb_miss(unsigned int cpu)
{
	unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
	int status = bfin_read_ICPLB_STATUS();
	int idx;
	unsigned long i_data;

	nr_icplb_miss[cpu]++;

	/* If inside the uncached DMA region, fault.  */
	if (addr >= _ramend - DMA_UNCACHED_REGION && addr < _ramend)
		return CPLB_PROT_VIOL;

	if (status & FAULT_USERSUPV)
		nr_icplb_supv_miss[cpu]++;

	/*
	 * First, try to find a CPLB that matches this address.  If we
	 * find one, then the fact that we're in the miss handler means
	 * that the instruction crosses a page boundary.
	 */
	for (idx = first_switched_icplb; idx < MAX_CPLBS; idx++) {
		if (icplb_tbl[cpu][idx].data & CPLB_VALID) {
			unsigned long this_addr = icplb_tbl[cpu][idx].addr;
			if (this_addr <= addr && this_addr + PAGE_SIZE > addr) {
				addr += PAGE_SIZE;
				break;
			}
		}
	}

	i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB;

#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
	/*
	 * Normal RAM, and possibly the reserved memory area, are
	 * cacheable.
	 */
	if (addr < _ramend ||
	    (addr < physical_mem_end && reserved_mem_icache_on))
		i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
#endif

	if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
		addr = L2_START;
		i_data = L2_IMEMORY;
	} else if (addr >= physical_mem_end) {
		if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
		    && (status & FAULT_USERSUPV)) {
			addr &= ~(1 * 1024 * 1024 - 1);
			i_data &= ~PAGE_SIZE_4KB;
			i_data |= PAGE_SIZE_1MB;
		} else
		    return CPLB_PROT_VIOL;
	} else if (addr >= _ramend) {
		i_data |= CPLB_USER_RD;
	} else {
		/*
		 * Two cases to distinguish - a supervisor access must
		 * necessarily be for a module page; we grant it
		 * unconditionally (could do better here in the future).
		 * Otherwise, check the x bitmap of the current process.
		 */
		if (!(status & FAULT_USERSUPV)) {
			unsigned long *mask = current_rwx_mask[cpu];

			if (mask) {
				int page = addr >> PAGE_SHIFT;
				int idx = page >> 5;
				int bit = 1 << (page & 31);

				mask += 2 * page_mask_nelts;
				if (mask[idx] & bit)
					i_data |= CPLB_USER_RD;
			}
		}
	}
	idx = evict_one_icplb(cpu);
	addr &= PAGE_MASK;
	icplb_tbl[cpu][idx].addr = addr;
	icplb_tbl[cpu][idx].data = i_data;

	_disable_icplb();
	bfin_write32(ICPLB_DATA0 + idx * 4, i_data);
	bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
	_enable_icplb();

	return 0;
}

static noinline int dcplb_protection_fault(unsigned int cpu)
{
	int status = bfin_read_DCPLB_STATUS();

	nr_dcplb_prot[cpu]++;

	if (status & FAULT_RW) {
		int idx = faulting_cplb_index(status);
		unsigned long data = dcplb_tbl[cpu][idx].data;
		if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) &&
		    write_permitted(status, data)) {
			data |= CPLB_DIRTY;
			dcplb_tbl[cpu][idx].data = data;
			bfin_write32(DCPLB_DATA0 + idx * 4, data);
			return 0;
		}
	}
	return CPLB_PROT_VIOL;
}

int cplb_hdr(int seqstat, struct pt_regs *regs)
{
	int cause = seqstat & 0x3f;
	unsigned int cpu = raw_smp_processor_id();
	switch (cause) {
	case 0x23:
		return dcplb_protection_fault(cpu);
	case 0x2C:
		return icplb_miss(cpu);
	case 0x26:
		return dcplb_miss(cpu);
	default:
		return 1;
	}
}

void flush_switched_cplbs(unsigned int cpu)
{
	int i;
	unsigned long flags;

	nr_cplb_flush[cpu]++;

	local_irq_save_hw(flags);
	_disable_icplb();
	for (i = first_switched_icplb; i < MAX_CPLBS; i++) {
		icplb_tbl[cpu][i].data = 0;
		bfin_write32(ICPLB_DATA0 + i * 4, 0);
	}
	_enable_icplb();

	_disable_dcplb();
	for (i = first_switched_dcplb; i < MAX_CPLBS; i++) {
		dcplb_tbl[cpu][i].data = 0;
		bfin_write32(DCPLB_DATA0 + i * 4, 0);
	}
	_enable_dcplb();
	local_irq_restore_hw(flags);

}

void set_mask_dcplbs(unsigned long *masks, unsigned int cpu)
{
	int i;
	unsigned long addr = (unsigned long)masks;
	unsigned long d_data;
	unsigned long flags;

	if (!masks) {
		current_rwx_mask[cpu] = masks;
		return;
	}

	local_irq_save_hw(flags);
	current_rwx_mask[cpu] = masks;

	if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
		addr = L2_START;
		d_data = L2_DMEMORY;
	} else {
		d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
		d_data |= CPLB_L1_CHBL;
# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
		d_data |= CPLB_L1_AOW | CPLB_WT;
# endif
#endif
	}

	_disable_dcplb();
	for (i = first_mask_dcplb; i < first_switched_dcplb; i++) {
		dcplb_tbl[cpu][i].addr = addr;
		dcplb_tbl[cpu][i].data = d_data;
		bfin_write32(DCPLB_DATA0 + i * 4, d_data);
		bfin_write32(DCPLB_ADDR0 + i * 4, addr);
		addr += PAGE_SIZE;
	}
	_enable_dcplb();
	local_irq_restore_hw(flags);
}
Commit	Line	Data
b97b8a99	1	/*
96f1050d	2	* Blackfin CPLB exception handling for when MPU in on
b97b8a99	3	*
96f1050d	4	* Copyright 2008-2009 Analog Devices Inc.
b97b8a99	5	*
96f1050d	6	* Licensed under the GPL-2 or later.
b97b8a99	7	*/
96f1050d	8
b97b8a99 BS	9	#include <linux/module.h>
	10	#include <linux/mm.h>
	11
	12	#include <asm/blackfin.h>
a92946bc	13	#include <asm/cacheflush.h>
eb7bd9c4	14	#include <asm/cplb.h>
b97b8a99 BS	15	#include <asm/cplbinit.h>
	16	#include <asm/mmu_context.h>
	17
dbdf20db BS	18	/*
	19	* WARNING
	20	*
	21	* This file is compiled with certain -ffixed-reg options. We have to
	22	* make sure not to call any functions here that could clobber these
	23	* registers.
	24	*/
b97b8a99 BS	25
	26	int page_mask_nelts;
	27	int page_mask_order;
b8a98989	28	unsigned long *current_rwx_mask[NR_CPUS];
b97b8a99	29
b8a98989 GY	30	int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS];
	31	int nr_icplb_supv_miss[NR_CPUS], nr_dcplb_prot[NR_CPUS];
	32	int nr_cplb_flush[NR_CPUS];
b97b8a99	33
b97b8a99 BS	34	/*
	35	* Given the contents of the status register, return the index of the
	36	* CPLB that caused the fault.
	37	*/
	38	static inline int faulting_cplb_index(int status)
	39	{
	40	int signbits = __builtin_bfin_norm_fr1x32(status & 0xFFFF);
	41	return 30 - signbits;
	42	}
	43
	44	/*
	45	* Given the contents of the status register and the DCPLB_DATA contents,
	46	* return true if a write access should be permitted.
	47	*/
	48	static inline int write_permitted(int status, unsigned long data)
	49	{
	50	if (status & FAULT_USERSUPV)
	51	return !!(data & CPLB_SUPV_WR);
	52	else
	53	return !!(data & CPLB_USER_WR);
	54	}
	55
	56	/* Counters to implement round-robin replacement. */
b8a98989	57	static int icplb_rr_index[NR_CPUS], dcplb_rr_index[NR_CPUS];
b97b8a99 BS	58
	59	/*
	60	* Find an ICPLB entry to be evicted and return its index.
	61	*/
b8a98989	62	static int evict_one_icplb(unsigned int cpu)
b97b8a99 BS	63	{
	64	int i;
	65	for (i = first_switched_icplb; i < MAX_CPLBS; i++)
b8a98989	66	if ((icplb_tbl[cpu][i].data & CPLB_VALID) == 0)
b97b8a99	67	return i;
b8a98989	68	i = first_switched_icplb + icplb_rr_index[cpu];
b97b8a99 BS	69	if (i >= MAX_CPLBS) {
b97b8a99 BS	70	i -= MAX_CPLBS - first_switched_icplb;
b8a98989	71	icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb;
b97b8a99	72	}
b8a98989	73	icplb_rr_index[cpu]++;
b97b8a99 BS	74	return i;
	75	}
	76
b8a98989	77	static int evict_one_dcplb(unsigned int cpu)
b97b8a99 BS	78	{
	79	int i;
	80	for (i = first_switched_dcplb; i < MAX_CPLBS; i++)
b8a98989	81	if ((dcplb_tbl[cpu][i].data & CPLB_VALID) == 0)
b97b8a99	82	return i;
b8a98989	83	i = first_switched_dcplb + dcplb_rr_index[cpu];
b97b8a99 BS	84	if (i >= MAX_CPLBS) {
b97b8a99 BS	85	i -= MAX_CPLBS - first_switched_dcplb;
b8a98989	86	dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb;
b97b8a99	87	}
b8a98989	88	dcplb_rr_index[cpu]++;
b97b8a99 BS	89	return i;
	90	}
	91
b8a98989	92	static noinline int dcplb_miss(unsigned int cpu)
b97b8a99 BS	93	{
	94	unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
	95	int status = bfin_read_DCPLB_STATUS();
	96	unsigned long *mask;
	97	int idx;
	98	unsigned long d_data;
	99
b8a98989	100	nr_dcplb_miss[cpu]++;
b97b8a99 BS	101
b97b8a99 BS	102	d_data = CPLB_SUPV_WR \| CPLB_VALID \| CPLB_DIRTY \| PAGE_SIZE_4KB;
41ba653f	103	#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
67834fa9	104	if (bfin_addr_dcacheable(addr)) {
b4bb68f7	105	d_data \|= CPLB_L1_CHBL \| ANOMALY_05000158_WORKAROUND;
41ba653f	106	# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
b4bb68f7	107	d_data \|= CPLB_L1_AOW \| CPLB_WT;
41ba653f	108	# endif
b97b8a99	109	}
b4bb68f7	110	#endif
41ba653f JZ	111
	112	if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
	113	addr = L2_START;
	114	d_data = L2_DMEMORY;
	115	} else if (addr >= physical_mem_end) {
b4bb68f7 BS	116	if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE
	117	&& (status & FAULT_USERSUPV)) {
	118	addr &= ~0x3fffff;
	119	d_data &= ~PAGE_SIZE_4KB;
	120	d_data \|= PAGE_SIZE_4MB;
4e354b54 MF	121	} else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
	122	&& (status & (FAULT_RW \| FAULT_USERSUPV)) == FAULT_USERSUPV) {
	123	addr &= ~(1 * 1024 * 1024 - 1);
	124	d_data &= ~PAGE_SIZE_4KB;
4bea8b20	125	d_data \|= PAGE_SIZE_1MB;
b4bb68f7 BS	126	} else
b4bb68f7 BS	127	return CPLB_PROT_VIOL;
1ebc723c BS	128	} else if (addr >= _ramend) {
1ebc723c BS	129	d_data \|= CPLB_USER_RD \| CPLB_USER_WR;
b4bb68f7	130	} else {
b8a98989	131	mask = current_rwx_mask[cpu];
b4bb68f7 BS	132	if (mask) {
b4bb68f7 BS	133	int page = addr >> PAGE_SHIFT;
b8a98989	134	int idx = page >> 5;
b4bb68f7 BS	135	int bit = 1 << (page & 31);
b4bb68f7 BS	136
b8a98989	137	if (mask[idx] & bit)
b4bb68f7	138	d_data \|= CPLB_USER_RD;
b97b8a99	139
b4bb68f7	140	mask += page_mask_nelts;
b8a98989	141	if (mask[idx] & bit)
b4bb68f7 BS	142	d_data \|= CPLB_USER_WR;
	143	}
	144	}
b8a98989	145	idx = evict_one_dcplb(cpu);
b97b8a99 BS	146
b97b8a99 BS	147	addr &= PAGE_MASK;
b8a98989 GY	148	dcplb_tbl[cpu][idx].addr = addr;
b8a98989 GY	149	dcplb_tbl[cpu][idx].data = d_data;
b97b8a99	150
eb7bd9c4	151	_disable_dcplb();
b97b8a99 BS	152	bfin_write32(DCPLB_DATA0 + idx * 4, d_data);
b97b8a99 BS	153	bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
eb7bd9c4	154	_enable_dcplb();
b97b8a99 BS	155
	156	return 0;
	157	}
	158
b8a98989	159	static noinline int icplb_miss(unsigned int cpu)
b97b8a99 BS	160	{
	161	unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
	162	int status = bfin_read_ICPLB_STATUS();
	163	int idx;
	164	unsigned long i_data;
	165
b8a98989	166	nr_icplb_miss[cpu]++;
b97b8a99	167
1ebc723c BS	168	/* If inside the uncached DMA region, fault. */
1ebc723c BS	169	if (addr >= _ramend - DMA_UNCACHED_REGION && addr < _ramend)
b97b8a99 BS	170	return CPLB_PROT_VIOL;
b97b8a99 BS	171
1ebc723c	172	if (status & FAULT_USERSUPV)
b8a98989	173	nr_icplb_supv_miss[cpu]++;
1ebc723c	174
b97b8a99 BS	175	/*
	176	* First, try to find a CPLB that matches this address. If we
	177	* find one, then the fact that we're in the miss handler means
	178	* that the instruction crosses a page boundary.
	179	*/
	180	for (idx = first_switched_icplb; idx < MAX_CPLBS; idx++) {
b8a98989 GY	181	if (icplb_tbl[cpu][idx].data & CPLB_VALID) {
b8a98989 GY	182	unsigned long this_addr = icplb_tbl[cpu][idx].addr;
b97b8a99 BS	183	if (this_addr <= addr && this_addr + PAGE_SIZE > addr) {
	184	addr += PAGE_SIZE;
	185	break;
	186	}
	187	}
	188	}
	189
	190	i_data = CPLB_VALID \| CPLB_PORTPRIO \| PAGE_SIZE_4KB;
b97b8a99	191
41ba653f	192	#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
b97b8a99	193	/*
1ebc723c BS	194	* Normal RAM, and possibly the reserved memory area, are
1ebc723c BS	195	* cacheable.
b97b8a99	196	*/
1ebc723c BS	197	if (addr < _ramend \|\|
	198	(addr < physical_mem_end && reserved_mem_icache_on))
	199	i_data \|= CPLB_L1_CHBL \| ANOMALY_05000158_WORKAROUND;
	200	#endif
b97b8a99	201
41ba653f JZ	202	if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
	203	addr = L2_START;
	204	i_data = L2_IMEMORY;
	205	} else if (addr >= physical_mem_end) {
4bea8b20 MF	206	if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
	207	&& (status & FAULT_USERSUPV)) {
	208	addr &= ~(1 * 1024 * 1024 - 1);
	209	i_data &= ~PAGE_SIZE_4KB;
	210	i_data \|= PAGE_SIZE_1MB;
	211	} else
	212	return CPLB_PROT_VIOL;
1ebc723c BS	213	} else if (addr >= _ramend) {
	214	i_data \|= CPLB_USER_RD;
	215	} else {
	216	/*
	217	* Two cases to distinguish - a supervisor access must
	218	* necessarily be for a module page; we grant it
	219	* unconditionally (could do better here in the future).
	220	* Otherwise, check the x bitmap of the current process.
	221	*/
	222	if (!(status & FAULT_USERSUPV)) {
b8a98989	223	unsigned long *mask = current_rwx_mask[cpu];
1ebc723c BS	224
	225	if (mask) {
	226	int page = addr >> PAGE_SHIFT;
b8a98989	227	int idx = page >> 5;
1ebc723c BS	228	int bit = 1 << (page & 31);
	229
	230	mask += 2 * page_mask_nelts;
b8a98989	231	if (mask[idx] & bit)
1ebc723c BS	232	i_data \|= CPLB_USER_RD;
1ebc723c BS	233	}
b97b8a99 BS	234	}
b97b8a99 BS	235	}
b8a98989	236	idx = evict_one_icplb(cpu);
b97b8a99	237	addr &= PAGE_MASK;
b8a98989 GY	238	icplb_tbl[cpu][idx].addr = addr;
b8a98989 GY	239	icplb_tbl[cpu][idx].data = i_data;
b97b8a99	240
eb7bd9c4	241	_disable_icplb();
b97b8a99 BS	242	bfin_write32(ICPLB_DATA0 + idx * 4, i_data);
b97b8a99 BS	243	bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
eb7bd9c4	244	_enable_icplb();
b97b8a99 BS	245
	246	return 0;
	247	}
	248
b8a98989	249	static noinline int dcplb_protection_fault(unsigned int cpu)
b97b8a99	250	{
b97b8a99 BS	251	int status = bfin_read_DCPLB_STATUS();
b97b8a99 BS	252
b8a98989	253	nr_dcplb_prot[cpu]++;
b97b8a99 BS	254
	255	if (status & FAULT_RW) {
	256	int idx = faulting_cplb_index(status);
b8a98989	257	unsigned long data = dcplb_tbl[cpu][idx].data;
b97b8a99 BS	258	if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) &&
	259	write_permitted(status, data)) {
	260	data \|= CPLB_DIRTY;
b8a98989	261	dcplb_tbl[cpu][idx].data = data;
b97b8a99 BS	262	bfin_write32(DCPLB_DATA0 + idx * 4, data);
	263	return 0;
	264	}
	265	}
	266	return CPLB_PROT_VIOL;
	267	}
	268
	269	int cplb_hdr(int seqstat, struct pt_regs *regs)
	270	{
	271	int cause = seqstat & 0x3f;
b6dbde27	272	unsigned int cpu = raw_smp_processor_id();
b97b8a99 BS	273	switch (cause) {
b97b8a99 BS	274	case 0x23:
b8a98989	275	return dcplb_protection_fault(cpu);
b97b8a99	276	case 0x2C:
b8a98989	277	return icplb_miss(cpu);
b97b8a99	278	case 0x26:
b8a98989	279	return dcplb_miss(cpu);
b97b8a99	280	default:
b4bb68f7	281	return 1;
b97b8a99 BS	282	}
	283	}
	284
b8a98989	285	void flush_switched_cplbs(unsigned int cpu)
b97b8a99 BS	286	{
b97b8a99 BS	287	int i;
5d2e3213	288	unsigned long flags;
b97b8a99	289
b8a98989	290	nr_cplb_flush[cpu]++;
b97b8a99	291
6a01f230	292	local_irq_save_hw(flags);
eb7bd9c4	293	_disable_icplb();
b97b8a99	294	for (i = first_switched_icplb; i < MAX_CPLBS; i++) {
b8a98989	295	icplb_tbl[cpu][i].data = 0;
b97b8a99 BS	296	bfin_write32(ICPLB_DATA0 + i * 4, 0);
b97b8a99 BS	297	}
eb7bd9c4	298	_enable_icplb();
b97b8a99	299
eb7bd9c4	300	_disable_dcplb();
d56daae9	301	for (i = first_switched_dcplb; i < MAX_CPLBS; i++) {
b8a98989	302	dcplb_tbl[cpu][i].data = 0;
b97b8a99 BS	303	bfin_write32(DCPLB_DATA0 + i * 4, 0);
b97b8a99 BS	304	}
eb7bd9c4	305	_enable_dcplb();
6a01f230	306	local_irq_restore_hw(flags);
5d2e3213	307
b97b8a99 BS	308	}
b97b8a99 BS	309
b8a98989	310	void set_mask_dcplbs(unsigned long *masks, unsigned int cpu)
b97b8a99 BS	311	{
	312	int i;
	313	unsigned long addr = (unsigned long)masks;
	314	unsigned long d_data;
5d2e3213	315	unsigned long flags;
b97b8a99	316
5d2e3213	317	if (!masks) {
b8a98989	318	current_rwx_mask[cpu] = masks;
b97b8a99	319	return;
5d2e3213 BS	320	}
5d2e3213 BS	321
6a01f230	322	local_irq_save_hw(flags);
b8a98989	323	current_rwx_mask[cpu] = masks;
b97b8a99	324
41ba653f JZ	325	if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
	326	addr = L2_START;
	327	d_data = L2_DMEMORY;
	328	} else {
	329	d_data = CPLB_SUPV_WR \| CPLB_VALID \| CPLB_DIRTY \| PAGE_SIZE_4KB;
	330	#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
	331	d_data \|= CPLB_L1_CHBL;
	332	# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
	333	d_data \|= CPLB_L1_AOW \| CPLB_WT;
	334	# endif
b97b8a99	335	#endif
41ba653f	336	}
b97b8a99	337
eb7bd9c4	338	_disable_dcplb();
b97b8a99	339	for (i = first_mask_dcplb; i < first_switched_dcplb; i++) {
b8a98989 GY	340	dcplb_tbl[cpu][i].addr = addr;
b8a98989 GY	341	dcplb_tbl[cpu][i].data = d_data;
b97b8a99 BS	342	bfin_write32(DCPLB_DATA0 + i * 4, d_data);
	343	bfin_write32(DCPLB_ADDR0 + i * 4, addr);
	344	addr += PAGE_SIZE;
	345	}
eb7bd9c4	346	_enable_dcplb();
6a01f230	347	local_irq_restore_hw(flags);
b97b8a99	348	}