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73ecfcf9 MF |
1 | /* |
2 | * debugfs interface to core/system MMRs | |
3 | * | |
4 | * Copyright 2007-2011 Analog Devices Inc. | |
5 | * | |
6 | * Licensed under the GPL-2 or later | |
7 | */ | |
8 | ||
9 | #include <linux/debugfs.h> | |
10 | #include <linux/fs.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/module.h> | |
45126da2 | 13 | #include <linux/i2c/bfin_twi.h> |
73ecfcf9 MF |
14 | |
15 | #include <asm/blackfin.h> | |
16 | #include <asm/gpio.h> | |
d09fb602 | 17 | #include <asm/gptimers.h> |
73ecfcf9 MF |
18 | #include <asm/bfin_can.h> |
19 | #include <asm/bfin_dma.h> | |
20 | #include <asm/bfin_ppi.h> | |
21 | #include <asm/bfin_serial.h> | |
22 | #include <asm/bfin5xx_spi.h> | |
23 | #include <asm/bfin_twi.h> | |
24 | ||
25 | /* Common code defines PORT_MUX on us, so redirect the MMR back locally */ | |
26 | #ifdef BFIN_PORT_MUX | |
27 | #undef PORT_MUX | |
28 | #define PORT_MUX BFIN_PORT_MUX | |
29 | #endif | |
30 | ||
94674b15 | 31 | #define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)(addr)) |
73ecfcf9 MF |
32 | #define d(name, bits, addr) _d(name, bits, addr, S_IRUSR|S_IWUSR) |
33 | #define d_RO(name, bits, addr) _d(name, bits, addr, S_IRUSR) | |
34 | #define d_WO(name, bits, addr) _d(name, bits, addr, S_IWUSR) | |
35 | ||
36 | #define D_RO(name, bits) d_RO(#name, bits, name) | |
37 | #define D_WO(name, bits) d_WO(#name, bits, name) | |
38 | #define D32(name) d(#name, 32, name) | |
39 | #define D16(name) d(#name, 16, name) | |
40 | ||
41 | #define REGS_OFF(peri, mmr) offsetof(struct bfin_##peri##_regs, mmr) | |
42 | #define __REGS(peri, sname, rname) \ | |
43 | do { \ | |
44 | struct bfin_##peri##_regs r; \ | |
45 | void *addr = (void *)(base + REGS_OFF(peri, rname)); \ | |
46 | strcpy(_buf, sname); \ | |
47 | if (sizeof(r.rname) == 2) \ | |
48 | debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, addr); \ | |
49 | else \ | |
50 | debugfs_create_x32(buf, S_IRUSR|S_IWUSR, parent, addr); \ | |
51 | } while (0) | |
52 | #define REGS_STR_PFX(buf, pfx, num) \ | |
53 | ({ \ | |
54 | buf + (num >= 0 ? \ | |
55 | sprintf(buf, #pfx "%i_", num) : \ | |
56 | sprintf(buf, #pfx "_")); \ | |
57 | }) | |
58 | #define REGS_STR_PFX_C(buf, pfx, num) \ | |
59 | ({ \ | |
60 | buf + (num >= 0 ? \ | |
61 | sprintf(buf, #pfx "%c_", 'A' + num) : \ | |
62 | sprintf(buf, #pfx "_")); \ | |
63 | }) | |
64 | ||
65 | /* | |
66 | * Core registers (not memory mapped) | |
67 | */ | |
68 | extern u32 last_seqstat; | |
69 | ||
70 | static int debug_cclk_get(void *data, u64 *val) | |
71 | { | |
72 | *val = get_cclk(); | |
73 | return 0; | |
74 | } | |
75 | DEFINE_SIMPLE_ATTRIBUTE(fops_debug_cclk, debug_cclk_get, NULL, "0x%08llx\n"); | |
76 | ||
77 | static int debug_sclk_get(void *data, u64 *val) | |
78 | { | |
79 | *val = get_sclk(); | |
80 | return 0; | |
81 | } | |
82 | DEFINE_SIMPLE_ATTRIBUTE(fops_debug_sclk, debug_sclk_get, NULL, "0x%08llx\n"); | |
83 | ||
84 | #define DEFINE_SYSREG(sr, pre, post) \ | |
85 | static int sysreg_##sr##_get(void *data, u64 *val) \ | |
86 | { \ | |
87 | unsigned long tmp; \ | |
88 | pre; \ | |
89 | __asm__ __volatile__("%0 = " #sr ";" : "=d"(tmp)); \ | |
90 | *val = tmp; \ | |
91 | return 0; \ | |
92 | } \ | |
93 | static int sysreg_##sr##_set(void *data, u64 val) \ | |
94 | { \ | |
95 | unsigned long tmp = val; \ | |
96 | __asm__ __volatile__(#sr " = %0;" : : "d"(tmp)); \ | |
97 | post; \ | |
98 | return 0; \ | |
99 | } \ | |
100 | DEFINE_SIMPLE_ATTRIBUTE(fops_sysreg_##sr, sysreg_##sr##_get, sysreg_##sr##_set, "0x%08llx\n") | |
101 | ||
102 | DEFINE_SYSREG(cycles, , ); | |
103 | DEFINE_SYSREG(cycles2, __asm__ __volatile__("%0 = cycles;" : "=d"(tmp)), ); | |
104 | DEFINE_SYSREG(emudat, , ); | |
105 | DEFINE_SYSREG(seqstat, , ); | |
106 | DEFINE_SYSREG(syscfg, , CSYNC()); | |
107 | #define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr) | |
108 | ||
b5affb01 | 109 | #ifndef CONFIG_BF60x |
73ecfcf9 MF |
110 | /* |
111 | * CAN | |
112 | */ | |
113 | #define CAN_OFF(mmr) REGS_OFF(can, mmr) | |
114 | #define __CAN(uname, lname) __REGS(can, #uname, lname) | |
115 | static void __init __maybe_unused | |
116 | bfin_debug_mmrs_can(struct dentry *parent, unsigned long base, int num) | |
117 | { | |
118 | static struct dentry *am, *mb; | |
119 | int i, j; | |
120 | char buf[32], *_buf = REGS_STR_PFX(buf, CAN, num); | |
121 | ||
122 | if (!am) { | |
123 | am = debugfs_create_dir("am", parent); | |
124 | mb = debugfs_create_dir("mb", parent); | |
125 | } | |
126 | ||
127 | __CAN(MC1, mc1); | |
128 | __CAN(MD1, md1); | |
129 | __CAN(TRS1, trs1); | |
130 | __CAN(TRR1, trr1); | |
131 | __CAN(TA1, ta1); | |
132 | __CAN(AA1, aa1); | |
133 | __CAN(RMP1, rmp1); | |
134 | __CAN(RML1, rml1); | |
135 | __CAN(MBTIF1, mbtif1); | |
136 | __CAN(MBRIF1, mbrif1); | |
137 | __CAN(MBIM1, mbim1); | |
138 | __CAN(RFH1, rfh1); | |
139 | __CAN(OPSS1, opss1); | |
140 | ||
141 | __CAN(MC2, mc2); | |
142 | __CAN(MD2, md2); | |
143 | __CAN(TRS2, trs2); | |
144 | __CAN(TRR2, trr2); | |
145 | __CAN(TA2, ta2); | |
146 | __CAN(AA2, aa2); | |
147 | __CAN(RMP2, rmp2); | |
148 | __CAN(RML2, rml2); | |
149 | __CAN(MBTIF2, mbtif2); | |
150 | __CAN(MBRIF2, mbrif2); | |
151 | __CAN(MBIM2, mbim2); | |
152 | __CAN(RFH2, rfh2); | |
153 | __CAN(OPSS2, opss2); | |
154 | ||
155 | __CAN(CLOCK, clock); | |
156 | __CAN(TIMING, timing); | |
157 | __CAN(DEBUG, debug); | |
158 | __CAN(STATUS, status); | |
159 | __CAN(CEC, cec); | |
160 | __CAN(GIS, gis); | |
161 | __CAN(GIM, gim); | |
162 | __CAN(GIF, gif); | |
163 | __CAN(CONTROL, control); | |
164 | __CAN(INTR, intr); | |
165 | __CAN(VERSION, version); | |
166 | __CAN(MBTD, mbtd); | |
167 | __CAN(EWR, ewr); | |
168 | __CAN(ESR, esr); | |
169 | /*__CAN(UCREG, ucreg); no longer exists */ | |
170 | __CAN(UCCNT, uccnt); | |
171 | __CAN(UCRC, ucrc); | |
172 | __CAN(UCCNF, uccnf); | |
173 | __CAN(VERSION2, version2); | |
174 | ||
175 | for (i = 0; i < 32; ++i) { | |
176 | sprintf(_buf, "AM%02iL", i); | |
177 | debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am, | |
178 | (u16 *)(base + CAN_OFF(msk[i].aml))); | |
179 | sprintf(_buf, "AM%02iH", i); | |
180 | debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am, | |
181 | (u16 *)(base + CAN_OFF(msk[i].amh))); | |
182 | ||
183 | for (j = 0; j < 3; ++j) { | |
184 | sprintf(_buf, "MB%02i_DATA%i", i, j); | |
185 | debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb, | |
186 | (u16 *)(base + CAN_OFF(chl[i].data[j*2]))); | |
187 | } | |
188 | sprintf(_buf, "MB%02i_LENGTH", i); | |
189 | debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb, | |
190 | (u16 *)(base + CAN_OFF(chl[i].dlc))); | |
191 | sprintf(_buf, "MB%02i_TIMESTAMP", i); | |
192 | debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb, | |
193 | (u16 *)(base + CAN_OFF(chl[i].tsv))); | |
194 | sprintf(_buf, "MB%02i_ID0", i); | |
195 | debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb, | |
196 | (u16 *)(base + CAN_OFF(chl[i].id0))); | |
197 | sprintf(_buf, "MB%02i_ID1", i); | |
198 | debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb, | |
199 | (u16 *)(base + CAN_OFF(chl[i].id1))); | |
200 | } | |
201 | } | |
202 | #define CAN(num) bfin_debug_mmrs_can(parent, CAN##num##_MC1, num) | |
203 | ||
204 | /* | |
205 | * DMA | |
206 | */ | |
207 | #define __DMA(uname, lname) __REGS(dma, #uname, lname) | |
208 | static void __init __maybe_unused | |
209 | bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdma, const char *pfx) | |
210 | { | |
211 | char buf[32], *_buf; | |
212 | ||
213 | if (mdma) | |
214 | _buf = buf + sprintf(buf, "%s_%c%i_", pfx, mdma, num); | |
215 | else | |
216 | _buf = buf + sprintf(buf, "%s%i_", pfx, num); | |
217 | ||
218 | __DMA(NEXT_DESC_PTR, next_desc_ptr); | |
219 | __DMA(START_ADDR, start_addr); | |
220 | __DMA(CONFIG, config); | |
221 | __DMA(X_COUNT, x_count); | |
222 | __DMA(X_MODIFY, x_modify); | |
223 | __DMA(Y_COUNT, y_count); | |
224 | __DMA(Y_MODIFY, y_modify); | |
225 | __DMA(CURR_DESC_PTR, curr_desc_ptr); | |
226 | __DMA(CURR_ADDR, curr_addr); | |
227 | __DMA(IRQ_STATUS, irq_status); | |
b5affb01 | 228 | #ifndef CONFIG_BF60x |
e1406256 MF |
229 | if (strcmp(pfx, "IMDMA") != 0) |
230 | __DMA(PERIPHERAL_MAP, peripheral_map); | |
b5affb01 | 231 | #endif |
73ecfcf9 MF |
232 | __DMA(CURR_X_COUNT, curr_x_count); |
233 | __DMA(CURR_Y_COUNT, curr_y_count); | |
234 | } | |
235 | #define _DMA(num, base, mdma, pfx) bfin_debug_mmrs_dma(parent, base, num, mdma, pfx "DMA") | |
236 | #define DMA(num) _DMA(num, DMA##num##_NEXT_DESC_PTR, 0, "") | |
237 | #define _MDMA(num, x) \ | |
238 | do { \ | |
d09fb602 MF |
239 | _DMA(num, x##DMA_D##num##_NEXT_DESC_PTR, 'D', #x); \ |
240 | _DMA(num, x##DMA_S##num##_NEXT_DESC_PTR, 'S', #x); \ | |
73ecfcf9 MF |
241 | } while (0) |
242 | #define MDMA(num) _MDMA(num, M) | |
243 | #define IMDMA(num) _MDMA(num, IM) | |
244 | ||
245 | /* | |
246 | * EPPI | |
247 | */ | |
248 | #define __EPPI(uname, lname) __REGS(eppi, #uname, lname) | |
249 | static void __init __maybe_unused | |
250 | bfin_debug_mmrs_eppi(struct dentry *parent, unsigned long base, int num) | |
251 | { | |
252 | char buf[32], *_buf = REGS_STR_PFX(buf, EPPI, num); | |
253 | __EPPI(STATUS, status); | |
254 | __EPPI(HCOUNT, hcount); | |
255 | __EPPI(HDELAY, hdelay); | |
256 | __EPPI(VCOUNT, vcount); | |
257 | __EPPI(VDELAY, vdelay); | |
258 | __EPPI(FRAME, frame); | |
259 | __EPPI(LINE, line); | |
260 | __EPPI(CLKDIV, clkdiv); | |
261 | __EPPI(CONTROL, control); | |
262 | __EPPI(FS1W_HBL, fs1w_hbl); | |
263 | __EPPI(FS1P_AVPL, fs1p_avpl); | |
264 | __EPPI(FS2W_LVB, fs2w_lvb); | |
265 | __EPPI(FS2P_LAVF, fs2p_lavf); | |
266 | __EPPI(CLIP, clip); | |
267 | } | |
268 | #define EPPI(num) bfin_debug_mmrs_eppi(parent, EPPI##num##_STATUS, num) | |
269 | ||
270 | /* | |
271 | * General Purpose Timers | |
272 | */ | |
d09fb602 | 273 | #define __GPTIMER(uname, lname) __REGS(gptimer, #uname, lname) |
73ecfcf9 MF |
274 | static void __init __maybe_unused |
275 | bfin_debug_mmrs_gptimer(struct dentry *parent, unsigned long base, int num) | |
276 | { | |
277 | char buf[32], *_buf = REGS_STR_PFX(buf, TIMER, num); | |
d09fb602 MF |
278 | __GPTIMER(CONFIG, config); |
279 | __GPTIMER(COUNTER, counter); | |
280 | __GPTIMER(PERIOD, period); | |
281 | __GPTIMER(WIDTH, width); | |
73ecfcf9 MF |
282 | } |
283 | #define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num) | |
284 | ||
af459864 MF |
285 | #define GPTIMER_GROUP_OFF(mmr) REGS_OFF(gptimer_group, mmr) |
286 | #define __GPTIMER_GROUP(uname, lname) __REGS(gptimer_group, #uname, lname) | |
287 | static void __init __maybe_unused | |
288 | bfin_debug_mmrs_gptimer_group(struct dentry *parent, unsigned long base, int num) | |
289 | { | |
290 | char buf[32], *_buf; | |
291 | ||
292 | if (num == -1) { | |
293 | _buf = buf + sprintf(buf, "TIMER_"); | |
294 | __GPTIMER_GROUP(ENABLE, enable); | |
295 | __GPTIMER_GROUP(DISABLE, disable); | |
296 | __GPTIMER_GROUP(STATUS, status); | |
297 | } else { | |
298 | /* These MMRs are a bit odd as the group # is a suffix */ | |
299 | _buf = buf + sprintf(buf, "TIMER_ENABLE%i", num); | |
300 | d(buf, 16, base + GPTIMER_GROUP_OFF(enable)); | |
301 | ||
302 | _buf = buf + sprintf(buf, "TIMER_DISABLE%i", num); | |
303 | d(buf, 16, base + GPTIMER_GROUP_OFF(disable)); | |
304 | ||
305 | _buf = buf + sprintf(buf, "TIMER_STATUS%i", num); | |
306 | d(buf, 32, base + GPTIMER_GROUP_OFF(status)); | |
307 | } | |
308 | } | |
309 | #define GPTIMER_GROUP(mmr, num) bfin_debug_mmrs_gptimer_group(parent, mmr, num) | |
310 | ||
73ecfcf9 MF |
311 | /* |
312 | * Handshake MDMA | |
313 | */ | |
314 | #define __HMDMA(uname, lname) __REGS(hmdma, #uname, lname) | |
315 | static void __init __maybe_unused | |
316 | bfin_debug_mmrs_hmdma(struct dentry *parent, unsigned long base, int num) | |
317 | { | |
318 | char buf[32], *_buf = REGS_STR_PFX(buf, HMDMA, num); | |
319 | __HMDMA(CONTROL, control); | |
320 | __HMDMA(ECINIT, ecinit); | |
321 | __HMDMA(BCINIT, bcinit); | |
322 | __HMDMA(ECURGENT, ecurgent); | |
323 | __HMDMA(ECOVERFLOW, ecoverflow); | |
324 | __HMDMA(ECOUNT, ecount); | |
325 | __HMDMA(BCOUNT, bcount); | |
326 | } | |
327 | #define HMDMA(num) bfin_debug_mmrs_hmdma(parent, HMDMA##num##_CONTROL, num) | |
328 | ||
0a7e5413 MF |
329 | /* |
330 | * Peripheral Interrupts (PINT/GPIO) | |
331 | */ | |
332 | #ifdef PINT0_MASK_SET | |
333 | #define __PINT(uname, lname) __REGS(pint, #uname, lname) | |
334 | static void __init __maybe_unused | |
335 | bfin_debug_mmrs_pint(struct dentry *parent, unsigned long base, int num) | |
336 | { | |
337 | char buf[32], *_buf = REGS_STR_PFX(buf, PINT, num); | |
338 | __PINT(MASK_SET, mask_set); | |
339 | __PINT(MASK_CLEAR, mask_clear); | |
340 | __PINT(REQUEST, request); | |
341 | __PINT(ASSIGN, assign); | |
342 | __PINT(EDGE_SET, edge_set); | |
343 | __PINT(EDGE_CLEAR, edge_clear); | |
344 | __PINT(INVERT_SET, invert_set); | |
345 | __PINT(INVERT_CLEAR, invert_clear); | |
346 | __PINT(PINSTATE, pinstate); | |
347 | __PINT(LATCH, latch); | |
348 | } | |
349 | #define PINT(num) bfin_debug_mmrs_pint(parent, PINT##num##_MASK_SET, num) | |
350 | #endif | |
351 | ||
73ecfcf9 MF |
352 | /* |
353 | * Port/GPIO | |
354 | */ | |
355 | #define bfin_gpio_regs gpio_port_t | |
356 | #define __PORT(uname, lname) __REGS(gpio, #uname, lname) | |
357 | static void __init __maybe_unused | |
358 | bfin_debug_mmrs_port(struct dentry *parent, unsigned long base, int num) | |
359 | { | |
360 | char buf[32], *_buf; | |
361 | #ifdef __ADSPBF54x__ | |
362 | _buf = REGS_STR_PFX_C(buf, PORT, num); | |
363 | __PORT(FER, port_fer); | |
364 | __PORT(SET, data_set); | |
365 | __PORT(CLEAR, data_clear); | |
366 | __PORT(DIR_SET, dir_set); | |
367 | __PORT(DIR_CLEAR, dir_clear); | |
368 | __PORT(INEN, inen); | |
369 | __PORT(MUX, port_mux); | |
370 | #else | |
371 | _buf = buf + sprintf(buf, "PORT%cIO_", num); | |
372 | __PORT(CLEAR, data_clear); | |
373 | __PORT(SET, data_set); | |
374 | __PORT(TOGGLE, toggle); | |
375 | __PORT(MASKA, maska); | |
376 | __PORT(MASKA_CLEAR, maska_clear); | |
377 | __PORT(MASKA_SET, maska_set); | |
378 | __PORT(MASKA_TOGGLE, maska_toggle); | |
379 | __PORT(MASKB, maskb); | |
380 | __PORT(MASKB_CLEAR, maskb_clear); | |
381 | __PORT(MASKB_SET, maskb_set); | |
382 | __PORT(MASKB_TOGGLE, maskb_toggle); | |
383 | __PORT(DIR, dir); | |
384 | __PORT(POLAR, polar); | |
385 | __PORT(EDGE, edge); | |
386 | __PORT(BOTH, both); | |
387 | __PORT(INEN, inen); | |
388 | #endif | |
389 | _buf[-1] = '\0'; | |
390 | d(buf, 16, base + REGS_OFF(gpio, data)); | |
391 | } | |
392 | #define PORT(base, num) bfin_debug_mmrs_port(parent, base, num) | |
393 | ||
394 | /* | |
395 | * PPI | |
396 | */ | |
397 | #define __PPI(uname, lname) __REGS(ppi, #uname, lname) | |
398 | static void __init __maybe_unused | |
399 | bfin_debug_mmrs_ppi(struct dentry *parent, unsigned long base, int num) | |
400 | { | |
401 | char buf[32], *_buf = REGS_STR_PFX(buf, PPI, num); | |
402 | __PPI(CONTROL, control); | |
403 | __PPI(STATUS, status); | |
404 | __PPI(COUNT, count); | |
405 | __PPI(DELAY, delay); | |
406 | __PPI(FRAME, frame); | |
407 | } | |
d09fb602 | 408 | #define PPI(num) bfin_debug_mmrs_ppi(parent, PPI##num##_CONTROL, num) |
73ecfcf9 MF |
409 | |
410 | /* | |
411 | * SPI | |
412 | */ | |
413 | #define __SPI(uname, lname) __REGS(spi, #uname, lname) | |
414 | static void __init __maybe_unused | |
415 | bfin_debug_mmrs_spi(struct dentry *parent, unsigned long base, int num) | |
416 | { | |
417 | char buf[32], *_buf = REGS_STR_PFX(buf, SPI, num); | |
418 | __SPI(CTL, ctl); | |
419 | __SPI(FLG, flg); | |
420 | __SPI(STAT, stat); | |
421 | __SPI(TDBR, tdbr); | |
422 | __SPI(RDBR, rdbr); | |
423 | __SPI(BAUD, baud); | |
424 | __SPI(SHADOW, shadow); | |
425 | } | |
426 | #define SPI(num) bfin_debug_mmrs_spi(parent, SPI##num##_REGBASE, num) | |
427 | ||
428 | /* | |
429 | * SPORT | |
430 | */ | |
431 | static inline int sport_width(void *mmr) | |
432 | { | |
433 | unsigned long lmmr = (unsigned long)mmr; | |
434 | if ((lmmr & 0xff) == 0x10) | |
435 | /* SPORT#_TX has 0x10 offset -> SPORT#_TCR2 has 0x04 offset */ | |
436 | lmmr -= 0xc; | |
437 | else | |
438 | /* SPORT#_RX has 0x18 offset -> SPORT#_RCR2 has 0x24 offset */ | |
439 | lmmr += 0xc; | |
440 | /* extract SLEN field from control register 2 and add 1 */ | |
441 | return (bfin_read16(lmmr) & 0x1f) + 1; | |
442 | } | |
443 | static int sport_set(void *mmr, u64 val) | |
444 | { | |
445 | unsigned long flags; | |
446 | local_irq_save(flags); | |
447 | if (sport_width(mmr) <= 16) | |
448 | bfin_write16(mmr, val); | |
449 | else | |
450 | bfin_write32(mmr, val); | |
451 | local_irq_restore(flags); | |
452 | return 0; | |
453 | } | |
454 | static int sport_get(void *mmr, u64 *val) | |
455 | { | |
456 | unsigned long flags; | |
457 | local_irq_save(flags); | |
458 | if (sport_width(mmr) <= 16) | |
459 | *val = bfin_read16(mmr); | |
460 | else | |
461 | *val = bfin_read32(mmr); | |
462 | local_irq_restore(flags); | |
463 | return 0; | |
464 | } | |
465 | DEFINE_SIMPLE_ATTRIBUTE(fops_sport, sport_get, sport_set, "0x%08llx\n"); | |
466 | /*DEFINE_SIMPLE_ATTRIBUTE(fops_sport_ro, sport_get, NULL, "0x%08llx\n");*/ | |
467 | DEFINE_SIMPLE_ATTRIBUTE(fops_sport_wo, NULL, sport_set, "0x%08llx\n"); | |
468 | #define SPORT_OFF(mmr) (SPORT0_##mmr - SPORT0_TCR1) | |
469 | #define _D_SPORT(name, perms, fops) \ | |
470 | do { \ | |
471 | strcpy(_buf, #name); \ | |
472 | debugfs_create_file(buf, perms, parent, (void *)(base + SPORT_OFF(name)), fops); \ | |
473 | } while (0) | |
474 | #define __SPORT_RW(name) _D_SPORT(name, S_IRUSR|S_IWUSR, &fops_sport) | |
475 | #define __SPORT_RO(name) _D_SPORT(name, S_IRUSR, &fops_sport_ro) | |
476 | #define __SPORT_WO(name) _D_SPORT(name, S_IWUSR, &fops_sport_wo) | |
477 | #define __SPORT(name, bits) \ | |
478 | do { \ | |
479 | strcpy(_buf, #name); \ | |
480 | debugfs_create_x##bits(buf, S_IRUSR|S_IWUSR, parent, (u##bits *)(base + SPORT_OFF(name))); \ | |
481 | } while (0) | |
482 | static void __init __maybe_unused | |
483 | bfin_debug_mmrs_sport(struct dentry *parent, unsigned long base, int num) | |
484 | { | |
485 | char buf[32], *_buf = REGS_STR_PFX(buf, SPORT, num); | |
486 | __SPORT(CHNL, 16); | |
487 | __SPORT(MCMC1, 16); | |
488 | __SPORT(MCMC2, 16); | |
489 | __SPORT(MRCS0, 32); | |
490 | __SPORT(MRCS1, 32); | |
491 | __SPORT(MRCS2, 32); | |
492 | __SPORT(MRCS3, 32); | |
493 | __SPORT(MTCS0, 32); | |
494 | __SPORT(MTCS1, 32); | |
495 | __SPORT(MTCS2, 32); | |
496 | __SPORT(MTCS3, 32); | |
497 | __SPORT(RCLKDIV, 16); | |
498 | __SPORT(RCR1, 16); | |
499 | __SPORT(RCR2, 16); | |
500 | __SPORT(RFSDIV, 16); | |
501 | __SPORT_RW(RX); | |
502 | __SPORT(STAT, 16); | |
503 | __SPORT(TCLKDIV, 16); | |
504 | __SPORT(TCR1, 16); | |
505 | __SPORT(TCR2, 16); | |
506 | __SPORT(TFSDIV, 16); | |
507 | __SPORT_WO(TX); | |
508 | } | |
509 | #define SPORT(num) bfin_debug_mmrs_sport(parent, SPORT##num##_TCR1, num) | |
510 | ||
511 | /* | |
512 | * TWI | |
513 | */ | |
514 | #define __TWI(uname, lname) __REGS(twi, #uname, lname) | |
515 | static void __init __maybe_unused | |
516 | bfin_debug_mmrs_twi(struct dentry *parent, unsigned long base, int num) | |
517 | { | |
518 | char buf[32], *_buf = REGS_STR_PFX(buf, TWI, num); | |
519 | __TWI(CLKDIV, clkdiv); | |
520 | __TWI(CONTROL, control); | |
521 | __TWI(SLAVE_CTL, slave_ctl); | |
522 | __TWI(SLAVE_STAT, slave_stat); | |
523 | __TWI(SLAVE_ADDR, slave_addr); | |
524 | __TWI(MASTER_CTL, master_ctl); | |
525 | __TWI(MASTER_STAT, master_stat); | |
526 | __TWI(MASTER_ADDR, master_addr); | |
527 | __TWI(INT_STAT, int_stat); | |
528 | __TWI(INT_MASK, int_mask); | |
529 | __TWI(FIFO_CTL, fifo_ctl); | |
530 | __TWI(FIFO_STAT, fifo_stat); | |
531 | __TWI(XMT_DATA8, xmt_data8); | |
532 | __TWI(XMT_DATA16, xmt_data16); | |
533 | __TWI(RCV_DATA8, rcv_data8); | |
534 | __TWI(RCV_DATA16, rcv_data16); | |
535 | } | |
536 | #define TWI(num) bfin_debug_mmrs_twi(parent, TWI##num##_CLKDIV, num) | |
537 | ||
538 | /* | |
539 | * UART | |
540 | */ | |
541 | #define __UART(uname, lname) __REGS(uart, #uname, lname) | |
542 | static void __init __maybe_unused | |
543 | bfin_debug_mmrs_uart(struct dentry *parent, unsigned long base, int num) | |
544 | { | |
545 | char buf[32], *_buf = REGS_STR_PFX(buf, UART, num); | |
546 | #ifdef BFIN_UART_BF54X_STYLE | |
547 | __UART(DLL, dll); | |
548 | __UART(DLH, dlh); | |
549 | __UART(GCTL, gctl); | |
550 | __UART(LCR, lcr); | |
551 | __UART(MCR, mcr); | |
552 | __UART(LSR, lsr); | |
553 | __UART(MSR, msr); | |
554 | __UART(SCR, scr); | |
555 | __UART(IER_SET, ier_set); | |
556 | __UART(IER_CLEAR, ier_clear); | |
557 | __UART(THR, thr); | |
558 | __UART(RBR, rbr); | |
559 | #else | |
560 | __UART(DLL, dll); | |
561 | __UART(THR, thr); | |
562 | __UART(RBR, rbr); | |
563 | __UART(DLH, dlh); | |
564 | __UART(IER, ier); | |
565 | __UART(IIR, iir); | |
566 | __UART(LCR, lcr); | |
567 | __UART(MCR, mcr); | |
568 | __UART(LSR, lsr); | |
569 | __UART(MSR, msr); | |
570 | __UART(SCR, scr); | |
571 | __UART(GCTL, gctl); | |
572 | #endif | |
573 | } | |
574 | #define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num) | |
b5affb01 | 575 | #endif /* CONFIG_BF60x */ |
73ecfcf9 MF |
576 | /* |
577 | * The actual debugfs generation | |
578 | */ | |
579 | static struct dentry *debug_mmrs_dentry; | |
580 | ||
581 | static int __init bfin_debug_mmrs_init(void) | |
582 | { | |
583 | struct dentry *top, *parent; | |
584 | ||
585 | pr_info("debug-mmrs: setting up Blackfin MMR debugfs\n"); | |
586 | ||
587 | top = debugfs_create_dir("blackfin", NULL); | |
588 | if (top == NULL) | |
589 | return -1; | |
590 | ||
591 | parent = debugfs_create_dir("core_regs", top); | |
592 | debugfs_create_file("cclk", S_IRUSR, parent, NULL, &fops_debug_cclk); | |
593 | debugfs_create_file("sclk", S_IRUSR, parent, NULL, &fops_debug_sclk); | |
594 | debugfs_create_x32("last_seqstat", S_IRUSR, parent, &last_seqstat); | |
595 | D_SYSREG(cycles); | |
596 | D_SYSREG(cycles2); | |
597 | D_SYSREG(emudat); | |
598 | D_SYSREG(seqstat); | |
599 | D_SYSREG(syscfg); | |
600 | ||
601 | /* Core MMRs */ | |
602 | parent = debugfs_create_dir("ctimer", top); | |
603 | D32(TCNTL); | |
604 | D32(TCOUNT); | |
605 | D32(TPERIOD); | |
606 | D32(TSCALE); | |
607 | ||
608 | parent = debugfs_create_dir("cec", top); | |
609 | D32(EVT0); | |
610 | D32(EVT1); | |
611 | D32(EVT2); | |
612 | D32(EVT3); | |
613 | D32(EVT4); | |
614 | D32(EVT5); | |
615 | D32(EVT6); | |
616 | D32(EVT7); | |
617 | D32(EVT8); | |
618 | D32(EVT9); | |
619 | D32(EVT10); | |
620 | D32(EVT11); | |
621 | D32(EVT12); | |
622 | D32(EVT13); | |
623 | D32(EVT14); | |
624 | D32(EVT15); | |
625 | D32(EVT_OVERRIDE); | |
626 | D32(IMASK); | |
627 | D32(IPEND); | |
628 | D32(ILAT); | |
629 | D32(IPRIO); | |
630 | ||
631 | parent = debugfs_create_dir("debug", top); | |
632 | D32(DBGSTAT); | |
633 | D32(DSPID); | |
634 | ||
635 | parent = debugfs_create_dir("mmu", top); | |
636 | D32(SRAM_BASE_ADDRESS); | |
637 | D32(DCPLB_ADDR0); | |
638 | D32(DCPLB_ADDR10); | |
639 | D32(DCPLB_ADDR11); | |
640 | D32(DCPLB_ADDR12); | |
641 | D32(DCPLB_ADDR13); | |
642 | D32(DCPLB_ADDR14); | |
643 | D32(DCPLB_ADDR15); | |
644 | D32(DCPLB_ADDR1); | |
645 | D32(DCPLB_ADDR2); | |
646 | D32(DCPLB_ADDR3); | |
647 | D32(DCPLB_ADDR4); | |
648 | D32(DCPLB_ADDR5); | |
649 | D32(DCPLB_ADDR6); | |
650 | D32(DCPLB_ADDR7); | |
651 | D32(DCPLB_ADDR8); | |
652 | D32(DCPLB_ADDR9); | |
653 | D32(DCPLB_DATA0); | |
654 | D32(DCPLB_DATA10); | |
655 | D32(DCPLB_DATA11); | |
656 | D32(DCPLB_DATA12); | |
657 | D32(DCPLB_DATA13); | |
658 | D32(DCPLB_DATA14); | |
659 | D32(DCPLB_DATA15); | |
660 | D32(DCPLB_DATA1); | |
661 | D32(DCPLB_DATA2); | |
662 | D32(DCPLB_DATA3); | |
663 | D32(DCPLB_DATA4); | |
664 | D32(DCPLB_DATA5); | |
665 | D32(DCPLB_DATA6); | |
666 | D32(DCPLB_DATA7); | |
667 | D32(DCPLB_DATA8); | |
668 | D32(DCPLB_DATA9); | |
669 | D32(DCPLB_FAULT_ADDR); | |
670 | D32(DCPLB_STATUS); | |
671 | D32(DMEM_CONTROL); | |
672 | D32(DTEST_COMMAND); | |
673 | D32(DTEST_DATA0); | |
674 | D32(DTEST_DATA1); | |
675 | ||
676 | D32(ICPLB_ADDR0); | |
677 | D32(ICPLB_ADDR1); | |
678 | D32(ICPLB_ADDR2); | |
679 | D32(ICPLB_ADDR3); | |
680 | D32(ICPLB_ADDR4); | |
681 | D32(ICPLB_ADDR5); | |
682 | D32(ICPLB_ADDR6); | |
683 | D32(ICPLB_ADDR7); | |
684 | D32(ICPLB_ADDR8); | |
685 | D32(ICPLB_ADDR9); | |
686 | D32(ICPLB_ADDR10); | |
687 | D32(ICPLB_ADDR11); | |
688 | D32(ICPLB_ADDR12); | |
689 | D32(ICPLB_ADDR13); | |
690 | D32(ICPLB_ADDR14); | |
691 | D32(ICPLB_ADDR15); | |
692 | D32(ICPLB_DATA0); | |
693 | D32(ICPLB_DATA1); | |
694 | D32(ICPLB_DATA2); | |
695 | D32(ICPLB_DATA3); | |
696 | D32(ICPLB_DATA4); | |
697 | D32(ICPLB_DATA5); | |
698 | D32(ICPLB_DATA6); | |
699 | D32(ICPLB_DATA7); | |
700 | D32(ICPLB_DATA8); | |
701 | D32(ICPLB_DATA9); | |
702 | D32(ICPLB_DATA10); | |
703 | D32(ICPLB_DATA11); | |
704 | D32(ICPLB_DATA12); | |
705 | D32(ICPLB_DATA13); | |
706 | D32(ICPLB_DATA14); | |
707 | D32(ICPLB_DATA15); | |
708 | D32(ICPLB_FAULT_ADDR); | |
709 | D32(ICPLB_STATUS); | |
710 | D32(IMEM_CONTROL); | |
711 | if (!ANOMALY_05000481) { | |
712 | D32(ITEST_COMMAND); | |
713 | D32(ITEST_DATA0); | |
714 | D32(ITEST_DATA1); | |
715 | } | |
716 | ||
717 | parent = debugfs_create_dir("perf", top); | |
718 | D32(PFCNTR0); | |
719 | D32(PFCNTR1); | |
720 | D32(PFCTL); | |
721 | ||
722 | parent = debugfs_create_dir("trace", top); | |
723 | D32(TBUF); | |
724 | D32(TBUFCTL); | |
725 | D32(TBUFSTAT); | |
726 | ||
727 | parent = debugfs_create_dir("watchpoint", top); | |
728 | D32(WPIACTL); | |
729 | D32(WPIA0); | |
730 | D32(WPIA1); | |
731 | D32(WPIA2); | |
732 | D32(WPIA3); | |
733 | D32(WPIA4); | |
734 | D32(WPIA5); | |
735 | D32(WPIACNT0); | |
736 | D32(WPIACNT1); | |
737 | D32(WPIACNT2); | |
738 | D32(WPIACNT3); | |
739 | D32(WPIACNT4); | |
740 | D32(WPIACNT5); | |
741 | D32(WPDACTL); | |
742 | D32(WPDA0); | |
743 | D32(WPDA1); | |
744 | D32(WPDACNT0); | |
745 | D32(WPDACNT1); | |
746 | D32(WPSTAT); | |
b5affb01 | 747 | #ifndef CONFIG_BF60x |
73ecfcf9 MF |
748 | /* System MMRs */ |
749 | #ifdef ATAPI_CONTROL | |
750 | parent = debugfs_create_dir("atapi", top); | |
751 | D16(ATAPI_CONTROL); | |
752 | D16(ATAPI_DEV_ADDR); | |
753 | D16(ATAPI_DEV_RXBUF); | |
754 | D16(ATAPI_DEV_TXBUF); | |
755 | D16(ATAPI_DMA_TFRCNT); | |
756 | D16(ATAPI_INT_MASK); | |
757 | D16(ATAPI_INT_STATUS); | |
758 | D16(ATAPI_LINE_STATUS); | |
759 | D16(ATAPI_MULTI_TIM_0); | |
760 | D16(ATAPI_MULTI_TIM_1); | |
761 | D16(ATAPI_MULTI_TIM_2); | |
762 | D16(ATAPI_PIO_TFRCNT); | |
763 | D16(ATAPI_PIO_TIM_0); | |
764 | D16(ATAPI_PIO_TIM_1); | |
765 | D16(ATAPI_REG_TIM_0); | |
766 | D16(ATAPI_SM_STATE); | |
767 | D16(ATAPI_STATUS); | |
768 | D16(ATAPI_TERMINATE); | |
769 | D16(ATAPI_UDMAOUT_TFRCNT); | |
770 | D16(ATAPI_ULTRA_TIM_0); | |
771 | D16(ATAPI_ULTRA_TIM_1); | |
772 | D16(ATAPI_ULTRA_TIM_2); | |
773 | D16(ATAPI_ULTRA_TIM_3); | |
774 | D16(ATAPI_UMAIN_TFRCNT); | |
775 | D16(ATAPI_XFER_LEN); | |
776 | #endif | |
777 | ||
778 | #if defined(CAN_MC1) || defined(CAN0_MC1) || defined(CAN1_MC1) | |
779 | parent = debugfs_create_dir("can", top); | |
780 | # ifdef CAN_MC1 | |
781 | bfin_debug_mmrs_can(parent, CAN_MC1, -1); | |
782 | # endif | |
783 | # ifdef CAN0_MC1 | |
784 | CAN(0); | |
785 | # endif | |
786 | # ifdef CAN1_MC1 | |
787 | CAN(1); | |
788 | # endif | |
789 | #endif | |
790 | ||
791 | #ifdef CNT_COMMAND | |
792 | parent = debugfs_create_dir("counter", top); | |
793 | D16(CNT_COMMAND); | |
794 | D16(CNT_CONFIG); | |
795 | D32(CNT_COUNTER); | |
796 | D16(CNT_DEBOUNCE); | |
797 | D16(CNT_IMASK); | |
798 | D32(CNT_MAX); | |
799 | D32(CNT_MIN); | |
800 | D16(CNT_STATUS); | |
801 | #endif | |
802 | ||
803 | parent = debugfs_create_dir("dmac", top); | |
ef0531b2 | 804 | #ifdef DMAC_TC_CNT |
73ecfcf9 MF |
805 | D16(DMAC_TC_CNT); |
806 | D16(DMAC_TC_PER); | |
807 | #endif | |
808 | #ifdef DMAC0_TC_CNT | |
809 | D16(DMAC0_TC_CNT); | |
810 | D16(DMAC0_TC_PER); | |
811 | #endif | |
812 | #ifdef DMAC1_TC_CNT | |
813 | D16(DMAC1_TC_CNT); | |
814 | D16(DMAC1_TC_PER); | |
815 | #endif | |
816 | #ifdef DMAC1_PERIMUX | |
817 | D16(DMAC1_PERIMUX); | |
818 | #endif | |
819 | ||
820 | #ifdef __ADSPBF561__ | |
821 | /* XXX: should rewrite the MMR map */ | |
822 | # define DMA0_NEXT_DESC_PTR DMA2_0_NEXT_DESC_PTR | |
823 | # define DMA1_NEXT_DESC_PTR DMA2_1_NEXT_DESC_PTR | |
824 | # define DMA2_NEXT_DESC_PTR DMA2_2_NEXT_DESC_PTR | |
825 | # define DMA3_NEXT_DESC_PTR DMA2_3_NEXT_DESC_PTR | |
826 | # define DMA4_NEXT_DESC_PTR DMA2_4_NEXT_DESC_PTR | |
827 | # define DMA5_NEXT_DESC_PTR DMA2_5_NEXT_DESC_PTR | |
828 | # define DMA6_NEXT_DESC_PTR DMA2_6_NEXT_DESC_PTR | |
829 | # define DMA7_NEXT_DESC_PTR DMA2_7_NEXT_DESC_PTR | |
830 | # define DMA8_NEXT_DESC_PTR DMA2_8_NEXT_DESC_PTR | |
831 | # define DMA9_NEXT_DESC_PTR DMA2_9_NEXT_DESC_PTR | |
832 | # define DMA10_NEXT_DESC_PTR DMA2_10_NEXT_DESC_PTR | |
833 | # define DMA11_NEXT_DESC_PTR DMA2_11_NEXT_DESC_PTR | |
834 | # define DMA12_NEXT_DESC_PTR DMA1_0_NEXT_DESC_PTR | |
835 | # define DMA13_NEXT_DESC_PTR DMA1_1_NEXT_DESC_PTR | |
836 | # define DMA14_NEXT_DESC_PTR DMA1_2_NEXT_DESC_PTR | |
837 | # define DMA15_NEXT_DESC_PTR DMA1_3_NEXT_DESC_PTR | |
838 | # define DMA16_NEXT_DESC_PTR DMA1_4_NEXT_DESC_PTR | |
839 | # define DMA17_NEXT_DESC_PTR DMA1_5_NEXT_DESC_PTR | |
840 | # define DMA18_NEXT_DESC_PTR DMA1_6_NEXT_DESC_PTR | |
841 | # define DMA19_NEXT_DESC_PTR DMA1_7_NEXT_DESC_PTR | |
842 | # define DMA20_NEXT_DESC_PTR DMA1_8_NEXT_DESC_PTR | |
843 | # define DMA21_NEXT_DESC_PTR DMA1_9_NEXT_DESC_PTR | |
844 | # define DMA22_NEXT_DESC_PTR DMA1_10_NEXT_DESC_PTR | |
845 | # define DMA23_NEXT_DESC_PTR DMA1_11_NEXT_DESC_PTR | |
846 | #endif | |
847 | parent = debugfs_create_dir("dma", top); | |
848 | DMA(0); | |
849 | DMA(1); | |
850 | DMA(1); | |
851 | DMA(2); | |
852 | DMA(3); | |
853 | DMA(4); | |
854 | DMA(5); | |
855 | DMA(6); | |
856 | DMA(7); | |
857 | #ifdef DMA8_NEXT_DESC_PTR | |
858 | DMA(8); | |
859 | DMA(9); | |
860 | DMA(10); | |
861 | DMA(11); | |
862 | #endif | |
863 | #ifdef DMA12_NEXT_DESC_PTR | |
864 | DMA(12); | |
865 | DMA(13); | |
866 | DMA(14); | |
867 | DMA(15); | |
868 | DMA(16); | |
869 | DMA(17); | |
870 | DMA(18); | |
871 | DMA(19); | |
872 | #endif | |
873 | #ifdef DMA20_NEXT_DESC_PTR | |
874 | DMA(20); | |
875 | DMA(21); | |
876 | DMA(22); | |
877 | DMA(23); | |
878 | #endif | |
879 | ||
880 | parent = debugfs_create_dir("ebiu_amc", top); | |
881 | D32(EBIU_AMBCTL0); | |
882 | D32(EBIU_AMBCTL1); | |
883 | D16(EBIU_AMGCTL); | |
884 | #ifdef EBIU_MBSCTL | |
885 | D16(EBIU_MBSCTL); | |
886 | D32(EBIU_ARBSTAT); | |
887 | D32(EBIU_MODE); | |
888 | D16(EBIU_FCTL); | |
889 | #endif | |
890 | ||
891 | #ifdef EBIU_SDGCTL | |
892 | parent = debugfs_create_dir("ebiu_sdram", top); | |
893 | # ifdef __ADSPBF561__ | |
894 | D32(EBIU_SDBCTL); | |
895 | # else | |
896 | D16(EBIU_SDBCTL); | |
897 | # endif | |
898 | D32(EBIU_SDGCTL); | |
899 | D16(EBIU_SDRRC); | |
900 | D16(EBIU_SDSTAT); | |
901 | #endif | |
902 | ||
903 | #ifdef EBIU_DDRACCT | |
904 | parent = debugfs_create_dir("ebiu_ddr", top); | |
905 | D32(EBIU_DDRACCT); | |
906 | D32(EBIU_DDRARCT); | |
907 | D32(EBIU_DDRBRC0); | |
908 | D32(EBIU_DDRBRC1); | |
909 | D32(EBIU_DDRBRC2); | |
910 | D32(EBIU_DDRBRC3); | |
911 | D32(EBIU_DDRBRC4); | |
912 | D32(EBIU_DDRBRC5); | |
913 | D32(EBIU_DDRBRC6); | |
914 | D32(EBIU_DDRBRC7); | |
915 | D32(EBIU_DDRBWC0); | |
916 | D32(EBIU_DDRBWC1); | |
917 | D32(EBIU_DDRBWC2); | |
918 | D32(EBIU_DDRBWC3); | |
919 | D32(EBIU_DDRBWC4); | |
920 | D32(EBIU_DDRBWC5); | |
921 | D32(EBIU_DDRBWC6); | |
922 | D32(EBIU_DDRBWC7); | |
923 | D32(EBIU_DDRCTL0); | |
924 | D32(EBIU_DDRCTL1); | |
925 | D32(EBIU_DDRCTL2); | |
926 | D32(EBIU_DDRCTL3); | |
927 | D32(EBIU_DDRGC0); | |
928 | D32(EBIU_DDRGC1); | |
929 | D32(EBIU_DDRGC2); | |
930 | D32(EBIU_DDRGC3); | |
931 | D32(EBIU_DDRMCCL); | |
932 | D32(EBIU_DDRMCEN); | |
933 | D32(EBIU_DDRQUE); | |
934 | D32(EBIU_DDRTACT); | |
935 | D32(EBIU_ERRADD); | |
936 | D16(EBIU_ERRMST); | |
937 | D16(EBIU_RSTCTL); | |
938 | #endif | |
939 | ||
940 | #ifdef EMAC_ADDRHI | |
941 | parent = debugfs_create_dir("emac", top); | |
942 | D32(EMAC_ADDRHI); | |
943 | D32(EMAC_ADDRLO); | |
944 | D32(EMAC_FLC); | |
945 | D32(EMAC_HASHHI); | |
946 | D32(EMAC_HASHLO); | |
947 | D32(EMAC_MMC_CTL); | |
948 | D32(EMAC_MMC_RIRQE); | |
949 | D32(EMAC_MMC_RIRQS); | |
950 | D32(EMAC_MMC_TIRQE); | |
951 | D32(EMAC_MMC_TIRQS); | |
952 | D32(EMAC_OPMODE); | |
953 | D32(EMAC_RXC_ALIGN); | |
954 | D32(EMAC_RXC_ALLFRM); | |
955 | D32(EMAC_RXC_ALLOCT); | |
956 | D32(EMAC_RXC_BROAD); | |
957 | D32(EMAC_RXC_DMAOVF); | |
958 | D32(EMAC_RXC_EQ64); | |
959 | D32(EMAC_RXC_FCS); | |
960 | D32(EMAC_RXC_GE1024); | |
961 | D32(EMAC_RXC_LNERRI); | |
962 | D32(EMAC_RXC_LNERRO); | |
963 | D32(EMAC_RXC_LONG); | |
964 | D32(EMAC_RXC_LT1024); | |
965 | D32(EMAC_RXC_LT128); | |
966 | D32(EMAC_RXC_LT256); | |
967 | D32(EMAC_RXC_LT512); | |
968 | D32(EMAC_RXC_MACCTL); | |
969 | D32(EMAC_RXC_MULTI); | |
970 | D32(EMAC_RXC_OCTET); | |
971 | D32(EMAC_RXC_OK); | |
972 | D32(EMAC_RXC_OPCODE); | |
973 | D32(EMAC_RXC_PAUSE); | |
974 | D32(EMAC_RXC_SHORT); | |
975 | D32(EMAC_RXC_TYPED); | |
976 | D32(EMAC_RXC_UNICST); | |
977 | D32(EMAC_RX_IRQE); | |
978 | D32(EMAC_RX_STAT); | |
979 | D32(EMAC_RX_STKY); | |
980 | D32(EMAC_STAADD); | |
981 | D32(EMAC_STADAT); | |
982 | D32(EMAC_SYSCTL); | |
983 | D32(EMAC_SYSTAT); | |
984 | D32(EMAC_TXC_1COL); | |
985 | D32(EMAC_TXC_ABORT); | |
986 | D32(EMAC_TXC_ALLFRM); | |
987 | D32(EMAC_TXC_ALLOCT); | |
988 | D32(EMAC_TXC_BROAD); | |
989 | D32(EMAC_TXC_CRSERR); | |
990 | D32(EMAC_TXC_DEFER); | |
991 | D32(EMAC_TXC_DMAUND); | |
992 | D32(EMAC_TXC_EQ64); | |
993 | D32(EMAC_TXC_GE1024); | |
994 | D32(EMAC_TXC_GT1COL); | |
995 | D32(EMAC_TXC_LATECL); | |
996 | D32(EMAC_TXC_LT1024); | |
997 | D32(EMAC_TXC_LT128); | |
998 | D32(EMAC_TXC_LT256); | |
999 | D32(EMAC_TXC_LT512); | |
1000 | D32(EMAC_TXC_MACCTL); | |
1001 | D32(EMAC_TXC_MULTI); | |
1002 | D32(EMAC_TXC_OCTET); | |
1003 | D32(EMAC_TXC_OK); | |
1004 | D32(EMAC_TXC_UNICST); | |
1005 | D32(EMAC_TXC_XS_COL); | |
1006 | D32(EMAC_TXC_XS_DFR); | |
1007 | D32(EMAC_TX_IRQE); | |
1008 | D32(EMAC_TX_STAT); | |
1009 | D32(EMAC_TX_STKY); | |
1010 | D32(EMAC_VLAN1); | |
1011 | D32(EMAC_VLAN2); | |
1012 | D32(EMAC_WKUP_CTL); | |
1013 | D32(EMAC_WKUP_FFCMD); | |
1014 | D32(EMAC_WKUP_FFCRC0); | |
1015 | D32(EMAC_WKUP_FFCRC1); | |
1016 | D32(EMAC_WKUP_FFMSK0); | |
1017 | D32(EMAC_WKUP_FFMSK1); | |
1018 | D32(EMAC_WKUP_FFMSK2); | |
1019 | D32(EMAC_WKUP_FFMSK3); | |
1020 | D32(EMAC_WKUP_FFOFF); | |
1021 | # ifdef EMAC_PTP_ACCR | |
1022 | D32(EMAC_PTP_ACCR); | |
1023 | D32(EMAC_PTP_ADDEND); | |
1024 | D32(EMAC_PTP_ALARMHI); | |
1025 | D32(EMAC_PTP_ALARMLO); | |
1026 | D16(EMAC_PTP_CTL); | |
1027 | D32(EMAC_PTP_FOFF); | |
1028 | D32(EMAC_PTP_FV1); | |
1029 | D32(EMAC_PTP_FV2); | |
1030 | D32(EMAC_PTP_FV3); | |
1031 | D16(EMAC_PTP_ID_OFF); | |
1032 | D32(EMAC_PTP_ID_SNAP); | |
1033 | D16(EMAC_PTP_IE); | |
1034 | D16(EMAC_PTP_ISTAT); | |
1035 | D32(EMAC_PTP_OFFSET); | |
1036 | D32(EMAC_PTP_PPS_PERIOD); | |
1037 | D32(EMAC_PTP_PPS_STARTHI); | |
1038 | D32(EMAC_PTP_PPS_STARTLO); | |
1039 | D32(EMAC_PTP_RXSNAPHI); | |
1040 | D32(EMAC_PTP_RXSNAPLO); | |
1041 | D32(EMAC_PTP_TIMEHI); | |
1042 | D32(EMAC_PTP_TIMELO); | |
1043 | D32(EMAC_PTP_TXSNAPHI); | |
1044 | D32(EMAC_PTP_TXSNAPLO); | |
1045 | # endif | |
1046 | #endif | |
1047 | ||
1048 | #if defined(EPPI0_STATUS) || defined(EPPI1_STATUS) || defined(EPPI2_STATUS) | |
1049 | parent = debugfs_create_dir("eppi", top); | |
1050 | # ifdef EPPI0_STATUS | |
1051 | EPPI(0); | |
1052 | # endif | |
1053 | # ifdef EPPI1_STATUS | |
1054 | EPPI(1); | |
1055 | # endif | |
1056 | # ifdef EPPI2_STATUS | |
1057 | EPPI(2); | |
1058 | # endif | |
1059 | #endif | |
1060 | ||
1061 | parent = debugfs_create_dir("gptimer", top); | |
af459864 MF |
1062 | #ifdef TIMER_ENABLE |
1063 | GPTIMER_GROUP(TIMER_ENABLE, -1); | |
73ecfcf9 | 1064 | #endif |
af459864 MF |
1065 | #ifdef TIMER_ENABLE0 |
1066 | GPTIMER_GROUP(TIMER_ENABLE0, 0); | |
73ecfcf9 | 1067 | #endif |
af459864 MF |
1068 | #ifdef TIMER_ENABLE1 |
1069 | GPTIMER_GROUP(TIMER_ENABLE1, 1); | |
73ecfcf9 MF |
1070 | #endif |
1071 | /* XXX: Should convert BF561 MMR names */ | |
1072 | #ifdef TMRS4_DISABLE | |
af459864 MF |
1073 | GPTIMER_GROUP(TMRS4_ENABLE, 0); |
1074 | GPTIMER_GROUP(TMRS8_ENABLE, 1); | |
73ecfcf9 MF |
1075 | #endif |
1076 | GPTIMER(0); | |
1077 | GPTIMER(1); | |
1078 | GPTIMER(2); | |
1079 | #ifdef TIMER3_CONFIG | |
1080 | GPTIMER(3); | |
1081 | GPTIMER(4); | |
1082 | GPTIMER(5); | |
1083 | GPTIMER(6); | |
1084 | GPTIMER(7); | |
1085 | #endif | |
1086 | #ifdef TIMER8_CONFIG | |
1087 | GPTIMER(8); | |
1088 | GPTIMER(9); | |
1089 | GPTIMER(10); | |
1090 | #endif | |
1091 | #ifdef TIMER11_CONFIG | |
1092 | GPTIMER(11); | |
1093 | #endif | |
1094 | ||
1095 | #ifdef HMDMA0_CONTROL | |
1096 | parent = debugfs_create_dir("hmdma", top); | |
1097 | HMDMA(0); | |
1098 | HMDMA(1); | |
1099 | #endif | |
1100 | ||
1101 | #ifdef HOST_CONTROL | |
1102 | parent = debugfs_create_dir("hostdp", top); | |
1103 | D16(HOST_CONTROL); | |
1104 | D16(HOST_STATUS); | |
1105 | D16(HOST_TIMEOUT); | |
1106 | #endif | |
1107 | ||
1108 | #ifdef IMDMA_S0_CONFIG | |
1109 | parent = debugfs_create_dir("imdma", top); | |
1110 | IMDMA(0); | |
1111 | IMDMA(1); | |
1112 | #endif | |
1113 | ||
1114 | #ifdef KPAD_CTL | |
1115 | parent = debugfs_create_dir("keypad", top); | |
1116 | D16(KPAD_CTL); | |
1117 | D16(KPAD_PRESCALE); | |
1118 | D16(KPAD_MSEL); | |
1119 | D16(KPAD_ROWCOL); | |
1120 | D16(KPAD_STAT); | |
1121 | D16(KPAD_SOFTEVAL); | |
1122 | #endif | |
1123 | ||
1124 | parent = debugfs_create_dir("mdma", top); | |
1125 | MDMA(0); | |
1126 | MDMA(1); | |
1127 | #ifdef MDMA_D2_CONFIG | |
1128 | MDMA(2); | |
1129 | MDMA(3); | |
1130 | #endif | |
1131 | ||
1132 | #ifdef MXVR_CONFIG | |
1133 | parent = debugfs_create_dir("mxvr", top); | |
1134 | D16(MXVR_CONFIG); | |
1135 | # ifdef MXVR_PLL_CTL_0 | |
1136 | D32(MXVR_PLL_CTL_0); | |
1137 | # endif | |
1138 | D32(MXVR_STATE_0); | |
1139 | D32(MXVR_STATE_1); | |
1140 | D32(MXVR_INT_STAT_0); | |
1141 | D32(MXVR_INT_STAT_1); | |
1142 | D32(MXVR_INT_EN_0); | |
1143 | D32(MXVR_INT_EN_1); | |
1144 | D16(MXVR_POSITION); | |
1145 | D16(MXVR_MAX_POSITION); | |
1146 | D16(MXVR_DELAY); | |
1147 | D16(MXVR_MAX_DELAY); | |
1148 | D32(MXVR_LADDR); | |
1149 | D16(MXVR_GADDR); | |
1150 | D32(MXVR_AADDR); | |
1151 | D32(MXVR_ALLOC_0); | |
1152 | D32(MXVR_ALLOC_1); | |
1153 | D32(MXVR_ALLOC_2); | |
1154 | D32(MXVR_ALLOC_3); | |
1155 | D32(MXVR_ALLOC_4); | |
1156 | D32(MXVR_ALLOC_5); | |
1157 | D32(MXVR_ALLOC_6); | |
1158 | D32(MXVR_ALLOC_7); | |
1159 | D32(MXVR_ALLOC_8); | |
1160 | D32(MXVR_ALLOC_9); | |
1161 | D32(MXVR_ALLOC_10); | |
1162 | D32(MXVR_ALLOC_11); | |
1163 | D32(MXVR_ALLOC_12); | |
1164 | D32(MXVR_ALLOC_13); | |
1165 | D32(MXVR_ALLOC_14); | |
1166 | D32(MXVR_SYNC_LCHAN_0); | |
1167 | D32(MXVR_SYNC_LCHAN_1); | |
1168 | D32(MXVR_SYNC_LCHAN_2); | |
1169 | D32(MXVR_SYNC_LCHAN_3); | |
1170 | D32(MXVR_SYNC_LCHAN_4); | |
1171 | D32(MXVR_SYNC_LCHAN_5); | |
1172 | D32(MXVR_SYNC_LCHAN_6); | |
1173 | D32(MXVR_SYNC_LCHAN_7); | |
1174 | D32(MXVR_DMA0_CONFIG); | |
1175 | D32(MXVR_DMA0_START_ADDR); | |
1176 | D16(MXVR_DMA0_COUNT); | |
1177 | D32(MXVR_DMA0_CURR_ADDR); | |
1178 | D16(MXVR_DMA0_CURR_COUNT); | |
1179 | D32(MXVR_DMA1_CONFIG); | |
1180 | D32(MXVR_DMA1_START_ADDR); | |
1181 | D16(MXVR_DMA1_COUNT); | |
1182 | D32(MXVR_DMA1_CURR_ADDR); | |
1183 | D16(MXVR_DMA1_CURR_COUNT); | |
1184 | D32(MXVR_DMA2_CONFIG); | |
1185 | D32(MXVR_DMA2_START_ADDR); | |
1186 | D16(MXVR_DMA2_COUNT); | |
1187 | D32(MXVR_DMA2_CURR_ADDR); | |
1188 | D16(MXVR_DMA2_CURR_COUNT); | |
1189 | D32(MXVR_DMA3_CONFIG); | |
1190 | D32(MXVR_DMA3_START_ADDR); | |
1191 | D16(MXVR_DMA3_COUNT); | |
1192 | D32(MXVR_DMA3_CURR_ADDR); | |
1193 | D16(MXVR_DMA3_CURR_COUNT); | |
1194 | D32(MXVR_DMA4_CONFIG); | |
1195 | D32(MXVR_DMA4_START_ADDR); | |
1196 | D16(MXVR_DMA4_COUNT); | |
1197 | D32(MXVR_DMA4_CURR_ADDR); | |
1198 | D16(MXVR_DMA4_CURR_COUNT); | |
1199 | D32(MXVR_DMA5_CONFIG); | |
1200 | D32(MXVR_DMA5_START_ADDR); | |
1201 | D16(MXVR_DMA5_COUNT); | |
1202 | D32(MXVR_DMA5_CURR_ADDR); | |
1203 | D16(MXVR_DMA5_CURR_COUNT); | |
1204 | D32(MXVR_DMA6_CONFIG); | |
1205 | D32(MXVR_DMA6_START_ADDR); | |
1206 | D16(MXVR_DMA6_COUNT); | |
1207 | D32(MXVR_DMA6_CURR_ADDR); | |
1208 | D16(MXVR_DMA6_CURR_COUNT); | |
1209 | D32(MXVR_DMA7_CONFIG); | |
1210 | D32(MXVR_DMA7_START_ADDR); | |
1211 | D16(MXVR_DMA7_COUNT); | |
1212 | D32(MXVR_DMA7_CURR_ADDR); | |
1213 | D16(MXVR_DMA7_CURR_COUNT); | |
1214 | D16(MXVR_AP_CTL); | |
1215 | D32(MXVR_APRB_START_ADDR); | |
1216 | D32(MXVR_APRB_CURR_ADDR); | |
1217 | D32(MXVR_APTB_START_ADDR); | |
1218 | D32(MXVR_APTB_CURR_ADDR); | |
1219 | D32(MXVR_CM_CTL); | |
1220 | D32(MXVR_CMRB_START_ADDR); | |
1221 | D32(MXVR_CMRB_CURR_ADDR); | |
1222 | D32(MXVR_CMTB_START_ADDR); | |
1223 | D32(MXVR_CMTB_CURR_ADDR); | |
1224 | D32(MXVR_RRDB_START_ADDR); | |
1225 | D32(MXVR_RRDB_CURR_ADDR); | |
1226 | D32(MXVR_PAT_DATA_0); | |
1227 | D32(MXVR_PAT_EN_0); | |
1228 | D32(MXVR_PAT_DATA_1); | |
1229 | D32(MXVR_PAT_EN_1); | |
1230 | D16(MXVR_FRAME_CNT_0); | |
1231 | D16(MXVR_FRAME_CNT_1); | |
1232 | D32(MXVR_ROUTING_0); | |
1233 | D32(MXVR_ROUTING_1); | |
1234 | D32(MXVR_ROUTING_2); | |
1235 | D32(MXVR_ROUTING_3); | |
1236 | D32(MXVR_ROUTING_4); | |
1237 | D32(MXVR_ROUTING_5); | |
1238 | D32(MXVR_ROUTING_6); | |
1239 | D32(MXVR_ROUTING_7); | |
1240 | D32(MXVR_ROUTING_8); | |
1241 | D32(MXVR_ROUTING_9); | |
1242 | D32(MXVR_ROUTING_10); | |
1243 | D32(MXVR_ROUTING_11); | |
1244 | D32(MXVR_ROUTING_12); | |
1245 | D32(MXVR_ROUTING_13); | |
1246 | D32(MXVR_ROUTING_14); | |
1247 | # ifdef MXVR_PLL_CTL_1 | |
1248 | D32(MXVR_PLL_CTL_1); | |
1249 | # endif | |
1250 | D16(MXVR_BLOCK_CNT); | |
1251 | # ifdef MXVR_CLK_CTL | |
1252 | D32(MXVR_CLK_CTL); | |
1253 | # endif | |
1254 | # ifdef MXVR_CDRPLL_CTL | |
1255 | D32(MXVR_CDRPLL_CTL); | |
1256 | # endif | |
1257 | # ifdef MXVR_FMPLL_CTL | |
1258 | D32(MXVR_FMPLL_CTL); | |
1259 | # endif | |
1260 | # ifdef MXVR_PIN_CTL | |
1261 | D16(MXVR_PIN_CTL); | |
1262 | # endif | |
1263 | # ifdef MXVR_SCLK_CNT | |
1264 | D16(MXVR_SCLK_CNT); | |
1265 | # endif | |
1266 | #endif | |
1267 | ||
1268 | #ifdef NFC_ADDR | |
1269 | parent = debugfs_create_dir("nfc", top); | |
1270 | D_WO(NFC_ADDR, 16); | |
1271 | D_WO(NFC_CMD, 16); | |
1272 | D_RO(NFC_COUNT, 16); | |
1273 | D16(NFC_CTL); | |
1274 | D_WO(NFC_DATA_RD, 16); | |
1275 | D_WO(NFC_DATA_WR, 16); | |
1276 | D_RO(NFC_ECC0, 16); | |
1277 | D_RO(NFC_ECC1, 16); | |
1278 | D_RO(NFC_ECC2, 16); | |
1279 | D_RO(NFC_ECC3, 16); | |
1280 | D16(NFC_IRQMASK); | |
1281 | D16(NFC_IRQSTAT); | |
1282 | D_WO(NFC_PGCTL, 16); | |
1283 | D_RO(NFC_READ, 16); | |
1284 | D16(NFC_RST); | |
1285 | D_RO(NFC_STAT, 16); | |
1286 | #endif | |
1287 | ||
1288 | #ifdef OTP_CONTROL | |
1289 | parent = debugfs_create_dir("otp", top); | |
1290 | D16(OTP_CONTROL); | |
1291 | D16(OTP_BEN); | |
1292 | D16(OTP_STATUS); | |
1293 | D32(OTP_TIMING); | |
1294 | D32(OTP_DATA0); | |
1295 | D32(OTP_DATA1); | |
1296 | D32(OTP_DATA2); | |
1297 | D32(OTP_DATA3); | |
1298 | #endif | |
1299 | ||
0a7e5413 MF |
1300 | #ifdef PINT0_MASK_SET |
1301 | parent = debugfs_create_dir("pint", top); | |
1302 | PINT(0); | |
1303 | PINT(1); | |
1304 | PINT(2); | |
1305 | PINT(3); | |
1306 | #endif | |
1307 | ||
73ecfcf9 MF |
1308 | #ifdef PIXC_CTL |
1309 | parent = debugfs_create_dir("pixc", top); | |
1310 | D16(PIXC_CTL); | |
1311 | D16(PIXC_PPL); | |
1312 | D16(PIXC_LPF); | |
1313 | D16(PIXC_AHSTART); | |
1314 | D16(PIXC_AHEND); | |
1315 | D16(PIXC_AVSTART); | |
1316 | D16(PIXC_AVEND); | |
1317 | D16(PIXC_ATRANSP); | |
1318 | D16(PIXC_BHSTART); | |
1319 | D16(PIXC_BHEND); | |
1320 | D16(PIXC_BVSTART); | |
1321 | D16(PIXC_BVEND); | |
1322 | D16(PIXC_BTRANSP); | |
1323 | D16(PIXC_INTRSTAT); | |
1324 | D32(PIXC_RYCON); | |
1325 | D32(PIXC_GUCON); | |
1326 | D32(PIXC_BVCON); | |
1327 | D32(PIXC_CCBIAS); | |
1328 | D32(PIXC_TC); | |
1329 | #endif | |
1330 | ||
1331 | parent = debugfs_create_dir("pll", top); | |
1332 | D16(PLL_CTL); | |
1333 | D16(PLL_DIV); | |
1334 | D16(PLL_LOCKCNT); | |
1335 | D16(PLL_STAT); | |
1336 | D16(VR_CTL); | |
1337 | D32(CHIPID); /* it's part of this hardware block */ | |
1338 | ||
d09fb602 | 1339 | #if defined(PPI_CONTROL) || defined(PPI0_CONTROL) || defined(PPI1_CONTROL) |
73ecfcf9 | 1340 | parent = debugfs_create_dir("ppi", top); |
d09fb602 MF |
1341 | # ifdef PPI_CONTROL |
1342 | bfin_debug_mmrs_ppi(parent, PPI_CONTROL, -1); | |
73ecfcf9 | 1343 | # endif |
d09fb602 | 1344 | # ifdef PPI0_CONTROL |
73ecfcf9 MF |
1345 | PPI(0); |
1346 | # endif | |
d09fb602 | 1347 | # ifdef PPI1_CONTROL |
73ecfcf9 MF |
1348 | PPI(1); |
1349 | # endif | |
1350 | #endif | |
1351 | ||
1352 | #ifdef PWM_CTRL | |
1353 | parent = debugfs_create_dir("pwm", top); | |
1354 | D16(PWM_CTRL); | |
1355 | D16(PWM_STAT); | |
1356 | D16(PWM_TM); | |
1357 | D16(PWM_DT); | |
1358 | D16(PWM_GATE); | |
1359 | D16(PWM_CHA); | |
1360 | D16(PWM_CHB); | |
1361 | D16(PWM_CHC); | |
1362 | D16(PWM_SEG); | |
1363 | D16(PWM_SYNCWT); | |
1364 | D16(PWM_CHAL); | |
1365 | D16(PWM_CHBL); | |
1366 | D16(PWM_CHCL); | |
1367 | D16(PWM_LSI); | |
1368 | D16(PWM_STAT2); | |
1369 | #endif | |
1370 | ||
1371 | #ifdef RSI_CONFIG | |
1372 | parent = debugfs_create_dir("rsi", top); | |
1373 | D32(RSI_ARGUMENT); | |
1374 | D16(RSI_CEATA_CONTROL); | |
1375 | D16(RSI_CLK_CONTROL); | |
1376 | D16(RSI_COMMAND); | |
1377 | D16(RSI_CONFIG); | |
1378 | D16(RSI_DATA_CNT); | |
1379 | D16(RSI_DATA_CONTROL); | |
1380 | D16(RSI_DATA_LGTH); | |
1381 | D32(RSI_DATA_TIMER); | |
1382 | D16(RSI_EMASK); | |
1383 | D16(RSI_ESTAT); | |
1384 | D32(RSI_FIFO); | |
1385 | D16(RSI_FIFO_CNT); | |
1386 | D32(RSI_MASK0); | |
1387 | D32(RSI_MASK1); | |
1388 | D16(RSI_PID0); | |
1389 | D16(RSI_PID1); | |
1390 | D16(RSI_PID2); | |
1391 | D16(RSI_PID3); | |
c320afe9 MF |
1392 | D16(RSI_PID4); |
1393 | D16(RSI_PID5); | |
1394 | D16(RSI_PID6); | |
1395 | D16(RSI_PID7); | |
73ecfcf9 MF |
1396 | D16(RSI_PWR_CONTROL); |
1397 | D16(RSI_RD_WAIT_EN); | |
1398 | D32(RSI_RESPONSE0); | |
1399 | D32(RSI_RESPONSE1); | |
1400 | D32(RSI_RESPONSE2); | |
1401 | D32(RSI_RESPONSE3); | |
1402 | D16(RSI_RESP_CMD); | |
1403 | D32(RSI_STATUS); | |
1404 | D_WO(RSI_STATUSCL, 16); | |
1405 | #endif | |
1406 | ||
1407 | #ifdef RTC_ALARM | |
1408 | parent = debugfs_create_dir("rtc", top); | |
1409 | D32(RTC_ALARM); | |
1410 | D16(RTC_ICTL); | |
1411 | D16(RTC_ISTAT); | |
1412 | D16(RTC_PREN); | |
1413 | D32(RTC_STAT); | |
1414 | D16(RTC_SWCNT); | |
1415 | #endif | |
1416 | ||
1417 | #ifdef SDH_CFG | |
1418 | parent = debugfs_create_dir("sdh", top); | |
1419 | D32(SDH_ARGUMENT); | |
1420 | D16(SDH_CFG); | |
1421 | D16(SDH_CLK_CTL); | |
1422 | D16(SDH_COMMAND); | |
1423 | D_RO(SDH_DATA_CNT, 16); | |
1424 | D16(SDH_DATA_CTL); | |
1425 | D16(SDH_DATA_LGTH); | |
1426 | D32(SDH_DATA_TIMER); | |
1427 | D16(SDH_E_MASK); | |
1428 | D16(SDH_E_STATUS); | |
1429 | D32(SDH_FIFO); | |
1430 | D_RO(SDH_FIFO_CNT, 16); | |
1431 | D32(SDH_MASK0); | |
1432 | D32(SDH_MASK1); | |
1433 | D_RO(SDH_PID0, 16); | |
1434 | D_RO(SDH_PID1, 16); | |
1435 | D_RO(SDH_PID2, 16); | |
1436 | D_RO(SDH_PID3, 16); | |
1437 | D_RO(SDH_PID4, 16); | |
1438 | D_RO(SDH_PID5, 16); | |
1439 | D_RO(SDH_PID6, 16); | |
1440 | D_RO(SDH_PID7, 16); | |
1441 | D16(SDH_PWR_CTL); | |
1442 | D16(SDH_RD_WAIT_EN); | |
1443 | D_RO(SDH_RESPONSE0, 32); | |
1444 | D_RO(SDH_RESPONSE1, 32); | |
1445 | D_RO(SDH_RESPONSE2, 32); | |
1446 | D_RO(SDH_RESPONSE3, 32); | |
1447 | D_RO(SDH_RESP_CMD, 16); | |
1448 | D_RO(SDH_STATUS, 32); | |
1449 | D_WO(SDH_STATUS_CLR, 16); | |
1450 | #endif | |
1451 | ||
1452 | #ifdef SECURE_CONTROL | |
1453 | parent = debugfs_create_dir("security", top); | |
1454 | D16(SECURE_CONTROL); | |
1455 | D16(SECURE_STATUS); | |
1456 | D32(SECURE_SYSSWT); | |
1457 | #endif | |
1458 | ||
1459 | parent = debugfs_create_dir("sic", top); | |
1460 | D16(SWRST); | |
1461 | D16(SYSCR); | |
1462 | D16(SIC_RVECT); | |
1463 | D32(SIC_IAR0); | |
1464 | D32(SIC_IAR1); | |
1465 | D32(SIC_IAR2); | |
1466 | #ifdef SIC_IAR3 | |
1467 | D32(SIC_IAR3); | |
1468 | #endif | |
1469 | #ifdef SIC_IAR4 | |
1470 | D32(SIC_IAR4); | |
1471 | D32(SIC_IAR5); | |
1472 | D32(SIC_IAR6); | |
1473 | #endif | |
1474 | #ifdef SIC_IAR7 | |
1475 | D32(SIC_IAR7); | |
1476 | #endif | |
1477 | #ifdef SIC_IAR8 | |
1478 | D32(SIC_IAR8); | |
1479 | D32(SIC_IAR9); | |
1480 | D32(SIC_IAR10); | |
1481 | D32(SIC_IAR11); | |
1482 | #endif | |
1483 | #ifdef SIC_IMASK | |
1484 | D32(SIC_IMASK); | |
1485 | D32(SIC_ISR); | |
1486 | D32(SIC_IWR); | |
1487 | #endif | |
1488 | #ifdef SIC_IMASK0 | |
1489 | D32(SIC_IMASK0); | |
1490 | D32(SIC_IMASK1); | |
1491 | D32(SIC_ISR0); | |
1492 | D32(SIC_ISR1); | |
1493 | D32(SIC_IWR0); | |
1494 | D32(SIC_IWR1); | |
1495 | #endif | |
1496 | #ifdef SIC_IMASK2 | |
1497 | D32(SIC_IMASK2); | |
1498 | D32(SIC_ISR2); | |
1499 | D32(SIC_IWR2); | |
1500 | #endif | |
1501 | #ifdef SICB_RVECT | |
1502 | D16(SICB_SWRST); | |
1503 | D16(SICB_SYSCR); | |
1504 | D16(SICB_RVECT); | |
1505 | D32(SICB_IAR0); | |
1506 | D32(SICB_IAR1); | |
1507 | D32(SICB_IAR2); | |
1508 | D32(SICB_IAR3); | |
1509 | D32(SICB_IAR4); | |
1510 | D32(SICB_IAR5); | |
1511 | D32(SICB_IAR6); | |
1512 | D32(SICB_IAR7); | |
1513 | D32(SICB_IMASK0); | |
1514 | D32(SICB_IMASK1); | |
1515 | D32(SICB_ISR0); | |
1516 | D32(SICB_ISR1); | |
1517 | D32(SICB_IWR0); | |
1518 | D32(SICB_IWR1); | |
1519 | #endif | |
1520 | ||
1521 | parent = debugfs_create_dir("spi", top); | |
1522 | #ifdef SPI0_REGBASE | |
1523 | SPI(0); | |
1524 | #endif | |
1525 | #ifdef SPI1_REGBASE | |
1526 | SPI(1); | |
1527 | #endif | |
1528 | #ifdef SPI2_REGBASE | |
1529 | SPI(2); | |
1530 | #endif | |
1531 | ||
1532 | parent = debugfs_create_dir("sport", top); | |
1533 | #ifdef SPORT0_STAT | |
1534 | SPORT(0); | |
1535 | #endif | |
1536 | #ifdef SPORT1_STAT | |
1537 | SPORT(1); | |
1538 | #endif | |
1539 | #ifdef SPORT2_STAT | |
1540 | SPORT(2); | |
1541 | #endif | |
1542 | #ifdef SPORT3_STAT | |
1543 | SPORT(3); | |
1544 | #endif | |
1545 | ||
1546 | #if defined(TWI_CLKDIV) || defined(TWI0_CLKDIV) || defined(TWI1_CLKDIV) | |
1547 | parent = debugfs_create_dir("twi", top); | |
1548 | # ifdef TWI_CLKDIV | |
1549 | bfin_debug_mmrs_twi(parent, TWI_CLKDIV, -1); | |
1550 | # endif | |
1551 | # ifdef TWI0_CLKDIV | |
1552 | TWI(0); | |
1553 | # endif | |
1554 | # ifdef TWI1_CLKDIV | |
1555 | TWI(1); | |
1556 | # endif | |
1557 | #endif | |
1558 | ||
1559 | parent = debugfs_create_dir("uart", top); | |
1560 | #ifdef BFIN_UART_DLL | |
1561 | bfin_debug_mmrs_uart(parent, BFIN_UART_DLL, -1); | |
1562 | #endif | |
1563 | #ifdef UART0_DLL | |
1564 | UART(0); | |
1565 | #endif | |
1566 | #ifdef UART1_DLL | |
1567 | UART(1); | |
1568 | #endif | |
1569 | #ifdef UART2_DLL | |
1570 | UART(2); | |
1571 | #endif | |
1572 | #ifdef UART3_DLL | |
1573 | UART(3); | |
1574 | #endif | |
1575 | ||
1576 | #ifdef USB_FADDR | |
1577 | parent = debugfs_create_dir("usb", top); | |
1578 | D16(USB_FADDR); | |
1579 | D16(USB_POWER); | |
1580 | D16(USB_INTRTX); | |
1581 | D16(USB_INTRRX); | |
1582 | D16(USB_INTRTXE); | |
1583 | D16(USB_INTRRXE); | |
1584 | D16(USB_INTRUSB); | |
1585 | D16(USB_INTRUSBE); | |
1586 | D16(USB_FRAME); | |
1587 | D16(USB_INDEX); | |
1588 | D16(USB_TESTMODE); | |
1589 | D16(USB_GLOBINTR); | |
1590 | D16(USB_GLOBAL_CTL); | |
1591 | D16(USB_TX_MAX_PACKET); | |
1592 | D16(USB_CSR0); | |
1593 | D16(USB_TXCSR); | |
1594 | D16(USB_RX_MAX_PACKET); | |
1595 | D16(USB_RXCSR); | |
1596 | D16(USB_COUNT0); | |
1597 | D16(USB_RXCOUNT); | |
1598 | D16(USB_TXTYPE); | |
1599 | D16(USB_NAKLIMIT0); | |
1600 | D16(USB_TXINTERVAL); | |
1601 | D16(USB_RXTYPE); | |
1602 | D16(USB_RXINTERVAL); | |
1603 | D16(USB_TXCOUNT); | |
1604 | D16(USB_EP0_FIFO); | |
1605 | D16(USB_EP1_FIFO); | |
1606 | D16(USB_EP2_FIFO); | |
1607 | D16(USB_EP3_FIFO); | |
1608 | D16(USB_EP4_FIFO); | |
1609 | D16(USB_EP5_FIFO); | |
1610 | D16(USB_EP6_FIFO); | |
1611 | D16(USB_EP7_FIFO); | |
1612 | D16(USB_OTG_DEV_CTL); | |
1613 | D16(USB_OTG_VBUS_IRQ); | |
1614 | D16(USB_OTG_VBUS_MASK); | |
1615 | D16(USB_LINKINFO); | |
1616 | D16(USB_VPLEN); | |
1617 | D16(USB_HS_EOF1); | |
1618 | D16(USB_FS_EOF1); | |
1619 | D16(USB_LS_EOF1); | |
1620 | D16(USB_APHY_CNTRL); | |
1621 | D16(USB_APHY_CALIB); | |
1622 | D16(USB_APHY_CNTRL2); | |
73ecfcf9 MF |
1623 | D16(USB_PLLOSC_CTRL); |
1624 | D16(USB_SRP_CLKDIV); | |
1625 | D16(USB_EP_NI0_TXMAXP); | |
1626 | D16(USB_EP_NI0_TXCSR); | |
1627 | D16(USB_EP_NI0_RXMAXP); | |
1628 | D16(USB_EP_NI0_RXCSR); | |
1629 | D16(USB_EP_NI0_RXCOUNT); | |
1630 | D16(USB_EP_NI0_TXTYPE); | |
1631 | D16(USB_EP_NI0_TXINTERVAL); | |
1632 | D16(USB_EP_NI0_RXTYPE); | |
1633 | D16(USB_EP_NI0_RXINTERVAL); | |
1634 | D16(USB_EP_NI0_TXCOUNT); | |
1635 | D16(USB_EP_NI1_TXMAXP); | |
1636 | D16(USB_EP_NI1_TXCSR); | |
1637 | D16(USB_EP_NI1_RXMAXP); | |
1638 | D16(USB_EP_NI1_RXCSR); | |
1639 | D16(USB_EP_NI1_RXCOUNT); | |
1640 | D16(USB_EP_NI1_TXTYPE); | |
1641 | D16(USB_EP_NI1_TXINTERVAL); | |
1642 | D16(USB_EP_NI1_RXTYPE); | |
1643 | D16(USB_EP_NI1_RXINTERVAL); | |
1644 | D16(USB_EP_NI1_TXCOUNT); | |
1645 | D16(USB_EP_NI2_TXMAXP); | |
1646 | D16(USB_EP_NI2_TXCSR); | |
1647 | D16(USB_EP_NI2_RXMAXP); | |
1648 | D16(USB_EP_NI2_RXCSR); | |
1649 | D16(USB_EP_NI2_RXCOUNT); | |
1650 | D16(USB_EP_NI2_TXTYPE); | |
1651 | D16(USB_EP_NI2_TXINTERVAL); | |
1652 | D16(USB_EP_NI2_RXTYPE); | |
1653 | D16(USB_EP_NI2_RXINTERVAL); | |
1654 | D16(USB_EP_NI2_TXCOUNT); | |
1655 | D16(USB_EP_NI3_TXMAXP); | |
1656 | D16(USB_EP_NI3_TXCSR); | |
1657 | D16(USB_EP_NI3_RXMAXP); | |
1658 | D16(USB_EP_NI3_RXCSR); | |
1659 | D16(USB_EP_NI3_RXCOUNT); | |
1660 | D16(USB_EP_NI3_TXTYPE); | |
1661 | D16(USB_EP_NI3_TXINTERVAL); | |
1662 | D16(USB_EP_NI3_RXTYPE); | |
1663 | D16(USB_EP_NI3_RXINTERVAL); | |
1664 | D16(USB_EP_NI3_TXCOUNT); | |
1665 | D16(USB_EP_NI4_TXMAXP); | |
1666 | D16(USB_EP_NI4_TXCSR); | |
1667 | D16(USB_EP_NI4_RXMAXP); | |
1668 | D16(USB_EP_NI4_RXCSR); | |
1669 | D16(USB_EP_NI4_RXCOUNT); | |
1670 | D16(USB_EP_NI4_TXTYPE); | |
1671 | D16(USB_EP_NI4_TXINTERVAL); | |
1672 | D16(USB_EP_NI4_RXTYPE); | |
1673 | D16(USB_EP_NI4_RXINTERVAL); | |
1674 | D16(USB_EP_NI4_TXCOUNT); | |
1675 | D16(USB_EP_NI5_TXMAXP); | |
1676 | D16(USB_EP_NI5_TXCSR); | |
1677 | D16(USB_EP_NI5_RXMAXP); | |
1678 | D16(USB_EP_NI5_RXCSR); | |
1679 | D16(USB_EP_NI5_RXCOUNT); | |
1680 | D16(USB_EP_NI5_TXTYPE); | |
1681 | D16(USB_EP_NI5_TXINTERVAL); | |
1682 | D16(USB_EP_NI5_RXTYPE); | |
1683 | D16(USB_EP_NI5_RXINTERVAL); | |
1684 | D16(USB_EP_NI5_TXCOUNT); | |
1685 | D16(USB_EP_NI6_TXMAXP); | |
1686 | D16(USB_EP_NI6_TXCSR); | |
1687 | D16(USB_EP_NI6_RXMAXP); | |
1688 | D16(USB_EP_NI6_RXCSR); | |
1689 | D16(USB_EP_NI6_RXCOUNT); | |
1690 | D16(USB_EP_NI6_TXTYPE); | |
1691 | D16(USB_EP_NI6_TXINTERVAL); | |
1692 | D16(USB_EP_NI6_RXTYPE); | |
1693 | D16(USB_EP_NI6_RXINTERVAL); | |
1694 | D16(USB_EP_NI6_TXCOUNT); | |
1695 | D16(USB_EP_NI7_TXMAXP); | |
1696 | D16(USB_EP_NI7_TXCSR); | |
1697 | D16(USB_EP_NI7_RXMAXP); | |
1698 | D16(USB_EP_NI7_RXCSR); | |
1699 | D16(USB_EP_NI7_RXCOUNT); | |
1700 | D16(USB_EP_NI7_TXTYPE); | |
1701 | D16(USB_EP_NI7_TXINTERVAL); | |
1702 | D16(USB_EP_NI7_RXTYPE); | |
1703 | D16(USB_EP_NI7_RXINTERVAL); | |
1704 | D16(USB_EP_NI7_TXCOUNT); | |
1705 | D16(USB_DMA_INTERRUPT); | |
1706 | D16(USB_DMA0CONTROL); | |
1707 | D16(USB_DMA0ADDRLOW); | |
1708 | D16(USB_DMA0ADDRHIGH); | |
1709 | D16(USB_DMA0COUNTLOW); | |
1710 | D16(USB_DMA0COUNTHIGH); | |
1711 | D16(USB_DMA1CONTROL); | |
1712 | D16(USB_DMA1ADDRLOW); | |
1713 | D16(USB_DMA1ADDRHIGH); | |
1714 | D16(USB_DMA1COUNTLOW); | |
1715 | D16(USB_DMA1COUNTHIGH); | |
1716 | D16(USB_DMA2CONTROL); | |
1717 | D16(USB_DMA2ADDRLOW); | |
1718 | D16(USB_DMA2ADDRHIGH); | |
1719 | D16(USB_DMA2COUNTLOW); | |
1720 | D16(USB_DMA2COUNTHIGH); | |
1721 | D16(USB_DMA3CONTROL); | |
1722 | D16(USB_DMA3ADDRLOW); | |
1723 | D16(USB_DMA3ADDRHIGH); | |
1724 | D16(USB_DMA3COUNTLOW); | |
1725 | D16(USB_DMA3COUNTHIGH); | |
1726 | D16(USB_DMA4CONTROL); | |
1727 | D16(USB_DMA4ADDRLOW); | |
1728 | D16(USB_DMA4ADDRHIGH); | |
1729 | D16(USB_DMA4COUNTLOW); | |
1730 | D16(USB_DMA4COUNTHIGH); | |
1731 | D16(USB_DMA5CONTROL); | |
1732 | D16(USB_DMA5ADDRLOW); | |
1733 | D16(USB_DMA5ADDRHIGH); | |
1734 | D16(USB_DMA5COUNTLOW); | |
1735 | D16(USB_DMA5COUNTHIGH); | |
1736 | D16(USB_DMA6CONTROL); | |
1737 | D16(USB_DMA6ADDRLOW); | |
1738 | D16(USB_DMA6ADDRHIGH); | |
1739 | D16(USB_DMA6COUNTLOW); | |
1740 | D16(USB_DMA6COUNTHIGH); | |
1741 | D16(USB_DMA7CONTROL); | |
1742 | D16(USB_DMA7ADDRLOW); | |
1743 | D16(USB_DMA7ADDRHIGH); | |
1744 | D16(USB_DMA7COUNTLOW); | |
1745 | D16(USB_DMA7COUNTHIGH); | |
1746 | #endif | |
1747 | ||
1748 | #ifdef WDOG_CNT | |
1749 | parent = debugfs_create_dir("watchdog", top); | |
1750 | D32(WDOG_CNT); | |
1751 | D16(WDOG_CTL); | |
1752 | D32(WDOG_STAT); | |
1753 | #endif | |
1754 | #ifdef WDOGA_CNT | |
1755 | parent = debugfs_create_dir("watchdog", top); | |
1756 | D32(WDOGA_CNT); | |
1757 | D16(WDOGA_CTL); | |
1758 | D32(WDOGA_STAT); | |
1759 | D32(WDOGB_CNT); | |
1760 | D16(WDOGB_CTL); | |
1761 | D32(WDOGB_STAT); | |
1762 | #endif | |
1763 | ||
1764 | /* BF533 glue */ | |
1765 | #ifdef FIO_FLAG_D | |
1766 | #define PORTFIO FIO_FLAG_D | |
1767 | #endif | |
1768 | /* BF561 glue */ | |
1769 | #ifdef FIO0_FLAG_D | |
1770 | #define PORTFIO FIO0_FLAG_D | |
1771 | #endif | |
1772 | #ifdef FIO1_FLAG_D | |
1773 | #define PORTGIO FIO1_FLAG_D | |
1774 | #endif | |
1775 | #ifdef FIO2_FLAG_D | |
1776 | #define PORTHIO FIO2_FLAG_D | |
1777 | #endif | |
1778 | parent = debugfs_create_dir("port", top); | |
1779 | #ifdef PORTFIO | |
1780 | PORT(PORTFIO, 'F'); | |
1781 | #endif | |
1782 | #ifdef PORTGIO | |
1783 | PORT(PORTGIO, 'G'); | |
1784 | #endif | |
1785 | #ifdef PORTHIO | |
1786 | PORT(PORTHIO, 'H'); | |
1787 | #endif | |
1788 | ||
1789 | #ifdef __ADSPBF51x__ | |
1790 | D16(PORTF_FER); | |
1791 | D16(PORTF_DRIVE); | |
1792 | D16(PORTF_HYSTERESIS); | |
1793 | D16(PORTF_MUX); | |
1794 | ||
1795 | D16(PORTG_FER); | |
1796 | D16(PORTG_DRIVE); | |
1797 | D16(PORTG_HYSTERESIS); | |
1798 | D16(PORTG_MUX); | |
1799 | ||
1800 | D16(PORTH_FER); | |
1801 | D16(PORTH_DRIVE); | |
1802 | D16(PORTH_HYSTERESIS); | |
1803 | D16(PORTH_MUX); | |
1804 | ||
1805 | D16(MISCPORT_DRIVE); | |
1806 | D16(MISCPORT_HYSTERESIS); | |
1807 | #endif /* BF51x */ | |
1808 | ||
1809 | #ifdef __ADSPBF52x__ | |
1810 | D16(PORTF_FER); | |
1811 | D16(PORTF_DRIVE); | |
1812 | D16(PORTF_HYSTERESIS); | |
1813 | D16(PORTF_MUX); | |
1814 | D16(PORTF_SLEW); | |
1815 | ||
1816 | D16(PORTG_FER); | |
1817 | D16(PORTG_DRIVE); | |
1818 | D16(PORTG_HYSTERESIS); | |
1819 | D16(PORTG_MUX); | |
1820 | D16(PORTG_SLEW); | |
1821 | ||
1822 | D16(PORTH_FER); | |
1823 | D16(PORTH_DRIVE); | |
1824 | D16(PORTH_HYSTERESIS); | |
1825 | D16(PORTH_MUX); | |
1826 | D16(PORTH_SLEW); | |
1827 | ||
1828 | D16(MISCPORT_DRIVE); | |
1829 | D16(MISCPORT_HYSTERESIS); | |
1830 | D16(MISCPORT_SLEW); | |
1831 | #endif /* BF52x */ | |
1832 | ||
1833 | #ifdef BF537_FAMILY | |
1834 | D16(PORTF_FER); | |
1835 | D16(PORTG_FER); | |
1836 | D16(PORTH_FER); | |
1837 | D16(PORT_MUX); | |
1838 | #endif /* BF534 BF536 BF537 */ | |
1839 | ||
1840 | #ifdef BF538_FAMILY | |
1841 | D16(PORTCIO_FER); | |
1842 | D16(PORTCIO); | |
1843 | D16(PORTCIO_CLEAR); | |
1844 | D16(PORTCIO_SET); | |
1845 | D16(PORTCIO_TOGGLE); | |
1846 | D16(PORTCIO_DIR); | |
1847 | D16(PORTCIO_INEN); | |
1848 | ||
1849 | D16(PORTDIO); | |
1850 | D16(PORTDIO_CLEAR); | |
1851 | D16(PORTDIO_DIR); | |
1852 | D16(PORTDIO_FER); | |
1853 | D16(PORTDIO_INEN); | |
1854 | D16(PORTDIO_SET); | |
1855 | D16(PORTDIO_TOGGLE); | |
1856 | ||
1857 | D16(PORTEIO); | |
1858 | D16(PORTEIO_CLEAR); | |
1859 | D16(PORTEIO_DIR); | |
1860 | D16(PORTEIO_FER); | |
1861 | D16(PORTEIO_INEN); | |
1862 | D16(PORTEIO_SET); | |
1863 | D16(PORTEIO_TOGGLE); | |
1864 | #endif /* BF538 BF539 */ | |
1865 | ||
1866 | #ifdef __ADSPBF54x__ | |
1867 | { | |
1868 | int num; | |
1869 | unsigned long base; | |
73ecfcf9 MF |
1870 | |
1871 | base = PORTA_FER; | |
1872 | for (num = 0; num < 10; ++num) { | |
1873 | PORT(base, num); | |
1874 | base += sizeof(struct bfin_gpio_regs); | |
1875 | } | |
1876 | ||
73ecfcf9 MF |
1877 | } |
1878 | #endif /* BF54x */ | |
b5affb01 | 1879 | #endif /* CONFIG_BF60x */ |
73ecfcf9 MF |
1880 | debug_mmrs_dentry = top; |
1881 | ||
1882 | return 0; | |
1883 | } | |
1884 | module_init(bfin_debug_mmrs_init); | |
1885 | ||
1886 | static void __exit bfin_debug_mmrs_exit(void) | |
1887 | { | |
1888 | debugfs_remove_recursive(debug_mmrs_dentry); | |
1889 | } | |
1890 | module_exit(bfin_debug_mmrs_exit); | |
1891 | ||
1892 | MODULE_LICENSE("GPL"); |