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Commit | Line | Data |
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60ffdb36 GY |
1 | /* |
2 | * Blackfin nmi_watchdog Driver | |
3 | * | |
4 | * Originally based on bfin_wdt.c | |
5 | * Copyright 2010-2010 Analog Devices Inc. | |
6 | * Graff Yang <graf.yang@analog.com> | |
7 | * | |
8 | * Enter bugs at http://blackfin.uclinux.org/ | |
9 | * | |
10 | * Licensed under the GPL-2 or later. | |
11 | */ | |
12 | ||
13 | #include <linux/bitops.h> | |
14 | #include <linux/hardirq.h> | |
67f9cbf9 | 15 | #include <linux/syscore_ops.h> |
60ffdb36 GY |
16 | #include <linux/pm.h> |
17 | #include <linux/nmi.h> | |
18 | #include <linux/smp.h> | |
19 | #include <linux/timer.h> | |
b17b0153 | 20 | #include <linux/sched/debug.h> |
60ffdb36 | 21 | #include <asm/blackfin.h> |
60063497 | 22 | #include <linux/atomic.h> |
60ffdb36 | 23 | #include <asm/cacheflush.h> |
64b33a00 | 24 | #include <asm/bfin_watchdog.h> |
60ffdb36 GY |
25 | |
26 | #define DRV_NAME "nmi-wdt" | |
27 | ||
28 | #define NMI_WDT_TIMEOUT 5 /* 5 seconds */ | |
29 | #define NMI_CHECK_TIMEOUT (4 * HZ) /* 4 seconds in jiffies */ | |
30 | static int nmi_wdt_cpu = 1; | |
31 | ||
32 | static unsigned int timeout = NMI_WDT_TIMEOUT; | |
33 | static int nmi_active; | |
34 | ||
35 | static unsigned short wdoga_ctl; | |
36 | static unsigned int wdoga_cnt; | |
37 | static struct corelock_slot saved_corelock; | |
38 | static atomic_t nmi_touched[NR_CPUS]; | |
39 | static struct timer_list ntimer; | |
40 | ||
41 | enum { | |
42 | COREA_ENTER_NMI = 0, | |
43 | COREA_EXIT_NMI, | |
44 | COREB_EXIT_NMI, | |
45 | ||
46 | NMI_EVENT_NR, | |
47 | }; | |
48 | static unsigned long nmi_event __attribute__ ((__section__(".l2.bss"))); | |
49 | ||
50 | /* we are in nmi, non-atomic bit ops is safe */ | |
51 | static inline void set_nmi_event(int event) | |
52 | { | |
53 | __set_bit(event, &nmi_event); | |
54 | } | |
55 | ||
56 | static inline void wait_nmi_event(int event) | |
57 | { | |
58 | while (!test_bit(event, &nmi_event)) | |
59 | barrier(); | |
60 | __clear_bit(event, &nmi_event); | |
61 | } | |
62 | ||
63 | static inline void send_corea_nmi(void) | |
64 | { | |
65 | wdoga_ctl = bfin_read_WDOGA_CTL(); | |
66 | wdoga_cnt = bfin_read_WDOGA_CNT(); | |
67 | ||
68 | bfin_write_WDOGA_CTL(WDEN_DISABLE); | |
69 | bfin_write_WDOGA_CNT(0); | |
70 | bfin_write_WDOGA_CTL(WDEN_ENABLE | ICTL_NMI); | |
71 | } | |
72 | ||
73 | static inline void restore_corea_nmi(void) | |
74 | { | |
75 | bfin_write_WDOGA_CTL(WDEN_DISABLE); | |
76 | bfin_write_WDOGA_CTL(WDOG_EXPIRED | WDEN_DISABLE | ICTL_NONE); | |
77 | ||
78 | bfin_write_WDOGA_CNT(wdoga_cnt); | |
79 | bfin_write_WDOGA_CTL(wdoga_ctl); | |
80 | } | |
81 | ||
82 | static inline void save_corelock(void) | |
83 | { | |
84 | saved_corelock = corelock; | |
85 | corelock.lock = 0; | |
86 | } | |
87 | ||
88 | static inline void restore_corelock(void) | |
89 | { | |
90 | corelock = saved_corelock; | |
91 | } | |
92 | ||
93 | ||
94 | static inline void nmi_wdt_keepalive(void) | |
95 | { | |
96 | bfin_write_WDOGB_STAT(0); | |
97 | } | |
98 | ||
99 | static inline void nmi_wdt_stop(void) | |
100 | { | |
101 | bfin_write_WDOGB_CTL(WDEN_DISABLE); | |
102 | } | |
103 | ||
104 | /* before calling this function, you must stop the WDT */ | |
105 | static inline void nmi_wdt_clear(void) | |
106 | { | |
107 | /* clear TRO bit, disable event generation */ | |
108 | bfin_write_WDOGB_CTL(WDOG_EXPIRED | WDEN_DISABLE | ICTL_NONE); | |
109 | } | |
110 | ||
111 | static inline void nmi_wdt_start(void) | |
112 | { | |
113 | bfin_write_WDOGB_CTL(WDEN_ENABLE | ICTL_NMI); | |
114 | } | |
115 | ||
116 | static inline int nmi_wdt_running(void) | |
117 | { | |
118 | return ((bfin_read_WDOGB_CTL() & WDEN_MASK) != WDEN_DISABLE); | |
119 | } | |
120 | ||
121 | static inline int nmi_wdt_set_timeout(unsigned long t) | |
122 | { | |
123 | u32 cnt, max_t, sclk; | |
124 | int run; | |
125 | ||
126 | sclk = get_sclk(); | |
127 | max_t = -1 / sclk; | |
128 | cnt = t * sclk; | |
129 | if (t > max_t) { | |
130 | pr_warning("NMI: timeout value is too large\n"); | |
131 | return -EINVAL; | |
132 | } | |
133 | ||
134 | run = nmi_wdt_running(); | |
135 | nmi_wdt_stop(); | |
136 | bfin_write_WDOGB_CNT(cnt); | |
137 | if (run) | |
138 | nmi_wdt_start(); | |
139 | ||
140 | timeout = t; | |
141 | ||
142 | return 0; | |
143 | } | |
144 | ||
145 | int check_nmi_wdt_touched(void) | |
146 | { | |
147 | unsigned int this_cpu = smp_processor_id(); | |
148 | unsigned int cpu; | |
fecedc80 | 149 | cpumask_t mask; |
60ffdb36 | 150 | |
fecedc80 | 151 | cpumask_copy(&mask, cpu_online_mask); |
60ffdb36 GY |
152 | if (!atomic_read(&nmi_touched[this_cpu])) |
153 | return 0; | |
154 | ||
155 | atomic_set(&nmi_touched[this_cpu], 0); | |
156 | ||
fecedc80 KM |
157 | cpumask_clear_cpu(this_cpu, &mask); |
158 | for_each_cpu(cpu, &mask) { | |
60ffdb36 GY |
159 | invalidate_dcache_range((unsigned long)(&nmi_touched[cpu]), |
160 | (unsigned long)(&nmi_touched[cpu])); | |
161 | if (!atomic_read(&nmi_touched[cpu])) | |
162 | return 0; | |
163 | atomic_set(&nmi_touched[cpu], 0); | |
164 | } | |
165 | ||
166 | return 1; | |
167 | } | |
168 | ||
e99e88a9 | 169 | static void nmi_wdt_timer(struct timer_list *unused) |
60ffdb36 GY |
170 | { |
171 | if (check_nmi_wdt_touched()) | |
172 | nmi_wdt_keepalive(); | |
173 | ||
174 | mod_timer(&ntimer, jiffies + NMI_CHECK_TIMEOUT); | |
175 | } | |
176 | ||
177 | static int __init init_nmi_wdt(void) | |
178 | { | |
179 | nmi_wdt_set_timeout(timeout); | |
180 | nmi_wdt_start(); | |
181 | nmi_active = true; | |
182 | ||
e99e88a9 | 183 | timer_setup(&ntimer, nmi_wdt_timer, 0); |
60ffdb36 GY |
184 | ntimer.expires = jiffies + NMI_CHECK_TIMEOUT; |
185 | add_timer(&ntimer); | |
186 | ||
187 | pr_info("nmi_wdt: initialized: timeout=%d sec\n", timeout); | |
188 | return 0; | |
189 | } | |
190 | device_initcall(init_nmi_wdt); | |
191 | ||
f2e0cff8 | 192 | void arch_touch_nmi_watchdog(void) |
60ffdb36 GY |
193 | { |
194 | atomic_set(&nmi_touched[smp_processor_id()], 1); | |
195 | } | |
196 | ||
197 | /* Suspend/resume support */ | |
198 | #ifdef CONFIG_PM | |
67f9cbf9 | 199 | static int nmi_wdt_suspend(void) |
60ffdb36 GY |
200 | { |
201 | nmi_wdt_stop(); | |
202 | return 0; | |
203 | } | |
204 | ||
67f9cbf9 | 205 | static void nmi_wdt_resume(void) |
60ffdb36 GY |
206 | { |
207 | if (nmi_active) | |
208 | nmi_wdt_start(); | |
60ffdb36 GY |
209 | } |
210 | ||
67f9cbf9 | 211 | static struct syscore_ops nmi_syscore_ops = { |
60ffdb36 GY |
212 | .resume = nmi_wdt_resume, |
213 | .suspend = nmi_wdt_suspend, | |
214 | }; | |
215 | ||
67f9cbf9 | 216 | static int __init init_nmi_wdt_syscore(void) |
60ffdb36 | 217 | { |
67f9cbf9 RW |
218 | if (nmi_active) |
219 | register_syscore_ops(&nmi_syscore_ops); | |
60ffdb36 | 220 | |
67f9cbf9 | 221 | return 0; |
60ffdb36 | 222 | } |
67f9cbf9 | 223 | late_initcall(init_nmi_wdt_syscore); |
60ffdb36 GY |
224 | |
225 | #endif /* CONFIG_PM */ | |
226 | ||
227 | ||
228 | asmlinkage notrace void do_nmi(struct pt_regs *fp) | |
229 | { | |
230 | unsigned int cpu = smp_processor_id(); | |
231 | nmi_enter(); | |
232 | ||
233 | cpu_pda[cpu].__nmi_count += 1; | |
234 | ||
235 | if (cpu == nmi_wdt_cpu) { | |
236 | /* CoreB goes here first */ | |
237 | ||
238 | /* reload the WDOG_STAT */ | |
239 | nmi_wdt_keepalive(); | |
240 | ||
241 | /* clear nmi interrupt for CoreB */ | |
242 | nmi_wdt_stop(); | |
243 | nmi_wdt_clear(); | |
244 | ||
245 | /* trigger NMI interrupt of CoreA */ | |
246 | send_corea_nmi(); | |
247 | ||
248 | /* waiting CoreB to enter NMI */ | |
249 | wait_nmi_event(COREA_ENTER_NMI); | |
250 | ||
251 | /* recover WDOGA's settings */ | |
252 | restore_corea_nmi(); | |
253 | ||
254 | save_corelock(); | |
255 | ||
256 | /* corelock is save/cleared, CoreA is dummping messages */ | |
257 | ||
258 | wait_nmi_event(COREA_EXIT_NMI); | |
259 | } else { | |
260 | /* OK, CoreA entered NMI */ | |
261 | set_nmi_event(COREA_ENTER_NMI); | |
262 | } | |
263 | ||
264 | pr_emerg("\nNMI Watchdog detected LOCKUP, dump for CPU %d\n", cpu); | |
265 | dump_bfin_process(fp); | |
266 | dump_bfin_mem(fp); | |
267 | show_regs(fp); | |
268 | dump_bfin_trace_buffer(); | |
269 | show_stack(current, (unsigned long *)fp); | |
270 | ||
271 | if (cpu == nmi_wdt_cpu) { | |
272 | pr_emerg("This fault is not recoverable, sorry!\n"); | |
273 | ||
274 | /* CoreA dump finished, restore the corelock */ | |
275 | restore_corelock(); | |
276 | ||
277 | set_nmi_event(COREB_EXIT_NMI); | |
278 | } else { | |
279 | /* CoreB dump finished, notice the CoreA we are done */ | |
280 | set_nmi_event(COREA_EXIT_NMI); | |
281 | ||
282 | /* synchronize with CoreA */ | |
283 | wait_nmi_event(COREB_EXIT_NMI); | |
284 | } | |
285 | ||
286 | nmi_exit(); | |
287 | } |