[mirror_ubuntu-bionic-kernel.git] / arch / blackfin / kernel / process.c

/*
 * Blackfin architecture-dependent process handling
 *
 * Copyright 2004-2009 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later
 */

#include <linux/module.h>
#include <linux/unistd.h>
#include <linux/user.h>
#include <linux/uaccess.h>
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/tick.h>
#include <linux/fs.h>
#include <linux/err.h>

#include <asm/blackfin.h>
#include <asm/fixed_code.h>
#include <asm/mem_map.h>
#include <asm/irq.h>

asmlinkage void ret_from_fork(void);

/* Points to the SDRAM backup memory for the stack that is currently in
 * L1 scratchpad memory.
 */
void *current_l1_stack_save;

/* The number of tasks currently using a L1 stack area.  The SRAM is
 * allocated/deallocated whenever this changes from/to zero.
 */
int nr_l1stack_tasks;

/* Start and length of the area in L1 scratchpad memory which we've allocated
 * for process stacks.
 */
void *l1_stack_base;
unsigned long l1_stack_len;

void (*pm_power_off)(void) = NULL;
EXPORT_SYMBOL(pm_power_off);

/*
 * The idle loop on BFIN
 */
#ifdef CONFIG_IDLE_L1
void arch_cpu_idle(void)__attribute__((l1_text));
#endif

/*
 * This is our default idle handler.  We need to disable
 * interrupts here to ensure we don't miss a wakeup call.
 */
void arch_cpu_idle(void)
{
#ifdef CONFIG_IPIPE
	ipipe_suspend_domain();
#endif
	hard_local_irq_disable();
	if (!need_resched())
		idle_with_irq_disabled();

	hard_local_irq_enable();
}

#ifdef CONFIG_HOTPLUG_CPU
void arch_cpu_idle_dead(void)
{
	cpu_die();
}
#endif

/*
 * Do necessary setup to start up a newly executed thread.
 *
 * pass the data segment into user programs if it exists,
 * it can't hurt anything as far as I can tell
 */
void start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
{
	regs->pc = new_ip;
	if (current->mm)
		regs->p5 = current->mm->start_data;
#ifndef CONFIG_SMP
	task_thread_info(current)->l1_task_info.stack_start =
		(void *)current->mm->context.stack_start;
	task_thread_info(current)->l1_task_info.lowest_sp = (void *)new_sp;
	memcpy(L1_SCRATCH_TASK_INFO, &task_thread_info(current)->l1_task_info,
	       sizeof(*L1_SCRATCH_TASK_INFO));
#endif
	wrusp(new_sp);
}
EXPORT_SYMBOL_GPL(start_thread);

void flush_thread(void)
{
}

asmlinkage int bfin_clone(unsigned long clone_flags, unsigned long newsp)
{
#ifdef __ARCH_SYNC_CORE_DCACHE
	if (current->nr_cpus_allowed == num_possible_cpus())
		set_cpus_allowed_ptr(current, cpumask_of(smp_processor_id()));
#endif
	if (newsp)
		newsp -= 12;
	return do_fork(clone_flags, newsp, 0, NULL, NULL);
}

int
copy_thread(unsigned long clone_flags,
	    unsigned long usp, unsigned long topstk,
	    struct task_struct *p)
{
	struct pt_regs *childregs;
	unsigned long *v;

	childregs = (struct pt_regs *) (task_stack_page(p) + THREAD_SIZE) - 1;
	v = ((unsigned long *)childregs) - 2;
	if (unlikely(p->flags & PF_KTHREAD)) {
		memset(childregs, 0, sizeof(struct pt_regs));
		v[0] = usp;
		v[1] = topstk;
		childregs->orig_p0 = -1;
		childregs->ipend = 0x8000;
		__asm__ __volatile__("%0 = syscfg;":"=da"(childregs->syscfg):);
		p->thread.usp = 0;
	} else {
		*childregs = *current_pt_regs();
		childregs->r0 = 0;
		p->thread.usp = usp ? : rdusp();
		v[0] = v[1] = 0;
	}

	p->thread.ksp = (unsigned long)v;
	p->thread.pc = (unsigned long)ret_from_fork;

	return 0;
}

unsigned long get_wchan(struct task_struct *p)
{
	unsigned long fp, pc;
	unsigned long stack_page;
	int count = 0;
	if (!p || p == current || p->state == TASK_RUNNING)
		return 0;

	stack_page = (unsigned long)p;
	fp = p->thread.usp;
	do {
		if (fp < stack_page + sizeof(struct thread_info) ||
		    fp >= 8184 + stack_page)
			return 0;
		pc = ((unsigned long *)fp)[1];
		if (!in_sched_functions(pc))
			return pc;
		fp = *(unsigned long *)fp;
	}
	while (count++ < 16);
	return 0;
}

void finish_atomic_sections (struct pt_regs *regs)
{
	int __user *up0 = (int __user *)regs->p0;

	switch (regs->pc) {
	default:
		/* not in middle of an atomic step, so resume like normal */
		return;

	case ATOMIC_XCHG32 + 2:
		put_user(regs->r1, up0);
		break;

	case ATOMIC_CAS32 + 2:
	case ATOMIC_CAS32 + 4:
		if (regs->r0 == regs->r1)
	case ATOMIC_CAS32 + 6:
			put_user(regs->r2, up0);
		break;

	case ATOMIC_ADD32 + 2:
		regs->r0 = regs->r1 + regs->r0;
		/* fall through */
	case ATOMIC_ADD32 + 4:
		put_user(regs->r0, up0);
		break;

	case ATOMIC_SUB32 + 2:
		regs->r0 = regs->r1 - regs->r0;
		/* fall through */
	case ATOMIC_SUB32 + 4:
		put_user(regs->r0, up0);
		break;

	case ATOMIC_IOR32 + 2:
		regs->r0 = regs->r1 | regs->r0;
		/* fall through */
	case ATOMIC_IOR32 + 4:
		put_user(regs->r0, up0);
		break;

	case ATOMIC_AND32 + 2:
		regs->r0 = regs->r1 & regs->r0;
		/* fall through */
	case ATOMIC_AND32 + 4:
		put_user(regs->r0, up0);
		break;

	case ATOMIC_XOR32 + 2:
		regs->r0 = regs->r1 ^ regs->r0;
		/* fall through */
	case ATOMIC_XOR32 + 4:
		put_user(regs->r0, up0);
		break;
	}

	/*
	 * We've finished the atomic section, and the only thing left for
	 * userspace is to do a RTS, so we might as well handle that too
	 * since we need to update the PC anyways.
	 */
	regs->pc = regs->rets;
}

static inline
int in_mem(unsigned long addr, unsigned long size,
           unsigned long start, unsigned long end)
{
	return addr >= start && addr + size <= end;
}
static inline
int in_mem_const_off(unsigned long addr, unsigned long size, unsigned long off,
                     unsigned long const_addr, unsigned long const_size)
{
	return const_size &&
	       in_mem(addr, size, const_addr + off, const_addr + const_size);
}
static inline
int in_mem_const(unsigned long addr, unsigned long size,
                 unsigned long const_addr, unsigned long const_size)
{
	return in_mem_const_off(addr, size, 0, const_addr, const_size);
}
#ifdef CONFIG_BF60x
#define ASYNC_ENABLED(bnum, bctlnum)	1
#else
#define ASYNC_ENABLED(bnum, bctlnum) \
({ \
	(bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
	bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
	1; \
})
#endif
/*
 * We can't read EBIU banks that aren't enabled or we end up hanging
 * on the access to the async space.  Make sure we validate accesses
 * that cross async banks too.
 *	0 - found, but unusable
 *	1 - found & usable
 *	2 - not found
 */
static
int in_async(unsigned long addr, unsigned long size)
{
	if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) {
		if (!ASYNC_ENABLED(0, 0))
			return 0;
		if (addr + size <= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE)
			return 1;
		size -= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE - addr;
		addr = ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE;
	}
	if (addr >= ASYNC_BANK1_BASE && addr < ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE) {
		if (!ASYNC_ENABLED(1, 0))
			return 0;
		if (addr + size <= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE)
			return 1;
		size -= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE - addr;
		addr = ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE;
	}
	if (addr >= ASYNC_BANK2_BASE && addr < ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE) {
		if (!ASYNC_ENABLED(2, 1))
			return 0;
		if (addr + size <= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE)
			return 1;
		size -= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE - addr;
		addr = ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE;
	}
	if (addr >= ASYNC_BANK3_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
		if (ASYNC_ENABLED(3, 1))
			return 0;
		if (addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
			return 1;
		return 0;
	}

	/* not within async bounds */
	return 2;
}

int bfin_mem_access_type(unsigned long addr, unsigned long size)
{
	int cpu = raw_smp_processor_id();

	/* Check that things do not wrap around */
	if (addr > ULONG_MAX - size)
		return -EFAULT;

	if (in_mem(addr, size, FIXED_CODE_START, physical_mem_end))
		return BFIN_MEM_ACCESS_CORE;

	if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
		return cpu == 0 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
	if (in_mem_const(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH))
		return cpu == 0 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
	if (in_mem_const(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH))
		return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
	if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH))
		return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
#ifdef COREB_L1_CODE_START
	if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
		return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
	if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
		return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
	if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
		return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
	if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
		return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
#endif
	if (in_mem_const(addr, size, L2_START, L2_LENGTH))
		return BFIN_MEM_ACCESS_CORE;

	if (addr >= SYSMMR_BASE)
		return BFIN_MEM_ACCESS_CORE_ONLY;

	switch (in_async(addr, size)) {
	case 0: return -EFAULT;
	case 1: return BFIN_MEM_ACCESS_CORE;
	case 2: /* fall through */;
	}

	if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
		return BFIN_MEM_ACCESS_CORE;
	if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
		return BFIN_MEM_ACCESS_DMA;

	return -EFAULT;
}

#if defined(CONFIG_ACCESS_CHECK)
#ifdef CONFIG_ACCESS_OK_L1
__attribute__((l1_text))
#endif
/* Return 1 if access to memory range is OK, 0 otherwise */
int _access_ok(unsigned long addr, unsigned long size)
{
	int aret;

	if (size == 0)
		return 1;
	/* Check that things do not wrap around */
	if (addr > ULONG_MAX - size)
		return 0;
	if (segment_eq(get_fs(), KERNEL_DS))
		return 1;
#ifdef CONFIG_MTD_UCLINUX
	if (1)
#else
	if (0)
#endif
	{
		if (in_mem(addr, size, memory_start, memory_end))
			return 1;
		if (in_mem(addr, size, memory_mtd_end, physical_mem_end))
			return 1;
# ifndef CONFIG_ROMFS_ON_MTD
		if (0)
# endif
			/* For XIP, allow user space to use pointers within the ROMFS.  */
			if (in_mem(addr, size, memory_mtd_start, memory_mtd_end))
				return 1;
	} else {
		if (in_mem(addr, size, memory_start, physical_mem_end))
			return 1;
	}

	if (in_mem(addr, size, (unsigned long)__init_begin, (unsigned long)__init_end))
		return 1;

	if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
		return 1;
	if (in_mem_const_off(addr, size, _etext_l1 - _stext_l1, L1_CODE_START, L1_CODE_LENGTH))
		return 1;
	if (in_mem_const_off(addr, size, _ebss_l1 - _sdata_l1, L1_DATA_A_START, L1_DATA_A_LENGTH))
		return 1;
	if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH))
		return 1;
#ifdef COREB_L1_CODE_START
	if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
		return 1;
	if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
		return 1;
	if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
		return 1;
	if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
		return 1;
#endif

#ifndef CONFIG_EXCEPTION_L1_SCRATCH
	if (in_mem_const(addr, size, (unsigned long)l1_stack_base, l1_stack_len))
		return 1;
#endif

	aret = in_async(addr, size);
	if (aret < 2)
		return aret;

	if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH))
		return 1;

	if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
		return 1;
	if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
		return 1;

	return 0;
}
EXPORT_SYMBOL(_access_ok);
#endif /* CONFIG_ACCESS_CHECK */
Commit	Line	Data
1394f032	1	/*
96f1050d	2	* Blackfin architecture-dependent process handling
1394f032	3	*
96f1050d	4	* Copyright 2004-2009 Analog Devices Inc.
1394f032	5	*
96f1050d	6	* Licensed under the GPL-2 or later
1394f032 BW	7	*/
	8
	9	#include <linux/module.h>
1394f032 BW	10	#include <linux/unistd.h>
1394f032 BW	11	#include <linux/user.h>
1f83b8f1	12	#include <linux/uaccess.h>
5a0e3ad6	13	#include <linux/slab.h>
8b5f79f9 VM	14	#include <linux/sched.h>
8b5f79f9 VM	15	#include <linux/tick.h>
d31c5ab1 BW	16	#include <linux/fs.h>
d31c5ab1 BW	17	#include <linux/err.h>
1394f032 BW	18
1394f032 BW	19	#include <asm/blackfin.h>
7adfb58f	20	#include <asm/fixed_code.h>
dbc895f9	21	#include <asm/mem_map.h>
3bed8d67	22	#include <asm/irq.h>
1394f032	23
1394f032 BW	24	asmlinkage void ret_from_fork(void);
	25
	26	/* Points to the SDRAM backup memory for the stack that is currently in
	27	* L1 scratchpad memory.
	28	*/
	29	void *current_l1_stack_save;
	30
	31	/* The number of tasks currently using a L1 stack area. The SRAM is
	32	* allocated/deallocated whenever this changes from/to zero.
	33	*/
	34	int nr_l1stack_tasks;
	35
	36	/* Start and length of the area in L1 scratchpad memory which we've allocated
	37	* for process stacks.
	38	*/
	39	void *l1_stack_base;
	40	unsigned long l1_stack_len;
	41
1394f032 BW	42	void (*pm_power_off)(void) = NULL;
	43	EXPORT_SYMBOL(pm_power_off);
	44
1394f032 BW	45	/*
	46	* The idle loop on BFIN
	47	*/
	48	#ifdef CONFIG_IDLE_L1
25d67f86	49	void arch_cpu_idle(void)__attribute__((l1_text));
1394f032 BW	50	#endif
1394f032 BW	51
8b5f79f9 VM	52	/*
	53	* This is our default idle handler. We need to disable
	54	* interrupts here to ensure we don't miss a wakeup call.
	55	*/
25d67f86	56	void arch_cpu_idle(void)
1394f032	57	{
6a01f230 YL	58	#ifdef CONFIG_IPIPE
	59	ipipe_suspend_domain();
	60	#endif
3b139cdb	61	hard_local_irq_disable();
8b5f79f9 VM	62	if (!need_resched())
8b5f79f9 VM	63	idle_with_irq_disabled();
1394f032	64
3b139cdb	65	hard_local_irq_enable();
8b5f79f9	66	}
1394f032	67
59f0eaaa	68	#ifdef CONFIG_HOTPLUG_CPU
25d67f86	69	void arch_cpu_idle_dead(void)
1394f032	70	{
25d67f86	71	cpu_die();
1394f032	72	}
25d67f86	73	#endif
1394f032	74
d5ce528c MF	75	/*
	76	* Do necessary setup to start up a newly executed thread.
	77	*
	78	* pass the data segment into user programs if it exists,
	79	* it can't hurt anything as far as I can tell
	80	*/
	81	void start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
	82	{
d5ce528c MF	83	regs->pc = new_ip;
	84	if (current->mm)
	85	regs->p5 = current->mm->start_data;
aa23531c	86	#ifndef CONFIG_SMP
d5ce528c MF	87	task_thread_info(current)->l1_task_info.stack_start =
	88	(void *)current->mm->context.stack_start;
	89	task_thread_info(current)->l1_task_info.lowest_sp = (void *)new_sp;
	90	memcpy(L1_SCRATCH_TASK_INFO, &task_thread_info(current)->l1_task_info,
	91	sizeof(*L1_SCRATCH_TASK_INFO));
	92	#endif
	93	wrusp(new_sp);
	94	}
	95	EXPORT_SYMBOL_GPL(start_thread);
	96
1394f032 BW	97	void flush_thread(void)
	98	{
	99	}
	100
135c37b8	101	asmlinkage int bfin_clone(unsigned long clone_flags, unsigned long newsp)
1394f032	102	{
8f65873e	103	#ifdef __ARCH_SYNC_CORE_DCACHE
29baa747	104	if (current->nr_cpus_allowed == num_possible_cpus())
e887eb61	105	set_cpus_allowed_ptr(current, cpumask_of(smp_processor_id()));
8f65873e	106	#endif
135c37b8	107	if (newsp)
1394f032	108	newsp -= 12;
e80d6661	109	return do_fork(clone_flags, newsp, 0, NULL, NULL);
1394f032 BW	110	}
	111
	112	int
6f2c55b8	113	copy_thread(unsigned long clone_flags,
1394f032	114	unsigned long usp, unsigned long topstk,
afa86fc4	115	struct task_struct *p)
1394f032 BW	116	{
1394f032 BW	117	struct pt_regs *childregs;
ee1e17c6	118	unsigned long *v;
1394f032 BW	119
1394f032 BW	120	childregs = (struct pt_regs *) (task_stack_page(p) + THREAD_SIZE) - 1;
ee1e17c6	121	v = ((unsigned long *)childregs) - 2;
afa86fc4	122	if (unlikely(p->flags & PF_KTHREAD)) {
ee1e17c6 AV	123	memset(childregs, 0, sizeof(struct pt_regs));
	124	v[0] = usp;
	125	v[1] = topstk;
	126	childregs->orig_p0 = -1;
	127	childregs->ipend = 0x8000;
	128	__asm__ __volatile__("%0 = syscfg;":"=da"(childregs->syscfg):);
	129	p->thread.usp = 0;
	130	} else {
afa86fc4	131	childregs = current_pt_regs();
ee1e17c6	132	childregs->r0 = 0;
135c37b8	133	p->thread.usp = usp ? : rdusp();
ee1e17c6 AV	134	v[0] = v[1] = 0;
ee1e17c6 AV	135	}
1394f032	136
ee1e17c6	137	p->thread.ksp = (unsigned long)v;
1394f032 BW	138	p->thread.pc = (unsigned long)ret_from_fork;
	139
	140	return 0;
	141	}
	142
1394f032 BW	143	unsigned long get_wchan(struct task_struct *p)
	144	{
	145	unsigned long fp, pc;
	146	unsigned long stack_page;
	147	int count = 0;
	148	if (!p \|\| p == current \|\| p->state == TASK_RUNNING)
	149	return 0;
	150
	151	stack_page = (unsigned long)p;
	152	fp = p->thread.usp;
	153	do {
	154	if (fp < stack_page + sizeof(struct thread_info) \|\|
	155	fp >= 8184 + stack_page)
	156	return 0;
	157	pc = ((unsigned long *)fp)[1];
	158	if (!in_sched_functions(pc))
	159	return pc;
	160	fp = (unsigned long )fp;
	161	}
	162	while (count++ < 16);
	163	return 0;
	164	}
	165
7adfb58f BS	166	void finish_atomic_sections (struct pt_regs *regs)
7adfb58f BS	167	{
19d6d7d5	168	int __user up0 = (int __user )regs->p0;
0ddeeca2	169
7adfb58f	170	switch (regs->pc) {
2f5a0864 MF	171	default:
	172	/* not in middle of an atomic step, so resume like normal */
	173	return;
	174
7adfb58f	175	case ATOMIC_XCHG32 + 2:
0ddeeca2	176	put_user(regs->r1, up0);
7adfb58f BS	177	break;
	178
	179	case ATOMIC_CAS32 + 2:
	180	case ATOMIC_CAS32 + 4:
	181	if (regs->r0 == regs->r1)
92649494	182	case ATOMIC_CAS32 + 6:
0ddeeca2	183	put_user(regs->r2, up0);
7adfb58f	184	break;
7adfb58f BS	185
	186	case ATOMIC_ADD32 + 2:
	187	regs->r0 = regs->r1 + regs->r0;
	188	/* fall through */
	189	case ATOMIC_ADD32 + 4:
0ddeeca2	190	put_user(regs->r0, up0);
7adfb58f BS	191	break;
	192
	193	case ATOMIC_SUB32 + 2:
	194	regs->r0 = regs->r1 - regs->r0;
	195	/* fall through */
	196	case ATOMIC_SUB32 + 4:
0ddeeca2	197	put_user(regs->r0, up0);
7adfb58f BS	198	break;
	199
	200	case ATOMIC_IOR32 + 2:
	201	regs->r0 = regs->r1 \| regs->r0;
	202	/* fall through */
	203	case ATOMIC_IOR32 + 4:
0ddeeca2	204	put_user(regs->r0, up0);
7adfb58f BS	205	break;
	206
	207	case ATOMIC_AND32 + 2:
	208	regs->r0 = regs->r1 & regs->r0;
	209	/* fall through */
	210	case ATOMIC_AND32 + 4:
0ddeeca2	211	put_user(regs->r0, up0);
7adfb58f BS	212	break;
	213
	214	case ATOMIC_XOR32 + 2:
	215	regs->r0 = regs->r1 ^ regs->r0;
	216	/* fall through */
	217	case ATOMIC_XOR32 + 4:
0ddeeca2	218	put_user(regs->r0, up0);
7adfb58f BS	219	break;
7adfb58f BS	220	}
2f5a0864 MF	221
	222	/*
	223	* We've finished the atomic section, and the only thing left for
	224	* userspace is to do a RTS, so we might as well handle that too
	225	* since we need to update the PC anyways.
	226	*/
	227	regs->pc = regs->rets;
7adfb58f BS	228	}
7adfb58f BS	229
e56e03b0 MF	230	static inline
	231	int in_mem(unsigned long addr, unsigned long size,
	232	unsigned long start, unsigned long end)
	233	{
	234	return addr >= start && addr + size <= end;
	235	}
	236	static inline
	237	int in_mem_const_off(unsigned long addr, unsigned long size, unsigned long off,
	238	unsigned long const_addr, unsigned long const_size)
	239	{
	240	return const_size &&
	241	in_mem(addr, size, const_addr + off, const_addr + const_size);
	242	}
	243	static inline
	244	int in_mem_const(unsigned long addr, unsigned long size,
	245	unsigned long const_addr, unsigned long const_size)
	246	{
fb4b5d3a	247	return in_mem_const_off(addr, size, 0, const_addr, const_size);
e56e03b0	248	}
b5affb01 BL	249	#ifdef CONFIG_BF60x
	250	#define ASYNC_ENABLED(bnum, bctlnum) 1
	251	#else
13048f88	252	#define ASYNC_ENABLED(bnum, bctlnum) \
e56e03b0	253	({ \
13048f88 BS	254	(bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
	255	bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
	256	1; \
e56e03b0	257	})
b5affb01	258	#endif
13048f88 BS	259	/*
	260	* We can't read EBIU banks that aren't enabled or we end up hanging
	261	* on the access to the async space. Make sure we validate accesses
	262	* that cross async banks too.
	263	* 0 - found, but unusable
	264	* 1 - found & usable
	265	* 2 - not found
	266	*/
	267	static
	268	int in_async(unsigned long addr, unsigned long size)
	269	{
	270	if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) {
	271	if (!ASYNC_ENABLED(0, 0))
	272	return 0;
	273	if (addr + size <= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE)
	274	return 1;
	275	size -= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE - addr;
	276	addr = ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE;
	277	}
	278	if (addr >= ASYNC_BANK1_BASE && addr < ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE) {
	279	if (!ASYNC_ENABLED(1, 0))
	280	return 0;
	281	if (addr + size <= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE)
	282	return 1;
	283	size -= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE - addr;
	284	addr = ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE;
	285	}
	286	if (addr >= ASYNC_BANK2_BASE && addr < ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE) {
	287	if (!ASYNC_ENABLED(2, 1))
	288	return 0;
	289	if (addr + size <= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE)
	290	return 1;
	291	size -= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE - addr;
	292	addr = ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE;
	293	}
	294	if (addr >= ASYNC_BANK3_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
	295	if (ASYNC_ENABLED(3, 1))
	296	return 0;
	297	if (addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
	298	return 1;
	299	return 0;
	300	}
	301
	302	/* not within async bounds */
	303	return 2;
	304	}
e56e03b0 MF	305
	306	int bfin_mem_access_type(unsigned long addr, unsigned long size)
	307	{
	308	int cpu = raw_smp_processor_id();
	309
	310	/* Check that things do not wrap around */
	311	if (addr > ULONG_MAX - size)
	312	return -EFAULT;
	313
	314	if (in_mem(addr, size, FIXED_CODE_START, physical_mem_end))
	315	return BFIN_MEM_ACCESS_CORE;
	316
	317	if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
	318	return cpu == 0 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
	319	if (in_mem_const(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH))
	320	return cpu == 0 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
	321	if (in_mem_const(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH))
	322	return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
	323	if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH))
	324	return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
	325	#ifdef COREB_L1_CODE_START
fb4b5d3a	326	if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
e56e03b0 MF	327	return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
	328	if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
	329	return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
fb4b5d3a	330	if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
e56e03b0	331	return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
fb4b5d3a	332	if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
e56e03b0 MF	333	return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
	334	#endif
	335	if (in_mem_const(addr, size, L2_START, L2_LENGTH))
	336	return BFIN_MEM_ACCESS_CORE;
	337
	338	if (addr >= SYSMMR_BASE)
	339	return BFIN_MEM_ACCESS_CORE_ONLY;
	340
13048f88 BS	341	switch (in_async(addr, size)) {
	342	case 0: return -EFAULT;
	343	case 1: return BFIN_MEM_ACCESS_CORE;
	344	case 2: /* fall through */;
	345	}
e56e03b0 MF	346
	347	if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
	348	return BFIN_MEM_ACCESS_CORE;
	349	if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
	350	return BFIN_MEM_ACCESS_DMA;
	351
	352	return -EFAULT;
	353	}
	354
1394f032	355	#if defined(CONFIG_ACCESS_CHECK)
a43b739f MF	356	#ifdef CONFIG_ACCESS_OK_L1
	357	__attribute__((l1_text))
	358	#endif
b03b08ba	359	/* Return 1 if access to memory range is OK, 0 otherwise */
1394f032 BW	360	int _access_ok(unsigned long addr, unsigned long size)
1394f032 BW	361	{
13048f88 BS	362	int aret;
13048f88 BS	363
bc41bb11 BS	364	if (size == 0)
bc41bb11 BS	365	return 1;
e56e03b0 MF	366	/* Check that things do not wrap around */
e56e03b0 MF	367	if (addr > ULONG_MAX - size)
1394f032	368	return 0;
1f83b8f1	369	if (segment_eq(get_fs(), KERNEL_DS))
1394f032 BW	370	return 1;
1394f032 BW	371	#ifdef CONFIG_MTD_UCLINUX
e56e03b0 MF	372	if (1)
	373	#else
	374	if (0)
	375	#endif
	376	{
	377	if (in_mem(addr, size, memory_start, memory_end))
	378	return 1;
	379	if (in_mem(addr, size, memory_mtd_end, physical_mem_end))
	380	return 1;
	381	# ifndef CONFIG_ROMFS_ON_MTD
	382	if (0)
	383	# endif
	384	/* For XIP, allow user space to use pointers within the ROMFS. */
	385	if (in_mem(addr, size, memory_mtd_start, memory_mtd_end))
	386	return 1;
	387	} else {
	388	if (in_mem(addr, size, memory_start, physical_mem_end))
	389	return 1;
	390	}
	391
	392	if (in_mem(addr, size, (unsigned long)__init_begin, (unsigned long)__init_end))
1394f032	393	return 1;
d5adb029	394
e56e03b0	395	if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
d5adb029	396	return 1;
e56e03b0	397	if (in_mem_const_off(addr, size, _etext_l1 - _stext_l1, L1_CODE_START, L1_CODE_LENGTH))
1394f032	398	return 1;
e56e03b0	399	if (in_mem_const_off(addr, size, _ebss_l1 - _sdata_l1, L1_DATA_A_START, L1_DATA_A_LENGTH))
1394f032	400	return 1;
e56e03b0	401	if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH))
1394f032	402	return 1;
e56e03b0	403	#ifdef COREB_L1_CODE_START
fb4b5d3a	404	if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
1394f032	405	return 1;
e56e03b0	406	if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
1394f032	407	return 1;
fb4b5d3a	408	if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
1394f032	409	return 1;
fb4b5d3a	410	if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
b2c2f303	411	return 1;
1394f032	412	#endif
13048f88	413
41c3e334 BS	414	#ifndef CONFIG_EXCEPTION_L1_SCRATCH
	415	if (in_mem_const(addr, size, (unsigned long)l1_stack_base, l1_stack_len))
	416	return 1;
	417	#endif
	418
13048f88 BS	419	aret = in_async(addr, size);
	420	if (aret < 2)
	421	return aret;
	422
e56e03b0 MF	423	if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH))
	424	return 1;
	425
	426	if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
	427	return 1;
	428	if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
	429	return 1;
	430
1394f032 BW	431	return 0;
	432	}
	433	EXPORT_SYMBOL(_access_ok);
	434	#endif /* CONFIG_ACCESS_CHECK */