[mirror_ubuntu-bionic-kernel.git] / arch / blackfin / kernel / process.c

/*
 * Blackfin architecture-dependent process handling
 *
 * Copyright 2004-2009 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later
 */

#include <linux/module.h>
#include <linux/unistd.h>
#include <linux/user.h>
#include <linux/uaccess.h>
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/sched/debug.h>
#include <linux/sched/task.h>
#include <linux/tick.h>
#include <linux/fs.h>
#include <linux/err.h>

#include <asm/blackfin.h>
#include <asm/fixed_code.h>
#include <asm/mem_map.h>
#include <asm/irq.h>

asmlinkage void ret_from_fork(void);

/* Points to the SDRAM backup memory for the stack that is currently in
 * L1 scratchpad memory.
 */
void *current_l1_stack_save;

/* The number of tasks currently using a L1 stack area.  The SRAM is
 * allocated/deallocated whenever this changes from/to zero.
 */
int nr_l1stack_tasks;

/* Start and length of the area in L1 scratchpad memory which we've allocated
 * for process stacks.
 */
void *l1_stack_base;
unsigned long l1_stack_len;

void (*pm_power_off)(void) = NULL;
EXPORT_SYMBOL(pm_power_off);

/*
 * The idle loop on BFIN
 */
#ifdef CONFIG_IDLE_L1
void arch_cpu_idle(void)__attribute__((l1_text));
#endif

/*
 * This is our default idle handler.  We need to disable
 * interrupts here to ensure we don't miss a wakeup call.
 */
void arch_cpu_idle(void)
{
#ifdef CONFIG_IPIPE
	ipipe_suspend_domain();
#endif
	hard_local_irq_disable();
	if (!need_resched())
		idle_with_irq_disabled();

	hard_local_irq_enable();
}

#ifdef CONFIG_HOTPLUG_CPU
void arch_cpu_idle_dead(void)
{
	cpu_die();
}
#endif

/*
 * Do necessary setup to start up a newly executed thread.
 *
 * pass the data segment into user programs if it exists,
 * it can't hurt anything as far as I can tell
 */
void start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
{
	regs->pc = new_ip;
	if (current->mm)
		regs->p5 = current->mm->start_data;
#ifndef CONFIG_SMP
	task_thread_info(current)->l1_task_info.stack_start =
		(void *)current->mm->context.stack_start;
	task_thread_info(current)->l1_task_info.lowest_sp = (void *)new_sp;
	memcpy(L1_SCRATCH_TASK_INFO, &task_thread_info(current)->l1_task_info,
	       sizeof(*L1_SCRATCH_TASK_INFO));
#endif
	wrusp(new_sp);
}
EXPORT_SYMBOL_GPL(start_thread);

void flush_thread(void)
{
}

asmlinkage int bfin_clone(unsigned long clone_flags, unsigned long newsp)
{
#ifdef __ARCH_SYNC_CORE_DCACHE
	if (current->nr_cpus_allowed == num_possible_cpus())
		set_cpus_allowed_ptr(current, cpumask_of(smp_processor_id()));
#endif
	if (newsp)
		newsp -= 12;
	return do_fork(clone_flags, newsp, 0, NULL, NULL);
}

int
copy_thread(unsigned long clone_flags,
	    unsigned long usp, unsigned long topstk,
	    struct task_struct *p)
{
	struct pt_regs *childregs;
	unsigned long *v;

	childregs = (struct pt_regs *) (task_stack_page(p) + THREAD_SIZE) - 1;
	v = ((unsigned long *)childregs) - 2;
	if (unlikely(p->flags & PF_KTHREAD)) {
		memset(childregs, 0, sizeof(struct pt_regs));
		v[0] = usp;
		v[1] = topstk;
		childregs->orig_p0 = -1;
		childregs->ipend = 0x8000;
		__asm__ __volatile__("%0 = syscfg;":"=da"(childregs->syscfg):);
		p->thread.usp = 0;
	} else {
		*childregs = *current_pt_regs();
		childregs->r0 = 0;
		p->thread.usp = usp ? : rdusp();
		v[0] = v[1] = 0;
	}

	p->thread.ksp = (unsigned long)v;
	p->thread.pc = (unsigned long)ret_from_fork;

	return 0;
}

unsigned long get_wchan(struct task_struct *p)
{
	unsigned long fp, pc;
	unsigned long stack_page;
	int count = 0;
	if (!p || p == current || p->state == TASK_RUNNING)
		return 0;

	stack_page = (unsigned long)p;
	fp = p->thread.usp;
	do {
		if (fp < stack_page + sizeof(struct thread_info) ||
		    fp >= 8184 + stack_page)
			return 0;
		pc = ((unsigned long *)fp)[1];
		if (!in_sched_functions(pc))
			return pc;
		fp = *(unsigned long *)fp;
	}
	while (count++ < 16);
	return 0;
}

void finish_atomic_sections (struct pt_regs *regs)
{
	int __user *up0 = (int __user *)regs->p0;

	switch (regs->pc) {
	default:
		/* not in middle of an atomic step, so resume like normal */
		return;

	case ATOMIC_XCHG32 + 2:
		put_user(regs->r1, up0);
		break;

	case ATOMIC_CAS32 + 2:
	case ATOMIC_CAS32 + 4:
		if (regs->r0 == regs->r1)
	case ATOMIC_CAS32 + 6:
			put_user(regs->r2, up0);
		break;

	case ATOMIC_ADD32 + 2:
		regs->r0 = regs->r1 + regs->r0;
		/* fall through */
	case ATOMIC_ADD32 + 4:
		put_user(regs->r0, up0);
		break;

	case ATOMIC_SUB32 + 2:
		regs->r0 = regs->r1 - regs->r0;
		/* fall through */
	case ATOMIC_SUB32 + 4:
		put_user(regs->r0, up0);
		break;

	case ATOMIC_IOR32 + 2:
		regs->r0 = regs->r1 | regs->r0;
		/* fall through */
	case ATOMIC_IOR32 + 4:
		put_user(regs->r0, up0);
		break;

	case ATOMIC_AND32 + 2:
		regs->r0 = regs->r1 & regs->r0;
		/* fall through */
	case ATOMIC_AND32 + 4:
		put_user(regs->r0, up0);
		break;

	case ATOMIC_XOR32 + 2:
		regs->r0 = regs->r1 ^ regs->r0;
		/* fall through */
	case ATOMIC_XOR32 + 4:
		put_user(regs->r0, up0);
		break;
	}

	/*
	 * We've finished the atomic section, and the only thing left for
	 * userspace is to do a RTS, so we might as well handle that too
	 * since we need to update the PC anyways.
	 */
	regs->pc = regs->rets;
}

static inline
int in_mem(unsigned long addr, unsigned long size,
           unsigned long start, unsigned long end)
{
	return addr >= start && addr + size <= end;
}
static inline
int in_mem_const_off(unsigned long addr, unsigned long size, unsigned long off,
                     unsigned long const_addr, unsigned long const_size)
{
	return const_size &&
	       in_mem(addr, size, const_addr + off, const_addr + const_size);
}
static inline
int in_mem_const(unsigned long addr, unsigned long size,
                 unsigned long const_addr, unsigned long const_size)
{
	return in_mem_const_off(addr, size, 0, const_addr, const_size);
}
#ifdef CONFIG_BF60x
#define ASYNC_ENABLED(bnum, bctlnum)	1
#else
#define ASYNC_ENABLED(bnum, bctlnum) \
({ \
	(bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
	bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
	1; \
})
#endif
/*
 * We can't read EBIU banks that aren't enabled or we end up hanging
 * on the access to the async space.  Make sure we validate accesses
 * that cross async banks too.
 *	0 - found, but unusable
 *	1 - found & usable
 *	2 - not found
 */
static
int in_async(unsigned long addr, unsigned long size)
{
	if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) {
		if (!ASYNC_ENABLED(0, 0))
			return 0;
		if (addr + size <= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE)
			return 1;
		size -= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE - addr;
		addr = ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE;
	}
	if (addr >= ASYNC_BANK1_BASE && addr < ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE) {
		if (!ASYNC_ENABLED(1, 0))
			return 0;
		if (addr + size <= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE)
			return 1;
		size -= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE - addr;
		addr = ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE;
	}
	if (addr >= ASYNC_BANK2_BASE && addr < ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE) {
		if (!ASYNC_ENABLED(2, 1))
			return 0;
		if (addr + size <= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE)
			return 1;
		size -= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE - addr;
		addr = ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE;
	}
	if (addr >= ASYNC_BANK3_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
		if (ASYNC_ENABLED(3, 1))
			return 0;
		if (addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
			return 1;
		return 0;
	}

	/* not within async bounds */
	return 2;
}

int bfin_mem_access_type(unsigned long addr, unsigned long size)
{
	int cpu = raw_smp_processor_id();

	/* Check that things do not wrap around */
	if (addr > ULONG_MAX - size)
		return -EFAULT;

	if (in_mem(addr, size, FIXED_CODE_START, physical_mem_end))
		return BFIN_MEM_ACCESS_CORE;

	if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
		return cpu == 0 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
	if (in_mem_const(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH))
		return cpu == 0 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
	if (in_mem_const(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH))
		return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
	if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH))
		return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
#ifdef COREB_L1_CODE_START
	if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
		return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
	if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
		return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
	if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
		return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
	if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
		return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
#endif
	if (in_mem_const(addr, size, L2_START, L2_LENGTH))
		return BFIN_MEM_ACCESS_CORE;

	if (addr >= SYSMMR_BASE)
		return BFIN_MEM_ACCESS_CORE_ONLY;

	switch (in_async(addr, size)) {
	case 0: return -EFAULT;
	case 1: return BFIN_MEM_ACCESS_CORE;
	case 2: /* fall through */;
	}

	if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
		return BFIN_MEM_ACCESS_CORE;
	if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
		return BFIN_MEM_ACCESS_DMA;

	return -EFAULT;
}

#if defined(CONFIG_ACCESS_CHECK)
#ifdef CONFIG_ACCESS_OK_L1
__attribute__((l1_text))
#endif
/* Return 1 if access to memory range is OK, 0 otherwise */
int _access_ok(unsigned long addr, unsigned long size)
{
	int aret;

	if (size == 0)
		return 1;
	/* Check that things do not wrap around */
	if (addr > ULONG_MAX - size)
		return 0;
	if (segment_eq(get_fs(), KERNEL_DS))
		return 1;
#ifdef CONFIG_MTD_UCLINUX
	if (1)
#else
	if (0)
#endif
	{
		if (in_mem(addr, size, memory_start, memory_end))
			return 1;
		if (in_mem(addr, size, memory_mtd_end, physical_mem_end))
			return 1;
# ifndef CONFIG_ROMFS_ON_MTD
		if (0)
# endif
			/* For XIP, allow user space to use pointers within the ROMFS.  */
			if (in_mem(addr, size, memory_mtd_start, memory_mtd_end))
				return 1;
	} else {
		if (in_mem(addr, size, memory_start, physical_mem_end))
			return 1;
	}

	if (in_mem(addr, size, (unsigned long)__init_begin, (unsigned long)__init_end))
		return 1;

	if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
		return 1;
	if (in_mem_const_off(addr, size, _etext_l1 - _stext_l1, L1_CODE_START, L1_CODE_LENGTH))
		return 1;
	if (in_mem_const_off(addr, size, _ebss_l1 - _sdata_l1, L1_DATA_A_START, L1_DATA_A_LENGTH))
		return 1;
	if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH))
		return 1;
#ifdef COREB_L1_CODE_START
	if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
		return 1;
	if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
		return 1;
	if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
		return 1;
	if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
		return 1;
#endif

#ifndef CONFIG_EXCEPTION_L1_SCRATCH
	if (in_mem_const(addr, size, (unsigned long)l1_stack_base, l1_stack_len))
		return 1;
#endif

	aret = in_async(addr, size);
	if (aret < 2)
		return aret;

	if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH))
		return 1;

	if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
		return 1;
	if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
		return 1;

	return 0;
}
EXPORT_SYMBOL(_access_ok);
#endif /* CONFIG_ACCESS_CHECK */
Commit	Line	Data
1394f032	1	/*
96f1050d	2	* Blackfin architecture-dependent process handling
1394f032	3	*
96f1050d	4	* Copyright 2004-2009 Analog Devices Inc.
1394f032	5	*
96f1050d	6	* Licensed under the GPL-2 or later
1394f032 BW	7	*/
	8
	9	#include <linux/module.h>
1394f032 BW	10	#include <linux/unistd.h>
1394f032 BW	11	#include <linux/user.h>
1f83b8f1	12	#include <linux/uaccess.h>
5a0e3ad6	13	#include <linux/slab.h>
8b5f79f9	14	#include <linux/sched.h>
b17b0153	15	#include <linux/sched/debug.h>
29930025	16	#include <linux/sched/task.h>
8b5f79f9	17	#include <linux/tick.h>
d31c5ab1 BW	18	#include <linux/fs.h>
d31c5ab1 BW	19	#include <linux/err.h>
1394f032 BW	20
1394f032 BW	21	#include <asm/blackfin.h>
7adfb58f	22	#include <asm/fixed_code.h>
dbc895f9	23	#include <asm/mem_map.h>
3bed8d67	24	#include <asm/irq.h>
1394f032	25
1394f032 BW	26	asmlinkage void ret_from_fork(void);
	27
	28	/* Points to the SDRAM backup memory for the stack that is currently in
	29	* L1 scratchpad memory.
	30	*/
	31	void *current_l1_stack_save;
	32
	33	/* The number of tasks currently using a L1 stack area. The SRAM is
	34	* allocated/deallocated whenever this changes from/to zero.
	35	*/
	36	int nr_l1stack_tasks;
	37
	38	/* Start and length of the area in L1 scratchpad memory which we've allocated
	39	* for process stacks.
	40	*/
	41	void *l1_stack_base;
	42	unsigned long l1_stack_len;
	43
1394f032 BW	44	void (*pm_power_off)(void) = NULL;
	45	EXPORT_SYMBOL(pm_power_off);
	46
1394f032 BW	47	/*
	48	* The idle loop on BFIN
	49	*/
	50	#ifdef CONFIG_IDLE_L1
25d67f86	51	void arch_cpu_idle(void)__attribute__((l1_text));
1394f032 BW	52	#endif
1394f032 BW	53
8b5f79f9 VM	54	/*
	55	* This is our default idle handler. We need to disable
	56	* interrupts here to ensure we don't miss a wakeup call.
	57	*/
25d67f86	58	void arch_cpu_idle(void)
1394f032	59	{
6a01f230 YL	60	#ifdef CONFIG_IPIPE
	61	ipipe_suspend_domain();
	62	#endif
3b139cdb	63	hard_local_irq_disable();
8b5f79f9 VM	64	if (!need_resched())
8b5f79f9 VM	65	idle_with_irq_disabled();
1394f032	66
3b139cdb	67	hard_local_irq_enable();
8b5f79f9	68	}
1394f032	69
59f0eaaa	70	#ifdef CONFIG_HOTPLUG_CPU
25d67f86	71	void arch_cpu_idle_dead(void)
1394f032	72	{
25d67f86	73	cpu_die();
1394f032	74	}
25d67f86	75	#endif
1394f032	76
d5ce528c MF	77	/*
	78	* Do necessary setup to start up a newly executed thread.
	79	*
	80	* pass the data segment into user programs if it exists,
	81	* it can't hurt anything as far as I can tell
	82	*/
	83	void start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
	84	{
d5ce528c MF	85	regs->pc = new_ip;
	86	if (current->mm)
	87	regs->p5 = current->mm->start_data;
aa23531c	88	#ifndef CONFIG_SMP
d5ce528c MF	89	task_thread_info(current)->l1_task_info.stack_start =
	90	(void *)current->mm->context.stack_start;
	91	task_thread_info(current)->l1_task_info.lowest_sp = (void *)new_sp;
	92	memcpy(L1_SCRATCH_TASK_INFO, &task_thread_info(current)->l1_task_info,
	93	sizeof(*L1_SCRATCH_TASK_INFO));
	94	#endif
	95	wrusp(new_sp);
	96	}
	97	EXPORT_SYMBOL_GPL(start_thread);
	98
1394f032 BW	99	void flush_thread(void)
	100	{
	101	}
	102
135c37b8	103	asmlinkage int bfin_clone(unsigned long clone_flags, unsigned long newsp)
1394f032	104	{
8f65873e	105	#ifdef __ARCH_SYNC_CORE_DCACHE
29baa747	106	if (current->nr_cpus_allowed == num_possible_cpus())
e887eb61	107	set_cpus_allowed_ptr(current, cpumask_of(smp_processor_id()));
8f65873e	108	#endif
135c37b8	109	if (newsp)
1394f032	110	newsp -= 12;
e80d6661	111	return do_fork(clone_flags, newsp, 0, NULL, NULL);
1394f032 BW	112	}
	113
	114	int
6f2c55b8	115	copy_thread(unsigned long clone_flags,
1394f032	116	unsigned long usp, unsigned long topstk,
afa86fc4	117	struct task_struct *p)
1394f032 BW	118	{
1394f032 BW	119	struct pt_regs *childregs;
ee1e17c6	120	unsigned long *v;
1394f032 BW	121
1394f032 BW	122	childregs = (struct pt_regs *) (task_stack_page(p) + THREAD_SIZE) - 1;
ee1e17c6	123	v = ((unsigned long *)childregs) - 2;
afa86fc4	124	if (unlikely(p->flags & PF_KTHREAD)) {
ee1e17c6 AV	125	memset(childregs, 0, sizeof(struct pt_regs));
	126	v[0] = usp;
	127	v[1] = topstk;
	128	childregs->orig_p0 = -1;
	129	childregs->ipend = 0x8000;
	130	__asm__ __volatile__("%0 = syscfg;":"=da"(childregs->syscfg):);
	131	p->thread.usp = 0;
	132	} else {
afa86fc4	133	childregs = current_pt_regs();
ee1e17c6	134	childregs->r0 = 0;
135c37b8	135	p->thread.usp = usp ? : rdusp();
ee1e17c6 AV	136	v[0] = v[1] = 0;
ee1e17c6 AV	137	}
1394f032	138
ee1e17c6	139	p->thread.ksp = (unsigned long)v;
1394f032 BW	140	p->thread.pc = (unsigned long)ret_from_fork;
	141
	142	return 0;
	143	}
	144
1394f032 BW	145	unsigned long get_wchan(struct task_struct *p)
	146	{
	147	unsigned long fp, pc;
	148	unsigned long stack_page;
	149	int count = 0;
	150	if (!p \|\| p == current \|\| p->state == TASK_RUNNING)
	151	return 0;
	152
	153	stack_page = (unsigned long)p;
	154	fp = p->thread.usp;
	155	do {
	156	if (fp < stack_page + sizeof(struct thread_info) \|\|
	157	fp >= 8184 + stack_page)
	158	return 0;
	159	pc = ((unsigned long *)fp)[1];
	160	if (!in_sched_functions(pc))
	161	return pc;
	162	fp = (unsigned long )fp;
	163	}
	164	while (count++ < 16);
	165	return 0;
	166	}
	167
7adfb58f BS	168	void finish_atomic_sections (struct pt_regs *regs)
7adfb58f BS	169	{
19d6d7d5	170	int __user up0 = (int __user )regs->p0;
0ddeeca2	171
7adfb58f	172	switch (regs->pc) {
2f5a0864 MF	173	default:
	174	/* not in middle of an atomic step, so resume like normal */
	175	return;
	176
7adfb58f	177	case ATOMIC_XCHG32 + 2:
0ddeeca2	178	put_user(regs->r1, up0);
7adfb58f BS	179	break;
	180
	181	case ATOMIC_CAS32 + 2:
	182	case ATOMIC_CAS32 + 4:
	183	if (regs->r0 == regs->r1)
92649494	184	case ATOMIC_CAS32 + 6:
0ddeeca2	185	put_user(regs->r2, up0);
7adfb58f	186	break;
7adfb58f BS	187
	188	case ATOMIC_ADD32 + 2:
	189	regs->r0 = regs->r1 + regs->r0;
	190	/* fall through */
	191	case ATOMIC_ADD32 + 4:
0ddeeca2	192	put_user(regs->r0, up0);
7adfb58f BS	193	break;
	194
	195	case ATOMIC_SUB32 + 2:
	196	regs->r0 = regs->r1 - regs->r0;
	197	/* fall through */
	198	case ATOMIC_SUB32 + 4:
0ddeeca2	199	put_user(regs->r0, up0);
7adfb58f BS	200	break;
	201
	202	case ATOMIC_IOR32 + 2:
	203	regs->r0 = regs->r1 \| regs->r0;
	204	/* fall through */
	205	case ATOMIC_IOR32 + 4:
0ddeeca2	206	put_user(regs->r0, up0);
7adfb58f BS	207	break;
	208
	209	case ATOMIC_AND32 + 2:
	210	regs->r0 = regs->r1 & regs->r0;
	211	/* fall through */
	212	case ATOMIC_AND32 + 4:
0ddeeca2	213	put_user(regs->r0, up0);
7adfb58f BS	214	break;
	215
	216	case ATOMIC_XOR32 + 2:
	217	regs->r0 = regs->r1 ^ regs->r0;
	218	/* fall through */
	219	case ATOMIC_XOR32 + 4:
0ddeeca2	220	put_user(regs->r0, up0);
7adfb58f BS	221	break;
7adfb58f BS	222	}
2f5a0864 MF	223
	224	/*
	225	* We've finished the atomic section, and the only thing left for
	226	* userspace is to do a RTS, so we might as well handle that too
	227	* since we need to update the PC anyways.
	228	*/
	229	regs->pc = regs->rets;
7adfb58f BS	230	}
7adfb58f BS	231
e56e03b0 MF	232	static inline
	233	int in_mem(unsigned long addr, unsigned long size,
	234	unsigned long start, unsigned long end)
	235	{
	236	return addr >= start && addr + size <= end;
	237	}
	238	static inline
	239	int in_mem_const_off(unsigned long addr, unsigned long size, unsigned long off,
	240	unsigned long const_addr, unsigned long const_size)
	241	{
	242	return const_size &&
	243	in_mem(addr, size, const_addr + off, const_addr + const_size);
	244	}
	245	static inline
	246	int in_mem_const(unsigned long addr, unsigned long size,
	247	unsigned long const_addr, unsigned long const_size)
	248	{
fb4b5d3a	249	return in_mem_const_off(addr, size, 0, const_addr, const_size);
e56e03b0	250	}
b5affb01 BL	251	#ifdef CONFIG_BF60x
	252	#define ASYNC_ENABLED(bnum, bctlnum) 1
	253	#else
13048f88	254	#define ASYNC_ENABLED(bnum, bctlnum) \
e56e03b0	255	({ \
13048f88 BS	256	(bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
	257	bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
	258	1; \
e56e03b0	259	})
b5affb01	260	#endif
13048f88 BS	261	/*
	262	* We can't read EBIU banks that aren't enabled or we end up hanging
	263	* on the access to the async space. Make sure we validate accesses
	264	* that cross async banks too.
	265	* 0 - found, but unusable
	266	* 1 - found & usable
	267	* 2 - not found
	268	*/
	269	static
	270	int in_async(unsigned long addr, unsigned long size)
	271	{
	272	if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) {
	273	if (!ASYNC_ENABLED(0, 0))
	274	return 0;
	275	if (addr + size <= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE)
	276	return 1;
	277	size -= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE - addr;
	278	addr = ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE;
	279	}
	280	if (addr >= ASYNC_BANK1_BASE && addr < ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE) {
	281	if (!ASYNC_ENABLED(1, 0))
	282	return 0;
	283	if (addr + size <= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE)
	284	return 1;
	285	size -= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE - addr;
	286	addr = ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE;
	287	}
	288	if (addr >= ASYNC_BANK2_BASE && addr < ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE) {
	289	if (!ASYNC_ENABLED(2, 1))
	290	return 0;
	291	if (addr + size <= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE)
	292	return 1;
	293	size -= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE - addr;
	294	addr = ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE;
	295	}
	296	if (addr >= ASYNC_BANK3_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
	297	if (ASYNC_ENABLED(3, 1))
	298	return 0;
	299	if (addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
	300	return 1;
	301	return 0;
	302	}
	303
	304	/* not within async bounds */
	305	return 2;
	306	}
e56e03b0 MF	307
	308	int bfin_mem_access_type(unsigned long addr, unsigned long size)
	309	{
	310	int cpu = raw_smp_processor_id();
	311
	312	/* Check that things do not wrap around */
	313	if (addr > ULONG_MAX - size)
	314	return -EFAULT;
	315
	316	if (in_mem(addr, size, FIXED_CODE_START, physical_mem_end))
	317	return BFIN_MEM_ACCESS_CORE;
	318
	319	if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
	320	return cpu == 0 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
	321	if (in_mem_const(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH))
	322	return cpu == 0 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
	323	if (in_mem_const(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH))
	324	return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
	325	if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH))
	326	return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
	327	#ifdef COREB_L1_CODE_START
fb4b5d3a	328	if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
e56e03b0 MF	329	return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
	330	if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
	331	return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
fb4b5d3a	332	if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
e56e03b0	333	return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
fb4b5d3a	334	if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
e56e03b0 MF	335	return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
	336	#endif
	337	if (in_mem_const(addr, size, L2_START, L2_LENGTH))
	338	return BFIN_MEM_ACCESS_CORE;
	339
	340	if (addr >= SYSMMR_BASE)
	341	return BFIN_MEM_ACCESS_CORE_ONLY;
	342
13048f88 BS	343	switch (in_async(addr, size)) {
	344	case 0: return -EFAULT;
	345	case 1: return BFIN_MEM_ACCESS_CORE;
	346	case 2: /* fall through */;
	347	}
e56e03b0 MF	348
	349	if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
	350	return BFIN_MEM_ACCESS_CORE;
	351	if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
	352	return BFIN_MEM_ACCESS_DMA;
	353
	354	return -EFAULT;
	355	}
	356
1394f032	357	#if defined(CONFIG_ACCESS_CHECK)
a43b739f MF	358	#ifdef CONFIG_ACCESS_OK_L1
	359	__attribute__((l1_text))
	360	#endif
b03b08ba	361	/* Return 1 if access to memory range is OK, 0 otherwise */
1394f032 BW	362	int _access_ok(unsigned long addr, unsigned long size)
1394f032 BW	363	{
13048f88 BS	364	int aret;
13048f88 BS	365
bc41bb11 BS	366	if (size == 0)
bc41bb11 BS	367	return 1;
e56e03b0 MF	368	/* Check that things do not wrap around */
e56e03b0 MF	369	if (addr > ULONG_MAX - size)
1394f032	370	return 0;
1f83b8f1	371	if (segment_eq(get_fs(), KERNEL_DS))
1394f032 BW	372	return 1;
1394f032 BW	373	#ifdef CONFIG_MTD_UCLINUX
e56e03b0 MF	374	if (1)
	375	#else
	376	if (0)
	377	#endif
	378	{
	379	if (in_mem(addr, size, memory_start, memory_end))
	380	return 1;
	381	if (in_mem(addr, size, memory_mtd_end, physical_mem_end))
	382	return 1;
	383	# ifndef CONFIG_ROMFS_ON_MTD
	384	if (0)
	385	# endif
	386	/* For XIP, allow user space to use pointers within the ROMFS. */
	387	if (in_mem(addr, size, memory_mtd_start, memory_mtd_end))
	388	return 1;
	389	} else {
	390	if (in_mem(addr, size, memory_start, physical_mem_end))
	391	return 1;
	392	}
	393
	394	if (in_mem(addr, size, (unsigned long)__init_begin, (unsigned long)__init_end))
1394f032	395	return 1;
d5adb029	396
e56e03b0	397	if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
d5adb029	398	return 1;
e56e03b0	399	if (in_mem_const_off(addr, size, _etext_l1 - _stext_l1, L1_CODE_START, L1_CODE_LENGTH))
1394f032	400	return 1;
e56e03b0	401	if (in_mem_const_off(addr, size, _ebss_l1 - _sdata_l1, L1_DATA_A_START, L1_DATA_A_LENGTH))
1394f032	402	return 1;
e56e03b0	403	if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH))
1394f032	404	return 1;
e56e03b0	405	#ifdef COREB_L1_CODE_START
fb4b5d3a	406	if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
1394f032	407	return 1;
e56e03b0	408	if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
1394f032	409	return 1;
fb4b5d3a	410	if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
1394f032	411	return 1;
fb4b5d3a	412	if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
b2c2f303	413	return 1;
1394f032	414	#endif
13048f88	415
41c3e334 BS	416	#ifndef CONFIG_EXCEPTION_L1_SCRATCH
	417	if (in_mem_const(addr, size, (unsigned long)l1_stack_base, l1_stack_len))
	418	return 1;
	419	#endif
	420
13048f88 BS	421	aret = in_async(addr, size);
	422	if (aret < 2)
	423	return aret;
	424
e56e03b0 MF	425	if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH))
	426	return 1;
	427
	428	if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
	429	return 1;
	430	if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
	431	return 1;
	432
1394f032 BW	433	return 0;
	434	}
	435	EXPORT_SYMBOL(_access_ok);
	436	#endif /* CONFIG_ACCESS_CHECK */