[mirror_ubuntu-bionic-kernel.git] / arch / blackfin / kernel / process.c

/*
 * Blackfin architecture-dependent process handling
 *
 * Copyright 2004-2009 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later
 */

#include <linux/module.h>
#include <linux/unistd.h>
#include <linux/user.h>
#include <linux/uaccess.h>
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/tick.h>
#include <linux/fs.h>
#include <linux/err.h>

#include <asm/blackfin.h>
#include <asm/fixed_code.h>
#include <asm/mem_map.h>
#include <asm/irq.h>

asmlinkage void ret_from_fork(void);

/* Points to the SDRAM backup memory for the stack that is currently in
 * L1 scratchpad memory.
 */
void *current_l1_stack_save;

/* The number of tasks currently using a L1 stack area.  The SRAM is
 * allocated/deallocated whenever this changes from/to zero.
 */
int nr_l1stack_tasks;

/* Start and length of the area in L1 scratchpad memory which we've allocated
 * for process stacks.
 */
void *l1_stack_base;
unsigned long l1_stack_len;

/*
 * Powermanagement idle function, if any..
 */
void (*pm_idle)(void) = NULL;
EXPORT_SYMBOL(pm_idle);

void (*pm_power_off)(void) = NULL;
EXPORT_SYMBOL(pm_power_off);

/*
 * The idle loop on BFIN
 */
#ifdef CONFIG_IDLE_L1
static void default_idle(void)__attribute__((l1_text));
void cpu_idle(void)__attribute__((l1_text));
#endif

/*
 * This is our default idle handler.  We need to disable
 * interrupts here to ensure we don't miss a wakeup call.
 */
static void default_idle(void)
{
#ifdef CONFIG_IPIPE
	ipipe_suspend_domain();
#endif
	hard_local_irq_disable();
	if (!need_resched())
		idle_with_irq_disabled();

	hard_local_irq_enable();
}

/*
 * The idle thread.  We try to conserve power, while trying to keep
 * overall latency low.  The architecture specific idle is passed
 * a value to indicate the level of "idleness" of the system.
 */
void cpu_idle(void)
{
	/* endless idle loop with no priority at all */
	while (1) {
		void (*idle)(void) = pm_idle;

#ifdef CONFIG_HOTPLUG_CPU
		if (cpu_is_offline(smp_processor_id()))
			cpu_die();
#endif
		if (!idle)
			idle = default_idle;
		tick_nohz_idle_enter();
		rcu_idle_enter();
		while (!need_resched())
			idle();
		rcu_idle_exit();
		tick_nohz_idle_exit();
		preempt_enable_no_resched();
		schedule();
		preempt_disable();
	}
}

/*
 * Do necessary setup to start up a newly executed thread.
 *
 * pass the data segment into user programs if it exists,
 * it can't hurt anything as far as I can tell
 */
void start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
{
	regs->pc = new_ip;
	if (current->mm)
		regs->p5 = current->mm->start_data;
#ifndef CONFIG_SMP
	task_thread_info(current)->l1_task_info.stack_start =
		(void *)current->mm->context.stack_start;
	task_thread_info(current)->l1_task_info.lowest_sp = (void *)new_sp;
	memcpy(L1_SCRATCH_TASK_INFO, &task_thread_info(current)->l1_task_info,
	       sizeof(*L1_SCRATCH_TASK_INFO));
#endif
	wrusp(new_sp);
}
EXPORT_SYMBOL_GPL(start_thread);

void flush_thread(void)
{
}

asmlinkage int bfin_vfork(struct pt_regs *regs)
{
	return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, rdusp(), regs, 0, NULL,
		       NULL);
}

asmlinkage int bfin_clone(struct pt_regs *regs)
{
	unsigned long clone_flags;
	unsigned long newsp;

#ifdef __ARCH_SYNC_CORE_DCACHE
	if (current->nr_cpus_allowed == num_possible_cpus())
		set_cpus_allowed_ptr(current, cpumask_of(smp_processor_id()));
#endif

	/* syscall2 puts clone_flags in r0 and usp in r1 */
	clone_flags = regs->r0;
	newsp = regs->r1;
	if (!newsp)
		newsp = rdusp();
	else
		newsp -= 12;
	return do_fork(clone_flags, newsp, regs, 0, NULL, NULL);
}

int
copy_thread(unsigned long clone_flags,
	    unsigned long usp, unsigned long topstk,
	    struct task_struct *p, struct pt_regs *regs)
{
	struct pt_regs *childregs;
	unsigned long *v;

	childregs = (struct pt_regs *) (task_stack_page(p) + THREAD_SIZE) - 1;
	v = ((unsigned long *)childregs) - 2;
	if (unlikely(!regs)) {
		memset(childregs, 0, sizeof(struct pt_regs));
		v[0] = usp;
		v[1] = topstk;
		childregs->orig_p0 = -1;
		childregs->ipend = 0x8000;
		__asm__ __volatile__("%0 = syscfg;":"=da"(childregs->syscfg):);
		p->thread.usp = 0;
	} else {
		*childregs = *regs;
		childregs->r0 = 0;
		p->thread.usp = usp;
		v[0] = v[1] = 0;
	}

	p->thread.ksp = (unsigned long)v;
	p->thread.pc = (unsigned long)ret_from_fork;

	return 0;
}

unsigned long get_wchan(struct task_struct *p)
{
	unsigned long fp, pc;
	unsigned long stack_page;
	int count = 0;
	if (!p || p == current || p->state == TASK_RUNNING)
		return 0;

	stack_page = (unsigned long)p;
	fp = p->thread.usp;
	do {
		if (fp < stack_page + sizeof(struct thread_info) ||
		    fp >= 8184 + stack_page)
			return 0;
		pc = ((unsigned long *)fp)[1];
		if (!in_sched_functions(pc))
			return pc;
		fp = *(unsigned long *)fp;
	}
	while (count++ < 16);
	return 0;
}

void finish_atomic_sections (struct pt_regs *regs)
{
	int __user *up0 = (int __user *)regs->p0;

	switch (regs->pc) {
	default:
		/* not in middle of an atomic step, so resume like normal */
		return;

	case ATOMIC_XCHG32 + 2:
		put_user(regs->r1, up0);
		break;

	case ATOMIC_CAS32 + 2:
	case ATOMIC_CAS32 + 4:
		if (regs->r0 == regs->r1)
	case ATOMIC_CAS32 + 6:
			put_user(regs->r2, up0);
		break;

	case ATOMIC_ADD32 + 2:
		regs->r0 = regs->r1 + regs->r0;
		/* fall through */
	case ATOMIC_ADD32 + 4:
		put_user(regs->r0, up0);
		break;

	case ATOMIC_SUB32 + 2:
		regs->r0 = regs->r1 - regs->r0;
		/* fall through */
	case ATOMIC_SUB32 + 4:
		put_user(regs->r0, up0);
		break;

	case ATOMIC_IOR32 + 2:
		regs->r0 = regs->r1 | regs->r0;
		/* fall through */
	case ATOMIC_IOR32 + 4:
		put_user(regs->r0, up0);
		break;

	case ATOMIC_AND32 + 2:
		regs->r0 = regs->r1 & regs->r0;
		/* fall through */
	case ATOMIC_AND32 + 4:
		put_user(regs->r0, up0);
		break;

	case ATOMIC_XOR32 + 2:
		regs->r0 = regs->r1 ^ regs->r0;
		/* fall through */
	case ATOMIC_XOR32 + 4:
		put_user(regs->r0, up0);
		break;
	}

	/*
	 * We've finished the atomic section, and the only thing left for
	 * userspace is to do a RTS, so we might as well handle that too
	 * since we need to update the PC anyways.
	 */
	regs->pc = regs->rets;
}

static inline
int in_mem(unsigned long addr, unsigned long size,
           unsigned long start, unsigned long end)
{
	return addr >= start && addr + size <= end;
}
static inline
int in_mem_const_off(unsigned long addr, unsigned long size, unsigned long off,
                     unsigned long const_addr, unsigned long const_size)
{
	return const_size &&
	       in_mem(addr, size, const_addr + off, const_addr + const_size);
}
static inline
int in_mem_const(unsigned long addr, unsigned long size,
                 unsigned long const_addr, unsigned long const_size)
{
	return in_mem_const_off(addr, size, 0, const_addr, const_size);
}
#ifdef CONFIG_BF60x
#define ASYNC_ENABLED(bnum, bctlnum)	1
#else
#define ASYNC_ENABLED(bnum, bctlnum) \
({ \
	(bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
	bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
	1; \
})
#endif
/*
 * We can't read EBIU banks that aren't enabled or we end up hanging
 * on the access to the async space.  Make sure we validate accesses
 * that cross async banks too.
 *	0 - found, but unusable
 *	1 - found & usable
 *	2 - not found
 */
static
int in_async(unsigned long addr, unsigned long size)
{
	if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) {
		if (!ASYNC_ENABLED(0, 0))
			return 0;
		if (addr + size <= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE)
			return 1;
		size -= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE - addr;
		addr = ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE;
	}
	if (addr >= ASYNC_BANK1_BASE && addr < ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE) {
		if (!ASYNC_ENABLED(1, 0))
			return 0;
		if (addr + size <= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE)
			return 1;
		size -= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE - addr;
		addr = ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE;
	}
	if (addr >= ASYNC_BANK2_BASE && addr < ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE) {
		if (!ASYNC_ENABLED(2, 1))
			return 0;
		if (addr + size <= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE)
			return 1;
		size -= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE - addr;
		addr = ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE;
	}
	if (addr >= ASYNC_BANK3_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
		if (ASYNC_ENABLED(3, 1))
			return 0;
		if (addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
			return 1;
		return 0;
	}

	/* not within async bounds */
	return 2;
}

int bfin_mem_access_type(unsigned long addr, unsigned long size)
{
	int cpu = raw_smp_processor_id();

	/* Check that things do not wrap around */
	if (addr > ULONG_MAX - size)
		return -EFAULT;

	if (in_mem(addr, size, FIXED_CODE_START, physical_mem_end))
		return BFIN_MEM_ACCESS_CORE;

	if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
		return cpu == 0 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
	if (in_mem_const(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH))
		return cpu == 0 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
	if (in_mem_const(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH))
		return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
	if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH))
		return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
#ifdef COREB_L1_CODE_START
	if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
		return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
	if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
		return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
	if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
		return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
	if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
		return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
#endif
	if (in_mem_const(addr, size, L2_START, L2_LENGTH))
		return BFIN_MEM_ACCESS_CORE;

	if (addr >= SYSMMR_BASE)
		return BFIN_MEM_ACCESS_CORE_ONLY;

	switch (in_async(addr, size)) {
	case 0: return -EFAULT;
	case 1: return BFIN_MEM_ACCESS_CORE;
	case 2: /* fall through */;
	}

	if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
		return BFIN_MEM_ACCESS_CORE;
	if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
		return BFIN_MEM_ACCESS_DMA;

	return -EFAULT;
}

#if defined(CONFIG_ACCESS_CHECK)
#ifdef CONFIG_ACCESS_OK_L1
__attribute__((l1_text))
#endif
/* Return 1 if access to memory range is OK, 0 otherwise */
int _access_ok(unsigned long addr, unsigned long size)
{
	int aret;

	if (size == 0)
		return 1;
	/* Check that things do not wrap around */
	if (addr > ULONG_MAX - size)
		return 0;
	if (segment_eq(get_fs(), KERNEL_DS))
		return 1;
#ifdef CONFIG_MTD_UCLINUX
	if (1)
#else
	if (0)
#endif
	{
		if (in_mem(addr, size, memory_start, memory_end))
			return 1;
		if (in_mem(addr, size, memory_mtd_end, physical_mem_end))
			return 1;
# ifndef CONFIG_ROMFS_ON_MTD
		if (0)
# endif
			/* For XIP, allow user space to use pointers within the ROMFS.  */
			if (in_mem(addr, size, memory_mtd_start, memory_mtd_end))
				return 1;
	} else {
		if (in_mem(addr, size, memory_start, physical_mem_end))
			return 1;
	}

	if (in_mem(addr, size, (unsigned long)__init_begin, (unsigned long)__init_end))
		return 1;

	if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
		return 1;
	if (in_mem_const_off(addr, size, _etext_l1 - _stext_l1, L1_CODE_START, L1_CODE_LENGTH))
		return 1;
	if (in_mem_const_off(addr, size, _ebss_l1 - _sdata_l1, L1_DATA_A_START, L1_DATA_A_LENGTH))
		return 1;
	if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH))
		return 1;
#ifdef COREB_L1_CODE_START
	if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
		return 1;
	if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
		return 1;
	if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
		return 1;
	if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
		return 1;
#endif

#ifndef CONFIG_EXCEPTION_L1_SCRATCH
	if (in_mem_const(addr, size, (unsigned long)l1_stack_base, l1_stack_len))
		return 1;
#endif

	aret = in_async(addr, size);
	if (aret < 2)
		return aret;

	if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH))
		return 1;

	if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
		return 1;
	if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
		return 1;

	return 0;
}
EXPORT_SYMBOL(_access_ok);
#endif /* CONFIG_ACCESS_CHECK */
Commit	Line	Data
1394f032	1	/*
96f1050d	2	* Blackfin architecture-dependent process handling
1394f032	3	*
96f1050d	4	* Copyright 2004-2009 Analog Devices Inc.
1394f032	5	*
96f1050d	6	* Licensed under the GPL-2 or later
1394f032 BW	7	*/
	8
	9	#include <linux/module.h>
1394f032 BW	10	#include <linux/unistd.h>
1394f032 BW	11	#include <linux/user.h>
1f83b8f1	12	#include <linux/uaccess.h>
5a0e3ad6	13	#include <linux/slab.h>
8b5f79f9 VM	14	#include <linux/sched.h>
8b5f79f9 VM	15	#include <linux/tick.h>
d31c5ab1 BW	16	#include <linux/fs.h>
d31c5ab1 BW	17	#include <linux/err.h>
1394f032 BW	18
1394f032 BW	19	#include <asm/blackfin.h>
7adfb58f	20	#include <asm/fixed_code.h>
dbc895f9	21	#include <asm/mem_map.h>
3bed8d67	22	#include <asm/irq.h>
1394f032	23
1394f032 BW	24	asmlinkage void ret_from_fork(void);
	25
	26	/* Points to the SDRAM backup memory for the stack that is currently in
	27	* L1 scratchpad memory.
	28	*/
	29	void *current_l1_stack_save;
	30
	31	/* The number of tasks currently using a L1 stack area. The SRAM is
	32	* allocated/deallocated whenever this changes from/to zero.
	33	*/
	34	int nr_l1stack_tasks;
	35
	36	/* Start and length of the area in L1 scratchpad memory which we've allocated
	37	* for process stacks.
	38	*/
	39	void *l1_stack_base;
	40	unsigned long l1_stack_len;
	41
	42	/*
	43	* Powermanagement idle function, if any..
	44	*/
	45	void (*pm_idle)(void) = NULL;
	46	EXPORT_SYMBOL(pm_idle);
	47
	48	void (*pm_power_off)(void) = NULL;
	49	EXPORT_SYMBOL(pm_power_off);
	50
1394f032 BW	51	/*
	52	* The idle loop on BFIN
	53	*/
	54	#ifdef CONFIG_IDLE_L1
8b5f79f9	55	static void default_idle(void)__attribute__((l1_text));
1394f032 BW	56	void cpu_idle(void)__attribute__((l1_text));
	57	#endif
	58
8b5f79f9 VM	59	/*
	60	* This is our default idle handler. We need to disable
	61	* interrupts here to ensure we don't miss a wakeup call.
	62	*/
	63	static void default_idle(void)
1394f032	64	{
6a01f230 YL	65	#ifdef CONFIG_IPIPE
	66	ipipe_suspend_domain();
	67	#endif
3b139cdb	68	hard_local_irq_disable();
8b5f79f9 VM	69	if (!need_resched())
8b5f79f9 VM	70	idle_with_irq_disabled();
1394f032	71
3b139cdb	72	hard_local_irq_enable();
8b5f79f9	73	}
1394f032 BW	74
1394f032 BW	75	/*
8b5f79f9 VM	76	* The idle thread. We try to conserve power, while trying to keep
	77	* overall latency low. The architecture specific idle is passed
	78	* a value to indicate the level of "idleness" of the system.
1394f032 BW	79	*/
	80	void cpu_idle(void)
	81	{
	82	/* endless idle loop with no priority at all */
	83	while (1) {
8b5f79f9 VM	84	void (*idle)(void) = pm_idle;
	85
	86	#ifdef CONFIG_HOTPLUG_CPU
	87	if (cpu_is_offline(smp_processor_id()))
	88	cpu_die();
	89	#endif
	90	if (!idle)
	91	idle = default_idle;
1268fbc7 FW	92	tick_nohz_idle_enter();
1268fbc7 FW	93	rcu_idle_enter();
8b5f79f9 VM	94	while (!need_resched())
8b5f79f9 VM	95	idle();
1268fbc7 FW	96	rcu_idle_exit();
1268fbc7 FW	97	tick_nohz_idle_exit();
b5affb01 BL	98	preempt_enable_no_resched();
	99	schedule();
	100	preempt_disable();
1394f032 BW	101	}
	102	}
	103
d5ce528c MF	104	/*
	105	* Do necessary setup to start up a newly executed thread.
	106	*
	107	* pass the data segment into user programs if it exists,
	108	* it can't hurt anything as far as I can tell
	109	*/
	110	void start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
	111	{
d5ce528c MF	112	regs->pc = new_ip;
	113	if (current->mm)
	114	regs->p5 = current->mm->start_data;
aa23531c	115	#ifndef CONFIG_SMP
d5ce528c MF	116	task_thread_info(current)->l1_task_info.stack_start =
	117	(void *)current->mm->context.stack_start;
	118	task_thread_info(current)->l1_task_info.lowest_sp = (void *)new_sp;
	119	memcpy(L1_SCRATCH_TASK_INFO, &task_thread_info(current)->l1_task_info,
	120	sizeof(*L1_SCRATCH_TASK_INFO));
	121	#endif
	122	wrusp(new_sp);
	123	}
	124	EXPORT_SYMBOL_GPL(start_thread);
	125
1394f032 BW	126	void flush_thread(void)
	127	{
	128	}
	129
	130	asmlinkage int bfin_vfork(struct pt_regs *regs)
	131	{
	132	return do_fork(CLONE_VFORK \| CLONE_VM \| SIGCHLD, rdusp(), regs, 0, NULL,
	133	NULL);
	134	}
	135
	136	asmlinkage int bfin_clone(struct pt_regs *regs)
	137	{
	138	unsigned long clone_flags;
	139	unsigned long newsp;
	140
8f65873e	141	#ifdef __ARCH_SYNC_CORE_DCACHE
29baa747	142	if (current->nr_cpus_allowed == num_possible_cpus())
e887eb61	143	set_cpus_allowed_ptr(current, cpumask_of(smp_processor_id()));
8f65873e GY	144	#endif
8f65873e GY	145
1394f032 BW	146	/* syscall2 puts clone_flags in r0 and usp in r1 */
	147	clone_flags = regs->r0;
	148	newsp = regs->r1;
	149	if (!newsp)
	150	newsp = rdusp();
	151	else
	152	newsp -= 12;
	153	return do_fork(clone_flags, newsp, regs, 0, NULL, NULL);
	154	}
	155
	156	int
6f2c55b8	157	copy_thread(unsigned long clone_flags,
1394f032 BW	158	unsigned long usp, unsigned long topstk,
	159	struct task_struct p, struct pt_regs regs)
	160	{
	161	struct pt_regs *childregs;
ee1e17c6	162	unsigned long *v;
1394f032 BW	163
1394f032 BW	164	childregs = (struct pt_regs *) (task_stack_page(p) + THREAD_SIZE) - 1;
ee1e17c6 AV	165	v = ((unsigned long *)childregs) - 2;
	166	if (unlikely(!regs)) {
	167	memset(childregs, 0, sizeof(struct pt_regs));
	168	v[0] = usp;
	169	v[1] = topstk;
	170	childregs->orig_p0 = -1;
	171	childregs->ipend = 0x8000;
	172	__asm__ __volatile__("%0 = syscfg;":"=da"(childregs->syscfg):);
	173	p->thread.usp = 0;
	174	} else {
	175	childregs = regs;
	176	childregs->r0 = 0;
	177	p->thread.usp = usp;
	178	v[0] = v[1] = 0;
	179	}
1394f032	180
ee1e17c6	181	p->thread.ksp = (unsigned long)v;
1394f032 BW	182	p->thread.pc = (unsigned long)ret_from_fork;
	183
	184	return 0;
	185	}
	186
1394f032 BW	187	unsigned long get_wchan(struct task_struct *p)
	188	{
	189	unsigned long fp, pc;
	190	unsigned long stack_page;
	191	int count = 0;
	192	if (!p \|\| p == current \|\| p->state == TASK_RUNNING)
	193	return 0;
	194
	195	stack_page = (unsigned long)p;
	196	fp = p->thread.usp;
	197	do {
	198	if (fp < stack_page + sizeof(struct thread_info) \|\|
	199	fp >= 8184 + stack_page)
	200	return 0;
	201	pc = ((unsigned long *)fp)[1];
	202	if (!in_sched_functions(pc))
	203	return pc;
	204	fp = (unsigned long )fp;
	205	}
	206	while (count++ < 16);
	207	return 0;
	208	}
	209
7adfb58f BS	210	void finish_atomic_sections (struct pt_regs *regs)
7adfb58f BS	211	{
19d6d7d5	212	int __user up0 = (int __user )regs->p0;
0ddeeca2	213
7adfb58f	214	switch (regs->pc) {
2f5a0864 MF	215	default:
	216	/* not in middle of an atomic step, so resume like normal */
	217	return;
	218
7adfb58f	219	case ATOMIC_XCHG32 + 2:
0ddeeca2	220	put_user(regs->r1, up0);
7adfb58f BS	221	break;
	222
	223	case ATOMIC_CAS32 + 2:
	224	case ATOMIC_CAS32 + 4:
	225	if (regs->r0 == regs->r1)
92649494	226	case ATOMIC_CAS32 + 6:
0ddeeca2	227	put_user(regs->r2, up0);
7adfb58f	228	break;
7adfb58f BS	229
	230	case ATOMIC_ADD32 + 2:
	231	regs->r0 = regs->r1 + regs->r0;
	232	/* fall through */
	233	case ATOMIC_ADD32 + 4:
0ddeeca2	234	put_user(regs->r0, up0);
7adfb58f BS	235	break;
	236
	237	case ATOMIC_SUB32 + 2:
	238	regs->r0 = regs->r1 - regs->r0;
	239	/* fall through */
	240	case ATOMIC_SUB32 + 4:
0ddeeca2	241	put_user(regs->r0, up0);
7adfb58f BS	242	break;
	243
	244	case ATOMIC_IOR32 + 2:
	245	regs->r0 = regs->r1 \| regs->r0;
	246	/* fall through */
	247	case ATOMIC_IOR32 + 4:
0ddeeca2	248	put_user(regs->r0, up0);
7adfb58f BS	249	break;
	250
	251	case ATOMIC_AND32 + 2:
	252	regs->r0 = regs->r1 & regs->r0;
	253	/* fall through */
	254	case ATOMIC_AND32 + 4:
0ddeeca2	255	put_user(regs->r0, up0);
7adfb58f BS	256	break;
	257
	258	case ATOMIC_XOR32 + 2:
	259	regs->r0 = regs->r1 ^ regs->r0;
	260	/* fall through */
	261	case ATOMIC_XOR32 + 4:
0ddeeca2	262	put_user(regs->r0, up0);
7adfb58f BS	263	break;
7adfb58f BS	264	}
2f5a0864 MF	265
	266	/*
	267	* We've finished the atomic section, and the only thing left for
	268	* userspace is to do a RTS, so we might as well handle that too
	269	* since we need to update the PC anyways.
	270	*/
	271	regs->pc = regs->rets;
7adfb58f BS	272	}
7adfb58f BS	273
e56e03b0 MF	274	static inline
	275	int in_mem(unsigned long addr, unsigned long size,
	276	unsigned long start, unsigned long end)
	277	{
	278	return addr >= start && addr + size <= end;
	279	}
	280	static inline
	281	int in_mem_const_off(unsigned long addr, unsigned long size, unsigned long off,
	282	unsigned long const_addr, unsigned long const_size)
	283	{
	284	return const_size &&
	285	in_mem(addr, size, const_addr + off, const_addr + const_size);
	286	}
	287	static inline
	288	int in_mem_const(unsigned long addr, unsigned long size,
	289	unsigned long const_addr, unsigned long const_size)
	290	{
fb4b5d3a	291	return in_mem_const_off(addr, size, 0, const_addr, const_size);
e56e03b0	292	}
b5affb01 BL	293	#ifdef CONFIG_BF60x
	294	#define ASYNC_ENABLED(bnum, bctlnum) 1
	295	#else
13048f88	296	#define ASYNC_ENABLED(bnum, bctlnum) \
e56e03b0	297	({ \
13048f88 BS	298	(bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
	299	bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
	300	1; \
e56e03b0	301	})
b5affb01	302	#endif
13048f88 BS	303	/*
	304	* We can't read EBIU banks that aren't enabled or we end up hanging
	305	* on the access to the async space. Make sure we validate accesses
	306	* that cross async banks too.
	307	* 0 - found, but unusable
	308	* 1 - found & usable
	309	* 2 - not found
	310	*/
	311	static
	312	int in_async(unsigned long addr, unsigned long size)
	313	{
	314	if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) {
	315	if (!ASYNC_ENABLED(0, 0))
	316	return 0;
	317	if (addr + size <= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE)
	318	return 1;
	319	size -= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE - addr;
	320	addr = ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE;
	321	}
	322	if (addr >= ASYNC_BANK1_BASE && addr < ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE) {
	323	if (!ASYNC_ENABLED(1, 0))
	324	return 0;
	325	if (addr + size <= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE)
	326	return 1;
	327	size -= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE - addr;
	328	addr = ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE;
	329	}
	330	if (addr >= ASYNC_BANK2_BASE && addr < ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE) {
	331	if (!ASYNC_ENABLED(2, 1))
	332	return 0;
	333	if (addr + size <= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE)
	334	return 1;
	335	size -= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE - addr;
	336	addr = ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE;
	337	}
	338	if (addr >= ASYNC_BANK3_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
	339	if (ASYNC_ENABLED(3, 1))
	340	return 0;
	341	if (addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
	342	return 1;
	343	return 0;
	344	}
	345
	346	/* not within async bounds */
	347	return 2;
	348	}
e56e03b0 MF	349
	350	int bfin_mem_access_type(unsigned long addr, unsigned long size)
	351	{
	352	int cpu = raw_smp_processor_id();
	353
	354	/* Check that things do not wrap around */
	355	if (addr > ULONG_MAX - size)
	356	return -EFAULT;
	357
	358	if (in_mem(addr, size, FIXED_CODE_START, physical_mem_end))
	359	return BFIN_MEM_ACCESS_CORE;
	360
	361	if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
	362	return cpu == 0 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
	363	if (in_mem_const(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH))
	364	return cpu == 0 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
	365	if (in_mem_const(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH))
	366	return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
	367	if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH))
	368	return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
	369	#ifdef COREB_L1_CODE_START
fb4b5d3a	370	if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
e56e03b0 MF	371	return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
	372	if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
	373	return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
fb4b5d3a	374	if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
e56e03b0	375	return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
fb4b5d3a	376	if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
e56e03b0 MF	377	return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
	378	#endif
	379	if (in_mem_const(addr, size, L2_START, L2_LENGTH))
	380	return BFIN_MEM_ACCESS_CORE;
	381
	382	if (addr >= SYSMMR_BASE)
	383	return BFIN_MEM_ACCESS_CORE_ONLY;
	384
13048f88 BS	385	switch (in_async(addr, size)) {
	386	case 0: return -EFAULT;
	387	case 1: return BFIN_MEM_ACCESS_CORE;
	388	case 2: /* fall through */;
	389	}
e56e03b0 MF	390
	391	if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
	392	return BFIN_MEM_ACCESS_CORE;
	393	if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
	394	return BFIN_MEM_ACCESS_DMA;
	395
	396	return -EFAULT;
	397	}
	398
1394f032	399	#if defined(CONFIG_ACCESS_CHECK)
a43b739f MF	400	#ifdef CONFIG_ACCESS_OK_L1
	401	__attribute__((l1_text))
	402	#endif
b03b08ba	403	/* Return 1 if access to memory range is OK, 0 otherwise */
1394f032 BW	404	int _access_ok(unsigned long addr, unsigned long size)
1394f032 BW	405	{
13048f88 BS	406	int aret;
13048f88 BS	407
bc41bb11 BS	408	if (size == 0)
bc41bb11 BS	409	return 1;
e56e03b0 MF	410	/* Check that things do not wrap around */
e56e03b0 MF	411	if (addr > ULONG_MAX - size)
1394f032	412	return 0;
1f83b8f1	413	if (segment_eq(get_fs(), KERNEL_DS))
1394f032 BW	414	return 1;
1394f032 BW	415	#ifdef CONFIG_MTD_UCLINUX
e56e03b0 MF	416	if (1)
	417	#else
	418	if (0)
	419	#endif
	420	{
	421	if (in_mem(addr, size, memory_start, memory_end))
	422	return 1;
	423	if (in_mem(addr, size, memory_mtd_end, physical_mem_end))
	424	return 1;
	425	# ifndef CONFIG_ROMFS_ON_MTD
	426	if (0)
	427	# endif
	428	/* For XIP, allow user space to use pointers within the ROMFS. */
	429	if (in_mem(addr, size, memory_mtd_start, memory_mtd_end))
	430	return 1;
	431	} else {
	432	if (in_mem(addr, size, memory_start, physical_mem_end))
	433	return 1;
	434	}
	435
	436	if (in_mem(addr, size, (unsigned long)__init_begin, (unsigned long)__init_end))
1394f032	437	return 1;
d5adb029	438
e56e03b0	439	if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
d5adb029	440	return 1;
e56e03b0	441	if (in_mem_const_off(addr, size, _etext_l1 - _stext_l1, L1_CODE_START, L1_CODE_LENGTH))
1394f032	442	return 1;
e56e03b0	443	if (in_mem_const_off(addr, size, _ebss_l1 - _sdata_l1, L1_DATA_A_START, L1_DATA_A_LENGTH))
1394f032	444	return 1;
e56e03b0	445	if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH))
1394f032	446	return 1;
e56e03b0	447	#ifdef COREB_L1_CODE_START
fb4b5d3a	448	if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
1394f032	449	return 1;
e56e03b0	450	if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
1394f032	451	return 1;
fb4b5d3a	452	if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
1394f032	453	return 1;
fb4b5d3a	454	if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
b2c2f303	455	return 1;
1394f032	456	#endif
13048f88	457
41c3e334 BS	458	#ifndef CONFIG_EXCEPTION_L1_SCRATCH
	459	if (in_mem_const(addr, size, (unsigned long)l1_stack_base, l1_stack_len))
	460	return 1;
	461	#endif
	462
13048f88 BS	463	aret = in_async(addr, size);
	464	if (aret < 2)
	465	return aret;
	466
e56e03b0 MF	467	if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH))
	468	return 1;
	469
	470	if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
	471	return 1;
	472	if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
	473	return 1;
	474
1394f032 BW	475	return 0;
	476	}
	477	EXPORT_SYMBOL(_access_ok);
	478	#endif /* CONFIG_ACCESS_CHECK */