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1394f032 | 1 | /* |
96f1050d | 2 | * Copyright 2004-2009 Analog Devices Inc. |
1394f032 | 3 | * |
550d5538 | 4 | * Licensed under the GPL-2 or later. |
1394f032 BW |
5 | */ |
6 | ||
7 | #include <linux/delay.h> | |
8 | #include <linux/console.h> | |
9 | #include <linux/bootmem.h> | |
10 | #include <linux/seq_file.h> | |
11 | #include <linux/cpu.h> | |
259fea42 | 12 | #include <linux/mm.h> |
1394f032 | 13 | #include <linux/module.h> |
1394f032 | 14 | #include <linux/tty.h> |
856783b3 | 15 | #include <linux/pfn.h> |
1394f032 | 16 | |
79df1b69 MF |
17 | #ifdef CONFIG_MTD_UCLINUX |
18 | #include <linux/mtd/map.h> | |
1394f032 BW |
19 | #include <linux/ext2_fs.h> |
20 | #include <linux/cramfs_fs.h> | |
21 | #include <linux/romfs_fs.h> | |
79df1b69 | 22 | #endif |
1394f032 | 23 | |
3bebca2d | 24 | #include <asm/cplb.h> |
1394f032 BW |
25 | #include <asm/cacheflush.h> |
26 | #include <asm/blackfin.h> | |
27 | #include <asm/cplbinit.h> | |
1754a5d9 | 28 | #include <asm/div64.h> |
8f65873e | 29 | #include <asm/cpu.h> |
7adfb58f | 30 | #include <asm/fixed_code.h> |
ce3afa1c | 31 | #include <asm/early_printk.h> |
1394f032 | 32 | |
a9c59c27 | 33 | u16 _bfin_swrst; |
d45118b1 | 34 | EXPORT_SYMBOL(_bfin_swrst); |
a9c59c27 | 35 | |
1394f032 | 36 | unsigned long memory_start, memory_end, physical_mem_end; |
3132b586 | 37 | unsigned long _rambase, _ramstart, _ramend; |
1394f032 BW |
38 | unsigned long reserved_mem_dcache_on; |
39 | unsigned long reserved_mem_icache_on; | |
40 | EXPORT_SYMBOL(memory_start); | |
41 | EXPORT_SYMBOL(memory_end); | |
42 | EXPORT_SYMBOL(physical_mem_end); | |
43 | EXPORT_SYMBOL(_ramend); | |
58c35bd3 | 44 | EXPORT_SYMBOL(reserved_mem_dcache_on); |
1394f032 BW |
45 | |
46 | #ifdef CONFIG_MTD_UCLINUX | |
79df1b69 | 47 | extern struct map_info uclinux_ram_map; |
1394f032 BW |
48 | unsigned long memory_mtd_end, memory_mtd_start, mtd_size; |
49 | unsigned long _ebss; | |
50 | EXPORT_SYMBOL(memory_mtd_end); | |
51 | EXPORT_SYMBOL(memory_mtd_start); | |
52 | EXPORT_SYMBOL(mtd_size); | |
53 | #endif | |
54 | ||
5e10b4a6 | 55 | char __initdata command_line[COMMAND_LINE_SIZE]; |
0c7a6b21 RG |
56 | void __initdata *init_retx, *init_saved_retx, *init_saved_seqstat, |
57 | *init_saved_icplb_fault_addr, *init_saved_dcplb_fault_addr; | |
1394f032 | 58 | |
856783b3 YL |
59 | /* boot memmap, for parsing "memmap=" */ |
60 | #define BFIN_MEMMAP_MAX 128 /* number of entries in bfin_memmap */ | |
61 | #define BFIN_MEMMAP_RAM 1 | |
62 | #define BFIN_MEMMAP_RESERVED 2 | |
af4c7d4b | 63 | static struct bfin_memmap { |
856783b3 YL |
64 | int nr_map; |
65 | struct bfin_memmap_entry { | |
66 | unsigned long long addr; /* start of memory segment */ | |
67 | unsigned long long size; | |
68 | unsigned long type; | |
69 | } map[BFIN_MEMMAP_MAX]; | |
70 | } bfin_memmap __initdata; | |
71 | ||
72 | /* for memmap sanitization */ | |
73 | struct change_member { | |
74 | struct bfin_memmap_entry *pentry; /* pointer to original entry */ | |
75 | unsigned long long addr; /* address for this change point */ | |
76 | }; | |
77 | static struct change_member change_point_list[2*BFIN_MEMMAP_MAX] __initdata; | |
78 | static struct change_member *change_point[2*BFIN_MEMMAP_MAX] __initdata; | |
79 | static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata; | |
80 | static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata; | |
81 | ||
8f65873e GY |
82 | DEFINE_PER_CPU(struct blackfin_cpudata, cpu_data); |
83 | ||
7f1e2f98 MF |
84 | static int early_init_clkin_hz(char *buf); |
85 | ||
3bebca2d | 86 | #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) |
8f65873e GY |
87 | void __init generate_cplb_tables(void) |
88 | { | |
89 | unsigned int cpu; | |
90 | ||
dbdf20db | 91 | generate_cplb_tables_all(); |
8f65873e GY |
92 | /* Generate per-CPU I&D CPLB tables */ |
93 | for (cpu = 0; cpu < num_possible_cpus(); ++cpu) | |
94 | generate_cplb_tables_cpu(cpu); | |
95 | } | |
1394f032 BW |
96 | #endif |
97 | ||
8f65873e GY |
98 | void __cpuinit bfin_setup_caches(unsigned int cpu) |
99 | { | |
3bebca2d | 100 | #ifdef CONFIG_BFIN_ICACHE |
8f65873e | 101 | bfin_icache_init(icplb_tbl[cpu]); |
1394f032 BW |
102 | #endif |
103 | ||
3bebca2d | 104 | #ifdef CONFIG_BFIN_DCACHE |
8f65873e | 105 | bfin_dcache_init(dcplb_tbl[cpu]); |
8f65873e GY |
106 | #endif |
107 | ||
108 | /* | |
109 | * In cache coherence emulation mode, we need to have the | |
110 | * D-cache enabled before running any atomic operation which | |
05d17dfa | 111 | * might involve cache invalidation (i.e. spinlock, rwlock). |
8f65873e GY |
112 | * So printk's are deferred until then. |
113 | */ | |
114 | #ifdef CONFIG_BFIN_ICACHE | |
115 | printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu); | |
41ba653f JZ |
116 | printk(KERN_INFO " External memory:" |
117 | # ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE | |
118 | " cacheable" | |
119 | # else | |
120 | " uncacheable" | |
121 | # endif | |
122 | " in instruction cache\n"); | |
123 | if (L2_LENGTH) | |
124 | printk(KERN_INFO " L2 SRAM :" | |
125 | # ifdef CONFIG_BFIN_L2_ICACHEABLE | |
126 | " cacheable" | |
127 | # else | |
128 | " uncacheable" | |
129 | # endif | |
130 | " in instruction cache\n"); | |
131 | ||
132 | #else | |
133 | printk(KERN_INFO "Instruction Cache Disabled for CPU%u\n", cpu); | |
8f65873e | 134 | #endif |
41ba653f | 135 | |
8f65873e | 136 | #ifdef CONFIG_BFIN_DCACHE |
41ba653f JZ |
137 | printk(KERN_INFO "Data Cache Enabled for CPU%u\n", cpu); |
138 | printk(KERN_INFO " External memory:" | |
139 | # if defined CONFIG_BFIN_EXTMEM_WRITEBACK | |
140 | " cacheable (write-back)" | |
141 | # elif defined CONFIG_BFIN_EXTMEM_WRITETHROUGH | |
142 | " cacheable (write-through)" | |
143 | # else | |
144 | " uncacheable" | |
145 | # endif | |
146 | " in data cache\n"); | |
147 | if (L2_LENGTH) | |
148 | printk(KERN_INFO " L2 SRAM :" | |
149 | # if defined CONFIG_BFIN_L2_WRITEBACK | |
150 | " cacheable (write-back)" | |
151 | # elif defined CONFIG_BFIN_L2_WRITETHROUGH | |
152 | " cacheable (write-through)" | |
153 | # else | |
154 | " uncacheable" | |
1394f032 | 155 | # endif |
41ba653f JZ |
156 | " in data cache\n"); |
157 | #else | |
158 | printk(KERN_INFO "Data Cache Disabled for CPU%u\n", cpu); | |
1394f032 BW |
159 | #endif |
160 | } | |
161 | ||
8f65873e GY |
162 | void __cpuinit bfin_setup_cpudata(unsigned int cpu) |
163 | { | |
164 | struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu); | |
165 | ||
166 | cpudata->idle = current; | |
8f65873e GY |
167 | cpudata->imemctl = bfin_read_IMEM_CONTROL(); |
168 | cpudata->dmemctl = bfin_read_DMEM_CONTROL(); | |
169 | } | |
170 | ||
171 | void __init bfin_cache_init(void) | |
172 | { | |
173 | #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) | |
174 | generate_cplb_tables(); | |
175 | #endif | |
176 | bfin_setup_caches(0); | |
177 | } | |
178 | ||
5b04f271 | 179 | void __init bfin_relocate_l1_mem(void) |
1394f032 | 180 | { |
5cd82a6d MF |
181 | unsigned long text_l1_len = (unsigned long)_text_l1_len; |
182 | unsigned long data_l1_len = (unsigned long)_data_l1_len; | |
183 | unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len; | |
184 | unsigned long l2_len = (unsigned long)_l2_len; | |
1394f032 | 185 | |
837ec2d5 RG |
186 | early_shadow_stamp(); |
187 | ||
fecbd736 RG |
188 | /* |
189 | * due to the ALIGN(4) in the arch/blackfin/kernel/vmlinux.lds.S | |
190 | * we know that everything about l1 text/data is nice and aligned, | |
191 | * so copy by 4 byte chunks, and don't worry about overlapping | |
192 | * src/dest. | |
193 | * | |
194 | * We can't use the dma_memcpy functions, since they can call | |
195 | * scheduler functions which might be in L1 :( and core writes | |
196 | * into L1 instruction cause bad access errors, so we are stuck, | |
197 | * we are required to use DMA, but can't use the common dma | |
198 | * functions. We can't use memcpy either - since that might be | |
199 | * going to be in the relocated L1 | |
200 | */ | |
201 | ||
dd3dd384 MF |
202 | blackfin_dma_early_init(); |
203 | ||
5cd82a6d MF |
204 | /* if necessary, copy L1 text to L1 instruction SRAM */ |
205 | if (L1_CODE_LENGTH && text_l1_len) | |
206 | early_dma_memcpy(_stext_l1, _text_l1_lma, text_l1_len); | |
1394f032 | 207 | |
5cd82a6d MF |
208 | /* if necessary, copy L1 data to L1 data bank A SRAM */ |
209 | if (L1_DATA_A_LENGTH && data_l1_len) | |
210 | early_dma_memcpy(_sdata_l1, _data_l1_lma, data_l1_len); | |
1394f032 | 211 | |
5cd82a6d MF |
212 | /* if necessary, copy L1 data B to L1 data bank B SRAM */ |
213 | if (L1_DATA_B_LENGTH && data_b_l1_len) | |
214 | early_dma_memcpy(_sdata_b_l1, _data_b_l1_lma, data_b_l1_len); | |
262c3825 | 215 | |
fecbd736 RG |
216 | early_dma_memcpy_done(); |
217 | ||
5cd82a6d MF |
218 | /* if necessary, copy L2 text/data to L2 SRAM */ |
219 | if (L2_LENGTH && l2_len) | |
220 | memcpy(_stext_l2, _l2_lma, l2_len); | |
1394f032 BW |
221 | } |
222 | ||
856783b3 YL |
223 | /* add_memory_region to memmap */ |
224 | static void __init add_memory_region(unsigned long long start, | |
225 | unsigned long long size, int type) | |
226 | { | |
227 | int i; | |
228 | ||
229 | i = bfin_memmap.nr_map; | |
230 | ||
231 | if (i == BFIN_MEMMAP_MAX) { | |
232 | printk(KERN_ERR "Ooops! Too many entries in the memory map!\n"); | |
233 | return; | |
234 | } | |
235 | ||
236 | bfin_memmap.map[i].addr = start; | |
237 | bfin_memmap.map[i].size = size; | |
238 | bfin_memmap.map[i].type = type; | |
239 | bfin_memmap.nr_map++; | |
240 | } | |
241 | ||
242 | /* | |
243 | * Sanitize the boot memmap, removing overlaps. | |
244 | */ | |
245 | static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map) | |
246 | { | |
247 | struct change_member *change_tmp; | |
248 | unsigned long current_type, last_type; | |
249 | unsigned long long last_addr; | |
250 | int chgidx, still_changing; | |
251 | int overlap_entries; | |
252 | int new_entry; | |
253 | int old_nr, new_nr, chg_nr; | |
254 | int i; | |
255 | ||
256 | /* | |
257 | Visually we're performing the following (1,2,3,4 = memory types) | |
258 | ||
259 | Sample memory map (w/overlaps): | |
260 | ____22__________________ | |
261 | ______________________4_ | |
262 | ____1111________________ | |
263 | _44_____________________ | |
264 | 11111111________________ | |
265 | ____________________33__ | |
266 | ___________44___________ | |
267 | __________33333_________ | |
268 | ______________22________ | |
269 | ___________________2222_ | |
270 | _________111111111______ | |
271 | _____________________11_ | |
272 | _________________4______ | |
273 | ||
274 | Sanitized equivalent (no overlap): | |
275 | 1_______________________ | |
276 | _44_____________________ | |
277 | ___1____________________ | |
278 | ____22__________________ | |
279 | ______11________________ | |
280 | _________1______________ | |
281 | __________3_____________ | |
282 | ___________44___________ | |
283 | _____________33_________ | |
284 | _______________2________ | |
285 | ________________1_______ | |
286 | _________________4______ | |
287 | ___________________2____ | |
288 | ____________________33__ | |
289 | ______________________4_ | |
290 | */ | |
291 | /* if there's only one memory region, don't bother */ | |
292 | if (*pnr_map < 2) | |
293 | return -1; | |
294 | ||
295 | old_nr = *pnr_map; | |
296 | ||
297 | /* bail out if we find any unreasonable addresses in memmap */ | |
298 | for (i = 0; i < old_nr; i++) | |
299 | if (map[i].addr + map[i].size < map[i].addr) | |
300 | return -1; | |
301 | ||
302 | /* create pointers for initial change-point information (for sorting) */ | |
303 | for (i = 0; i < 2*old_nr; i++) | |
304 | change_point[i] = &change_point_list[i]; | |
305 | ||
306 | /* record all known change-points (starting and ending addresses), | |
307 | omitting those that are for empty memory regions */ | |
308 | chgidx = 0; | |
8f65873e | 309 | for (i = 0; i < old_nr; i++) { |
856783b3 YL |
310 | if (map[i].size != 0) { |
311 | change_point[chgidx]->addr = map[i].addr; | |
312 | change_point[chgidx++]->pentry = &map[i]; | |
313 | change_point[chgidx]->addr = map[i].addr + map[i].size; | |
314 | change_point[chgidx++]->pentry = &map[i]; | |
315 | } | |
316 | } | |
8f65873e | 317 | chg_nr = chgidx; /* true number of change-points */ |
856783b3 YL |
318 | |
319 | /* sort change-point list by memory addresses (low -> high) */ | |
320 | still_changing = 1; | |
8f65873e | 321 | while (still_changing) { |
856783b3 | 322 | still_changing = 0; |
8f65873e | 323 | for (i = 1; i < chg_nr; i++) { |
856783b3 YL |
324 | /* if <current_addr> > <last_addr>, swap */ |
325 | /* or, if current=<start_addr> & last=<end_addr>, swap */ | |
326 | if ((change_point[i]->addr < change_point[i-1]->addr) || | |
327 | ((change_point[i]->addr == change_point[i-1]->addr) && | |
328 | (change_point[i]->addr == change_point[i]->pentry->addr) && | |
329 | (change_point[i-1]->addr != change_point[i-1]->pentry->addr)) | |
330 | ) { | |
331 | change_tmp = change_point[i]; | |
332 | change_point[i] = change_point[i-1]; | |
333 | change_point[i-1] = change_tmp; | |
334 | still_changing = 1; | |
335 | } | |
336 | } | |
337 | } | |
338 | ||
339 | /* create a new memmap, removing overlaps */ | |
8f65873e GY |
340 | overlap_entries = 0; /* number of entries in the overlap table */ |
341 | new_entry = 0; /* index for creating new memmap entries */ | |
342 | last_type = 0; /* start with undefined memory type */ | |
343 | last_addr = 0; /* start with 0 as last starting address */ | |
856783b3 YL |
344 | /* loop through change-points, determining affect on the new memmap */ |
345 | for (chgidx = 0; chgidx < chg_nr; chgidx++) { | |
346 | /* keep track of all overlapping memmap entries */ | |
347 | if (change_point[chgidx]->addr == change_point[chgidx]->pentry->addr) { | |
348 | /* add map entry to overlap list (> 1 entry implies an overlap) */ | |
349 | overlap_list[overlap_entries++] = change_point[chgidx]->pentry; | |
350 | } else { | |
351 | /* remove entry from list (order independent, so swap with last) */ | |
352 | for (i = 0; i < overlap_entries; i++) { | |
353 | if (overlap_list[i] == change_point[chgidx]->pentry) | |
354 | overlap_list[i] = overlap_list[overlap_entries-1]; | |
355 | } | |
356 | overlap_entries--; | |
357 | } | |
358 | /* if there are overlapping entries, decide which "type" to use */ | |
359 | /* (larger value takes precedence -- 1=usable, 2,3,4,4+=unusable) */ | |
360 | current_type = 0; | |
361 | for (i = 0; i < overlap_entries; i++) | |
362 | if (overlap_list[i]->type > current_type) | |
363 | current_type = overlap_list[i]->type; | |
364 | /* continue building up new memmap based on this information */ | |
8f65873e | 365 | if (current_type != last_type) { |
856783b3 YL |
366 | if (last_type != 0) { |
367 | new_map[new_entry].size = | |
368 | change_point[chgidx]->addr - last_addr; | |
369 | /* move forward only if the new size was non-zero */ | |
370 | if (new_map[new_entry].size != 0) | |
371 | if (++new_entry >= BFIN_MEMMAP_MAX) | |
8f65873e | 372 | break; /* no more space left for new entries */ |
856783b3 YL |
373 | } |
374 | if (current_type != 0) { | |
375 | new_map[new_entry].addr = change_point[chgidx]->addr; | |
376 | new_map[new_entry].type = current_type; | |
377 | last_addr = change_point[chgidx]->addr; | |
378 | } | |
379 | last_type = current_type; | |
380 | } | |
381 | } | |
8f65873e | 382 | new_nr = new_entry; /* retain count for new entries */ |
856783b3 | 383 | |
8f65873e | 384 | /* copy new mapping into original location */ |
856783b3 YL |
385 | memcpy(map, new_map, new_nr*sizeof(struct bfin_memmap_entry)); |
386 | *pnr_map = new_nr; | |
387 | ||
388 | return 0; | |
389 | } | |
390 | ||
391 | static void __init print_memory_map(char *who) | |
392 | { | |
393 | int i; | |
394 | ||
395 | for (i = 0; i < bfin_memmap.nr_map; i++) { | |
396 | printk(KERN_DEBUG " %s: %016Lx - %016Lx ", who, | |
397 | bfin_memmap.map[i].addr, | |
398 | bfin_memmap.map[i].addr + bfin_memmap.map[i].size); | |
399 | switch (bfin_memmap.map[i].type) { | |
400 | case BFIN_MEMMAP_RAM: | |
ad361c98 JP |
401 | printk(KERN_CONT "(usable)\n"); |
402 | break; | |
856783b3 | 403 | case BFIN_MEMMAP_RESERVED: |
ad361c98 JP |
404 | printk(KERN_CONT "(reserved)\n"); |
405 | break; | |
406 | default: | |
407 | printk(KERN_CONT "type %lu\n", bfin_memmap.map[i].type); | |
408 | break; | |
856783b3 YL |
409 | } |
410 | } | |
411 | } | |
412 | ||
413 | static __init int parse_memmap(char *arg) | |
414 | { | |
415 | unsigned long long start_at, mem_size; | |
416 | ||
417 | if (!arg) | |
418 | return -EINVAL; | |
419 | ||
420 | mem_size = memparse(arg, &arg); | |
421 | if (*arg == '@') { | |
422 | start_at = memparse(arg+1, &arg); | |
423 | add_memory_region(start_at, mem_size, BFIN_MEMMAP_RAM); | |
424 | } else if (*arg == '$') { | |
425 | start_at = memparse(arg+1, &arg); | |
426 | add_memory_region(start_at, mem_size, BFIN_MEMMAP_RESERVED); | |
427 | } | |
428 | ||
429 | return 0; | |
430 | } | |
431 | ||
1394f032 BW |
432 | /* |
433 | * Initial parsing of the command line. Currently, we support: | |
434 | * - Controlling the linux memory size: mem=xxx[KMG] | |
435 | * - Controlling the physical memory size: max_mem=xxx[KMG][$][#] | |
436 | * $ -> reserved memory is dcacheable | |
437 | * # -> reserved memory is icacheable | |
856783b3 YL |
438 | * - "memmap=XXX[KkmM][@][$]XXX[KkmM]" defines a memory region |
439 | * @ from <start> to <start>+<mem>, type RAM | |
440 | * $ from <start> to <start>+<mem>, type RESERVED | |
1394f032 BW |
441 | */ |
442 | static __init void parse_cmdline_early(char *cmdline_p) | |
443 | { | |
444 | char c = ' ', *to = cmdline_p; | |
445 | unsigned int memsize; | |
446 | for (;;) { | |
447 | if (c == ' ') { | |
1394f032 BW |
448 | if (!memcmp(to, "mem=", 4)) { |
449 | to += 4; | |
450 | memsize = memparse(to, &to); | |
451 | if (memsize) | |
452 | _ramend = memsize; | |
453 | ||
454 | } else if (!memcmp(to, "max_mem=", 8)) { | |
455 | to += 8; | |
456 | memsize = memparse(to, &to); | |
457 | if (memsize) { | |
458 | physical_mem_end = memsize; | |
459 | if (*to != ' ') { | |
460 | if (*to == '$' | |
461 | || *(to + 1) == '$') | |
8f65873e | 462 | reserved_mem_dcache_on = 1; |
1394f032 BW |
463 | if (*to == '#' |
464 | || *(to + 1) == '#') | |
8f65873e | 465 | reserved_mem_icache_on = 1; |
1394f032 BW |
466 | } |
467 | } | |
7f1e2f98 MF |
468 | } else if (!memcmp(to, "clkin_hz=", 9)) { |
469 | to += 9; | |
470 | early_init_clkin_hz(to); | |
bd854c07 | 471 | #ifdef CONFIG_EARLY_PRINTK |
ce3afa1c RG |
472 | } else if (!memcmp(to, "earlyprintk=", 12)) { |
473 | to += 12; | |
474 | setup_early_printk(to); | |
bd854c07 | 475 | #endif |
856783b3 YL |
476 | } else if (!memcmp(to, "memmap=", 7)) { |
477 | to += 7; | |
478 | parse_memmap(to); | |
1394f032 | 479 | } |
1394f032 BW |
480 | } |
481 | c = *(to++); | |
482 | if (!c) | |
483 | break; | |
484 | } | |
485 | } | |
486 | ||
856783b3 YL |
487 | /* |
488 | * Setup memory defaults from user config. | |
489 | * The physical memory layout looks like: | |
490 | * | |
491 | * [_rambase, _ramstart]: kernel image | |
492 | * [memory_start, memory_end]: dynamic memory managed by kernel | |
493 | * [memory_end, _ramend]: reserved memory | |
3094c981 | 494 | * [memory_mtd_start(memory_end), |
856783b3 YL |
495 | * memory_mtd_start + mtd_size]: rootfs (if any) |
496 | * [_ramend - DMA_UNCACHED_REGION, | |
497 | * _ramend]: uncached DMA region | |
498 | * [_ramend, physical_mem_end]: memory not managed by kernel | |
856783b3 | 499 | */ |
8f65873e | 500 | static __init void memory_setup(void) |
1394f032 | 501 | { |
c0eab3b7 MF |
502 | #ifdef CONFIG_MTD_UCLINUX |
503 | unsigned long mtd_phys = 0; | |
504 | #endif | |
2f812c0b | 505 | unsigned long max_mem; |
c0eab3b7 | 506 | |
856783b3 | 507 | _rambase = (unsigned long)_stext; |
b7627acc | 508 | _ramstart = (unsigned long)_end; |
1394f032 | 509 | |
856783b3 YL |
510 | if (DMA_UNCACHED_REGION > (_ramend - _ramstart)) { |
511 | console_init(); | |
d8804adf | 512 | panic("DMA region exceeds memory limit: %lu.", |
856783b3 | 513 | _ramend - _ramstart); |
1aafd909 | 514 | } |
2f812c0b RG |
515 | max_mem = memory_end = _ramend - DMA_UNCACHED_REGION; |
516 | ||
517 | #if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263) | |
518 | /* Due to a Hardware Anomaly we need to limit the size of usable | |
519 | * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on | |
520 | * 05000263 - Hardware loop corrupted when taking an ICPLB exception | |
521 | */ | |
522 | # if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO)) | |
523 | if (max_mem >= 56 * 1024 * 1024) | |
524 | max_mem = 56 * 1024 * 1024; | |
525 | # else | |
526 | if (max_mem >= 60 * 1024 * 1024) | |
527 | max_mem = 60 * 1024 * 1024; | |
528 | # endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */ | |
529 | #endif /* ANOMALY_05000263 */ | |
530 | ||
1394f032 | 531 | |
b97b8a99 | 532 | #ifdef CONFIG_MPU |
8f65873e | 533 | /* Round up to multiple of 4MB */ |
b97b8a99 BS |
534 | memory_start = (_ramstart + 0x3fffff) & ~0x3fffff; |
535 | #else | |
1394f032 | 536 | memory_start = PAGE_ALIGN(_ramstart); |
b97b8a99 | 537 | #endif |
1394f032 BW |
538 | |
539 | #if defined(CONFIG_MTD_UCLINUX) | |
540 | /* generic memory mapped MTD driver */ | |
541 | memory_mtd_end = memory_end; | |
542 | ||
543 | mtd_phys = _ramstart; | |
544 | mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8))); | |
545 | ||
546 | # if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS) | |
547 | if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC) | |
548 | mtd_size = | |
549 | PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10); | |
550 | # endif | |
551 | ||
552 | # if defined(CONFIG_CRAMFS) | |
553 | if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC) | |
554 | mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4))); | |
555 | # endif | |
556 | ||
557 | # if defined(CONFIG_ROMFS_FS) | |
558 | if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0 | |
2f812c0b | 559 | && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) { |
1394f032 BW |
560 | mtd_size = |
561 | PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2])); | |
2f812c0b RG |
562 | |
563 | /* ROM_FS is XIP, so if we found it, we need to limit memory */ | |
564 | if (memory_end > max_mem) { | |
565 | pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem >> 20); | |
566 | memory_end = max_mem; | |
567 | } | |
568 | } | |
1394f032 BW |
569 | # endif /* CONFIG_ROMFS_FS */ |
570 | ||
dc437b1b RG |
571 | /* Since the default MTD_UCLINUX has no magic number, we just blindly |
572 | * read 8 past the end of the kernel's image, and look at it. | |
573 | * When no image is attached, mtd_size is set to a random number | |
574 | * Do some basic sanity checks before operating on things | |
575 | */ | |
576 | if (mtd_size == 0 || memory_end <= mtd_size) { | |
577 | pr_emerg("Could not find valid ram mtd attached.\n"); | |
578 | } else { | |
579 | memory_end -= mtd_size; | |
580 | ||
581 | /* Relocate MTD image to the top of memory after the uncached memory area */ | |
582 | uclinux_ram_map.phys = memory_mtd_start = memory_end; | |
583 | uclinux_ram_map.size = mtd_size; | |
584 | pr_info("Found mtd parition at 0x%p, (len=0x%lx), moving to 0x%p\n", | |
585 | _end, mtd_size, (void *)memory_mtd_start); | |
586 | dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size); | |
1394f032 | 587 | } |
1394f032 BW |
588 | #endif /* CONFIG_MTD_UCLINUX */ |
589 | ||
2f812c0b RG |
590 | /* We need lo limit memory, since everything could have a text section |
591 | * of userspace in it, and expose anomaly 05000263. If the anomaly | |
592 | * doesn't exist, or we don't need to - then dont. | |
1394f032 | 593 | */ |
2f812c0b RG |
594 | if (memory_end > max_mem) { |
595 | pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem >> 20); | |
596 | memory_end = max_mem; | |
597 | } | |
1394f032 | 598 | |
b97b8a99 BS |
599 | #ifdef CONFIG_MPU |
600 | page_mask_nelts = ((_ramend >> PAGE_SHIFT) + 31) / 32; | |
601 | page_mask_order = get_order(3 * page_mask_nelts * sizeof(long)); | |
602 | #endif | |
603 | ||
1394f032 | 604 | #if !defined(CONFIG_MTD_UCLINUX) |
856783b3 YL |
605 | /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/ |
606 | memory_end -= SIZE_4K; | |
1394f032 | 607 | #endif |
856783b3 | 608 | |
1394f032 BW |
609 | init_mm.start_code = (unsigned long)_stext; |
610 | init_mm.end_code = (unsigned long)_etext; | |
611 | init_mm.end_data = (unsigned long)_edata; | |
612 | init_mm.brk = (unsigned long)0; | |
613 | ||
856783b3 YL |
614 | printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20); |
615 | printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20); | |
616 | ||
b7627acc | 617 | printk(KERN_INFO "Memory map:\n" |
ad361c98 JP |
618 | " fixedcode = 0x%p-0x%p\n" |
619 | " text = 0x%p-0x%p\n" | |
620 | " rodata = 0x%p-0x%p\n" | |
621 | " bss = 0x%p-0x%p\n" | |
622 | " data = 0x%p-0x%p\n" | |
623 | " stack = 0x%p-0x%p\n" | |
624 | " init = 0x%p-0x%p\n" | |
625 | " available = 0x%p-0x%p\n" | |
856783b3 | 626 | #ifdef CONFIG_MTD_UCLINUX |
ad361c98 | 627 | " rootfs = 0x%p-0x%p\n" |
856783b3 YL |
628 | #endif |
629 | #if DMA_UNCACHED_REGION > 0 | |
ad361c98 | 630 | " DMA Zone = 0x%p-0x%p\n" |
856783b3 | 631 | #endif |
8929ecf8 MF |
632 | , (void *)FIXED_CODE_START, (void *)FIXED_CODE_END, |
633 | _stext, _etext, | |
856783b3 | 634 | __start_rodata, __end_rodata, |
b7627acc | 635 | __bss_start, __bss_stop, |
856783b3 YL |
636 | _sdata, _edata, |
637 | (void *)&init_thread_union, | |
638 | (void *)((int)(&init_thread_union) + 0x2000), | |
b7627acc MF |
639 | __init_begin, __init_end, |
640 | (void *)_ramstart, (void *)memory_end | |
856783b3 YL |
641 | #ifdef CONFIG_MTD_UCLINUX |
642 | , (void *)memory_mtd_start, (void *)(memory_mtd_start + mtd_size) | |
643 | #endif | |
644 | #if DMA_UNCACHED_REGION > 0 | |
645 | , (void *)(_ramend - DMA_UNCACHED_REGION), (void *)(_ramend) | |
646 | #endif | |
647 | ); | |
648 | } | |
649 | ||
2e8d7965 YL |
650 | /* |
651 | * Find the lowest, highest page frame number we have available | |
652 | */ | |
653 | void __init find_min_max_pfn(void) | |
654 | { | |
655 | int i; | |
656 | ||
657 | max_pfn = 0; | |
658 | min_low_pfn = memory_end; | |
659 | ||
660 | for (i = 0; i < bfin_memmap.nr_map; i++) { | |
661 | unsigned long start, end; | |
662 | /* RAM? */ | |
663 | if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM) | |
664 | continue; | |
665 | start = PFN_UP(bfin_memmap.map[i].addr); | |
666 | end = PFN_DOWN(bfin_memmap.map[i].addr + | |
667 | bfin_memmap.map[i].size); | |
668 | if (start >= end) | |
669 | continue; | |
670 | if (end > max_pfn) | |
671 | max_pfn = end; | |
672 | if (start < min_low_pfn) | |
673 | min_low_pfn = start; | |
674 | } | |
675 | } | |
676 | ||
856783b3 YL |
677 | static __init void setup_bootmem_allocator(void) |
678 | { | |
679 | int bootmap_size; | |
680 | int i; | |
2e8d7965 | 681 | unsigned long start_pfn, end_pfn; |
856783b3 YL |
682 | unsigned long curr_pfn, last_pfn, size; |
683 | ||
684 | /* mark memory between memory_start and memory_end usable */ | |
685 | add_memory_region(memory_start, | |
686 | memory_end - memory_start, BFIN_MEMMAP_RAM); | |
687 | /* sanity check for overlap */ | |
688 | sanitize_memmap(bfin_memmap.map, &bfin_memmap.nr_map); | |
689 | print_memory_map("boot memmap"); | |
690 | ||
05d17dfa | 691 | /* initialize globals in linux/bootmem.h */ |
2e8d7965 YL |
692 | find_min_max_pfn(); |
693 | /* pfn of the last usable page frame */ | |
694 | if (max_pfn > memory_end >> PAGE_SHIFT) | |
695 | max_pfn = memory_end >> PAGE_SHIFT; | |
696 | /* pfn of last page frame directly mapped by kernel */ | |
697 | max_low_pfn = max_pfn; | |
698 | /* pfn of the first usable page frame after kernel image*/ | |
699 | if (min_low_pfn < memory_start >> PAGE_SHIFT) | |
700 | min_low_pfn = memory_start >> PAGE_SHIFT; | |
701 | ||
702 | start_pfn = PAGE_OFFSET >> PAGE_SHIFT; | |
703 | end_pfn = memory_end >> PAGE_SHIFT; | |
856783b3 YL |
704 | |
705 | /* | |
8f65873e | 706 | * give all the memory to the bootmap allocator, tell it to put the |
856783b3 YL |
707 | * boot mem_map at the start of memory. |
708 | */ | |
709 | bootmap_size = init_bootmem_node(NODE_DATA(0), | |
710 | memory_start >> PAGE_SHIFT, /* map goes here */ | |
2e8d7965 | 711 | start_pfn, end_pfn); |
856783b3 YL |
712 | |
713 | /* register the memmap regions with the bootmem allocator */ | |
714 | for (i = 0; i < bfin_memmap.nr_map; i++) { | |
715 | /* | |
716 | * Reserve usable memory | |
717 | */ | |
718 | if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM) | |
719 | continue; | |
720 | /* | |
721 | * We are rounding up the start address of usable memory: | |
722 | */ | |
723 | curr_pfn = PFN_UP(bfin_memmap.map[i].addr); | |
2e8d7965 | 724 | if (curr_pfn >= end_pfn) |
856783b3 YL |
725 | continue; |
726 | /* | |
727 | * ... and at the end of the usable range downwards: | |
728 | */ | |
729 | last_pfn = PFN_DOWN(bfin_memmap.map[i].addr + | |
730 | bfin_memmap.map[i].size); | |
731 | ||
2e8d7965 YL |
732 | if (last_pfn > end_pfn) |
733 | last_pfn = end_pfn; | |
856783b3 YL |
734 | |
735 | /* | |
736 | * .. finally, did all the rounding and playing | |
737 | * around just make the area go away? | |
738 | */ | |
739 | if (last_pfn <= curr_pfn) | |
740 | continue; | |
741 | ||
742 | size = last_pfn - curr_pfn; | |
743 | free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size)); | |
744 | } | |
745 | ||
746 | /* reserve memory before memory_start, including bootmap */ | |
747 | reserve_bootmem(PAGE_OFFSET, | |
748 | memory_start + bootmap_size + PAGE_SIZE - 1 - PAGE_OFFSET, | |
749 | BOOTMEM_DEFAULT); | |
750 | } | |
751 | ||
a086ee22 MF |
752 | #define EBSZ_TO_MEG(ebsz) \ |
753 | ({ \ | |
754 | int meg = 0; \ | |
755 | switch (ebsz & 0xf) { \ | |
756 | case 0x1: meg = 16; break; \ | |
757 | case 0x3: meg = 32; break; \ | |
758 | case 0x5: meg = 64; break; \ | |
759 | case 0x7: meg = 128; break; \ | |
760 | case 0x9: meg = 256; break; \ | |
761 | case 0xb: meg = 512; break; \ | |
762 | } \ | |
763 | meg; \ | |
764 | }) | |
765 | static inline int __init get_mem_size(void) | |
766 | { | |
99d95bbd MH |
767 | #if defined(EBIU_SDBCTL) |
768 | # if defined(BF561_FAMILY) | |
a086ee22 MF |
769 | int ret = 0; |
770 | u32 sdbctl = bfin_read_EBIU_SDBCTL(); | |
771 | ret += EBSZ_TO_MEG(sdbctl >> 0); | |
772 | ret += EBSZ_TO_MEG(sdbctl >> 8); | |
773 | ret += EBSZ_TO_MEG(sdbctl >> 16); | |
774 | ret += EBSZ_TO_MEG(sdbctl >> 24); | |
775 | return ret; | |
99d95bbd | 776 | # else |
a086ee22 | 777 | return EBSZ_TO_MEG(bfin_read_EBIU_SDBCTL()); |
99d95bbd MH |
778 | # endif |
779 | #elif defined(EBIU_DDRCTL1) | |
1e78042c MH |
780 | u32 ddrctl = bfin_read_EBIU_DDRCTL1(); |
781 | int ret = 0; | |
782 | switch (ddrctl & 0xc0000) { | |
783 | case DEVSZ_64: ret = 64 / 8; | |
784 | case DEVSZ_128: ret = 128 / 8; | |
785 | case DEVSZ_256: ret = 256 / 8; | |
786 | case DEVSZ_512: ret = 512 / 8; | |
787 | } | |
788 | switch (ddrctl & 0x30000) { | |
789 | case DEVWD_4: ret *= 2; | |
790 | case DEVWD_8: ret *= 2; | |
791 | case DEVWD_16: break; | |
a086ee22 | 792 | } |
b1b154e5 MF |
793 | if ((ddrctl & 0xc000) == 0x4000) |
794 | ret *= 2; | |
1e78042c | 795 | return ret; |
a086ee22 MF |
796 | #endif |
797 | BUG(); | |
798 | } | |
799 | ||
856783b3 YL |
800 | void __init setup_arch(char **cmdline_p) |
801 | { | |
9f8e895d | 802 | unsigned long sclk, cclk; |
856783b3 | 803 | |
3f871fea RG |
804 | enable_shadow_console(); |
805 | ||
bd854c07 RG |
806 | /* Check to make sure we are running on the right processor */ |
807 | if (unlikely(CPUID != bfin_cpuid())) | |
808 | printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n", | |
809 | CPU, bfin_cpuid(), bfin_revid()); | |
810 | ||
856783b3 YL |
811 | #ifdef CONFIG_DUMMY_CONSOLE |
812 | conswitchp = &dummy_con; | |
813 | #endif | |
814 | ||
815 | #if defined(CONFIG_CMDLINE_BOOL) | |
816 | strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line)); | |
817 | command_line[sizeof(command_line) - 1] = 0; | |
818 | #endif | |
819 | ||
820 | /* Keep a copy of command line */ | |
821 | *cmdline_p = &command_line[0]; | |
822 | memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE); | |
823 | boot_command_line[COMMAND_LINE_SIZE - 1] = '\0'; | |
824 | ||
856783b3 YL |
825 | memset(&bfin_memmap, 0, sizeof(bfin_memmap)); |
826 | ||
bd854c07 RG |
827 | /* If the user does not specify things on the command line, use |
828 | * what the bootloader set things up as | |
829 | */ | |
830 | physical_mem_end = 0; | |
856783b3 YL |
831 | parse_cmdline_early(&command_line[0]); |
832 | ||
bd854c07 RG |
833 | if (_ramend == 0) |
834 | _ramend = get_mem_size() * 1024 * 1024; | |
835 | ||
856783b3 YL |
836 | if (physical_mem_end == 0) |
837 | physical_mem_end = _ramend; | |
838 | ||
839 | memory_setup(); | |
840 | ||
7e64acab MF |
841 | /* Initialize Async memory banks */ |
842 | bfin_write_EBIU_AMBCTL0(AMBCTL0VAL); | |
843 | bfin_write_EBIU_AMBCTL1(AMBCTL1VAL); | |
844 | bfin_write_EBIU_AMGCTL(AMGCTLVAL); | |
845 | #ifdef CONFIG_EBIU_MBSCTLVAL | |
846 | bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTLVAL); | |
847 | bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL); | |
848 | bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL); | |
849 | #endif | |
850 | ||
856783b3 YL |
851 | cclk = get_cclk(); |
852 | sclk = get_sclk(); | |
853 | ||
7f3aee3c SZ |
854 | if ((ANOMALY_05000273 || ANOMALY_05000274) && (cclk >> 1) < sclk) |
855 | panic("ANOMALY 05000273 or 05000274: CCLK must be >= 2*SCLK"); | |
856783b3 YL |
856 | |
857 | #ifdef BF561_FAMILY | |
858 | if (ANOMALY_05000266) { | |
859 | bfin_read_IMDMA_D0_IRQ_STATUS(); | |
860 | bfin_read_IMDMA_D1_IRQ_STATUS(); | |
861 | } | |
862 | #endif | |
863 | printk(KERN_INFO "Hardware Trace "); | |
864 | if (bfin_read_TBUFCTL() & 0x1) | |
ad361c98 | 865 | printk(KERN_CONT "Active "); |
856783b3 | 866 | else |
ad361c98 | 867 | printk(KERN_CONT "Off "); |
856783b3 | 868 | if (bfin_read_TBUFCTL() & 0x2) |
ad361c98 | 869 | printk(KERN_CONT "and Enabled\n"); |
856783b3 | 870 | else |
ad361c98 | 871 | printk(KERN_CONT "and Disabled\n"); |
856783b3 | 872 | |
76e8fe4d RG |
873 | printk(KERN_INFO "Boot Mode: %i\n", bfin_read_SYSCR() & 0xF); |
874 | ||
ed1fb604 MF |
875 | /* Newer parts mirror SWRST bits in SYSCR */ |
876 | #if defined(CONFIG_BF53x) || defined(CONFIG_BF561) || \ | |
877 | defined(CONFIG_BF538) || defined(CONFIG_BF539) | |
7728ec33 | 878 | _bfin_swrst = bfin_read_SWRST(); |
ed1fb604 | 879 | #else |
0de4adfb SZ |
880 | /* Clear boot mode field */ |
881 | _bfin_swrst = bfin_read_SYSCR() & ~0xf; | |
ed1fb604 | 882 | #endif |
7728ec33 | 883 | |
0c7a6b21 RG |
884 | #ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT |
885 | bfin_write_SWRST(_bfin_swrst & ~DOUBLE_FAULT); | |
886 | #endif | |
887 | #ifdef CONFIG_DEBUG_DOUBLEFAULT_RESET | |
888 | bfin_write_SWRST(_bfin_swrst | DOUBLE_FAULT); | |
889 | #endif | |
2d200980 | 890 | |
8f65873e GY |
891 | #ifdef CONFIG_SMP |
892 | if (_bfin_swrst & SWRST_DBL_FAULT_A) { | |
893 | #else | |
0c7a6b21 | 894 | if (_bfin_swrst & RESET_DOUBLE) { |
8f65873e | 895 | #endif |
0c7a6b21 RG |
896 | printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n"); |
897 | #ifdef CONFIG_DEBUG_DOUBLEFAULT | |
898 | /* We assume the crashing kernel, and the current symbol table match */ | |
899 | printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n", | |
900 | (int)init_saved_seqstat & SEQSTAT_EXCAUSE, init_saved_retx); | |
901 | printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr); | |
902 | printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr); | |
903 | #endif | |
904 | printk(KERN_NOTICE " The instruction at %pF caused a double exception\n", | |
905 | init_retx); | |
906 | } else if (_bfin_swrst & RESET_WDOG) | |
7728ec33 RG |
907 | printk(KERN_INFO "Recovering from Watchdog event\n"); |
908 | else if (_bfin_swrst & RESET_SOFTWARE) | |
909 | printk(KERN_NOTICE "Reset caused by Software reset\n"); | |
910 | ||
972de7d9 | 911 | printk(KERN_INFO "Blackfin support (C) 2004-2009 Analog Devices, Inc.\n"); |
de3025f4 JZ |
912 | if (bfin_compiled_revid() == 0xffff) |
913 | printk(KERN_INFO "Compiled for ADSP-%s Rev any\n", CPU); | |
914 | else if (bfin_compiled_revid() == -1) | |
915 | printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU); | |
916 | else | |
917 | printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid()); | |
e482cad2 | 918 | |
bd854c07 | 919 | if (likely(CPUID == bfin_cpuid())) { |
e482cad2 RG |
920 | if (bfin_revid() != bfin_compiled_revid()) { |
921 | if (bfin_compiled_revid() == -1) | |
922 | printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n", | |
923 | bfin_revid()); | |
7419a327 | 924 | else if (bfin_compiled_revid() != 0xffff) { |
e482cad2 RG |
925 | printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n", |
926 | bfin_compiled_revid(), bfin_revid()); | |
7419a327 | 927 | if (bfin_compiled_revid() > bfin_revid()) |
d8804adf | 928 | panic("Error: you are missing anomaly workarounds for this rev"); |
7419a327 | 929 | } |
e482cad2 | 930 | } |
da986b9f | 931 | if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX) |
e482cad2 RG |
932 | printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n", |
933 | CPU, bfin_revid()); | |
de3025f4 | 934 | } |
0c0497c2 | 935 | |
1394f032 BW |
936 | printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n"); |
937 | ||
b5c0e2e8 | 938 | printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n", |
8f65873e | 939 | cclk / 1000000, sclk / 1000000); |
1394f032 | 940 | |
856783b3 | 941 | setup_bootmem_allocator(); |
1394f032 | 942 | |
1394f032 BW |
943 | paging_init(); |
944 | ||
7adfb58f BS |
945 | /* Copy atomic sequences to their fixed location, and sanity check that |
946 | these locations are the ones that we advertise to userspace. */ | |
947 | memcpy((void *)FIXED_CODE_START, &fixed_code_start, | |
948 | FIXED_CODE_END - FIXED_CODE_START); | |
949 | BUG_ON((char *)&sigreturn_stub - (char *)&fixed_code_start | |
950 | != SIGRETURN_STUB - FIXED_CODE_START); | |
951 | BUG_ON((char *)&atomic_xchg32 - (char *)&fixed_code_start | |
952 | != ATOMIC_XCHG32 - FIXED_CODE_START); | |
953 | BUG_ON((char *)&atomic_cas32 - (char *)&fixed_code_start | |
954 | != ATOMIC_CAS32 - FIXED_CODE_START); | |
955 | BUG_ON((char *)&atomic_add32 - (char *)&fixed_code_start | |
956 | != ATOMIC_ADD32 - FIXED_CODE_START); | |
957 | BUG_ON((char *)&atomic_sub32 - (char *)&fixed_code_start | |
958 | != ATOMIC_SUB32 - FIXED_CODE_START); | |
959 | BUG_ON((char *)&atomic_ior32 - (char *)&fixed_code_start | |
960 | != ATOMIC_IOR32 - FIXED_CODE_START); | |
961 | BUG_ON((char *)&atomic_and32 - (char *)&fixed_code_start | |
962 | != ATOMIC_AND32 - FIXED_CODE_START); | |
963 | BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start | |
964 | != ATOMIC_XOR32 - FIXED_CODE_START); | |
9f336a53 RG |
965 | BUG_ON((char *)&safe_user_instruction - (char *)&fixed_code_start |
966 | != SAFE_USER_INSTRUCTION - FIXED_CODE_START); | |
29440a2b | 967 | |
8f65873e GY |
968 | #ifdef CONFIG_SMP |
969 | platform_init_cpus(); | |
970 | #endif | |
8be80ed3 | 971 | init_exception_vectors(); |
8f65873e | 972 | bfin_cache_init(); /* Initialize caches for the boot CPU */ |
1394f032 BW |
973 | } |
974 | ||
1394f032 BW |
975 | static int __init topology_init(void) |
976 | { | |
8f65873e GY |
977 | unsigned int cpu; |
978 | /* Record CPU-private information for the boot processor. */ | |
979 | bfin_setup_cpudata(0); | |
6cda2e90 MH |
980 | |
981 | for_each_possible_cpu(cpu) { | |
8f65873e | 982 | register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu); |
6cda2e90 MH |
983 | } |
984 | ||
1394f032 | 985 | return 0; |
1394f032 BW |
986 | } |
987 | ||
988 | subsys_initcall(topology_init); | |
989 | ||
7f1e2f98 MF |
990 | /* Get the input clock frequency */ |
991 | static u_long cached_clkin_hz = CONFIG_CLKIN_HZ; | |
992 | static u_long get_clkin_hz(void) | |
993 | { | |
994 | return cached_clkin_hz; | |
995 | } | |
996 | static int __init early_init_clkin_hz(char *buf) | |
997 | { | |
998 | cached_clkin_hz = simple_strtoul(buf, NULL, 0); | |
508808cd MF |
999 | #ifdef BFIN_KERNEL_CLOCK |
1000 | if (cached_clkin_hz != CONFIG_CLKIN_HZ) | |
1001 | panic("cannot change clkin_hz when reprogramming clocks"); | |
1002 | #endif | |
7f1e2f98 MF |
1003 | return 1; |
1004 | } | |
1005 | early_param("clkin_hz=", early_init_clkin_hz); | |
1006 | ||
3a2521fa | 1007 | /* Get the voltage input multiplier */ |
52a07812 | 1008 | static u_long get_vco(void) |
1394f032 | 1009 | { |
e32f55d9 MF |
1010 | static u_long cached_vco; |
1011 | u_long msel, pll_ctl; | |
1394f032 | 1012 | |
e32f55d9 MF |
1013 | /* The assumption here is that VCO never changes at runtime. |
1014 | * If, someday, we support that, then we'll have to change this. | |
1015 | */ | |
1016 | if (cached_vco) | |
3a2521fa | 1017 | return cached_vco; |
3a2521fa | 1018 | |
e32f55d9 | 1019 | pll_ctl = bfin_read_PLL_CTL(); |
3a2521fa | 1020 | msel = (pll_ctl >> 9) & 0x3F; |
1394f032 BW |
1021 | if (0 == msel) |
1022 | msel = 64; | |
1023 | ||
7f1e2f98 | 1024 | cached_vco = get_clkin_hz(); |
3a2521fa MF |
1025 | cached_vco >>= (1 & pll_ctl); /* DF bit */ |
1026 | cached_vco *= msel; | |
1027 | return cached_vco; | |
1394f032 BW |
1028 | } |
1029 | ||
2f6cf7bf | 1030 | /* Get the Core clock */ |
1394f032 BW |
1031 | u_long get_cclk(void) |
1032 | { | |
e32f55d9 | 1033 | static u_long cached_cclk_pll_div, cached_cclk; |
1394f032 | 1034 | u_long csel, ssel; |
3a2521fa | 1035 | |
1394f032 | 1036 | if (bfin_read_PLL_STAT() & 0x1) |
7f1e2f98 | 1037 | return get_clkin_hz(); |
1394f032 BW |
1038 | |
1039 | ssel = bfin_read_PLL_DIV(); | |
3a2521fa MF |
1040 | if (ssel == cached_cclk_pll_div) |
1041 | return cached_cclk; | |
1042 | else | |
1043 | cached_cclk_pll_div = ssel; | |
1044 | ||
1394f032 BW |
1045 | csel = ((ssel >> 4) & 0x03); |
1046 | ssel &= 0xf; | |
1047 | if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */ | |
3a2521fa MF |
1048 | cached_cclk = get_vco() / ssel; |
1049 | else | |
1050 | cached_cclk = get_vco() >> csel; | |
1051 | return cached_cclk; | |
1394f032 | 1052 | } |
1394f032 BW |
1053 | EXPORT_SYMBOL(get_cclk); |
1054 | ||
1055 | /* Get the System clock */ | |
1056 | u_long get_sclk(void) | |
1057 | { | |
e32f55d9 | 1058 | static u_long cached_sclk; |
1394f032 BW |
1059 | u_long ssel; |
1060 | ||
e32f55d9 MF |
1061 | /* The assumption here is that SCLK never changes at runtime. |
1062 | * If, someday, we support that, then we'll have to change this. | |
1063 | */ | |
1064 | if (cached_sclk) | |
1065 | return cached_sclk; | |
1066 | ||
1394f032 | 1067 | if (bfin_read_PLL_STAT() & 0x1) |
7f1e2f98 | 1068 | return get_clkin_hz(); |
1394f032 | 1069 | |
e32f55d9 | 1070 | ssel = bfin_read_PLL_DIV() & 0xf; |
1394f032 BW |
1071 | if (0 == ssel) { |
1072 | printk(KERN_WARNING "Invalid System Clock\n"); | |
1073 | ssel = 1; | |
1074 | } | |
1075 | ||
3a2521fa MF |
1076 | cached_sclk = get_vco() / ssel; |
1077 | return cached_sclk; | |
1394f032 | 1078 | } |
1394f032 BW |
1079 | EXPORT_SYMBOL(get_sclk); |
1080 | ||
2f6cf7bf MF |
1081 | unsigned long sclk_to_usecs(unsigned long sclk) |
1082 | { | |
1754a5d9 MF |
1083 | u64 tmp = USEC_PER_SEC * (u64)sclk; |
1084 | do_div(tmp, get_sclk()); | |
1085 | return tmp; | |
2f6cf7bf MF |
1086 | } |
1087 | EXPORT_SYMBOL(sclk_to_usecs); | |
1088 | ||
1089 | unsigned long usecs_to_sclk(unsigned long usecs) | |
1090 | { | |
1754a5d9 MF |
1091 | u64 tmp = get_sclk() * (u64)usecs; |
1092 | do_div(tmp, USEC_PER_SEC); | |
1093 | return tmp; | |
2f6cf7bf MF |
1094 | } |
1095 | EXPORT_SYMBOL(usecs_to_sclk); | |
1096 | ||
1394f032 BW |
1097 | /* |
1098 | * Get CPU information for use by the procfs. | |
1099 | */ | |
1100 | static int show_cpuinfo(struct seq_file *m, void *v) | |
1101 | { | |
066954a3 | 1102 | char *cpu, *mmu, *fpu, *vendor, *cache; |
1394f032 | 1103 | uint32_t revid; |
275123e8 | 1104 | int cpu_num = *(unsigned int *)v; |
a5f0717e | 1105 | u_long sclk, cclk; |
9de3a0b6 | 1106 | u_int icache_size = BFIN_ICACHESIZE / 1024, dcache_size = 0, dsup_banks = 0; |
275123e8 | 1107 | struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu_num); |
1394f032 BW |
1108 | |
1109 | cpu = CPU; | |
1110 | mmu = "none"; | |
1111 | fpu = "none"; | |
1112 | revid = bfin_revid(); | |
1394f032 | 1113 | |
1394f032 | 1114 | sclk = get_sclk(); |
a5f0717e | 1115 | cclk = get_cclk(); |
1394f032 | 1116 | |
73b0c0b0 | 1117 | switch (bfin_read_CHIPID() & CHIPID_MANUFACTURE) { |
066954a3 MF |
1118 | case 0xca: |
1119 | vendor = "Analog Devices"; | |
73b0c0b0 RG |
1120 | break; |
1121 | default: | |
066954a3 MF |
1122 | vendor = "unknown"; |
1123 | break; | |
73b0c0b0 | 1124 | } |
1394f032 | 1125 | |
275123e8 | 1126 | seq_printf(m, "processor\t: %d\n" "vendor_id\t: %s\n", cpu_num, vendor); |
e482cad2 RG |
1127 | |
1128 | if (CPUID == bfin_cpuid()) | |
1129 | seq_printf(m, "cpu family\t: 0x%04x\n", CPUID); | |
1130 | else | |
1131 | seq_printf(m, "cpu family\t: Compiled for:0x%04x, running on:0x%04x\n", | |
1132 | CPUID, bfin_cpuid()); | |
1133 | ||
1134 | seq_printf(m, "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n" | |
2466ac65 | 1135 | "stepping\t: %d ", |
a5f0717e | 1136 | cpu, cclk/1000000, sclk/1000000, |
253bcf4f RG |
1137 | #ifdef CONFIG_MPU |
1138 | "mpu on", | |
1139 | #else | |
1140 | "mpu off", | |
1141 | #endif | |
73b0c0b0 RG |
1142 | revid); |
1143 | ||
2466ac65 RG |
1144 | if (bfin_revid() != bfin_compiled_revid()) { |
1145 | if (bfin_compiled_revid() == -1) | |
1146 | seq_printf(m, "(Compiled for Rev none)"); | |
1147 | else if (bfin_compiled_revid() == 0xffff) | |
1148 | seq_printf(m, "(Compiled for Rev any)"); | |
1149 | else | |
1150 | seq_printf(m, "(Compiled for Rev %d)", bfin_compiled_revid()); | |
1151 | } | |
1152 | ||
1153 | seq_printf(m, "\ncpu MHz\t\t: %lu.%03lu/%lu.%03lu\n", | |
a5f0717e | 1154 | cclk/1000000, cclk%1000000, |
73b0c0b0 RG |
1155 | sclk/1000000, sclk%1000000); |
1156 | seq_printf(m, "bogomips\t: %lu.%02lu\n" | |
1157 | "Calibration\t: %lu loops\n", | |
c70c754f MH |
1158 | (loops_per_jiffy * HZ) / 500000, |
1159 | ((loops_per_jiffy * HZ) / 5000) % 100, | |
1160 | (loops_per_jiffy * HZ)); | |
73b0c0b0 RG |
1161 | |
1162 | /* Check Cache configutation */ | |
8f65873e | 1163 | switch (cpudata->dmemctl & (1 << DMC0_P | 1 << DMC1_P)) { |
1f83b8f1 | 1164 | case ACACHE_BSRAM: |
066954a3 | 1165 | cache = "dbank-A/B\t: cache/sram"; |
1f83b8f1 MF |
1166 | dcache_size = 16; |
1167 | dsup_banks = 1; | |
1168 | break; | |
1169 | case ACACHE_BCACHE: | |
066954a3 | 1170 | cache = "dbank-A/B\t: cache/cache"; |
1f83b8f1 MF |
1171 | dcache_size = 32; |
1172 | dsup_banks = 2; | |
1173 | break; | |
1174 | case ASRAM_BSRAM: | |
066954a3 | 1175 | cache = "dbank-A/B\t: sram/sram"; |
1f83b8f1 MF |
1176 | dcache_size = 0; |
1177 | dsup_banks = 0; | |
1178 | break; | |
1179 | default: | |
066954a3 | 1180 | cache = "unknown"; |
73b0c0b0 RG |
1181 | dcache_size = 0; |
1182 | dsup_banks = 0; | |
1394f032 BW |
1183 | break; |
1184 | } | |
1185 | ||
73b0c0b0 | 1186 | /* Is it turned on? */ |
8f65873e | 1187 | if ((cpudata->dmemctl & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE)) |
73b0c0b0 | 1188 | dcache_size = 0; |
1394f032 | 1189 | |
8f65873e | 1190 | if ((cpudata->imemctl & (IMC | ENICPLB)) != (IMC | ENICPLB)) |
9de3a0b6 RG |
1191 | icache_size = 0; |
1192 | ||
73b0c0b0 | 1193 | seq_printf(m, "cache size\t: %d KB(L1 icache) " |
41ba653f JZ |
1194 | "%d KB(L1 dcache) %d KB(L2 cache)\n", |
1195 | icache_size, dcache_size, 0); | |
73b0c0b0 | 1196 | seq_printf(m, "%s\n", cache); |
41ba653f JZ |
1197 | seq_printf(m, "external memory\t: " |
1198 | #if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) | |
1199 | "cacheable" | |
1200 | #else | |
1201 | "uncacheable" | |
1202 | #endif | |
1203 | " in instruction cache\n"); | |
1204 | seq_printf(m, "external memory\t: " | |
1205 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) | |
1206 | "cacheable (write-back)" | |
1207 | #elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH) | |
1208 | "cacheable (write-through)" | |
1209 | #else | |
1210 | "uncacheable" | |
1211 | #endif | |
1212 | " in data cache\n"); | |
73b0c0b0 | 1213 | |
9de3a0b6 RG |
1214 | if (icache_size) |
1215 | seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n", | |
1216 | BFIN_ISUBBANKS, BFIN_IWAYS, BFIN_ILINES); | |
1217 | else | |
1218 | seq_printf(m, "icache setup\t: off\n"); | |
1219 | ||
1394f032 | 1220 | seq_printf(m, |
73b0c0b0 | 1221 | "dcache setup\t: %d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n", |
3bebca2d RG |
1222 | dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS, |
1223 | BFIN_DLINES); | |
8f65873e | 1224 | #ifdef __ARCH_SYNC_CORE_DCACHE |
275123e8 | 1225 | seq_printf(m, "SMP Dcache Flushes\t: %lu\n\n", cpudata->dcache_invld_count); |
8f65873e | 1226 | #endif |
47e9dedb SZ |
1227 | #ifdef __ARCH_SYNC_CORE_ICACHE |
1228 | seq_printf(m, "SMP Icache Flushes\t: %lu\n\n", cpudata->icache_invld_count); | |
1229 | #endif | |
275123e8 MF |
1230 | |
1231 | if (cpu_num != num_possible_cpus() - 1) | |
8f65873e GY |
1232 | return 0; |
1233 | ||
41ba653f | 1234 | if (L2_LENGTH) { |
275123e8 | 1235 | seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400); |
41ba653f JZ |
1236 | seq_printf(m, "L2 SRAM\t\t: " |
1237 | #if defined(CONFIG_BFIN_L2_ICACHEABLE) | |
1238 | "cacheable" | |
1239 | #else | |
1240 | "uncacheable" | |
1241 | #endif | |
1242 | " in instruction cache\n"); | |
1243 | seq_printf(m, "L2 SRAM\t\t: " | |
1244 | #if defined(CONFIG_BFIN_L2_WRITEBACK) | |
1245 | "cacheable (write-back)" | |
1246 | #elif defined(CONFIG_BFIN_L2_WRITETHROUGH) | |
1247 | "cacheable (write-through)" | |
1248 | #else | |
1249 | "uncacheable" | |
1250 | #endif | |
1251 | " in data cache\n"); | |
1252 | } | |
066954a3 | 1253 | seq_printf(m, "board name\t: %s\n", bfin_board_name); |
73b0c0b0 RG |
1254 | seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n", |
1255 | physical_mem_end >> 10, (void *)0, (void *)physical_mem_end); | |
1256 | seq_printf(m, "kernel memory\t: %d kB (0x%p -> 0x%p)\n", | |
1257 | ((int)memory_end - (int)_stext) >> 10, | |
1258 | _stext, | |
1259 | (void *)memory_end); | |
8f65873e | 1260 | seq_printf(m, "\n"); |
73b0c0b0 | 1261 | |
1394f032 BW |
1262 | return 0; |
1263 | } | |
1264 | ||
1265 | static void *c_start(struct seq_file *m, loff_t *pos) | |
1266 | { | |
55f2feae GY |
1267 | if (*pos == 0) |
1268 | *pos = first_cpu(cpu_online_map); | |
1269 | if (*pos >= num_online_cpus()) | |
1270 | return NULL; | |
1271 | ||
1272 | return pos; | |
1394f032 BW |
1273 | } |
1274 | ||
1275 | static void *c_next(struct seq_file *m, void *v, loff_t *pos) | |
1276 | { | |
55f2feae GY |
1277 | *pos = next_cpu(*pos, cpu_online_map); |
1278 | ||
1394f032 BW |
1279 | return c_start(m, pos); |
1280 | } | |
1281 | ||
1282 | static void c_stop(struct seq_file *m, void *v) | |
1283 | { | |
1284 | } | |
1285 | ||
03a44825 | 1286 | const struct seq_operations cpuinfo_op = { |
1394f032 BW |
1287 | .start = c_start, |
1288 | .next = c_next, | |
1289 | .stop = c_stop, | |
1290 | .show = show_cpuinfo, | |
1291 | }; | |
1292 | ||
5e10b4a6 | 1293 | void __init cmdline_init(const char *r0) |
1394f032 | 1294 | { |
837ec2d5 | 1295 | early_shadow_stamp(); |
1394f032 | 1296 | if (r0) |
52a07812 | 1297 | strncpy(command_line, r0, COMMAND_LINE_SIZE); |
1394f032 | 1298 | } |