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Commit | Line | Data |
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1394f032 | 1 | /* |
550d5538 | 2 | * arch/blackfin/kernel/setup.c |
1394f032 | 3 | * |
550d5538 | 4 | * Copyright 2004-2006 Analog Devices Inc. |
1394f032 | 5 | * |
550d5538 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
1394f032 | 7 | * |
550d5538 | 8 | * Licensed under the GPL-2 or later. |
1394f032 BW |
9 | */ |
10 | ||
11 | #include <linux/delay.h> | |
12 | #include <linux/console.h> | |
13 | #include <linux/bootmem.h> | |
14 | #include <linux/seq_file.h> | |
15 | #include <linux/cpu.h> | |
259fea42 | 16 | #include <linux/mm.h> |
1394f032 | 17 | #include <linux/module.h> |
1394f032 | 18 | #include <linux/tty.h> |
856783b3 | 19 | #include <linux/pfn.h> |
1394f032 | 20 | |
79df1b69 MF |
21 | #ifdef CONFIG_MTD_UCLINUX |
22 | #include <linux/mtd/map.h> | |
1394f032 BW |
23 | #include <linux/ext2_fs.h> |
24 | #include <linux/cramfs_fs.h> | |
25 | #include <linux/romfs_fs.h> | |
79df1b69 | 26 | #endif |
1394f032 | 27 | |
3bebca2d | 28 | #include <asm/cplb.h> |
1394f032 BW |
29 | #include <asm/cacheflush.h> |
30 | #include <asm/blackfin.h> | |
31 | #include <asm/cplbinit.h> | |
1754a5d9 | 32 | #include <asm/div64.h> |
8f65873e | 33 | #include <asm/cpu.h> |
7adfb58f | 34 | #include <asm/fixed_code.h> |
ce3afa1c | 35 | #include <asm/early_printk.h> |
1394f032 | 36 | |
a9c59c27 | 37 | u16 _bfin_swrst; |
d45118b1 | 38 | EXPORT_SYMBOL(_bfin_swrst); |
a9c59c27 | 39 | |
1394f032 | 40 | unsigned long memory_start, memory_end, physical_mem_end; |
3132b586 | 41 | unsigned long _rambase, _ramstart, _ramend; |
1394f032 BW |
42 | unsigned long reserved_mem_dcache_on; |
43 | unsigned long reserved_mem_icache_on; | |
44 | EXPORT_SYMBOL(memory_start); | |
45 | EXPORT_SYMBOL(memory_end); | |
46 | EXPORT_SYMBOL(physical_mem_end); | |
47 | EXPORT_SYMBOL(_ramend); | |
58c35bd3 | 48 | EXPORT_SYMBOL(reserved_mem_dcache_on); |
1394f032 BW |
49 | |
50 | #ifdef CONFIG_MTD_UCLINUX | |
79df1b69 | 51 | extern struct map_info uclinux_ram_map; |
1394f032 BW |
52 | unsigned long memory_mtd_end, memory_mtd_start, mtd_size; |
53 | unsigned long _ebss; | |
54 | EXPORT_SYMBOL(memory_mtd_end); | |
55 | EXPORT_SYMBOL(memory_mtd_start); | |
56 | EXPORT_SYMBOL(mtd_size); | |
57 | #endif | |
58 | ||
5e10b4a6 | 59 | char __initdata command_line[COMMAND_LINE_SIZE]; |
0c7a6b21 RG |
60 | void __initdata *init_retx, *init_saved_retx, *init_saved_seqstat, |
61 | *init_saved_icplb_fault_addr, *init_saved_dcplb_fault_addr; | |
1394f032 | 62 | |
856783b3 YL |
63 | /* boot memmap, for parsing "memmap=" */ |
64 | #define BFIN_MEMMAP_MAX 128 /* number of entries in bfin_memmap */ | |
65 | #define BFIN_MEMMAP_RAM 1 | |
66 | #define BFIN_MEMMAP_RESERVED 2 | |
af4c7d4b | 67 | static struct bfin_memmap { |
856783b3 YL |
68 | int nr_map; |
69 | struct bfin_memmap_entry { | |
70 | unsigned long long addr; /* start of memory segment */ | |
71 | unsigned long long size; | |
72 | unsigned long type; | |
73 | } map[BFIN_MEMMAP_MAX]; | |
74 | } bfin_memmap __initdata; | |
75 | ||
76 | /* for memmap sanitization */ | |
77 | struct change_member { | |
78 | struct bfin_memmap_entry *pentry; /* pointer to original entry */ | |
79 | unsigned long long addr; /* address for this change point */ | |
80 | }; | |
81 | static struct change_member change_point_list[2*BFIN_MEMMAP_MAX] __initdata; | |
82 | static struct change_member *change_point[2*BFIN_MEMMAP_MAX] __initdata; | |
83 | static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata; | |
84 | static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata; | |
85 | ||
8f65873e GY |
86 | DEFINE_PER_CPU(struct blackfin_cpudata, cpu_data); |
87 | ||
7f1e2f98 MF |
88 | static int early_init_clkin_hz(char *buf); |
89 | ||
3bebca2d | 90 | #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) |
8f65873e GY |
91 | void __init generate_cplb_tables(void) |
92 | { | |
93 | unsigned int cpu; | |
94 | ||
dbdf20db | 95 | generate_cplb_tables_all(); |
8f65873e GY |
96 | /* Generate per-CPU I&D CPLB tables */ |
97 | for (cpu = 0; cpu < num_possible_cpus(); ++cpu) | |
98 | generate_cplb_tables_cpu(cpu); | |
99 | } | |
1394f032 BW |
100 | #endif |
101 | ||
8f65873e GY |
102 | void __cpuinit bfin_setup_caches(unsigned int cpu) |
103 | { | |
3bebca2d | 104 | #ifdef CONFIG_BFIN_ICACHE |
8f65873e | 105 | bfin_icache_init(icplb_tbl[cpu]); |
1394f032 BW |
106 | #endif |
107 | ||
3bebca2d | 108 | #ifdef CONFIG_BFIN_DCACHE |
8f65873e | 109 | bfin_dcache_init(dcplb_tbl[cpu]); |
8f65873e GY |
110 | #endif |
111 | ||
112 | /* | |
113 | * In cache coherence emulation mode, we need to have the | |
114 | * D-cache enabled before running any atomic operation which | |
115 | * might invove cache invalidation (i.e. spinlock, rwlock). | |
116 | * So printk's are deferred until then. | |
117 | */ | |
118 | #ifdef CONFIG_BFIN_ICACHE | |
119 | printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu); | |
41ba653f JZ |
120 | printk(KERN_INFO " External memory:" |
121 | # ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE | |
122 | " cacheable" | |
123 | # else | |
124 | " uncacheable" | |
125 | # endif | |
126 | " in instruction cache\n"); | |
127 | if (L2_LENGTH) | |
128 | printk(KERN_INFO " L2 SRAM :" | |
129 | # ifdef CONFIG_BFIN_L2_ICACHEABLE | |
130 | " cacheable" | |
131 | # else | |
132 | " uncacheable" | |
133 | # endif | |
134 | " in instruction cache\n"); | |
135 | ||
136 | #else | |
137 | printk(KERN_INFO "Instruction Cache Disabled for CPU%u\n", cpu); | |
8f65873e | 138 | #endif |
41ba653f | 139 | |
8f65873e | 140 | #ifdef CONFIG_BFIN_DCACHE |
41ba653f JZ |
141 | printk(KERN_INFO "Data Cache Enabled for CPU%u\n", cpu); |
142 | printk(KERN_INFO " External memory:" | |
143 | # if defined CONFIG_BFIN_EXTMEM_WRITEBACK | |
144 | " cacheable (write-back)" | |
145 | # elif defined CONFIG_BFIN_EXTMEM_WRITETHROUGH | |
146 | " cacheable (write-through)" | |
147 | # else | |
148 | " uncacheable" | |
149 | # endif | |
150 | " in data cache\n"); | |
151 | if (L2_LENGTH) | |
152 | printk(KERN_INFO " L2 SRAM :" | |
153 | # if defined CONFIG_BFIN_L2_WRITEBACK | |
154 | " cacheable (write-back)" | |
155 | # elif defined CONFIG_BFIN_L2_WRITETHROUGH | |
156 | " cacheable (write-through)" | |
157 | # else | |
158 | " uncacheable" | |
1394f032 | 159 | # endif |
41ba653f JZ |
160 | " in data cache\n"); |
161 | #else | |
162 | printk(KERN_INFO "Data Cache Disabled for CPU%u\n", cpu); | |
1394f032 BW |
163 | #endif |
164 | } | |
165 | ||
8f65873e GY |
166 | void __cpuinit bfin_setup_cpudata(unsigned int cpu) |
167 | { | |
168 | struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu); | |
169 | ||
170 | cpudata->idle = current; | |
8f65873e GY |
171 | cpudata->imemctl = bfin_read_IMEM_CONTROL(); |
172 | cpudata->dmemctl = bfin_read_DMEM_CONTROL(); | |
173 | } | |
174 | ||
175 | void __init bfin_cache_init(void) | |
176 | { | |
177 | #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) | |
178 | generate_cplb_tables(); | |
179 | #endif | |
180 | bfin_setup_caches(0); | |
181 | } | |
182 | ||
5b04f271 | 183 | void __init bfin_relocate_l1_mem(void) |
1394f032 BW |
184 | { |
185 | unsigned long l1_code_length; | |
186 | unsigned long l1_data_a_length; | |
187 | unsigned long l1_data_b_length; | |
262c3825 | 188 | unsigned long l2_length; |
1394f032 | 189 | |
fecbd736 RG |
190 | /* |
191 | * due to the ALIGN(4) in the arch/blackfin/kernel/vmlinux.lds.S | |
192 | * we know that everything about l1 text/data is nice and aligned, | |
193 | * so copy by 4 byte chunks, and don't worry about overlapping | |
194 | * src/dest. | |
195 | * | |
196 | * We can't use the dma_memcpy functions, since they can call | |
197 | * scheduler functions which might be in L1 :( and core writes | |
198 | * into L1 instruction cause bad access errors, so we are stuck, | |
199 | * we are required to use DMA, but can't use the common dma | |
200 | * functions. We can't use memcpy either - since that might be | |
201 | * going to be in the relocated L1 | |
202 | */ | |
203 | ||
dd3dd384 MF |
204 | blackfin_dma_early_init(); |
205 | ||
fecbd736 | 206 | /* if necessary, copy _stext_l1 to _etext_l1 to L1 instruction SRAM */ |
1394f032 | 207 | l1_code_length = _etext_l1 - _stext_l1; |
fecbd736 RG |
208 | if (l1_code_length) |
209 | early_dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length); | |
1394f032 | 210 | |
fecbd736 | 211 | /* if necessary, copy _sdata_l1 to _sbss_l1 to L1 data bank A SRAM */ |
3b1f26a5 | 212 | l1_data_a_length = _sbss_l1 - _sdata_l1; |
fecbd736 RG |
213 | if (l1_data_a_length) |
214 | early_dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length); | |
1394f032 | 215 | |
fecbd736 | 216 | /* if necessary, copy _sdata_b_l1 to _sbss_b_l1 to L1 data bank B SRAM */ |
3b1f26a5 | 217 | l1_data_b_length = _sbss_b_l1 - _sdata_b_l1; |
fecbd736 RG |
218 | if (l1_data_b_length) |
219 | early_dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length + | |
1394f032 | 220 | l1_data_a_length, l1_data_b_length); |
262c3825 | 221 | |
fecbd736 RG |
222 | early_dma_memcpy_done(); |
223 | ||
224 | /* if necessary, copy _stext_l2 to _edata_l2 to L2 SRAM */ | |
07aa7be5 | 225 | if (L2_LENGTH != 0) { |
3b1f26a5 | 226 | l2_length = _sbss_l2 - _stext_l2; |
fecbd736 RG |
227 | if (l2_length) |
228 | memcpy(_stext_l2, _l2_lma_start, l2_length); | |
07aa7be5 | 229 | } |
1394f032 BW |
230 | } |
231 | ||
856783b3 YL |
232 | /* add_memory_region to memmap */ |
233 | static void __init add_memory_region(unsigned long long start, | |
234 | unsigned long long size, int type) | |
235 | { | |
236 | int i; | |
237 | ||
238 | i = bfin_memmap.nr_map; | |
239 | ||
240 | if (i == BFIN_MEMMAP_MAX) { | |
241 | printk(KERN_ERR "Ooops! Too many entries in the memory map!\n"); | |
242 | return; | |
243 | } | |
244 | ||
245 | bfin_memmap.map[i].addr = start; | |
246 | bfin_memmap.map[i].size = size; | |
247 | bfin_memmap.map[i].type = type; | |
248 | bfin_memmap.nr_map++; | |
249 | } | |
250 | ||
251 | /* | |
252 | * Sanitize the boot memmap, removing overlaps. | |
253 | */ | |
254 | static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map) | |
255 | { | |
256 | struct change_member *change_tmp; | |
257 | unsigned long current_type, last_type; | |
258 | unsigned long long last_addr; | |
259 | int chgidx, still_changing; | |
260 | int overlap_entries; | |
261 | int new_entry; | |
262 | int old_nr, new_nr, chg_nr; | |
263 | int i; | |
264 | ||
265 | /* | |
266 | Visually we're performing the following (1,2,3,4 = memory types) | |
267 | ||
268 | Sample memory map (w/overlaps): | |
269 | ____22__________________ | |
270 | ______________________4_ | |
271 | ____1111________________ | |
272 | _44_____________________ | |
273 | 11111111________________ | |
274 | ____________________33__ | |
275 | ___________44___________ | |
276 | __________33333_________ | |
277 | ______________22________ | |
278 | ___________________2222_ | |
279 | _________111111111______ | |
280 | _____________________11_ | |
281 | _________________4______ | |
282 | ||
283 | Sanitized equivalent (no overlap): | |
284 | 1_______________________ | |
285 | _44_____________________ | |
286 | ___1____________________ | |
287 | ____22__________________ | |
288 | ______11________________ | |
289 | _________1______________ | |
290 | __________3_____________ | |
291 | ___________44___________ | |
292 | _____________33_________ | |
293 | _______________2________ | |
294 | ________________1_______ | |
295 | _________________4______ | |
296 | ___________________2____ | |
297 | ____________________33__ | |
298 | ______________________4_ | |
299 | */ | |
300 | /* if there's only one memory region, don't bother */ | |
301 | if (*pnr_map < 2) | |
302 | return -1; | |
303 | ||
304 | old_nr = *pnr_map; | |
305 | ||
306 | /* bail out if we find any unreasonable addresses in memmap */ | |
307 | for (i = 0; i < old_nr; i++) | |
308 | if (map[i].addr + map[i].size < map[i].addr) | |
309 | return -1; | |
310 | ||
311 | /* create pointers for initial change-point information (for sorting) */ | |
312 | for (i = 0; i < 2*old_nr; i++) | |
313 | change_point[i] = &change_point_list[i]; | |
314 | ||
315 | /* record all known change-points (starting and ending addresses), | |
316 | omitting those that are for empty memory regions */ | |
317 | chgidx = 0; | |
8f65873e | 318 | for (i = 0; i < old_nr; i++) { |
856783b3 YL |
319 | if (map[i].size != 0) { |
320 | change_point[chgidx]->addr = map[i].addr; | |
321 | change_point[chgidx++]->pentry = &map[i]; | |
322 | change_point[chgidx]->addr = map[i].addr + map[i].size; | |
323 | change_point[chgidx++]->pentry = &map[i]; | |
324 | } | |
325 | } | |
8f65873e | 326 | chg_nr = chgidx; /* true number of change-points */ |
856783b3 YL |
327 | |
328 | /* sort change-point list by memory addresses (low -> high) */ | |
329 | still_changing = 1; | |
8f65873e | 330 | while (still_changing) { |
856783b3 | 331 | still_changing = 0; |
8f65873e | 332 | for (i = 1; i < chg_nr; i++) { |
856783b3 YL |
333 | /* if <current_addr> > <last_addr>, swap */ |
334 | /* or, if current=<start_addr> & last=<end_addr>, swap */ | |
335 | if ((change_point[i]->addr < change_point[i-1]->addr) || | |
336 | ((change_point[i]->addr == change_point[i-1]->addr) && | |
337 | (change_point[i]->addr == change_point[i]->pentry->addr) && | |
338 | (change_point[i-1]->addr != change_point[i-1]->pentry->addr)) | |
339 | ) { | |
340 | change_tmp = change_point[i]; | |
341 | change_point[i] = change_point[i-1]; | |
342 | change_point[i-1] = change_tmp; | |
343 | still_changing = 1; | |
344 | } | |
345 | } | |
346 | } | |
347 | ||
348 | /* create a new memmap, removing overlaps */ | |
8f65873e GY |
349 | overlap_entries = 0; /* number of entries in the overlap table */ |
350 | new_entry = 0; /* index for creating new memmap entries */ | |
351 | last_type = 0; /* start with undefined memory type */ | |
352 | last_addr = 0; /* start with 0 as last starting address */ | |
856783b3 YL |
353 | /* loop through change-points, determining affect on the new memmap */ |
354 | for (chgidx = 0; chgidx < chg_nr; chgidx++) { | |
355 | /* keep track of all overlapping memmap entries */ | |
356 | if (change_point[chgidx]->addr == change_point[chgidx]->pentry->addr) { | |
357 | /* add map entry to overlap list (> 1 entry implies an overlap) */ | |
358 | overlap_list[overlap_entries++] = change_point[chgidx]->pentry; | |
359 | } else { | |
360 | /* remove entry from list (order independent, so swap with last) */ | |
361 | for (i = 0; i < overlap_entries; i++) { | |
362 | if (overlap_list[i] == change_point[chgidx]->pentry) | |
363 | overlap_list[i] = overlap_list[overlap_entries-1]; | |
364 | } | |
365 | overlap_entries--; | |
366 | } | |
367 | /* if there are overlapping entries, decide which "type" to use */ | |
368 | /* (larger value takes precedence -- 1=usable, 2,3,4,4+=unusable) */ | |
369 | current_type = 0; | |
370 | for (i = 0; i < overlap_entries; i++) | |
371 | if (overlap_list[i]->type > current_type) | |
372 | current_type = overlap_list[i]->type; | |
373 | /* continue building up new memmap based on this information */ | |
8f65873e | 374 | if (current_type != last_type) { |
856783b3 YL |
375 | if (last_type != 0) { |
376 | new_map[new_entry].size = | |
377 | change_point[chgidx]->addr - last_addr; | |
378 | /* move forward only if the new size was non-zero */ | |
379 | if (new_map[new_entry].size != 0) | |
380 | if (++new_entry >= BFIN_MEMMAP_MAX) | |
8f65873e | 381 | break; /* no more space left for new entries */ |
856783b3 YL |
382 | } |
383 | if (current_type != 0) { | |
384 | new_map[new_entry].addr = change_point[chgidx]->addr; | |
385 | new_map[new_entry].type = current_type; | |
386 | last_addr = change_point[chgidx]->addr; | |
387 | } | |
388 | last_type = current_type; | |
389 | } | |
390 | } | |
8f65873e | 391 | new_nr = new_entry; /* retain count for new entries */ |
856783b3 | 392 | |
8f65873e | 393 | /* copy new mapping into original location */ |
856783b3 YL |
394 | memcpy(map, new_map, new_nr*sizeof(struct bfin_memmap_entry)); |
395 | *pnr_map = new_nr; | |
396 | ||
397 | return 0; | |
398 | } | |
399 | ||
400 | static void __init print_memory_map(char *who) | |
401 | { | |
402 | int i; | |
403 | ||
404 | for (i = 0; i < bfin_memmap.nr_map; i++) { | |
405 | printk(KERN_DEBUG " %s: %016Lx - %016Lx ", who, | |
406 | bfin_memmap.map[i].addr, | |
407 | bfin_memmap.map[i].addr + bfin_memmap.map[i].size); | |
408 | switch (bfin_memmap.map[i].type) { | |
409 | case BFIN_MEMMAP_RAM: | |
ad361c98 JP |
410 | printk(KERN_CONT "(usable)\n"); |
411 | break; | |
856783b3 | 412 | case BFIN_MEMMAP_RESERVED: |
ad361c98 JP |
413 | printk(KERN_CONT "(reserved)\n"); |
414 | break; | |
415 | default: | |
416 | printk(KERN_CONT "type %lu\n", bfin_memmap.map[i].type); | |
417 | break; | |
856783b3 YL |
418 | } |
419 | } | |
420 | } | |
421 | ||
422 | static __init int parse_memmap(char *arg) | |
423 | { | |
424 | unsigned long long start_at, mem_size; | |
425 | ||
426 | if (!arg) | |
427 | return -EINVAL; | |
428 | ||
429 | mem_size = memparse(arg, &arg); | |
430 | if (*arg == '@') { | |
431 | start_at = memparse(arg+1, &arg); | |
432 | add_memory_region(start_at, mem_size, BFIN_MEMMAP_RAM); | |
433 | } else if (*arg == '$') { | |
434 | start_at = memparse(arg+1, &arg); | |
435 | add_memory_region(start_at, mem_size, BFIN_MEMMAP_RESERVED); | |
436 | } | |
437 | ||
438 | return 0; | |
439 | } | |
440 | ||
1394f032 BW |
441 | /* |
442 | * Initial parsing of the command line. Currently, we support: | |
443 | * - Controlling the linux memory size: mem=xxx[KMG] | |
444 | * - Controlling the physical memory size: max_mem=xxx[KMG][$][#] | |
445 | * $ -> reserved memory is dcacheable | |
446 | * # -> reserved memory is icacheable | |
856783b3 YL |
447 | * - "memmap=XXX[KkmM][@][$]XXX[KkmM]" defines a memory region |
448 | * @ from <start> to <start>+<mem>, type RAM | |
449 | * $ from <start> to <start>+<mem>, type RESERVED | |
1394f032 BW |
450 | */ |
451 | static __init void parse_cmdline_early(char *cmdline_p) | |
452 | { | |
453 | char c = ' ', *to = cmdline_p; | |
454 | unsigned int memsize; | |
455 | for (;;) { | |
456 | if (c == ' ') { | |
1394f032 BW |
457 | if (!memcmp(to, "mem=", 4)) { |
458 | to += 4; | |
459 | memsize = memparse(to, &to); | |
460 | if (memsize) | |
461 | _ramend = memsize; | |
462 | ||
463 | } else if (!memcmp(to, "max_mem=", 8)) { | |
464 | to += 8; | |
465 | memsize = memparse(to, &to); | |
466 | if (memsize) { | |
467 | physical_mem_end = memsize; | |
468 | if (*to != ' ') { | |
469 | if (*to == '$' | |
470 | || *(to + 1) == '$') | |
8f65873e | 471 | reserved_mem_dcache_on = 1; |
1394f032 BW |
472 | if (*to == '#' |
473 | || *(to + 1) == '#') | |
8f65873e | 474 | reserved_mem_icache_on = 1; |
1394f032 BW |
475 | } |
476 | } | |
7f1e2f98 MF |
477 | } else if (!memcmp(to, "clkin_hz=", 9)) { |
478 | to += 9; | |
479 | early_init_clkin_hz(to); | |
bd854c07 | 480 | #ifdef CONFIG_EARLY_PRINTK |
ce3afa1c RG |
481 | } else if (!memcmp(to, "earlyprintk=", 12)) { |
482 | to += 12; | |
483 | setup_early_printk(to); | |
bd854c07 | 484 | #endif |
856783b3 YL |
485 | } else if (!memcmp(to, "memmap=", 7)) { |
486 | to += 7; | |
487 | parse_memmap(to); | |
1394f032 | 488 | } |
1394f032 BW |
489 | } |
490 | c = *(to++); | |
491 | if (!c) | |
492 | break; | |
493 | } | |
494 | } | |
495 | ||
856783b3 YL |
496 | /* |
497 | * Setup memory defaults from user config. | |
498 | * The physical memory layout looks like: | |
499 | * | |
500 | * [_rambase, _ramstart]: kernel image | |
501 | * [memory_start, memory_end]: dynamic memory managed by kernel | |
502 | * [memory_end, _ramend]: reserved memory | |
3094c981 | 503 | * [memory_mtd_start(memory_end), |
856783b3 YL |
504 | * memory_mtd_start + mtd_size]: rootfs (if any) |
505 | * [_ramend - DMA_UNCACHED_REGION, | |
506 | * _ramend]: uncached DMA region | |
507 | * [_ramend, physical_mem_end]: memory not managed by kernel | |
856783b3 | 508 | */ |
8f65873e | 509 | static __init void memory_setup(void) |
1394f032 | 510 | { |
c0eab3b7 MF |
511 | #ifdef CONFIG_MTD_UCLINUX |
512 | unsigned long mtd_phys = 0; | |
513 | #endif | |
2f812c0b | 514 | unsigned long max_mem; |
c0eab3b7 | 515 | |
856783b3 | 516 | _rambase = (unsigned long)_stext; |
b7627acc | 517 | _ramstart = (unsigned long)_end; |
1394f032 | 518 | |
856783b3 YL |
519 | if (DMA_UNCACHED_REGION > (_ramend - _ramstart)) { |
520 | console_init(); | |
d8804adf | 521 | panic("DMA region exceeds memory limit: %lu.", |
856783b3 | 522 | _ramend - _ramstart); |
1aafd909 | 523 | } |
2f812c0b RG |
524 | max_mem = memory_end = _ramend - DMA_UNCACHED_REGION; |
525 | ||
526 | #if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263) | |
527 | /* Due to a Hardware Anomaly we need to limit the size of usable | |
528 | * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on | |
529 | * 05000263 - Hardware loop corrupted when taking an ICPLB exception | |
530 | */ | |
531 | # if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO)) | |
532 | if (max_mem >= 56 * 1024 * 1024) | |
533 | max_mem = 56 * 1024 * 1024; | |
534 | # else | |
535 | if (max_mem >= 60 * 1024 * 1024) | |
536 | max_mem = 60 * 1024 * 1024; | |
537 | # endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */ | |
538 | #endif /* ANOMALY_05000263 */ | |
539 | ||
1394f032 | 540 | |
b97b8a99 | 541 | #ifdef CONFIG_MPU |
8f65873e | 542 | /* Round up to multiple of 4MB */ |
b97b8a99 BS |
543 | memory_start = (_ramstart + 0x3fffff) & ~0x3fffff; |
544 | #else | |
1394f032 | 545 | memory_start = PAGE_ALIGN(_ramstart); |
b97b8a99 | 546 | #endif |
1394f032 BW |
547 | |
548 | #if defined(CONFIG_MTD_UCLINUX) | |
549 | /* generic memory mapped MTD driver */ | |
550 | memory_mtd_end = memory_end; | |
551 | ||
552 | mtd_phys = _ramstart; | |
553 | mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8))); | |
554 | ||
555 | # if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS) | |
556 | if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC) | |
557 | mtd_size = | |
558 | PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10); | |
559 | # endif | |
560 | ||
561 | # if defined(CONFIG_CRAMFS) | |
562 | if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC) | |
563 | mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4))); | |
564 | # endif | |
565 | ||
566 | # if defined(CONFIG_ROMFS_FS) | |
567 | if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0 | |
2f812c0b | 568 | && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) { |
1394f032 BW |
569 | mtd_size = |
570 | PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2])); | |
2f812c0b RG |
571 | |
572 | /* ROM_FS is XIP, so if we found it, we need to limit memory */ | |
573 | if (memory_end > max_mem) { | |
574 | pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem >> 20); | |
575 | memory_end = max_mem; | |
576 | } | |
577 | } | |
1394f032 BW |
578 | # endif /* CONFIG_ROMFS_FS */ |
579 | ||
dc437b1b RG |
580 | /* Since the default MTD_UCLINUX has no magic number, we just blindly |
581 | * read 8 past the end of the kernel's image, and look at it. | |
582 | * When no image is attached, mtd_size is set to a random number | |
583 | * Do some basic sanity checks before operating on things | |
584 | */ | |
585 | if (mtd_size == 0 || memory_end <= mtd_size) { | |
586 | pr_emerg("Could not find valid ram mtd attached.\n"); | |
587 | } else { | |
588 | memory_end -= mtd_size; | |
589 | ||
590 | /* Relocate MTD image to the top of memory after the uncached memory area */ | |
591 | uclinux_ram_map.phys = memory_mtd_start = memory_end; | |
592 | uclinux_ram_map.size = mtd_size; | |
593 | pr_info("Found mtd parition at 0x%p, (len=0x%lx), moving to 0x%p\n", | |
594 | _end, mtd_size, (void *)memory_mtd_start); | |
595 | dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size); | |
1394f032 | 596 | } |
1394f032 BW |
597 | #endif /* CONFIG_MTD_UCLINUX */ |
598 | ||
2f812c0b RG |
599 | /* We need lo limit memory, since everything could have a text section |
600 | * of userspace in it, and expose anomaly 05000263. If the anomaly | |
601 | * doesn't exist, or we don't need to - then dont. | |
1394f032 | 602 | */ |
2f812c0b RG |
603 | if (memory_end > max_mem) { |
604 | pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem >> 20); | |
605 | memory_end = max_mem; | |
606 | } | |
1394f032 | 607 | |
b97b8a99 BS |
608 | #ifdef CONFIG_MPU |
609 | page_mask_nelts = ((_ramend >> PAGE_SHIFT) + 31) / 32; | |
610 | page_mask_order = get_order(3 * page_mask_nelts * sizeof(long)); | |
611 | #endif | |
612 | ||
1394f032 | 613 | #if !defined(CONFIG_MTD_UCLINUX) |
856783b3 YL |
614 | /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/ |
615 | memory_end -= SIZE_4K; | |
1394f032 | 616 | #endif |
856783b3 | 617 | |
1394f032 BW |
618 | init_mm.start_code = (unsigned long)_stext; |
619 | init_mm.end_code = (unsigned long)_etext; | |
620 | init_mm.end_data = (unsigned long)_edata; | |
621 | init_mm.brk = (unsigned long)0; | |
622 | ||
856783b3 YL |
623 | printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20); |
624 | printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20); | |
625 | ||
b7627acc | 626 | printk(KERN_INFO "Memory map:\n" |
ad361c98 JP |
627 | " fixedcode = 0x%p-0x%p\n" |
628 | " text = 0x%p-0x%p\n" | |
629 | " rodata = 0x%p-0x%p\n" | |
630 | " bss = 0x%p-0x%p\n" | |
631 | " data = 0x%p-0x%p\n" | |
632 | " stack = 0x%p-0x%p\n" | |
633 | " init = 0x%p-0x%p\n" | |
634 | " available = 0x%p-0x%p\n" | |
856783b3 | 635 | #ifdef CONFIG_MTD_UCLINUX |
ad361c98 | 636 | " rootfs = 0x%p-0x%p\n" |
856783b3 YL |
637 | #endif |
638 | #if DMA_UNCACHED_REGION > 0 | |
ad361c98 | 639 | " DMA Zone = 0x%p-0x%p\n" |
856783b3 | 640 | #endif |
8929ecf8 MF |
641 | , (void *)FIXED_CODE_START, (void *)FIXED_CODE_END, |
642 | _stext, _etext, | |
856783b3 | 643 | __start_rodata, __end_rodata, |
b7627acc | 644 | __bss_start, __bss_stop, |
856783b3 YL |
645 | _sdata, _edata, |
646 | (void *)&init_thread_union, | |
647 | (void *)((int)(&init_thread_union) + 0x2000), | |
b7627acc MF |
648 | __init_begin, __init_end, |
649 | (void *)_ramstart, (void *)memory_end | |
856783b3 YL |
650 | #ifdef CONFIG_MTD_UCLINUX |
651 | , (void *)memory_mtd_start, (void *)(memory_mtd_start + mtd_size) | |
652 | #endif | |
653 | #if DMA_UNCACHED_REGION > 0 | |
654 | , (void *)(_ramend - DMA_UNCACHED_REGION), (void *)(_ramend) | |
655 | #endif | |
656 | ); | |
657 | } | |
658 | ||
2e8d7965 YL |
659 | /* |
660 | * Find the lowest, highest page frame number we have available | |
661 | */ | |
662 | void __init find_min_max_pfn(void) | |
663 | { | |
664 | int i; | |
665 | ||
666 | max_pfn = 0; | |
667 | min_low_pfn = memory_end; | |
668 | ||
669 | for (i = 0; i < bfin_memmap.nr_map; i++) { | |
670 | unsigned long start, end; | |
671 | /* RAM? */ | |
672 | if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM) | |
673 | continue; | |
674 | start = PFN_UP(bfin_memmap.map[i].addr); | |
675 | end = PFN_DOWN(bfin_memmap.map[i].addr + | |
676 | bfin_memmap.map[i].size); | |
677 | if (start >= end) | |
678 | continue; | |
679 | if (end > max_pfn) | |
680 | max_pfn = end; | |
681 | if (start < min_low_pfn) | |
682 | min_low_pfn = start; | |
683 | } | |
684 | } | |
685 | ||
856783b3 YL |
686 | static __init void setup_bootmem_allocator(void) |
687 | { | |
688 | int bootmap_size; | |
689 | int i; | |
2e8d7965 | 690 | unsigned long start_pfn, end_pfn; |
856783b3 YL |
691 | unsigned long curr_pfn, last_pfn, size; |
692 | ||
693 | /* mark memory between memory_start and memory_end usable */ | |
694 | add_memory_region(memory_start, | |
695 | memory_end - memory_start, BFIN_MEMMAP_RAM); | |
696 | /* sanity check for overlap */ | |
697 | sanitize_memmap(bfin_memmap.map, &bfin_memmap.nr_map); | |
698 | print_memory_map("boot memmap"); | |
699 | ||
2e8d7965 YL |
700 | /* intialize globals in linux/bootmem.h */ |
701 | find_min_max_pfn(); | |
702 | /* pfn of the last usable page frame */ | |
703 | if (max_pfn > memory_end >> PAGE_SHIFT) | |
704 | max_pfn = memory_end >> PAGE_SHIFT; | |
705 | /* pfn of last page frame directly mapped by kernel */ | |
706 | max_low_pfn = max_pfn; | |
707 | /* pfn of the first usable page frame after kernel image*/ | |
708 | if (min_low_pfn < memory_start >> PAGE_SHIFT) | |
709 | min_low_pfn = memory_start >> PAGE_SHIFT; | |
710 | ||
711 | start_pfn = PAGE_OFFSET >> PAGE_SHIFT; | |
712 | end_pfn = memory_end >> PAGE_SHIFT; | |
856783b3 YL |
713 | |
714 | /* | |
8f65873e | 715 | * give all the memory to the bootmap allocator, tell it to put the |
856783b3 YL |
716 | * boot mem_map at the start of memory. |
717 | */ | |
718 | bootmap_size = init_bootmem_node(NODE_DATA(0), | |
719 | memory_start >> PAGE_SHIFT, /* map goes here */ | |
2e8d7965 | 720 | start_pfn, end_pfn); |
856783b3 YL |
721 | |
722 | /* register the memmap regions with the bootmem allocator */ | |
723 | for (i = 0; i < bfin_memmap.nr_map; i++) { | |
724 | /* | |
725 | * Reserve usable memory | |
726 | */ | |
727 | if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM) | |
728 | continue; | |
729 | /* | |
730 | * We are rounding up the start address of usable memory: | |
731 | */ | |
732 | curr_pfn = PFN_UP(bfin_memmap.map[i].addr); | |
2e8d7965 | 733 | if (curr_pfn >= end_pfn) |
856783b3 YL |
734 | continue; |
735 | /* | |
736 | * ... and at the end of the usable range downwards: | |
737 | */ | |
738 | last_pfn = PFN_DOWN(bfin_memmap.map[i].addr + | |
739 | bfin_memmap.map[i].size); | |
740 | ||
2e8d7965 YL |
741 | if (last_pfn > end_pfn) |
742 | last_pfn = end_pfn; | |
856783b3 YL |
743 | |
744 | /* | |
745 | * .. finally, did all the rounding and playing | |
746 | * around just make the area go away? | |
747 | */ | |
748 | if (last_pfn <= curr_pfn) | |
749 | continue; | |
750 | ||
751 | size = last_pfn - curr_pfn; | |
752 | free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size)); | |
753 | } | |
754 | ||
755 | /* reserve memory before memory_start, including bootmap */ | |
756 | reserve_bootmem(PAGE_OFFSET, | |
757 | memory_start + bootmap_size + PAGE_SIZE - 1 - PAGE_OFFSET, | |
758 | BOOTMEM_DEFAULT); | |
759 | } | |
760 | ||
a086ee22 MF |
761 | #define EBSZ_TO_MEG(ebsz) \ |
762 | ({ \ | |
763 | int meg = 0; \ | |
764 | switch (ebsz & 0xf) { \ | |
765 | case 0x1: meg = 16; break; \ | |
766 | case 0x3: meg = 32; break; \ | |
767 | case 0x5: meg = 64; break; \ | |
768 | case 0x7: meg = 128; break; \ | |
769 | case 0x9: meg = 256; break; \ | |
770 | case 0xb: meg = 512; break; \ | |
771 | } \ | |
772 | meg; \ | |
773 | }) | |
774 | static inline int __init get_mem_size(void) | |
775 | { | |
99d95bbd MH |
776 | #if defined(EBIU_SDBCTL) |
777 | # if defined(BF561_FAMILY) | |
a086ee22 MF |
778 | int ret = 0; |
779 | u32 sdbctl = bfin_read_EBIU_SDBCTL(); | |
780 | ret += EBSZ_TO_MEG(sdbctl >> 0); | |
781 | ret += EBSZ_TO_MEG(sdbctl >> 8); | |
782 | ret += EBSZ_TO_MEG(sdbctl >> 16); | |
783 | ret += EBSZ_TO_MEG(sdbctl >> 24); | |
784 | return ret; | |
99d95bbd | 785 | # else |
a086ee22 | 786 | return EBSZ_TO_MEG(bfin_read_EBIU_SDBCTL()); |
99d95bbd MH |
787 | # endif |
788 | #elif defined(EBIU_DDRCTL1) | |
1e78042c MH |
789 | u32 ddrctl = bfin_read_EBIU_DDRCTL1(); |
790 | int ret = 0; | |
791 | switch (ddrctl & 0xc0000) { | |
792 | case DEVSZ_64: ret = 64 / 8; | |
793 | case DEVSZ_128: ret = 128 / 8; | |
794 | case DEVSZ_256: ret = 256 / 8; | |
795 | case DEVSZ_512: ret = 512 / 8; | |
796 | } | |
797 | switch (ddrctl & 0x30000) { | |
798 | case DEVWD_4: ret *= 2; | |
799 | case DEVWD_8: ret *= 2; | |
800 | case DEVWD_16: break; | |
a086ee22 | 801 | } |
b1b154e5 MF |
802 | if ((ddrctl & 0xc000) == 0x4000) |
803 | ret *= 2; | |
1e78042c | 804 | return ret; |
a086ee22 MF |
805 | #endif |
806 | BUG(); | |
807 | } | |
808 | ||
856783b3 YL |
809 | void __init setup_arch(char **cmdline_p) |
810 | { | |
9f8e895d | 811 | unsigned long sclk, cclk; |
856783b3 | 812 | |
bd854c07 RG |
813 | /* Check to make sure we are running on the right processor */ |
814 | if (unlikely(CPUID != bfin_cpuid())) | |
815 | printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n", | |
816 | CPU, bfin_cpuid(), bfin_revid()); | |
817 | ||
856783b3 YL |
818 | #ifdef CONFIG_DUMMY_CONSOLE |
819 | conswitchp = &dummy_con; | |
820 | #endif | |
821 | ||
822 | #if defined(CONFIG_CMDLINE_BOOL) | |
823 | strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line)); | |
824 | command_line[sizeof(command_line) - 1] = 0; | |
825 | #endif | |
826 | ||
827 | /* Keep a copy of command line */ | |
828 | *cmdline_p = &command_line[0]; | |
829 | memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE); | |
830 | boot_command_line[COMMAND_LINE_SIZE - 1] = '\0'; | |
831 | ||
856783b3 YL |
832 | memset(&bfin_memmap, 0, sizeof(bfin_memmap)); |
833 | ||
bd854c07 RG |
834 | /* If the user does not specify things on the command line, use |
835 | * what the bootloader set things up as | |
836 | */ | |
837 | physical_mem_end = 0; | |
856783b3 YL |
838 | parse_cmdline_early(&command_line[0]); |
839 | ||
bd854c07 RG |
840 | if (_ramend == 0) |
841 | _ramend = get_mem_size() * 1024 * 1024; | |
842 | ||
856783b3 YL |
843 | if (physical_mem_end == 0) |
844 | physical_mem_end = _ramend; | |
845 | ||
846 | memory_setup(); | |
847 | ||
7e64acab MF |
848 | /* Initialize Async memory banks */ |
849 | bfin_write_EBIU_AMBCTL0(AMBCTL0VAL); | |
850 | bfin_write_EBIU_AMBCTL1(AMBCTL1VAL); | |
851 | bfin_write_EBIU_AMGCTL(AMGCTLVAL); | |
852 | #ifdef CONFIG_EBIU_MBSCTLVAL | |
853 | bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTLVAL); | |
854 | bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL); | |
855 | bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL); | |
856 | #endif | |
857 | ||
856783b3 YL |
858 | cclk = get_cclk(); |
859 | sclk = get_sclk(); | |
860 | ||
7f3aee3c SZ |
861 | if ((ANOMALY_05000273 || ANOMALY_05000274) && (cclk >> 1) < sclk) |
862 | panic("ANOMALY 05000273 or 05000274: CCLK must be >= 2*SCLK"); | |
856783b3 YL |
863 | |
864 | #ifdef BF561_FAMILY | |
865 | if (ANOMALY_05000266) { | |
866 | bfin_read_IMDMA_D0_IRQ_STATUS(); | |
867 | bfin_read_IMDMA_D1_IRQ_STATUS(); | |
868 | } | |
869 | #endif | |
870 | printk(KERN_INFO "Hardware Trace "); | |
871 | if (bfin_read_TBUFCTL() & 0x1) | |
ad361c98 | 872 | printk(KERN_CONT "Active "); |
856783b3 | 873 | else |
ad361c98 | 874 | printk(KERN_CONT "Off "); |
856783b3 | 875 | if (bfin_read_TBUFCTL() & 0x2) |
ad361c98 | 876 | printk(KERN_CONT "and Enabled\n"); |
856783b3 | 877 | else |
ad361c98 | 878 | printk(KERN_CONT "and Disabled\n"); |
856783b3 | 879 | |
76e8fe4d RG |
880 | printk(KERN_INFO "Boot Mode: %i\n", bfin_read_SYSCR() & 0xF); |
881 | ||
ed1fb604 MF |
882 | /* Newer parts mirror SWRST bits in SYSCR */ |
883 | #if defined(CONFIG_BF53x) || defined(CONFIG_BF561) || \ | |
884 | defined(CONFIG_BF538) || defined(CONFIG_BF539) | |
7728ec33 | 885 | _bfin_swrst = bfin_read_SWRST(); |
ed1fb604 | 886 | #else |
0de4adfb SZ |
887 | /* Clear boot mode field */ |
888 | _bfin_swrst = bfin_read_SYSCR() & ~0xf; | |
ed1fb604 | 889 | #endif |
7728ec33 | 890 | |
0c7a6b21 RG |
891 | #ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT |
892 | bfin_write_SWRST(_bfin_swrst & ~DOUBLE_FAULT); | |
893 | #endif | |
894 | #ifdef CONFIG_DEBUG_DOUBLEFAULT_RESET | |
895 | bfin_write_SWRST(_bfin_swrst | DOUBLE_FAULT); | |
896 | #endif | |
2d200980 | 897 | |
8f65873e GY |
898 | #ifdef CONFIG_SMP |
899 | if (_bfin_swrst & SWRST_DBL_FAULT_A) { | |
900 | #else | |
0c7a6b21 | 901 | if (_bfin_swrst & RESET_DOUBLE) { |
8f65873e | 902 | #endif |
0c7a6b21 RG |
903 | printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n"); |
904 | #ifdef CONFIG_DEBUG_DOUBLEFAULT | |
905 | /* We assume the crashing kernel, and the current symbol table match */ | |
906 | printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n", | |
907 | (int)init_saved_seqstat & SEQSTAT_EXCAUSE, init_saved_retx); | |
908 | printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr); | |
909 | printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr); | |
910 | #endif | |
911 | printk(KERN_NOTICE " The instruction at %pF caused a double exception\n", | |
912 | init_retx); | |
913 | } else if (_bfin_swrst & RESET_WDOG) | |
7728ec33 RG |
914 | printk(KERN_INFO "Recovering from Watchdog event\n"); |
915 | else if (_bfin_swrst & RESET_SOFTWARE) | |
916 | printk(KERN_NOTICE "Reset caused by Software reset\n"); | |
917 | ||
972de7d9 | 918 | printk(KERN_INFO "Blackfin support (C) 2004-2009 Analog Devices, Inc.\n"); |
de3025f4 JZ |
919 | if (bfin_compiled_revid() == 0xffff) |
920 | printk(KERN_INFO "Compiled for ADSP-%s Rev any\n", CPU); | |
921 | else if (bfin_compiled_revid() == -1) | |
922 | printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU); | |
923 | else | |
924 | printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid()); | |
e482cad2 | 925 | |
bd854c07 | 926 | if (likely(CPUID == bfin_cpuid())) { |
e482cad2 RG |
927 | if (bfin_revid() != bfin_compiled_revid()) { |
928 | if (bfin_compiled_revid() == -1) | |
929 | printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n", | |
930 | bfin_revid()); | |
7419a327 | 931 | else if (bfin_compiled_revid() != 0xffff) { |
e482cad2 RG |
932 | printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n", |
933 | bfin_compiled_revid(), bfin_revid()); | |
7419a327 | 934 | if (bfin_compiled_revid() > bfin_revid()) |
d8804adf | 935 | panic("Error: you are missing anomaly workarounds for this rev"); |
7419a327 | 936 | } |
e482cad2 | 937 | } |
da986b9f | 938 | if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX) |
e482cad2 RG |
939 | printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n", |
940 | CPU, bfin_revid()); | |
de3025f4 | 941 | } |
0c0497c2 | 942 | |
1394f032 BW |
943 | printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n"); |
944 | ||
b5c0e2e8 | 945 | printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n", |
8f65873e | 946 | cclk / 1000000, sclk / 1000000); |
1394f032 | 947 | |
856783b3 | 948 | setup_bootmem_allocator(); |
1394f032 | 949 | |
1394f032 BW |
950 | paging_init(); |
951 | ||
7adfb58f BS |
952 | /* Copy atomic sequences to their fixed location, and sanity check that |
953 | these locations are the ones that we advertise to userspace. */ | |
954 | memcpy((void *)FIXED_CODE_START, &fixed_code_start, | |
955 | FIXED_CODE_END - FIXED_CODE_START); | |
956 | BUG_ON((char *)&sigreturn_stub - (char *)&fixed_code_start | |
957 | != SIGRETURN_STUB - FIXED_CODE_START); | |
958 | BUG_ON((char *)&atomic_xchg32 - (char *)&fixed_code_start | |
959 | != ATOMIC_XCHG32 - FIXED_CODE_START); | |
960 | BUG_ON((char *)&atomic_cas32 - (char *)&fixed_code_start | |
961 | != ATOMIC_CAS32 - FIXED_CODE_START); | |
962 | BUG_ON((char *)&atomic_add32 - (char *)&fixed_code_start | |
963 | != ATOMIC_ADD32 - FIXED_CODE_START); | |
964 | BUG_ON((char *)&atomic_sub32 - (char *)&fixed_code_start | |
965 | != ATOMIC_SUB32 - FIXED_CODE_START); | |
966 | BUG_ON((char *)&atomic_ior32 - (char *)&fixed_code_start | |
967 | != ATOMIC_IOR32 - FIXED_CODE_START); | |
968 | BUG_ON((char *)&atomic_and32 - (char *)&fixed_code_start | |
969 | != ATOMIC_AND32 - FIXED_CODE_START); | |
970 | BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start | |
971 | != ATOMIC_XOR32 - FIXED_CODE_START); | |
9f336a53 RG |
972 | BUG_ON((char *)&safe_user_instruction - (char *)&fixed_code_start |
973 | != SAFE_USER_INSTRUCTION - FIXED_CODE_START); | |
29440a2b | 974 | |
8f65873e GY |
975 | #ifdef CONFIG_SMP |
976 | platform_init_cpus(); | |
977 | #endif | |
8be80ed3 | 978 | init_exception_vectors(); |
8f65873e | 979 | bfin_cache_init(); /* Initialize caches for the boot CPU */ |
1394f032 BW |
980 | } |
981 | ||
1394f032 BW |
982 | static int __init topology_init(void) |
983 | { | |
8f65873e GY |
984 | unsigned int cpu; |
985 | /* Record CPU-private information for the boot processor. */ | |
986 | bfin_setup_cpudata(0); | |
6cda2e90 MH |
987 | |
988 | for_each_possible_cpu(cpu) { | |
8f65873e | 989 | register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu); |
6cda2e90 MH |
990 | } |
991 | ||
1394f032 | 992 | return 0; |
1394f032 BW |
993 | } |
994 | ||
995 | subsys_initcall(topology_init); | |
996 | ||
7f1e2f98 MF |
997 | /* Get the input clock frequency */ |
998 | static u_long cached_clkin_hz = CONFIG_CLKIN_HZ; | |
999 | static u_long get_clkin_hz(void) | |
1000 | { | |
1001 | return cached_clkin_hz; | |
1002 | } | |
1003 | static int __init early_init_clkin_hz(char *buf) | |
1004 | { | |
1005 | cached_clkin_hz = simple_strtoul(buf, NULL, 0); | |
508808cd MF |
1006 | #ifdef BFIN_KERNEL_CLOCK |
1007 | if (cached_clkin_hz != CONFIG_CLKIN_HZ) | |
1008 | panic("cannot change clkin_hz when reprogramming clocks"); | |
1009 | #endif | |
7f1e2f98 MF |
1010 | return 1; |
1011 | } | |
1012 | early_param("clkin_hz=", early_init_clkin_hz); | |
1013 | ||
3a2521fa | 1014 | /* Get the voltage input multiplier */ |
52a07812 | 1015 | static u_long get_vco(void) |
1394f032 | 1016 | { |
e32f55d9 MF |
1017 | static u_long cached_vco; |
1018 | u_long msel, pll_ctl; | |
1394f032 | 1019 | |
e32f55d9 MF |
1020 | /* The assumption here is that VCO never changes at runtime. |
1021 | * If, someday, we support that, then we'll have to change this. | |
1022 | */ | |
1023 | if (cached_vco) | |
3a2521fa | 1024 | return cached_vco; |
3a2521fa | 1025 | |
e32f55d9 | 1026 | pll_ctl = bfin_read_PLL_CTL(); |
3a2521fa | 1027 | msel = (pll_ctl >> 9) & 0x3F; |
1394f032 BW |
1028 | if (0 == msel) |
1029 | msel = 64; | |
1030 | ||
7f1e2f98 | 1031 | cached_vco = get_clkin_hz(); |
3a2521fa MF |
1032 | cached_vco >>= (1 & pll_ctl); /* DF bit */ |
1033 | cached_vco *= msel; | |
1034 | return cached_vco; | |
1394f032 BW |
1035 | } |
1036 | ||
2f6cf7bf | 1037 | /* Get the Core clock */ |
1394f032 BW |
1038 | u_long get_cclk(void) |
1039 | { | |
e32f55d9 | 1040 | static u_long cached_cclk_pll_div, cached_cclk; |
1394f032 | 1041 | u_long csel, ssel; |
3a2521fa | 1042 | |
1394f032 | 1043 | if (bfin_read_PLL_STAT() & 0x1) |
7f1e2f98 | 1044 | return get_clkin_hz(); |
1394f032 BW |
1045 | |
1046 | ssel = bfin_read_PLL_DIV(); | |
3a2521fa MF |
1047 | if (ssel == cached_cclk_pll_div) |
1048 | return cached_cclk; | |
1049 | else | |
1050 | cached_cclk_pll_div = ssel; | |
1051 | ||
1394f032 BW |
1052 | csel = ((ssel >> 4) & 0x03); |
1053 | ssel &= 0xf; | |
1054 | if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */ | |
3a2521fa MF |
1055 | cached_cclk = get_vco() / ssel; |
1056 | else | |
1057 | cached_cclk = get_vco() >> csel; | |
1058 | return cached_cclk; | |
1394f032 | 1059 | } |
1394f032 BW |
1060 | EXPORT_SYMBOL(get_cclk); |
1061 | ||
1062 | /* Get the System clock */ | |
1063 | u_long get_sclk(void) | |
1064 | { | |
e32f55d9 | 1065 | static u_long cached_sclk; |
1394f032 BW |
1066 | u_long ssel; |
1067 | ||
e32f55d9 MF |
1068 | /* The assumption here is that SCLK never changes at runtime. |
1069 | * If, someday, we support that, then we'll have to change this. | |
1070 | */ | |
1071 | if (cached_sclk) | |
1072 | return cached_sclk; | |
1073 | ||
1394f032 | 1074 | if (bfin_read_PLL_STAT() & 0x1) |
7f1e2f98 | 1075 | return get_clkin_hz(); |
1394f032 | 1076 | |
e32f55d9 | 1077 | ssel = bfin_read_PLL_DIV() & 0xf; |
1394f032 BW |
1078 | if (0 == ssel) { |
1079 | printk(KERN_WARNING "Invalid System Clock\n"); | |
1080 | ssel = 1; | |
1081 | } | |
1082 | ||
3a2521fa MF |
1083 | cached_sclk = get_vco() / ssel; |
1084 | return cached_sclk; | |
1394f032 | 1085 | } |
1394f032 BW |
1086 | EXPORT_SYMBOL(get_sclk); |
1087 | ||
2f6cf7bf MF |
1088 | unsigned long sclk_to_usecs(unsigned long sclk) |
1089 | { | |
1754a5d9 MF |
1090 | u64 tmp = USEC_PER_SEC * (u64)sclk; |
1091 | do_div(tmp, get_sclk()); | |
1092 | return tmp; | |
2f6cf7bf MF |
1093 | } |
1094 | EXPORT_SYMBOL(sclk_to_usecs); | |
1095 | ||
1096 | unsigned long usecs_to_sclk(unsigned long usecs) | |
1097 | { | |
1754a5d9 MF |
1098 | u64 tmp = get_sclk() * (u64)usecs; |
1099 | do_div(tmp, USEC_PER_SEC); | |
1100 | return tmp; | |
2f6cf7bf MF |
1101 | } |
1102 | EXPORT_SYMBOL(usecs_to_sclk); | |
1103 | ||
1394f032 BW |
1104 | /* |
1105 | * Get CPU information for use by the procfs. | |
1106 | */ | |
1107 | static int show_cpuinfo(struct seq_file *m, void *v) | |
1108 | { | |
066954a3 | 1109 | char *cpu, *mmu, *fpu, *vendor, *cache; |
1394f032 | 1110 | uint32_t revid; |
275123e8 | 1111 | int cpu_num = *(unsigned int *)v; |
a5f0717e | 1112 | u_long sclk, cclk; |
9de3a0b6 | 1113 | u_int icache_size = BFIN_ICACHESIZE / 1024, dcache_size = 0, dsup_banks = 0; |
275123e8 | 1114 | struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu_num); |
1394f032 BW |
1115 | |
1116 | cpu = CPU; | |
1117 | mmu = "none"; | |
1118 | fpu = "none"; | |
1119 | revid = bfin_revid(); | |
1394f032 | 1120 | |
1394f032 | 1121 | sclk = get_sclk(); |
a5f0717e | 1122 | cclk = get_cclk(); |
1394f032 | 1123 | |
73b0c0b0 | 1124 | switch (bfin_read_CHIPID() & CHIPID_MANUFACTURE) { |
066954a3 MF |
1125 | case 0xca: |
1126 | vendor = "Analog Devices"; | |
73b0c0b0 RG |
1127 | break; |
1128 | default: | |
066954a3 MF |
1129 | vendor = "unknown"; |
1130 | break; | |
73b0c0b0 | 1131 | } |
1394f032 | 1132 | |
275123e8 | 1133 | seq_printf(m, "processor\t: %d\n" "vendor_id\t: %s\n", cpu_num, vendor); |
e482cad2 RG |
1134 | |
1135 | if (CPUID == bfin_cpuid()) | |
1136 | seq_printf(m, "cpu family\t: 0x%04x\n", CPUID); | |
1137 | else | |
1138 | seq_printf(m, "cpu family\t: Compiled for:0x%04x, running on:0x%04x\n", | |
1139 | CPUID, bfin_cpuid()); | |
1140 | ||
1141 | seq_printf(m, "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n" | |
2466ac65 | 1142 | "stepping\t: %d ", |
a5f0717e | 1143 | cpu, cclk/1000000, sclk/1000000, |
253bcf4f RG |
1144 | #ifdef CONFIG_MPU |
1145 | "mpu on", | |
1146 | #else | |
1147 | "mpu off", | |
1148 | #endif | |
73b0c0b0 RG |
1149 | revid); |
1150 | ||
2466ac65 RG |
1151 | if (bfin_revid() != bfin_compiled_revid()) { |
1152 | if (bfin_compiled_revid() == -1) | |
1153 | seq_printf(m, "(Compiled for Rev none)"); | |
1154 | else if (bfin_compiled_revid() == 0xffff) | |
1155 | seq_printf(m, "(Compiled for Rev any)"); | |
1156 | else | |
1157 | seq_printf(m, "(Compiled for Rev %d)", bfin_compiled_revid()); | |
1158 | } | |
1159 | ||
1160 | seq_printf(m, "\ncpu MHz\t\t: %lu.%03lu/%lu.%03lu\n", | |
a5f0717e | 1161 | cclk/1000000, cclk%1000000, |
73b0c0b0 RG |
1162 | sclk/1000000, sclk%1000000); |
1163 | seq_printf(m, "bogomips\t: %lu.%02lu\n" | |
1164 | "Calibration\t: %lu loops\n", | |
c70c754f MH |
1165 | (loops_per_jiffy * HZ) / 500000, |
1166 | ((loops_per_jiffy * HZ) / 5000) % 100, | |
1167 | (loops_per_jiffy * HZ)); | |
73b0c0b0 RG |
1168 | |
1169 | /* Check Cache configutation */ | |
8f65873e | 1170 | switch (cpudata->dmemctl & (1 << DMC0_P | 1 << DMC1_P)) { |
1f83b8f1 | 1171 | case ACACHE_BSRAM: |
066954a3 | 1172 | cache = "dbank-A/B\t: cache/sram"; |
1f83b8f1 MF |
1173 | dcache_size = 16; |
1174 | dsup_banks = 1; | |
1175 | break; | |
1176 | case ACACHE_BCACHE: | |
066954a3 | 1177 | cache = "dbank-A/B\t: cache/cache"; |
1f83b8f1 MF |
1178 | dcache_size = 32; |
1179 | dsup_banks = 2; | |
1180 | break; | |
1181 | case ASRAM_BSRAM: | |
066954a3 | 1182 | cache = "dbank-A/B\t: sram/sram"; |
1f83b8f1 MF |
1183 | dcache_size = 0; |
1184 | dsup_banks = 0; | |
1185 | break; | |
1186 | default: | |
066954a3 | 1187 | cache = "unknown"; |
73b0c0b0 RG |
1188 | dcache_size = 0; |
1189 | dsup_banks = 0; | |
1394f032 BW |
1190 | break; |
1191 | } | |
1192 | ||
73b0c0b0 | 1193 | /* Is it turned on? */ |
8f65873e | 1194 | if ((cpudata->dmemctl & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE)) |
73b0c0b0 | 1195 | dcache_size = 0; |
1394f032 | 1196 | |
8f65873e | 1197 | if ((cpudata->imemctl & (IMC | ENICPLB)) != (IMC | ENICPLB)) |
9de3a0b6 RG |
1198 | icache_size = 0; |
1199 | ||
73b0c0b0 | 1200 | seq_printf(m, "cache size\t: %d KB(L1 icache) " |
41ba653f JZ |
1201 | "%d KB(L1 dcache) %d KB(L2 cache)\n", |
1202 | icache_size, dcache_size, 0); | |
73b0c0b0 | 1203 | seq_printf(m, "%s\n", cache); |
41ba653f JZ |
1204 | seq_printf(m, "external memory\t: " |
1205 | #if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) | |
1206 | "cacheable" | |
1207 | #else | |
1208 | "uncacheable" | |
1209 | #endif | |
1210 | " in instruction cache\n"); | |
1211 | seq_printf(m, "external memory\t: " | |
1212 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) | |
1213 | "cacheable (write-back)" | |
1214 | #elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH) | |
1215 | "cacheable (write-through)" | |
1216 | #else | |
1217 | "uncacheable" | |
1218 | #endif | |
1219 | " in data cache\n"); | |
73b0c0b0 | 1220 | |
9de3a0b6 RG |
1221 | if (icache_size) |
1222 | seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n", | |
1223 | BFIN_ISUBBANKS, BFIN_IWAYS, BFIN_ILINES); | |
1224 | else | |
1225 | seq_printf(m, "icache setup\t: off\n"); | |
1226 | ||
1394f032 | 1227 | seq_printf(m, |
73b0c0b0 | 1228 | "dcache setup\t: %d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n", |
3bebca2d RG |
1229 | dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS, |
1230 | BFIN_DLINES); | |
8f65873e | 1231 | #ifdef __ARCH_SYNC_CORE_DCACHE |
275123e8 | 1232 | seq_printf(m, "SMP Dcache Flushes\t: %lu\n\n", cpudata->dcache_invld_count); |
8f65873e | 1233 | #endif |
47e9dedb SZ |
1234 | #ifdef __ARCH_SYNC_CORE_ICACHE |
1235 | seq_printf(m, "SMP Icache Flushes\t: %lu\n\n", cpudata->icache_invld_count); | |
1236 | #endif | |
3bebca2d | 1237 | #ifdef CONFIG_BFIN_ICACHE_LOCK |
8f65873e | 1238 | switch ((cpudata->imemctl >> 3) & WAYALL_L) { |
1394f032 BW |
1239 | case WAY0_L: |
1240 | seq_printf(m, "Way0 Locked-Down\n"); | |
1241 | break; | |
1242 | case WAY1_L: | |
1243 | seq_printf(m, "Way1 Locked-Down\n"); | |
1244 | break; | |
1245 | case WAY01_L: | |
1246 | seq_printf(m, "Way0,Way1 Locked-Down\n"); | |
1247 | break; | |
1248 | case WAY2_L: | |
1249 | seq_printf(m, "Way2 Locked-Down\n"); | |
1250 | break; | |
1251 | case WAY02_L: | |
1252 | seq_printf(m, "Way0,Way2 Locked-Down\n"); | |
1253 | break; | |
1254 | case WAY12_L: | |
1255 | seq_printf(m, "Way1,Way2 Locked-Down\n"); | |
1256 | break; | |
1257 | case WAY012_L: | |
1258 | seq_printf(m, "Way0,Way1 & Way2 Locked-Down\n"); | |
1259 | break; | |
1260 | case WAY3_L: | |
1261 | seq_printf(m, "Way3 Locked-Down\n"); | |
1262 | break; | |
1263 | case WAY03_L: | |
1264 | seq_printf(m, "Way0,Way3 Locked-Down\n"); | |
1265 | break; | |
1266 | case WAY13_L: | |
1267 | seq_printf(m, "Way1,Way3 Locked-Down\n"); | |
1268 | break; | |
1269 | case WAY013_L: | |
1270 | seq_printf(m, "Way 0,Way1,Way3 Locked-Down\n"); | |
1271 | break; | |
1272 | case WAY32_L: | |
1273 | seq_printf(m, "Way3,Way2 Locked-Down\n"); | |
1274 | break; | |
1275 | case WAY320_L: | |
1276 | seq_printf(m, "Way3,Way2,Way0 Locked-Down\n"); | |
1277 | break; | |
1278 | case WAY321_L: | |
1279 | seq_printf(m, "Way3,Way2,Way1 Locked-Down\n"); | |
1280 | break; | |
1281 | case WAYALL_L: | |
1282 | seq_printf(m, "All Ways are locked\n"); | |
1283 | break; | |
1284 | default: | |
1285 | seq_printf(m, "No Ways are locked\n"); | |
1286 | } | |
8f65873e | 1287 | #endif |
275123e8 MF |
1288 | |
1289 | if (cpu_num != num_possible_cpus() - 1) | |
8f65873e GY |
1290 | return 0; |
1291 | ||
41ba653f | 1292 | if (L2_LENGTH) { |
275123e8 | 1293 | seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400); |
41ba653f JZ |
1294 | seq_printf(m, "L2 SRAM\t\t: " |
1295 | #if defined(CONFIG_BFIN_L2_ICACHEABLE) | |
1296 | "cacheable" | |
1297 | #else | |
1298 | "uncacheable" | |
1299 | #endif | |
1300 | " in instruction cache\n"); | |
1301 | seq_printf(m, "L2 SRAM\t\t: " | |
1302 | #if defined(CONFIG_BFIN_L2_WRITEBACK) | |
1303 | "cacheable (write-back)" | |
1304 | #elif defined(CONFIG_BFIN_L2_WRITETHROUGH) | |
1305 | "cacheable (write-through)" | |
1306 | #else | |
1307 | "uncacheable" | |
1308 | #endif | |
1309 | " in data cache\n"); | |
1310 | } | |
066954a3 | 1311 | seq_printf(m, "board name\t: %s\n", bfin_board_name); |
73b0c0b0 RG |
1312 | seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n", |
1313 | physical_mem_end >> 10, (void *)0, (void *)physical_mem_end); | |
1314 | seq_printf(m, "kernel memory\t: %d kB (0x%p -> 0x%p)\n", | |
1315 | ((int)memory_end - (int)_stext) >> 10, | |
1316 | _stext, | |
1317 | (void *)memory_end); | |
8f65873e | 1318 | seq_printf(m, "\n"); |
73b0c0b0 | 1319 | |
1394f032 BW |
1320 | return 0; |
1321 | } | |
1322 | ||
1323 | static void *c_start(struct seq_file *m, loff_t *pos) | |
1324 | { | |
55f2feae GY |
1325 | if (*pos == 0) |
1326 | *pos = first_cpu(cpu_online_map); | |
1327 | if (*pos >= num_online_cpus()) | |
1328 | return NULL; | |
1329 | ||
1330 | return pos; | |
1394f032 BW |
1331 | } |
1332 | ||
1333 | static void *c_next(struct seq_file *m, void *v, loff_t *pos) | |
1334 | { | |
55f2feae GY |
1335 | *pos = next_cpu(*pos, cpu_online_map); |
1336 | ||
1394f032 BW |
1337 | return c_start(m, pos); |
1338 | } | |
1339 | ||
1340 | static void c_stop(struct seq_file *m, void *v) | |
1341 | { | |
1342 | } | |
1343 | ||
03a44825 | 1344 | const struct seq_operations cpuinfo_op = { |
1394f032 BW |
1345 | .start = c_start, |
1346 | .next = c_next, | |
1347 | .stop = c_stop, | |
1348 | .show = show_cpuinfo, | |
1349 | }; | |
1350 | ||
5e10b4a6 | 1351 | void __init cmdline_init(const char *r0) |
1394f032 BW |
1352 | { |
1353 | if (r0) | |
52a07812 | 1354 | strncpy(command_line, r0, COMMAND_LINE_SIZE); |
1394f032 | 1355 | } |