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Commit | Line | Data |
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1394f032 | 1 | /* |
be1577e3 | 2 | * Copyright 2004-2010 Analog Devices Inc. |
1394f032 | 3 | * |
550d5538 | 4 | * Licensed under the GPL-2 or later. |
1394f032 BW |
5 | */ |
6 | ||
7 | #include <linux/delay.h> | |
8 | #include <linux/console.h> | |
9 | #include <linux/bootmem.h> | |
10 | #include <linux/seq_file.h> | |
11 | #include <linux/cpu.h> | |
259fea42 | 12 | #include <linux/mm.h> |
1394f032 | 13 | #include <linux/module.h> |
1394f032 | 14 | #include <linux/tty.h> |
856783b3 | 15 | #include <linux/pfn.h> |
1394f032 | 16 | |
79df1b69 MF |
17 | #ifdef CONFIG_MTD_UCLINUX |
18 | #include <linux/mtd/map.h> | |
1394f032 BW |
19 | #include <linux/ext2_fs.h> |
20 | #include <linux/cramfs_fs.h> | |
21 | #include <linux/romfs_fs.h> | |
79df1b69 | 22 | #endif |
1394f032 | 23 | |
3bebca2d | 24 | #include <asm/cplb.h> |
1394f032 BW |
25 | #include <asm/cacheflush.h> |
26 | #include <asm/blackfin.h> | |
27 | #include <asm/cplbinit.h> | |
b5affb01 | 28 | #include <asm/clocks.h> |
1754a5d9 | 29 | #include <asm/div64.h> |
8f65873e | 30 | #include <asm/cpu.h> |
7adfb58f | 31 | #include <asm/fixed_code.h> |
ce3afa1c | 32 | #include <asm/early_printk.h> |
6327a574 | 33 | #include <asm/irq_handler.h> |
3bed8d67 | 34 | #include <asm/pda.h> |
1394f032 | 35 | |
a9c59c27 | 36 | u16 _bfin_swrst; |
d45118b1 | 37 | EXPORT_SYMBOL(_bfin_swrst); |
a9c59c27 | 38 | |
1394f032 | 39 | unsigned long memory_start, memory_end, physical_mem_end; |
3132b586 | 40 | unsigned long _rambase, _ramstart, _ramend; |
1394f032 BW |
41 | unsigned long reserved_mem_dcache_on; |
42 | unsigned long reserved_mem_icache_on; | |
43 | EXPORT_SYMBOL(memory_start); | |
44 | EXPORT_SYMBOL(memory_end); | |
45 | EXPORT_SYMBOL(physical_mem_end); | |
46 | EXPORT_SYMBOL(_ramend); | |
58c35bd3 | 47 | EXPORT_SYMBOL(reserved_mem_dcache_on); |
1394f032 BW |
48 | |
49 | #ifdef CONFIG_MTD_UCLINUX | |
79df1b69 | 50 | extern struct map_info uclinux_ram_map; |
1394f032 BW |
51 | unsigned long memory_mtd_end, memory_mtd_start, mtd_size; |
52 | unsigned long _ebss; | |
53 | EXPORT_SYMBOL(memory_mtd_end); | |
54 | EXPORT_SYMBOL(memory_mtd_start); | |
55 | EXPORT_SYMBOL(mtd_size); | |
56 | #endif | |
57 | ||
5e10b4a6 | 58 | char __initdata command_line[COMMAND_LINE_SIZE]; |
fb1d9be5 | 59 | struct blackfin_initial_pda __initdata initial_pda; |
1394f032 | 60 | |
856783b3 YL |
61 | /* boot memmap, for parsing "memmap=" */ |
62 | #define BFIN_MEMMAP_MAX 128 /* number of entries in bfin_memmap */ | |
63 | #define BFIN_MEMMAP_RAM 1 | |
64 | #define BFIN_MEMMAP_RESERVED 2 | |
af4c7d4b | 65 | static struct bfin_memmap { |
856783b3 YL |
66 | int nr_map; |
67 | struct bfin_memmap_entry { | |
68 | unsigned long long addr; /* start of memory segment */ | |
69 | unsigned long long size; | |
70 | unsigned long type; | |
71 | } map[BFIN_MEMMAP_MAX]; | |
72 | } bfin_memmap __initdata; | |
73 | ||
74 | /* for memmap sanitization */ | |
75 | struct change_member { | |
76 | struct bfin_memmap_entry *pentry; /* pointer to original entry */ | |
77 | unsigned long long addr; /* address for this change point */ | |
78 | }; | |
79 | static struct change_member change_point_list[2*BFIN_MEMMAP_MAX] __initdata; | |
80 | static struct change_member *change_point[2*BFIN_MEMMAP_MAX] __initdata; | |
81 | static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata; | |
82 | static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata; | |
83 | ||
8f65873e GY |
84 | DEFINE_PER_CPU(struct blackfin_cpudata, cpu_data); |
85 | ||
7f1e2f98 MF |
86 | static int early_init_clkin_hz(char *buf); |
87 | ||
3bebca2d | 88 | #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) |
8f65873e GY |
89 | void __init generate_cplb_tables(void) |
90 | { | |
91 | unsigned int cpu; | |
92 | ||
dbdf20db | 93 | generate_cplb_tables_all(); |
8f65873e GY |
94 | /* Generate per-CPU I&D CPLB tables */ |
95 | for (cpu = 0; cpu < num_possible_cpus(); ++cpu) | |
96 | generate_cplb_tables_cpu(cpu); | |
97 | } | |
1394f032 BW |
98 | #endif |
99 | ||
8f65873e GY |
100 | void __cpuinit bfin_setup_caches(unsigned int cpu) |
101 | { | |
3bebca2d | 102 | #ifdef CONFIG_BFIN_ICACHE |
8f65873e | 103 | bfin_icache_init(icplb_tbl[cpu]); |
1394f032 BW |
104 | #endif |
105 | ||
3bebca2d | 106 | #ifdef CONFIG_BFIN_DCACHE |
8f65873e | 107 | bfin_dcache_init(dcplb_tbl[cpu]); |
8f65873e GY |
108 | #endif |
109 | ||
44491fbc MF |
110 | bfin_setup_cpudata(cpu); |
111 | ||
8f65873e GY |
112 | /* |
113 | * In cache coherence emulation mode, we need to have the | |
114 | * D-cache enabled before running any atomic operation which | |
05d17dfa | 115 | * might involve cache invalidation (i.e. spinlock, rwlock). |
8f65873e GY |
116 | * So printk's are deferred until then. |
117 | */ | |
118 | #ifdef CONFIG_BFIN_ICACHE | |
119 | printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu); | |
41ba653f JZ |
120 | printk(KERN_INFO " External memory:" |
121 | # ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE | |
122 | " cacheable" | |
123 | # else | |
124 | " uncacheable" | |
125 | # endif | |
126 | " in instruction cache\n"); | |
127 | if (L2_LENGTH) | |
128 | printk(KERN_INFO " L2 SRAM :" | |
129 | # ifdef CONFIG_BFIN_L2_ICACHEABLE | |
130 | " cacheable" | |
131 | # else | |
132 | " uncacheable" | |
133 | # endif | |
134 | " in instruction cache\n"); | |
135 | ||
136 | #else | |
137 | printk(KERN_INFO "Instruction Cache Disabled for CPU%u\n", cpu); | |
8f65873e | 138 | #endif |
41ba653f | 139 | |
8f65873e | 140 | #ifdef CONFIG_BFIN_DCACHE |
41ba653f JZ |
141 | printk(KERN_INFO "Data Cache Enabled for CPU%u\n", cpu); |
142 | printk(KERN_INFO " External memory:" | |
143 | # if defined CONFIG_BFIN_EXTMEM_WRITEBACK | |
144 | " cacheable (write-back)" | |
145 | # elif defined CONFIG_BFIN_EXTMEM_WRITETHROUGH | |
146 | " cacheable (write-through)" | |
147 | # else | |
148 | " uncacheable" | |
149 | # endif | |
150 | " in data cache\n"); | |
151 | if (L2_LENGTH) | |
152 | printk(KERN_INFO " L2 SRAM :" | |
153 | # if defined CONFIG_BFIN_L2_WRITEBACK | |
154 | " cacheable (write-back)" | |
155 | # elif defined CONFIG_BFIN_L2_WRITETHROUGH | |
156 | " cacheable (write-through)" | |
157 | # else | |
158 | " uncacheable" | |
1394f032 | 159 | # endif |
41ba653f JZ |
160 | " in data cache\n"); |
161 | #else | |
162 | printk(KERN_INFO "Data Cache Disabled for CPU%u\n", cpu); | |
1394f032 BW |
163 | #endif |
164 | } | |
165 | ||
8f65873e GY |
166 | void __cpuinit bfin_setup_cpudata(unsigned int cpu) |
167 | { | |
168 | struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu); | |
169 | ||
8f65873e GY |
170 | cpudata->imemctl = bfin_read_IMEM_CONTROL(); |
171 | cpudata->dmemctl = bfin_read_DMEM_CONTROL(); | |
172 | } | |
173 | ||
174 | void __init bfin_cache_init(void) | |
175 | { | |
176 | #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) | |
177 | generate_cplb_tables(); | |
178 | #endif | |
179 | bfin_setup_caches(0); | |
180 | } | |
181 | ||
5b04f271 | 182 | void __init bfin_relocate_l1_mem(void) |
1394f032 | 183 | { |
5cd82a6d MF |
184 | unsigned long text_l1_len = (unsigned long)_text_l1_len; |
185 | unsigned long data_l1_len = (unsigned long)_data_l1_len; | |
186 | unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len; | |
187 | unsigned long l2_len = (unsigned long)_l2_len; | |
1394f032 | 188 | |
837ec2d5 RG |
189 | early_shadow_stamp(); |
190 | ||
fecbd736 RG |
191 | /* |
192 | * due to the ALIGN(4) in the arch/blackfin/kernel/vmlinux.lds.S | |
193 | * we know that everything about l1 text/data is nice and aligned, | |
194 | * so copy by 4 byte chunks, and don't worry about overlapping | |
195 | * src/dest. | |
196 | * | |
197 | * We can't use the dma_memcpy functions, since they can call | |
198 | * scheduler functions which might be in L1 :( and core writes | |
199 | * into L1 instruction cause bad access errors, so we are stuck, | |
200 | * we are required to use DMA, but can't use the common dma | |
201 | * functions. We can't use memcpy either - since that might be | |
202 | * going to be in the relocated L1 | |
203 | */ | |
204 | ||
dd3dd384 MF |
205 | blackfin_dma_early_init(); |
206 | ||
5cd82a6d MF |
207 | /* if necessary, copy L1 text to L1 instruction SRAM */ |
208 | if (L1_CODE_LENGTH && text_l1_len) | |
209 | early_dma_memcpy(_stext_l1, _text_l1_lma, text_l1_len); | |
1394f032 | 210 | |
5cd82a6d MF |
211 | /* if necessary, copy L1 data to L1 data bank A SRAM */ |
212 | if (L1_DATA_A_LENGTH && data_l1_len) | |
213 | early_dma_memcpy(_sdata_l1, _data_l1_lma, data_l1_len); | |
1394f032 | 214 | |
5cd82a6d MF |
215 | /* if necessary, copy L1 data B to L1 data bank B SRAM */ |
216 | if (L1_DATA_B_LENGTH && data_b_l1_len) | |
217 | early_dma_memcpy(_sdata_b_l1, _data_b_l1_lma, data_b_l1_len); | |
262c3825 | 218 | |
fecbd736 RG |
219 | early_dma_memcpy_done(); |
220 | ||
c6345ab1 SZ |
221 | #if defined(CONFIG_SMP) && defined(CONFIG_ICACHE_FLUSH_L1) |
222 | blackfin_iflush_l1_entry[0] = (unsigned long)blackfin_icache_flush_range_l1; | |
223 | #endif | |
224 | ||
5cd82a6d MF |
225 | /* if necessary, copy L2 text/data to L2 SRAM */ |
226 | if (L2_LENGTH && l2_len) | |
227 | memcpy(_stext_l2, _l2_lma, l2_len); | |
1394f032 BW |
228 | } |
229 | ||
c6345ab1 SZ |
230 | #ifdef CONFIG_SMP |
231 | void __init bfin_relocate_coreb_l1_mem(void) | |
232 | { | |
233 | unsigned long text_l1_len = (unsigned long)_text_l1_len; | |
234 | unsigned long data_l1_len = (unsigned long)_data_l1_len; | |
235 | unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len; | |
236 | ||
237 | blackfin_dma_early_init(); | |
238 | ||
239 | /* if necessary, copy L1 text to L1 instruction SRAM */ | |
240 | if (L1_CODE_LENGTH && text_l1_len) | |
241 | early_dma_memcpy((void *)COREB_L1_CODE_START, _text_l1_lma, | |
242 | text_l1_len); | |
243 | ||
244 | /* if necessary, copy L1 data to L1 data bank A SRAM */ | |
245 | if (L1_DATA_A_LENGTH && data_l1_len) | |
246 | early_dma_memcpy((void *)COREB_L1_DATA_A_START, _data_l1_lma, | |
247 | data_l1_len); | |
248 | ||
249 | /* if necessary, copy L1 data B to L1 data bank B SRAM */ | |
250 | if (L1_DATA_B_LENGTH && data_b_l1_len) | |
251 | early_dma_memcpy((void *)COREB_L1_DATA_B_START, _data_b_l1_lma, | |
252 | data_b_l1_len); | |
253 | ||
254 | early_dma_memcpy_done(); | |
255 | ||
256 | #ifdef CONFIG_ICACHE_FLUSH_L1 | |
257 | blackfin_iflush_l1_entry[1] = (unsigned long)blackfin_icache_flush_range_l1 - | |
258 | (unsigned long)_stext_l1 + COREB_L1_CODE_START; | |
259 | #endif | |
260 | } | |
261 | #endif | |
262 | ||
d86bfb16 BS |
263 | #ifdef CONFIG_ROMKERNEL |
264 | void __init bfin_relocate_xip_data(void) | |
265 | { | |
266 | early_shadow_stamp(); | |
267 | ||
268 | memcpy(_sdata, _data_lma, (unsigned long)_data_len - THREAD_SIZE + sizeof(struct thread_info)); | |
269 | memcpy(_sinitdata, _init_data_lma, (unsigned long)_init_data_len); | |
270 | } | |
271 | #endif | |
272 | ||
856783b3 YL |
273 | /* add_memory_region to memmap */ |
274 | static void __init add_memory_region(unsigned long long start, | |
275 | unsigned long long size, int type) | |
276 | { | |
277 | int i; | |
278 | ||
279 | i = bfin_memmap.nr_map; | |
280 | ||
281 | if (i == BFIN_MEMMAP_MAX) { | |
282 | printk(KERN_ERR "Ooops! Too many entries in the memory map!\n"); | |
283 | return; | |
284 | } | |
285 | ||
286 | bfin_memmap.map[i].addr = start; | |
287 | bfin_memmap.map[i].size = size; | |
288 | bfin_memmap.map[i].type = type; | |
289 | bfin_memmap.nr_map++; | |
290 | } | |
291 | ||
292 | /* | |
293 | * Sanitize the boot memmap, removing overlaps. | |
294 | */ | |
295 | static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map) | |
296 | { | |
297 | struct change_member *change_tmp; | |
298 | unsigned long current_type, last_type; | |
299 | unsigned long long last_addr; | |
300 | int chgidx, still_changing; | |
301 | int overlap_entries; | |
302 | int new_entry; | |
303 | int old_nr, new_nr, chg_nr; | |
304 | int i; | |
305 | ||
306 | /* | |
307 | Visually we're performing the following (1,2,3,4 = memory types) | |
308 | ||
309 | Sample memory map (w/overlaps): | |
310 | ____22__________________ | |
311 | ______________________4_ | |
312 | ____1111________________ | |
313 | _44_____________________ | |
314 | 11111111________________ | |
315 | ____________________33__ | |
316 | ___________44___________ | |
317 | __________33333_________ | |
318 | ______________22________ | |
319 | ___________________2222_ | |
320 | _________111111111______ | |
321 | _____________________11_ | |
322 | _________________4______ | |
323 | ||
324 | Sanitized equivalent (no overlap): | |
325 | 1_______________________ | |
326 | _44_____________________ | |
327 | ___1____________________ | |
328 | ____22__________________ | |
329 | ______11________________ | |
330 | _________1______________ | |
331 | __________3_____________ | |
332 | ___________44___________ | |
333 | _____________33_________ | |
334 | _______________2________ | |
335 | ________________1_______ | |
336 | _________________4______ | |
337 | ___________________2____ | |
338 | ____________________33__ | |
339 | ______________________4_ | |
340 | */ | |
341 | /* if there's only one memory region, don't bother */ | |
342 | if (*pnr_map < 2) | |
343 | return -1; | |
344 | ||
345 | old_nr = *pnr_map; | |
346 | ||
347 | /* bail out if we find any unreasonable addresses in memmap */ | |
348 | for (i = 0; i < old_nr; i++) | |
349 | if (map[i].addr + map[i].size < map[i].addr) | |
350 | return -1; | |
351 | ||
352 | /* create pointers for initial change-point information (for sorting) */ | |
353 | for (i = 0; i < 2*old_nr; i++) | |
354 | change_point[i] = &change_point_list[i]; | |
355 | ||
356 | /* record all known change-points (starting and ending addresses), | |
357 | omitting those that are for empty memory regions */ | |
358 | chgidx = 0; | |
8f65873e | 359 | for (i = 0; i < old_nr; i++) { |
856783b3 YL |
360 | if (map[i].size != 0) { |
361 | change_point[chgidx]->addr = map[i].addr; | |
362 | change_point[chgidx++]->pentry = &map[i]; | |
363 | change_point[chgidx]->addr = map[i].addr + map[i].size; | |
364 | change_point[chgidx++]->pentry = &map[i]; | |
365 | } | |
366 | } | |
8f65873e | 367 | chg_nr = chgidx; /* true number of change-points */ |
856783b3 YL |
368 | |
369 | /* sort change-point list by memory addresses (low -> high) */ | |
370 | still_changing = 1; | |
8f65873e | 371 | while (still_changing) { |
856783b3 | 372 | still_changing = 0; |
8f65873e | 373 | for (i = 1; i < chg_nr; i++) { |
856783b3 YL |
374 | /* if <current_addr> > <last_addr>, swap */ |
375 | /* or, if current=<start_addr> & last=<end_addr>, swap */ | |
376 | if ((change_point[i]->addr < change_point[i-1]->addr) || | |
377 | ((change_point[i]->addr == change_point[i-1]->addr) && | |
378 | (change_point[i]->addr == change_point[i]->pentry->addr) && | |
379 | (change_point[i-1]->addr != change_point[i-1]->pentry->addr)) | |
380 | ) { | |
381 | change_tmp = change_point[i]; | |
382 | change_point[i] = change_point[i-1]; | |
383 | change_point[i-1] = change_tmp; | |
384 | still_changing = 1; | |
385 | } | |
386 | } | |
387 | } | |
388 | ||
389 | /* create a new memmap, removing overlaps */ | |
8f65873e GY |
390 | overlap_entries = 0; /* number of entries in the overlap table */ |
391 | new_entry = 0; /* index for creating new memmap entries */ | |
392 | last_type = 0; /* start with undefined memory type */ | |
393 | last_addr = 0; /* start with 0 as last starting address */ | |
856783b3 YL |
394 | /* loop through change-points, determining affect on the new memmap */ |
395 | for (chgidx = 0; chgidx < chg_nr; chgidx++) { | |
396 | /* keep track of all overlapping memmap entries */ | |
397 | if (change_point[chgidx]->addr == change_point[chgidx]->pentry->addr) { | |
398 | /* add map entry to overlap list (> 1 entry implies an overlap) */ | |
399 | overlap_list[overlap_entries++] = change_point[chgidx]->pentry; | |
400 | } else { | |
401 | /* remove entry from list (order independent, so swap with last) */ | |
402 | for (i = 0; i < overlap_entries; i++) { | |
403 | if (overlap_list[i] == change_point[chgidx]->pentry) | |
404 | overlap_list[i] = overlap_list[overlap_entries-1]; | |
405 | } | |
406 | overlap_entries--; | |
407 | } | |
408 | /* if there are overlapping entries, decide which "type" to use */ | |
409 | /* (larger value takes precedence -- 1=usable, 2,3,4,4+=unusable) */ | |
410 | current_type = 0; | |
411 | for (i = 0; i < overlap_entries; i++) | |
412 | if (overlap_list[i]->type > current_type) | |
413 | current_type = overlap_list[i]->type; | |
414 | /* continue building up new memmap based on this information */ | |
8f65873e | 415 | if (current_type != last_type) { |
856783b3 YL |
416 | if (last_type != 0) { |
417 | new_map[new_entry].size = | |
418 | change_point[chgidx]->addr - last_addr; | |
419 | /* move forward only if the new size was non-zero */ | |
420 | if (new_map[new_entry].size != 0) | |
421 | if (++new_entry >= BFIN_MEMMAP_MAX) | |
8f65873e | 422 | break; /* no more space left for new entries */ |
856783b3 YL |
423 | } |
424 | if (current_type != 0) { | |
425 | new_map[new_entry].addr = change_point[chgidx]->addr; | |
426 | new_map[new_entry].type = current_type; | |
427 | last_addr = change_point[chgidx]->addr; | |
428 | } | |
429 | last_type = current_type; | |
430 | } | |
431 | } | |
8f65873e | 432 | new_nr = new_entry; /* retain count for new entries */ |
856783b3 | 433 | |
8f65873e | 434 | /* copy new mapping into original location */ |
856783b3 YL |
435 | memcpy(map, new_map, new_nr*sizeof(struct bfin_memmap_entry)); |
436 | *pnr_map = new_nr; | |
437 | ||
438 | return 0; | |
439 | } | |
440 | ||
441 | static void __init print_memory_map(char *who) | |
442 | { | |
443 | int i; | |
444 | ||
445 | for (i = 0; i < bfin_memmap.nr_map; i++) { | |
446 | printk(KERN_DEBUG " %s: %016Lx - %016Lx ", who, | |
447 | bfin_memmap.map[i].addr, | |
448 | bfin_memmap.map[i].addr + bfin_memmap.map[i].size); | |
449 | switch (bfin_memmap.map[i].type) { | |
450 | case BFIN_MEMMAP_RAM: | |
ad361c98 JP |
451 | printk(KERN_CONT "(usable)\n"); |
452 | break; | |
856783b3 | 453 | case BFIN_MEMMAP_RESERVED: |
ad361c98 JP |
454 | printk(KERN_CONT "(reserved)\n"); |
455 | break; | |
456 | default: | |
457 | printk(KERN_CONT "type %lu\n", bfin_memmap.map[i].type); | |
458 | break; | |
856783b3 YL |
459 | } |
460 | } | |
461 | } | |
462 | ||
463 | static __init int parse_memmap(char *arg) | |
464 | { | |
465 | unsigned long long start_at, mem_size; | |
466 | ||
467 | if (!arg) | |
468 | return -EINVAL; | |
469 | ||
470 | mem_size = memparse(arg, &arg); | |
471 | if (*arg == '@') { | |
472 | start_at = memparse(arg+1, &arg); | |
473 | add_memory_region(start_at, mem_size, BFIN_MEMMAP_RAM); | |
474 | } else if (*arg == '$') { | |
475 | start_at = memparse(arg+1, &arg); | |
476 | add_memory_region(start_at, mem_size, BFIN_MEMMAP_RESERVED); | |
477 | } | |
478 | ||
479 | return 0; | |
480 | } | |
481 | ||
1394f032 BW |
482 | /* |
483 | * Initial parsing of the command line. Currently, we support: | |
484 | * - Controlling the linux memory size: mem=xxx[KMG] | |
485 | * - Controlling the physical memory size: max_mem=xxx[KMG][$][#] | |
486 | * $ -> reserved memory is dcacheable | |
487 | * # -> reserved memory is icacheable | |
856783b3 YL |
488 | * - "memmap=XXX[KkmM][@][$]XXX[KkmM]" defines a memory region |
489 | * @ from <start> to <start>+<mem>, type RAM | |
490 | * $ from <start> to <start>+<mem>, type RESERVED | |
1394f032 BW |
491 | */ |
492 | static __init void parse_cmdline_early(char *cmdline_p) | |
493 | { | |
494 | char c = ' ', *to = cmdline_p; | |
495 | unsigned int memsize; | |
496 | for (;;) { | |
497 | if (c == ' ') { | |
1394f032 BW |
498 | if (!memcmp(to, "mem=", 4)) { |
499 | to += 4; | |
500 | memsize = memparse(to, &to); | |
501 | if (memsize) | |
502 | _ramend = memsize; | |
503 | ||
504 | } else if (!memcmp(to, "max_mem=", 8)) { | |
505 | to += 8; | |
506 | memsize = memparse(to, &to); | |
507 | if (memsize) { | |
508 | physical_mem_end = memsize; | |
509 | if (*to != ' ') { | |
510 | if (*to == '$' | |
511 | || *(to + 1) == '$') | |
8f65873e | 512 | reserved_mem_dcache_on = 1; |
1394f032 BW |
513 | if (*to == '#' |
514 | || *(to + 1) == '#') | |
8f65873e | 515 | reserved_mem_icache_on = 1; |
1394f032 BW |
516 | } |
517 | } | |
7f1e2f98 MF |
518 | } else if (!memcmp(to, "clkin_hz=", 9)) { |
519 | to += 9; | |
520 | early_init_clkin_hz(to); | |
bd854c07 | 521 | #ifdef CONFIG_EARLY_PRINTK |
ce3afa1c RG |
522 | } else if (!memcmp(to, "earlyprintk=", 12)) { |
523 | to += 12; | |
524 | setup_early_printk(to); | |
bd854c07 | 525 | #endif |
856783b3 YL |
526 | } else if (!memcmp(to, "memmap=", 7)) { |
527 | to += 7; | |
528 | parse_memmap(to); | |
1394f032 | 529 | } |
1394f032 BW |
530 | } |
531 | c = *(to++); | |
532 | if (!c) | |
533 | break; | |
534 | } | |
535 | } | |
536 | ||
856783b3 YL |
537 | /* |
538 | * Setup memory defaults from user config. | |
539 | * The physical memory layout looks like: | |
540 | * | |
541 | * [_rambase, _ramstart]: kernel image | |
542 | * [memory_start, memory_end]: dynamic memory managed by kernel | |
543 | * [memory_end, _ramend]: reserved memory | |
3094c981 | 544 | * [memory_mtd_start(memory_end), |
856783b3 YL |
545 | * memory_mtd_start + mtd_size]: rootfs (if any) |
546 | * [_ramend - DMA_UNCACHED_REGION, | |
547 | * _ramend]: uncached DMA region | |
548 | * [_ramend, physical_mem_end]: memory not managed by kernel | |
856783b3 | 549 | */ |
8f65873e | 550 | static __init void memory_setup(void) |
1394f032 | 551 | { |
c0eab3b7 MF |
552 | #ifdef CONFIG_MTD_UCLINUX |
553 | unsigned long mtd_phys = 0; | |
554 | #endif | |
2f812c0b | 555 | unsigned long max_mem; |
c0eab3b7 | 556 | |
d86bfb16 | 557 | _rambase = CONFIG_BOOT_LOAD; |
b7627acc | 558 | _ramstart = (unsigned long)_end; |
1394f032 | 559 | |
856783b3 YL |
560 | if (DMA_UNCACHED_REGION > (_ramend - _ramstart)) { |
561 | console_init(); | |
d8804adf | 562 | panic("DMA region exceeds memory limit: %lu.", |
856783b3 | 563 | _ramend - _ramstart); |
1aafd909 | 564 | } |
2f812c0b RG |
565 | max_mem = memory_end = _ramend - DMA_UNCACHED_REGION; |
566 | ||
567 | #if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263) | |
568 | /* Due to a Hardware Anomaly we need to limit the size of usable | |
569 | * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on | |
570 | * 05000263 - Hardware loop corrupted when taking an ICPLB exception | |
571 | */ | |
572 | # if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO)) | |
573 | if (max_mem >= 56 * 1024 * 1024) | |
574 | max_mem = 56 * 1024 * 1024; | |
575 | # else | |
576 | if (max_mem >= 60 * 1024 * 1024) | |
577 | max_mem = 60 * 1024 * 1024; | |
578 | # endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */ | |
579 | #endif /* ANOMALY_05000263 */ | |
580 | ||
1394f032 | 581 | |
b97b8a99 | 582 | #ifdef CONFIG_MPU |
8f65873e | 583 | /* Round up to multiple of 4MB */ |
b97b8a99 BS |
584 | memory_start = (_ramstart + 0x3fffff) & ~0x3fffff; |
585 | #else | |
1394f032 | 586 | memory_start = PAGE_ALIGN(_ramstart); |
b97b8a99 | 587 | #endif |
1394f032 BW |
588 | |
589 | #if defined(CONFIG_MTD_UCLINUX) | |
590 | /* generic memory mapped MTD driver */ | |
591 | memory_mtd_end = memory_end; | |
592 | ||
593 | mtd_phys = _ramstart; | |
594 | mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8))); | |
595 | ||
596 | # if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS) | |
b5affb01 BL |
597 | if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC) |
598 | mtd_size = | |
599 | PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10); | |
1394f032 BW |
600 | # endif |
601 | ||
602 | # if defined(CONFIG_CRAMFS) | |
603 | if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC) | |
604 | mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4))); | |
605 | # endif | |
606 | ||
607 | # if defined(CONFIG_ROMFS_FS) | |
608 | if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0 | |
2f812c0b | 609 | && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) { |
1394f032 BW |
610 | mtd_size = |
611 | PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2])); | |
2f812c0b RG |
612 | |
613 | /* ROM_FS is XIP, so if we found it, we need to limit memory */ | |
614 | if (memory_end > max_mem) { | |
b5affb01 BL |
615 | pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", |
616 | (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20); | |
2f812c0b RG |
617 | memory_end = max_mem; |
618 | } | |
619 | } | |
1394f032 BW |
620 | # endif /* CONFIG_ROMFS_FS */ |
621 | ||
dc437b1b RG |
622 | /* Since the default MTD_UCLINUX has no magic number, we just blindly |
623 | * read 8 past the end of the kernel's image, and look at it. | |
624 | * When no image is attached, mtd_size is set to a random number | |
625 | * Do some basic sanity checks before operating on things | |
626 | */ | |
627 | if (mtd_size == 0 || memory_end <= mtd_size) { | |
628 | pr_emerg("Could not find valid ram mtd attached.\n"); | |
629 | } else { | |
630 | memory_end -= mtd_size; | |
631 | ||
632 | /* Relocate MTD image to the top of memory after the uncached memory area */ | |
633 | uclinux_ram_map.phys = memory_mtd_start = memory_end; | |
634 | uclinux_ram_map.size = mtd_size; | |
635 | pr_info("Found mtd parition at 0x%p, (len=0x%lx), moving to 0x%p\n", | |
636 | _end, mtd_size, (void *)memory_mtd_start); | |
637 | dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size); | |
1394f032 | 638 | } |
1394f032 BW |
639 | #endif /* CONFIG_MTD_UCLINUX */ |
640 | ||
2f812c0b RG |
641 | /* We need lo limit memory, since everything could have a text section |
642 | * of userspace in it, and expose anomaly 05000263. If the anomaly | |
643 | * doesn't exist, or we don't need to - then dont. | |
1394f032 | 644 | */ |
2f812c0b | 645 | if (memory_end > max_mem) { |
b5affb01 BL |
646 | pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", |
647 | (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20); | |
2f812c0b RG |
648 | memory_end = max_mem; |
649 | } | |
1394f032 | 650 | |
b97b8a99 | 651 | #ifdef CONFIG_MPU |
e18e7dd3 BS |
652 | #if defined(CONFIG_ROMFS_ON_MTD) && defined(CONFIG_MTD_ROM) |
653 | page_mask_nelts = (((_ramend + ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE - | |
654 | ASYNC_BANK0_BASE) >> PAGE_SHIFT) + 31) / 32; | |
655 | #else | |
b97b8a99 | 656 | page_mask_nelts = ((_ramend >> PAGE_SHIFT) + 31) / 32; |
e18e7dd3 | 657 | #endif |
b97b8a99 BS |
658 | page_mask_order = get_order(3 * page_mask_nelts * sizeof(long)); |
659 | #endif | |
660 | ||
1394f032 BW |
661 | init_mm.start_code = (unsigned long)_stext; |
662 | init_mm.end_code = (unsigned long)_etext; | |
663 | init_mm.end_data = (unsigned long)_edata; | |
664 | init_mm.brk = (unsigned long)0; | |
665 | ||
b5affb01 BL |
666 | printk(KERN_INFO "Board Memory: %ldMB\n", (physical_mem_end - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20); |
667 | printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", (_ramend - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20); | |
856783b3 | 668 | |
b7627acc | 669 | printk(KERN_INFO "Memory map:\n" |
ad361c98 JP |
670 | " fixedcode = 0x%p-0x%p\n" |
671 | " text = 0x%p-0x%p\n" | |
672 | " rodata = 0x%p-0x%p\n" | |
673 | " bss = 0x%p-0x%p\n" | |
674 | " data = 0x%p-0x%p\n" | |
675 | " stack = 0x%p-0x%p\n" | |
676 | " init = 0x%p-0x%p\n" | |
677 | " available = 0x%p-0x%p\n" | |
856783b3 | 678 | #ifdef CONFIG_MTD_UCLINUX |
ad361c98 | 679 | " rootfs = 0x%p-0x%p\n" |
856783b3 YL |
680 | #endif |
681 | #if DMA_UNCACHED_REGION > 0 | |
ad361c98 | 682 | " DMA Zone = 0x%p-0x%p\n" |
856783b3 | 683 | #endif |
8929ecf8 MF |
684 | , (void *)FIXED_CODE_START, (void *)FIXED_CODE_END, |
685 | _stext, _etext, | |
856783b3 | 686 | __start_rodata, __end_rodata, |
b7627acc | 687 | __bss_start, __bss_stop, |
856783b3 YL |
688 | _sdata, _edata, |
689 | (void *)&init_thread_union, | |
6feda3a6 | 690 | (void *)((int)(&init_thread_union) + THREAD_SIZE), |
b7627acc MF |
691 | __init_begin, __init_end, |
692 | (void *)_ramstart, (void *)memory_end | |
856783b3 YL |
693 | #ifdef CONFIG_MTD_UCLINUX |
694 | , (void *)memory_mtd_start, (void *)(memory_mtd_start + mtd_size) | |
695 | #endif | |
696 | #if DMA_UNCACHED_REGION > 0 | |
697 | , (void *)(_ramend - DMA_UNCACHED_REGION), (void *)(_ramend) | |
698 | #endif | |
699 | ); | |
700 | } | |
701 | ||
2e8d7965 YL |
702 | /* |
703 | * Find the lowest, highest page frame number we have available | |
704 | */ | |
705 | void __init find_min_max_pfn(void) | |
706 | { | |
707 | int i; | |
708 | ||
709 | max_pfn = 0; | |
b5affb01 | 710 | min_low_pfn = PFN_DOWN(memory_end); |
2e8d7965 YL |
711 | |
712 | for (i = 0; i < bfin_memmap.nr_map; i++) { | |
713 | unsigned long start, end; | |
714 | /* RAM? */ | |
715 | if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM) | |
716 | continue; | |
717 | start = PFN_UP(bfin_memmap.map[i].addr); | |
718 | end = PFN_DOWN(bfin_memmap.map[i].addr + | |
719 | bfin_memmap.map[i].size); | |
720 | if (start >= end) | |
721 | continue; | |
722 | if (end > max_pfn) | |
723 | max_pfn = end; | |
724 | if (start < min_low_pfn) | |
725 | min_low_pfn = start; | |
726 | } | |
727 | } | |
728 | ||
856783b3 YL |
729 | static __init void setup_bootmem_allocator(void) |
730 | { | |
731 | int bootmap_size; | |
732 | int i; | |
2e8d7965 | 733 | unsigned long start_pfn, end_pfn; |
856783b3 YL |
734 | unsigned long curr_pfn, last_pfn, size; |
735 | ||
736 | /* mark memory between memory_start and memory_end usable */ | |
737 | add_memory_region(memory_start, | |
738 | memory_end - memory_start, BFIN_MEMMAP_RAM); | |
739 | /* sanity check for overlap */ | |
740 | sanitize_memmap(bfin_memmap.map, &bfin_memmap.nr_map); | |
741 | print_memory_map("boot memmap"); | |
742 | ||
05d17dfa | 743 | /* initialize globals in linux/bootmem.h */ |
2e8d7965 YL |
744 | find_min_max_pfn(); |
745 | /* pfn of the last usable page frame */ | |
746 | if (max_pfn > memory_end >> PAGE_SHIFT) | |
747 | max_pfn = memory_end >> PAGE_SHIFT; | |
748 | /* pfn of last page frame directly mapped by kernel */ | |
749 | max_low_pfn = max_pfn; | |
750 | /* pfn of the first usable page frame after kernel image*/ | |
751 | if (min_low_pfn < memory_start >> PAGE_SHIFT) | |
752 | min_low_pfn = memory_start >> PAGE_SHIFT; | |
b5affb01 | 753 | start_pfn = CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT; |
2e8d7965 | 754 | end_pfn = memory_end >> PAGE_SHIFT; |
856783b3 YL |
755 | |
756 | /* | |
8f65873e | 757 | * give all the memory to the bootmap allocator, tell it to put the |
856783b3 YL |
758 | * boot mem_map at the start of memory. |
759 | */ | |
760 | bootmap_size = init_bootmem_node(NODE_DATA(0), | |
761 | memory_start >> PAGE_SHIFT, /* map goes here */ | |
2e8d7965 | 762 | start_pfn, end_pfn); |
856783b3 YL |
763 | |
764 | /* register the memmap regions with the bootmem allocator */ | |
765 | for (i = 0; i < bfin_memmap.nr_map; i++) { | |
766 | /* | |
767 | * Reserve usable memory | |
768 | */ | |
769 | if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM) | |
770 | continue; | |
771 | /* | |
772 | * We are rounding up the start address of usable memory: | |
773 | */ | |
774 | curr_pfn = PFN_UP(bfin_memmap.map[i].addr); | |
2e8d7965 | 775 | if (curr_pfn >= end_pfn) |
856783b3 YL |
776 | continue; |
777 | /* | |
778 | * ... and at the end of the usable range downwards: | |
779 | */ | |
780 | last_pfn = PFN_DOWN(bfin_memmap.map[i].addr + | |
781 | bfin_memmap.map[i].size); | |
782 | ||
2e8d7965 YL |
783 | if (last_pfn > end_pfn) |
784 | last_pfn = end_pfn; | |
856783b3 YL |
785 | |
786 | /* | |
787 | * .. finally, did all the rounding and playing | |
788 | * around just make the area go away? | |
789 | */ | |
790 | if (last_pfn <= curr_pfn) | |
791 | continue; | |
792 | ||
793 | size = last_pfn - curr_pfn; | |
794 | free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size)); | |
795 | } | |
796 | ||
797 | /* reserve memory before memory_start, including bootmap */ | |
b5affb01 BL |
798 | reserve_bootmem(CONFIG_PHY_RAM_BASE_ADDRESS, |
799 | memory_start + bootmap_size + PAGE_SIZE - 1 - CONFIG_PHY_RAM_BASE_ADDRESS, | |
856783b3 YL |
800 | BOOTMEM_DEFAULT); |
801 | } | |
802 | ||
a086ee22 MF |
803 | #define EBSZ_TO_MEG(ebsz) \ |
804 | ({ \ | |
805 | int meg = 0; \ | |
806 | switch (ebsz & 0xf) { \ | |
807 | case 0x1: meg = 16; break; \ | |
808 | case 0x3: meg = 32; break; \ | |
809 | case 0x5: meg = 64; break; \ | |
810 | case 0x7: meg = 128; break; \ | |
811 | case 0x9: meg = 256; break; \ | |
812 | case 0xb: meg = 512; break; \ | |
813 | } \ | |
814 | meg; \ | |
815 | }) | |
816 | static inline int __init get_mem_size(void) | |
817 | { | |
99d95bbd MH |
818 | #if defined(EBIU_SDBCTL) |
819 | # if defined(BF561_FAMILY) | |
a086ee22 MF |
820 | int ret = 0; |
821 | u32 sdbctl = bfin_read_EBIU_SDBCTL(); | |
822 | ret += EBSZ_TO_MEG(sdbctl >> 0); | |
823 | ret += EBSZ_TO_MEG(sdbctl >> 8); | |
824 | ret += EBSZ_TO_MEG(sdbctl >> 16); | |
825 | ret += EBSZ_TO_MEG(sdbctl >> 24); | |
826 | return ret; | |
99d95bbd | 827 | # else |
a086ee22 | 828 | return EBSZ_TO_MEG(bfin_read_EBIU_SDBCTL()); |
99d95bbd MH |
829 | # endif |
830 | #elif defined(EBIU_DDRCTL1) | |
1e78042c MH |
831 | u32 ddrctl = bfin_read_EBIU_DDRCTL1(); |
832 | int ret = 0; | |
833 | switch (ddrctl & 0xc0000) { | |
4dbeccdf SM |
834 | case DEVSZ_64: |
835 | ret = 64 / 8; | |
836 | break; | |
837 | case DEVSZ_128: | |
838 | ret = 128 / 8; | |
839 | break; | |
840 | case DEVSZ_256: | |
841 | ret = 256 / 8; | |
842 | break; | |
843 | case DEVSZ_512: | |
844 | ret = 512 / 8; | |
845 | break; | |
1e78042c MH |
846 | } |
847 | switch (ddrctl & 0x30000) { | |
b5affb01 BL |
848 | case DEVWD_4: |
849 | ret *= 2; | |
850 | case DEVWD_8: | |
851 | ret *= 2; | |
852 | case DEVWD_16: | |
853 | break; | |
a086ee22 | 854 | } |
b1b154e5 MF |
855 | if ((ddrctl & 0xc000) == 0x4000) |
856 | ret *= 2; | |
1e78042c | 857 | return ret; |
b5affb01 BL |
858 | #elif defined(CONFIG_BF60x) |
859 | u32 ddrctl = bfin_read_DDR0_CFG(); | |
860 | int ret; | |
861 | switch (ddrctl & 0xf00) { | |
862 | case DEVSZ_64: | |
863 | ret = 64 / 8; | |
864 | break; | |
865 | case DEVSZ_128: | |
866 | ret = 128 / 8; | |
867 | break; | |
868 | case DEVSZ_256: | |
869 | ret = 256 / 8; | |
870 | break; | |
871 | case DEVSZ_512: | |
872 | ret = 512 / 8; | |
873 | break; | |
874 | case DEVSZ_1G: | |
875 | ret = 1024 / 8; | |
876 | break; | |
877 | case DEVSZ_2G: | |
878 | ret = 2048 / 8; | |
879 | break; | |
880 | } | |
881 | return ret; | |
a086ee22 MF |
882 | #endif |
883 | BUG(); | |
884 | } | |
885 | ||
b635f191 SZ |
886 | __attribute__((weak)) |
887 | void __init native_machine_early_platform_add_devices(void) | |
888 | { | |
889 | } | |
890 | ||
1d3dbda6 SZ |
891 | #ifdef CONFIG_BF60x |
892 | static inline u_long bfin_get_clk(char *name) | |
893 | { | |
894 | struct clk *clk; | |
895 | u_long clk_rate; | |
896 | ||
897 | clk = clk_get(NULL, name); | |
898 | if (IS_ERR(clk)) | |
899 | return 0; | |
900 | ||
901 | clk_rate = clk_get_rate(clk); | |
902 | clk_put(clk); | |
903 | return clk_rate; | |
904 | } | |
905 | #endif | |
906 | ||
856783b3 YL |
907 | void __init setup_arch(char **cmdline_p) |
908 | { | |
00b5c50e | 909 | u32 mmr; |
9f8e895d | 910 | unsigned long sclk, cclk; |
856783b3 | 911 | |
b635f191 SZ |
912 | native_machine_early_platform_add_devices(); |
913 | ||
3f871fea RG |
914 | enable_shadow_console(); |
915 | ||
bd854c07 | 916 | /* Check to make sure we are running on the right processor */ |
b5affb01 | 917 | mmr = bfin_cpuid(); |
bd854c07 RG |
918 | if (unlikely(CPUID != bfin_cpuid())) |
919 | printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n", | |
920 | CPU, bfin_cpuid(), bfin_revid()); | |
921 | ||
856783b3 YL |
922 | #ifdef CONFIG_DUMMY_CONSOLE |
923 | conswitchp = &dummy_con; | |
924 | #endif | |
925 | ||
926 | #if defined(CONFIG_CMDLINE_BOOL) | |
927 | strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line)); | |
928 | command_line[sizeof(command_line) - 1] = 0; | |
929 | #endif | |
930 | ||
931 | /* Keep a copy of command line */ | |
932 | *cmdline_p = &command_line[0]; | |
933 | memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE); | |
934 | boot_command_line[COMMAND_LINE_SIZE - 1] = '\0'; | |
935 | ||
856783b3 YL |
936 | memset(&bfin_memmap, 0, sizeof(bfin_memmap)); |
937 | ||
b5affb01 BL |
938 | #ifdef CONFIG_BF60x |
939 | /* Should init clock device before parse command early */ | |
940 | clk_init(); | |
941 | #endif | |
bd854c07 RG |
942 | /* If the user does not specify things on the command line, use |
943 | * what the bootloader set things up as | |
944 | */ | |
945 | physical_mem_end = 0; | |
856783b3 YL |
946 | parse_cmdline_early(&command_line[0]); |
947 | ||
bd854c07 RG |
948 | if (_ramend == 0) |
949 | _ramend = get_mem_size() * 1024 * 1024; | |
950 | ||
856783b3 YL |
951 | if (physical_mem_end == 0) |
952 | physical_mem_end = _ramend; | |
953 | ||
954 | memory_setup(); | |
955 | ||
b5affb01 | 956 | #ifndef CONFIG_BF60x |
7e64acab MF |
957 | /* Initialize Async memory banks */ |
958 | bfin_write_EBIU_AMBCTL0(AMBCTL0VAL); | |
959 | bfin_write_EBIU_AMBCTL1(AMBCTL1VAL); | |
960 | bfin_write_EBIU_AMGCTL(AMGCTLVAL); | |
961 | #ifdef CONFIG_EBIU_MBSCTLVAL | |
962 | bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTLVAL); | |
963 | bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL); | |
964 | bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL); | |
965 | #endif | |
b5affb01 | 966 | #endif |
7a4a207e | 967 | #ifdef CONFIG_BFIN_HYSTERESIS_CONTROL |
3086fd27 MF |
968 | bfin_write_PORTF_HYSTERESIS(HYST_PORTF_0_15); |
969 | bfin_write_PORTG_HYSTERESIS(HYST_PORTG_0_15); | |
970 | bfin_write_PORTH_HYSTERESIS(HYST_PORTH_0_15); | |
971 | bfin_write_MISCPORT_HYSTERESIS((bfin_read_MISCPORT_HYSTERESIS() & | |
7a4a207e MH |
972 | ~HYST_NONEGPIO_MASK) | HYST_NONEGPIO); |
973 | #endif | |
7e64acab | 974 | |
856783b3 YL |
975 | cclk = get_cclk(); |
976 | sclk = get_sclk(); | |
977 | ||
7f3aee3c SZ |
978 | if ((ANOMALY_05000273 || ANOMALY_05000274) && (cclk >> 1) < sclk) |
979 | panic("ANOMALY 05000273 or 05000274: CCLK must be >= 2*SCLK"); | |
856783b3 YL |
980 | |
981 | #ifdef BF561_FAMILY | |
982 | if (ANOMALY_05000266) { | |
983 | bfin_read_IMDMA_D0_IRQ_STATUS(); | |
984 | bfin_read_IMDMA_D1_IRQ_STATUS(); | |
985 | } | |
986 | #endif | |
856783b3 | 987 | |
00b5c50e MF |
988 | mmr = bfin_read_TBUFCTL(); |
989 | printk(KERN_INFO "Hardware Trace %s and %sabled\n", | |
990 | (mmr & 0x1) ? "active" : "off", | |
991 | (mmr & 0x2) ? "en" : "dis"); | |
b5affb01 | 992 | #ifndef CONFIG_BF60x |
00b5c50e MF |
993 | mmr = bfin_read_SYSCR(); |
994 | printk(KERN_INFO "Boot Mode: %i\n", mmr & 0xF); | |
76e8fe4d | 995 | |
ed1fb604 MF |
996 | /* Newer parts mirror SWRST bits in SYSCR */ |
997 | #if defined(CONFIG_BF53x) || defined(CONFIG_BF561) || \ | |
998 | defined(CONFIG_BF538) || defined(CONFIG_BF539) | |
7728ec33 | 999 | _bfin_swrst = bfin_read_SWRST(); |
ed1fb604 | 1000 | #else |
0de4adfb | 1001 | /* Clear boot mode field */ |
00b5c50e | 1002 | _bfin_swrst = mmr & ~0xf; |
ed1fb604 | 1003 | #endif |
7728ec33 | 1004 | |
0c7a6b21 RG |
1005 | #ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT |
1006 | bfin_write_SWRST(_bfin_swrst & ~DOUBLE_FAULT); | |
1007 | #endif | |
1008 | #ifdef CONFIG_DEBUG_DOUBLEFAULT_RESET | |
1009 | bfin_write_SWRST(_bfin_swrst | DOUBLE_FAULT); | |
1010 | #endif | |
2d200980 | 1011 | |
8f65873e GY |
1012 | #ifdef CONFIG_SMP |
1013 | if (_bfin_swrst & SWRST_DBL_FAULT_A) { | |
1014 | #else | |
0c7a6b21 | 1015 | if (_bfin_swrst & RESET_DOUBLE) { |
8f65873e | 1016 | #endif |
0c7a6b21 RG |
1017 | printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n"); |
1018 | #ifdef CONFIG_DEBUG_DOUBLEFAULT | |
1019 | /* We assume the crashing kernel, and the current symbol table match */ | |
fb1d9be5 MF |
1020 | printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n", |
1021 | initial_pda.seqstat_doublefault & SEQSTAT_EXCAUSE, | |
1022 | initial_pda.retx_doublefault); | |
1023 | printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", | |
1024 | initial_pda.dcplb_doublefault_addr); | |
1025 | printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", | |
1026 | initial_pda.icplb_doublefault_addr); | |
0c7a6b21 RG |
1027 | #endif |
1028 | printk(KERN_NOTICE " The instruction at %pF caused a double exception\n", | |
fb1d9be5 | 1029 | initial_pda.retx); |
0c7a6b21 | 1030 | } else if (_bfin_swrst & RESET_WDOG) |
7728ec33 RG |
1031 | printk(KERN_INFO "Recovering from Watchdog event\n"); |
1032 | else if (_bfin_swrst & RESET_SOFTWARE) | |
1033 | printk(KERN_NOTICE "Reset caused by Software reset\n"); | |
b5affb01 | 1034 | #endif |
be1577e3 | 1035 | printk(KERN_INFO "Blackfin support (C) 2004-2010 Analog Devices, Inc.\n"); |
de3025f4 | 1036 | if (bfin_compiled_revid() == 0xffff) |
7a1a8cc1 | 1037 | printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid()); |
de3025f4 JZ |
1038 | else if (bfin_compiled_revid() == -1) |
1039 | printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU); | |
1040 | else | |
1041 | printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid()); | |
e482cad2 | 1042 | |
bd854c07 | 1043 | if (likely(CPUID == bfin_cpuid())) { |
e482cad2 RG |
1044 | if (bfin_revid() != bfin_compiled_revid()) { |
1045 | if (bfin_compiled_revid() == -1) | |
1046 | printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n", | |
1047 | bfin_revid()); | |
7419a327 | 1048 | else if (bfin_compiled_revid() != 0xffff) { |
e482cad2 RG |
1049 | printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n", |
1050 | bfin_compiled_revid(), bfin_revid()); | |
7419a327 | 1051 | if (bfin_compiled_revid() > bfin_revid()) |
d8804adf | 1052 | panic("Error: you are missing anomaly workarounds for this rev"); |
7419a327 | 1053 | } |
e482cad2 | 1054 | } |
da986b9f | 1055 | if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX) |
e482cad2 RG |
1056 | printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n", |
1057 | CPU, bfin_revid()); | |
de3025f4 | 1058 | } |
0c0497c2 | 1059 | |
1394f032 BW |
1060 | printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n"); |
1061 | ||
7c141c1c BL |
1062 | #ifdef CONFIG_BF60x |
1063 | printk(KERN_INFO "Processor Speed: %lu MHz core clock, %lu MHz SCLk, %lu MHz SCLK0, %lu MHz SCLK1 and %lu MHz DCLK\n", | |
1d3dbda6 | 1064 | cclk / 1000000, bfin_get_clk("SYSCLK") / 1000000, get_sclk0() / 1000000, get_sclk1() / 1000000, get_dclk() / 1000000); |
7c141c1c | 1065 | #else |
b5c0e2e8 | 1066 | printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n", |
8f65873e | 1067 | cclk / 1000000, sclk / 1000000); |
7c141c1c | 1068 | #endif |
1394f032 | 1069 | |
856783b3 | 1070 | setup_bootmem_allocator(); |
1394f032 | 1071 | |
1394f032 BW |
1072 | paging_init(); |
1073 | ||
7adfb58f BS |
1074 | /* Copy atomic sequences to their fixed location, and sanity check that |
1075 | these locations are the ones that we advertise to userspace. */ | |
1076 | memcpy((void *)FIXED_CODE_START, &fixed_code_start, | |
1077 | FIXED_CODE_END - FIXED_CODE_START); | |
1078 | BUG_ON((char *)&sigreturn_stub - (char *)&fixed_code_start | |
1079 | != SIGRETURN_STUB - FIXED_CODE_START); | |
1080 | BUG_ON((char *)&atomic_xchg32 - (char *)&fixed_code_start | |
1081 | != ATOMIC_XCHG32 - FIXED_CODE_START); | |
1082 | BUG_ON((char *)&atomic_cas32 - (char *)&fixed_code_start | |
1083 | != ATOMIC_CAS32 - FIXED_CODE_START); | |
1084 | BUG_ON((char *)&atomic_add32 - (char *)&fixed_code_start | |
1085 | != ATOMIC_ADD32 - FIXED_CODE_START); | |
1086 | BUG_ON((char *)&atomic_sub32 - (char *)&fixed_code_start | |
1087 | != ATOMIC_SUB32 - FIXED_CODE_START); | |
1088 | BUG_ON((char *)&atomic_ior32 - (char *)&fixed_code_start | |
1089 | != ATOMIC_IOR32 - FIXED_CODE_START); | |
1090 | BUG_ON((char *)&atomic_and32 - (char *)&fixed_code_start | |
1091 | != ATOMIC_AND32 - FIXED_CODE_START); | |
1092 | BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start | |
1093 | != ATOMIC_XOR32 - FIXED_CODE_START); | |
9f336a53 RG |
1094 | BUG_ON((char *)&safe_user_instruction - (char *)&fixed_code_start |
1095 | != SAFE_USER_INSTRUCTION - FIXED_CODE_START); | |
29440a2b | 1096 | |
8f65873e GY |
1097 | #ifdef CONFIG_SMP |
1098 | platform_init_cpus(); | |
1099 | #endif | |
8be80ed3 | 1100 | init_exception_vectors(); |
8f65873e | 1101 | bfin_cache_init(); /* Initialize caches for the boot CPU */ |
1394f032 BW |
1102 | } |
1103 | ||
1394f032 BW |
1104 | static int __init topology_init(void) |
1105 | { | |
8f65873e | 1106 | unsigned int cpu; |
6cda2e90 MH |
1107 | |
1108 | for_each_possible_cpu(cpu) { | |
8f65873e | 1109 | register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu); |
6cda2e90 MH |
1110 | } |
1111 | ||
1394f032 | 1112 | return 0; |
1394f032 BW |
1113 | } |
1114 | ||
1115 | subsys_initcall(topology_init); | |
1116 | ||
7f1e2f98 MF |
1117 | /* Get the input clock frequency */ |
1118 | static u_long cached_clkin_hz = CONFIG_CLKIN_HZ; | |
b5affb01 | 1119 | #ifndef CONFIG_BF60x |
7f1e2f98 MF |
1120 | static u_long get_clkin_hz(void) |
1121 | { | |
1122 | return cached_clkin_hz; | |
1123 | } | |
b5affb01 | 1124 | #endif |
7f1e2f98 MF |
1125 | static int __init early_init_clkin_hz(char *buf) |
1126 | { | |
1127 | cached_clkin_hz = simple_strtoul(buf, NULL, 0); | |
508808cd MF |
1128 | #ifdef BFIN_KERNEL_CLOCK |
1129 | if (cached_clkin_hz != CONFIG_CLKIN_HZ) | |
1130 | panic("cannot change clkin_hz when reprogramming clocks"); | |
1131 | #endif | |
7f1e2f98 MF |
1132 | return 1; |
1133 | } | |
1134 | early_param("clkin_hz=", early_init_clkin_hz); | |
1135 | ||
b5affb01 | 1136 | #ifndef CONFIG_BF60x |
3a2521fa | 1137 | /* Get the voltage input multiplier */ |
52a07812 | 1138 | static u_long get_vco(void) |
1394f032 | 1139 | { |
e32f55d9 MF |
1140 | static u_long cached_vco; |
1141 | u_long msel, pll_ctl; | |
1394f032 | 1142 | |
e32f55d9 MF |
1143 | /* The assumption here is that VCO never changes at runtime. |
1144 | * If, someday, we support that, then we'll have to change this. | |
1145 | */ | |
1146 | if (cached_vco) | |
3a2521fa | 1147 | return cached_vco; |
3a2521fa | 1148 | |
e32f55d9 | 1149 | pll_ctl = bfin_read_PLL_CTL(); |
3a2521fa | 1150 | msel = (pll_ctl >> 9) & 0x3F; |
1394f032 BW |
1151 | if (0 == msel) |
1152 | msel = 64; | |
1153 | ||
7f1e2f98 | 1154 | cached_vco = get_clkin_hz(); |
3a2521fa MF |
1155 | cached_vco >>= (1 & pll_ctl); /* DF bit */ |
1156 | cached_vco *= msel; | |
1157 | return cached_vco; | |
1394f032 | 1158 | } |
b5affb01 | 1159 | #endif |
1394f032 | 1160 | |
2f6cf7bf | 1161 | /* Get the Core clock */ |
1394f032 BW |
1162 | u_long get_cclk(void) |
1163 | { | |
b5affb01 | 1164 | #ifdef CONFIG_BF60x |
1d3dbda6 | 1165 | return bfin_get_clk("CCLK"); |
b5affb01 | 1166 | #else |
e32f55d9 | 1167 | static u_long cached_cclk_pll_div, cached_cclk; |
1394f032 | 1168 | u_long csel, ssel; |
3a2521fa | 1169 | |
1394f032 | 1170 | if (bfin_read_PLL_STAT() & 0x1) |
7f1e2f98 | 1171 | return get_clkin_hz(); |
1394f032 BW |
1172 | |
1173 | ssel = bfin_read_PLL_DIV(); | |
3a2521fa MF |
1174 | if (ssel == cached_cclk_pll_div) |
1175 | return cached_cclk; | |
1176 | else | |
1177 | cached_cclk_pll_div = ssel; | |
1178 | ||
1394f032 BW |
1179 | csel = ((ssel >> 4) & 0x03); |
1180 | ssel &= 0xf; | |
1181 | if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */ | |
3a2521fa MF |
1182 | cached_cclk = get_vco() / ssel; |
1183 | else | |
1184 | cached_cclk = get_vco() >> csel; | |
1185 | return cached_cclk; | |
b5affb01 | 1186 | #endif |
1394f032 | 1187 | } |
1394f032 BW |
1188 | EXPORT_SYMBOL(get_cclk); |
1189 | ||
b5affb01 BL |
1190 | #ifdef CONFIG_BF60x |
1191 | /* Get the bf60x clock of SCLK0 domain */ | |
1192 | u_long get_sclk0(void) | |
1193 | { | |
1d3dbda6 | 1194 | return bfin_get_clk("SCLK0"); |
b5affb01 BL |
1195 | } |
1196 | EXPORT_SYMBOL(get_sclk0); | |
1197 | ||
1198 | /* Get the bf60x clock of SCLK1 domain */ | |
1199 | u_long get_sclk1(void) | |
1200 | { | |
1d3dbda6 | 1201 | return bfin_get_clk("SCLK1"); |
b5affb01 BL |
1202 | } |
1203 | EXPORT_SYMBOL(get_sclk1); | |
1204 | ||
1205 | /* Get the bf60x DRAM clock */ | |
1206 | u_long get_dclk(void) | |
1207 | { | |
1d3dbda6 | 1208 | return bfin_get_clk("DCLK"); |
b5affb01 BL |
1209 | } |
1210 | EXPORT_SYMBOL(get_dclk); | |
1211 | #endif | |
1212 | ||
1d3dbda6 | 1213 | /* Get the default system clock */ |
1394f032 BW |
1214 | u_long get_sclk(void) |
1215 | { | |
b5affb01 BL |
1216 | #ifdef CONFIG_BF60x |
1217 | return get_sclk0(); | |
1218 | #else | |
e32f55d9 | 1219 | static u_long cached_sclk; |
1394f032 BW |
1220 | u_long ssel; |
1221 | ||
e32f55d9 MF |
1222 | /* The assumption here is that SCLK never changes at runtime. |
1223 | * If, someday, we support that, then we'll have to change this. | |
1224 | */ | |
1225 | if (cached_sclk) | |
1226 | return cached_sclk; | |
1227 | ||
1394f032 | 1228 | if (bfin_read_PLL_STAT() & 0x1) |
7f1e2f98 | 1229 | return get_clkin_hz(); |
1394f032 | 1230 | |
e32f55d9 | 1231 | ssel = bfin_read_PLL_DIV() & 0xf; |
1394f032 BW |
1232 | if (0 == ssel) { |
1233 | printk(KERN_WARNING "Invalid System Clock\n"); | |
1234 | ssel = 1; | |
1235 | } | |
1236 | ||
3a2521fa MF |
1237 | cached_sclk = get_vco() / ssel; |
1238 | return cached_sclk; | |
b5affb01 | 1239 | #endif |
1394f032 | 1240 | } |
1394f032 BW |
1241 | EXPORT_SYMBOL(get_sclk); |
1242 | ||
2f6cf7bf MF |
1243 | unsigned long sclk_to_usecs(unsigned long sclk) |
1244 | { | |
1754a5d9 MF |
1245 | u64 tmp = USEC_PER_SEC * (u64)sclk; |
1246 | do_div(tmp, get_sclk()); | |
1247 | return tmp; | |
2f6cf7bf MF |
1248 | } |
1249 | EXPORT_SYMBOL(sclk_to_usecs); | |
1250 | ||
1251 | unsigned long usecs_to_sclk(unsigned long usecs) | |
1252 | { | |
1754a5d9 MF |
1253 | u64 tmp = get_sclk() * (u64)usecs; |
1254 | do_div(tmp, USEC_PER_SEC); | |
1255 | return tmp; | |
2f6cf7bf MF |
1256 | } |
1257 | EXPORT_SYMBOL(usecs_to_sclk); | |
1258 | ||
1394f032 BW |
1259 | /* |
1260 | * Get CPU information for use by the procfs. | |
1261 | */ | |
1262 | static int show_cpuinfo(struct seq_file *m, void *v) | |
1263 | { | |
066954a3 | 1264 | char *cpu, *mmu, *fpu, *vendor, *cache; |
1394f032 | 1265 | uint32_t revid; |
275123e8 | 1266 | int cpu_num = *(unsigned int *)v; |
a5f0717e | 1267 | u_long sclk, cclk; |
9de3a0b6 | 1268 | u_int icache_size = BFIN_ICACHESIZE / 1024, dcache_size = 0, dsup_banks = 0; |
275123e8 | 1269 | struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu_num); |
1394f032 BW |
1270 | |
1271 | cpu = CPU; | |
1272 | mmu = "none"; | |
1273 | fpu = "none"; | |
1274 | revid = bfin_revid(); | |
1394f032 | 1275 | |
1394f032 | 1276 | sclk = get_sclk(); |
a5f0717e | 1277 | cclk = get_cclk(); |
1394f032 | 1278 | |
73b0c0b0 | 1279 | switch (bfin_read_CHIPID() & CHIPID_MANUFACTURE) { |
066954a3 MF |
1280 | case 0xca: |
1281 | vendor = "Analog Devices"; | |
73b0c0b0 RG |
1282 | break; |
1283 | default: | |
066954a3 MF |
1284 | vendor = "unknown"; |
1285 | break; | |
73b0c0b0 | 1286 | } |
1394f032 | 1287 | |
275123e8 | 1288 | seq_printf(m, "processor\t: %d\n" "vendor_id\t: %s\n", cpu_num, vendor); |
e482cad2 RG |
1289 | |
1290 | if (CPUID == bfin_cpuid()) | |
1291 | seq_printf(m, "cpu family\t: 0x%04x\n", CPUID); | |
1292 | else | |
1293 | seq_printf(m, "cpu family\t: Compiled for:0x%04x, running on:0x%04x\n", | |
1294 | CPUID, bfin_cpuid()); | |
1295 | ||
1296 | seq_printf(m, "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n" | |
2466ac65 | 1297 | "stepping\t: %d ", |
a5f0717e | 1298 | cpu, cclk/1000000, sclk/1000000, |
253bcf4f RG |
1299 | #ifdef CONFIG_MPU |
1300 | "mpu on", | |
1301 | #else | |
1302 | "mpu off", | |
1303 | #endif | |
73b0c0b0 RG |
1304 | revid); |
1305 | ||
2466ac65 RG |
1306 | if (bfin_revid() != bfin_compiled_revid()) { |
1307 | if (bfin_compiled_revid() == -1) | |
1308 | seq_printf(m, "(Compiled for Rev none)"); | |
1309 | else if (bfin_compiled_revid() == 0xffff) | |
1310 | seq_printf(m, "(Compiled for Rev any)"); | |
1311 | else | |
1312 | seq_printf(m, "(Compiled for Rev %d)", bfin_compiled_revid()); | |
1313 | } | |
1314 | ||
1315 | seq_printf(m, "\ncpu MHz\t\t: %lu.%03lu/%lu.%03lu\n", | |
a5f0717e | 1316 | cclk/1000000, cclk%1000000, |
73b0c0b0 RG |
1317 | sclk/1000000, sclk%1000000); |
1318 | seq_printf(m, "bogomips\t: %lu.%02lu\n" | |
1319 | "Calibration\t: %lu loops\n", | |
c70c754f MH |
1320 | (loops_per_jiffy * HZ) / 500000, |
1321 | ((loops_per_jiffy * HZ) / 5000) % 100, | |
1322 | (loops_per_jiffy * HZ)); | |
73b0c0b0 RG |
1323 | |
1324 | /* Check Cache configutation */ | |
8f65873e | 1325 | switch (cpudata->dmemctl & (1 << DMC0_P | 1 << DMC1_P)) { |
1f83b8f1 | 1326 | case ACACHE_BSRAM: |
066954a3 | 1327 | cache = "dbank-A/B\t: cache/sram"; |
1f83b8f1 MF |
1328 | dcache_size = 16; |
1329 | dsup_banks = 1; | |
1330 | break; | |
1331 | case ACACHE_BCACHE: | |
066954a3 | 1332 | cache = "dbank-A/B\t: cache/cache"; |
1f83b8f1 MF |
1333 | dcache_size = 32; |
1334 | dsup_banks = 2; | |
1335 | break; | |
1336 | case ASRAM_BSRAM: | |
066954a3 | 1337 | cache = "dbank-A/B\t: sram/sram"; |
1f83b8f1 MF |
1338 | dcache_size = 0; |
1339 | dsup_banks = 0; | |
1340 | break; | |
1341 | default: | |
066954a3 | 1342 | cache = "unknown"; |
73b0c0b0 RG |
1343 | dcache_size = 0; |
1344 | dsup_banks = 0; | |
1394f032 BW |
1345 | break; |
1346 | } | |
1347 | ||
73b0c0b0 | 1348 | /* Is it turned on? */ |
8f65873e | 1349 | if ((cpudata->dmemctl & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE)) |
73b0c0b0 | 1350 | dcache_size = 0; |
1394f032 | 1351 | |
8f65873e | 1352 | if ((cpudata->imemctl & (IMC | ENICPLB)) != (IMC | ENICPLB)) |
9de3a0b6 RG |
1353 | icache_size = 0; |
1354 | ||
73b0c0b0 | 1355 | seq_printf(m, "cache size\t: %d KB(L1 icache) " |
41ba653f JZ |
1356 | "%d KB(L1 dcache) %d KB(L2 cache)\n", |
1357 | icache_size, dcache_size, 0); | |
73b0c0b0 | 1358 | seq_printf(m, "%s\n", cache); |
41ba653f JZ |
1359 | seq_printf(m, "external memory\t: " |
1360 | #if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) | |
1361 | "cacheable" | |
1362 | #else | |
1363 | "uncacheable" | |
1364 | #endif | |
1365 | " in instruction cache\n"); | |
1366 | seq_printf(m, "external memory\t: " | |
1367 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) | |
1368 | "cacheable (write-back)" | |
1369 | #elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH) | |
1370 | "cacheable (write-through)" | |
1371 | #else | |
1372 | "uncacheable" | |
1373 | #endif | |
1374 | " in data cache\n"); | |
73b0c0b0 | 1375 | |
9de3a0b6 RG |
1376 | if (icache_size) |
1377 | seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n", | |
1378 | BFIN_ISUBBANKS, BFIN_IWAYS, BFIN_ILINES); | |
1379 | else | |
1380 | seq_printf(m, "icache setup\t: off\n"); | |
1381 | ||
1394f032 | 1382 | seq_printf(m, |
73b0c0b0 | 1383 | "dcache setup\t: %d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n", |
3bebca2d RG |
1384 | dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS, |
1385 | BFIN_DLINES); | |
8f65873e | 1386 | #ifdef __ARCH_SYNC_CORE_DCACHE |
8d011f70 | 1387 | seq_printf(m, "dcache flushes\t: %lu\n", dcache_invld_count[cpu_num]); |
8f65873e | 1388 | #endif |
47e9dedb | 1389 | #ifdef __ARCH_SYNC_CORE_ICACHE |
8d011f70 | 1390 | seq_printf(m, "icache flushes\t: %lu\n", icache_invld_count[cpu_num]); |
47e9dedb | 1391 | #endif |
275123e8 | 1392 | |
8d011f70 MF |
1393 | seq_printf(m, "\n"); |
1394 | ||
275123e8 | 1395 | if (cpu_num != num_possible_cpus() - 1) |
8f65873e GY |
1396 | return 0; |
1397 | ||
41ba653f | 1398 | if (L2_LENGTH) { |
275123e8 | 1399 | seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400); |
41ba653f JZ |
1400 | seq_printf(m, "L2 SRAM\t\t: " |
1401 | #if defined(CONFIG_BFIN_L2_ICACHEABLE) | |
1402 | "cacheable" | |
1403 | #else | |
1404 | "uncacheable" | |
1405 | #endif | |
1406 | " in instruction cache\n"); | |
1407 | seq_printf(m, "L2 SRAM\t\t: " | |
1408 | #if defined(CONFIG_BFIN_L2_WRITEBACK) | |
1409 | "cacheable (write-back)" | |
1410 | #elif defined(CONFIG_BFIN_L2_WRITETHROUGH) | |
1411 | "cacheable (write-through)" | |
1412 | #else | |
1413 | "uncacheable" | |
1414 | #endif | |
1415 | " in data cache\n"); | |
1416 | } | |
066954a3 | 1417 | seq_printf(m, "board name\t: %s\n", bfin_board_name); |
8d011f70 MF |
1418 | seq_printf(m, "board memory\t: %ld kB (0x%08lx -> 0x%08lx)\n", |
1419 | physical_mem_end >> 10, 0ul, physical_mem_end); | |
1420 | seq_printf(m, "kernel memory\t: %d kB (0x%08lx -> 0x%08lx)\n", | |
d86bfb16 | 1421 | ((int)memory_end - (int)_rambase) >> 10, |
8d011f70 | 1422 | _rambase, memory_end); |
73b0c0b0 | 1423 | |
1394f032 BW |
1424 | return 0; |
1425 | } | |
1426 | ||
1427 | static void *c_start(struct seq_file *m, loff_t *pos) | |
1428 | { | |
55f2feae | 1429 | if (*pos == 0) |
fecedc80 | 1430 | *pos = cpumask_first(cpu_online_mask); |
55f2feae GY |
1431 | if (*pos >= num_online_cpus()) |
1432 | return NULL; | |
1433 | ||
1434 | return pos; | |
1394f032 BW |
1435 | } |
1436 | ||
1437 | static void *c_next(struct seq_file *m, void *v, loff_t *pos) | |
1438 | { | |
fecedc80 | 1439 | *pos = cpumask_next(*pos, cpu_online_mask); |
55f2feae | 1440 | |
1394f032 BW |
1441 | return c_start(m, pos); |
1442 | } | |
1443 | ||
1444 | static void c_stop(struct seq_file *m, void *v) | |
1445 | { | |
1446 | } | |
1447 | ||
03a44825 | 1448 | const struct seq_operations cpuinfo_op = { |
1394f032 BW |
1449 | .start = c_start, |
1450 | .next = c_next, | |
1451 | .stop = c_stop, | |
1452 | .show = show_cpuinfo, | |
1453 | }; | |
1454 | ||
5e10b4a6 | 1455 | void __init cmdline_init(const char *r0) |
1394f032 | 1456 | { |
837ec2d5 | 1457 | early_shadow_stamp(); |
1394f032 | 1458 | if (r0) |
52a07812 | 1459 | strncpy(command_line, r0, COMMAND_LINE_SIZE); |
1394f032 | 1460 | } |