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sched/headers: Prepare for new header dependencies before moving code to <linux/sched...
[mirror_ubuntu-bionic-kernel.git] / arch / blackfin / kernel / trace.c
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2a12c463
RG		 1/* provide some functions which dump the trace buffer, in a nice way for people
2 * to read it, and understand what is going on
3 *
4 * Copyright 2004-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later
7 */
8
9#include <linux/kernel.h>
10#include <linux/hardirq.h>
11#include <linux/thread_info.h>
12#include <linux/mm.h>
2214f707 13#include <linux/oom.h>
3f07c014 14#include <linux/sched/signal.h>
b17b0153 15#include <linux/sched/debug.h>
29930025 16#include <linux/sched/task.h>
2a12c463
RG		 17#include <linux/uaccess.h>
18#include <linux/module.h>
19#include <linux/kallsyms.h>
20#include <linux/err.h>
21#include <linux/fs.h>
df9ee292 22#include <linux/irq.h>
2a12c463
RG		 23#include <asm/dma.h>
24#include <asm/trace.h>
25#include <asm/fixed_code.h>
26#include <asm/traps.h>
d60805ad 27#include <asm/irq_handler.h>
3bed8d67 28#include <asm/pda.h>
2a12c463 29
2a12c463
RG		 30void decode_address(char *buf, unsigned long address)
31{
2a12c463
RG		 32 struct task_struct *p;
33 struct mm_struct *mm;
af1be5a5 34 unsigned long offset;
2a12c463
RG		 35 struct rb_node *n;
36
37#ifdef CONFIG_KALLSYMS
38 unsigned long symsize;
39 const char *symname;
40 char *modname;
41 char *delim = ":";
42 char namebuf[128];
43#endif
44
45 buf += sprintf(buf, "<0x%08lx> ", address);
46
47#ifdef CONFIG_KALLSYMS
48 /* look up the address and see if we are in kernel space */
49 symname = kallsyms_lookup(address, &symsize, &offset, &modname, namebuf);
50
51 if (symname) {
52 /* yeah! kernel space! */
53 if (!modname)
54 modname = delim = "";
55 sprintf(buf, "{ %s%s%s%s + 0x%lx }",
56 delim, modname, delim, symname,
57 (unsigned long)offset);
58 return;
59 }
60#endif
61
62 if (address >= FIXED_CODE_START && address < FIXED_CODE_END) {
63 /* Problem in fixed code section? */
64 strcat(buf, "/* Maybe fixed code section */");
65 return;
66
67 } else if (address < CONFIG_BOOT_LOAD) {
68 /* Problem somewhere before the kernel start address */
69 strcat(buf, "/* Maybe null pointer? */");
70 return;
71
72 } else if (address >= COREMMR_BASE) {
73 strcat(buf, "/* core mmrs */");
74 return;
75
76 } else if (address >= SYSMMR_BASE) {
77 strcat(buf, "/* system mmrs */");
78 return;
79
80 } else if (address >= L1_ROM_START && address < L1_ROM_START + L1_ROM_LENGTH) {
81 strcat(buf, "/* on-chip L1 ROM */");
82 return;
9a95e2f1
RG		 83
84 } else if (address >= L1_SCRATCH_START && address < L1_SCRATCH_START + L1_SCRATCH_LENGTH) {
85 strcat(buf, "/* on-chip scratchpad */");
86 return;
87
88 } else if (address >= physical_mem_end && address < ASYNC_BANK0_BASE) {
89 strcat(buf, "/* unconnected memory */");
90 return;
91
92 } else if (address >= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE && address < BOOT_ROM_START) {
93 strcat(buf, "/* reserved memory */");
94 return;
95
96 } else if (address >= L1_DATA_A_START && address < L1_DATA_A_START + L1_DATA_A_LENGTH) {
97 strcat(buf, "/* on-chip Data Bank A */");
98 return;
99
100 } else if (address >= L1_DATA_B_START && address < L1_DATA_B_START + L1_DATA_B_LENGTH) {
101 strcat(buf, "/* on-chip Data Bank B */");
102 return;
2a12c463
RG		 103 }
104
105 /*
106 * Don't walk any of the vmas if we are oopsing, it has been known
107 * to cause problems - corrupt vmas (kernel crashes) cause double faults
108 */
109 if (oops_in_progress) {
110 strcat(buf, "/* kernel dynamic memory (maybe user-space) */");
111 return;
112 }
113
114 /* looks like we're off in user-land, so let's walk all the
115 * mappings of all our processes and see if we can't be a whee
116 * bit more specific
117 */
af1be5a5 118 read_lock(&tasklist_lock);
2a12c463 119 for_each_process(p) {
2214f707 120 struct task_struct *t;
2a12c463 121
2214f707
AV		 122 t = find_lock_task_mm(p);
123 if (!t)
2a12c463 124 continue;
2214f707
AV		 125
126 mm = t->mm;
127 if (!down_read_trylock(&mm->mmap_sem))
128 goto __continue;
2a12c463
RG		 129
130 for (n = rb_first(&mm->mm_rb); n; n = rb_next(n)) {
131 struct vm_area_struct *vma;
132
133 vma = rb_entry(n, struct vm_area_struct, vm_rb);
134
135 if (address >= vma->vm_start && address < vma->vm_end) {
136 char _tmpbuf[256];
2214f707 137 char *name = t->comm;
2a12c463
RG		 138 struct file *file = vma->vm_file;
139
140 if (file) {
9bf39ab2 141 char *d_name = file_path(file, _tmpbuf,
2a12c463
RG		 142 sizeof(_tmpbuf));
143 if (!IS_ERR(d_name))
144 name = d_name;
145 }
146
147 /* FLAT does not have its text aligned to the start of
148 * the map while FDPIC ELF does ...
149 */
150
151 /* before we can check flat/fdpic, we need to
152 * make sure current is valid
153 */
154 if ((unsigned long)current >= FIXED_CODE_START &&
155 !((unsigned long)current & 0x3)) {
156 if (current->mm &&
157 (address > current->mm->start_code) &&
158 (address < current->mm->end_code))
159 offset = address - current->mm->start_code;
160 else
161 offset = (address - vma->vm_start) +
162 (vma->vm_pgoff << PAGE_SHIFT);
163
164 sprintf(buf, "[ %s + 0x%lx ]", name, offset);
165 } else
166 sprintf(buf, "[ %s vma:0x%lx-0x%lx]",
167 name, vma->vm_start, vma->vm_end);
168
169 up_read(&mm->mmap_sem);
2214f707 170 task_unlock(t);
2a12c463
RG		 171
172 if (buf[0] == '\0')
173 sprintf(buf, "[ %s ] dynamic memory", name);
174
175 goto done;
176 }
177 }
178
179 up_read(&mm->mmap_sem);
2214f707
AV		 180__continue:
181 task_unlock(t);
2a12c463
RG		 182 }
183
184 /*
185 * we were unable to find this address anywhere,
186 * or some MMs were skipped because they were in use.
187 */
188 sprintf(buf, "/* kernel dynamic memory */");
189
190done:
af1be5a5 191 read_unlock(&tasklist_lock);
2a12c463
RG		 192}
193
194#define EXPAND_LEN ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 256 - 1)
195
196/*
197 * Similar to get_user, do some address checking, then dereference
198 * Return true on success, false on bad address
199 */
9a95e2f1 200bool get_mem16(unsigned short *val, unsigned short *address)
2a12c463
RG		 201{
202 unsigned long addr = (unsigned long)address;
203
204 /* Check for odd addresses */
205 if (addr & 0x1)
206 return false;
207
2a12c463
RG		 208 switch (bfin_mem_access_type(addr, 2)) {
209 case BFIN_MEM_ACCESS_CORE:
210 case BFIN_MEM_ACCESS_CORE_ONLY:
211 *val = *address;
212 return true;
213 case BFIN_MEM_ACCESS_DMA:
214 dma_memcpy(val, address, 2);
215 return true;
216 case BFIN_MEM_ACCESS_ITEST:
217 isram_memcpy(val, address, 2);
218 return true;
219 default: /* invalid access */
220 return false;
221 }
222}
223
9a95e2f1
RG		 224bool get_instruction(unsigned int *val, unsigned short *address)
225{
226 unsigned long addr = (unsigned long)address;
227 unsigned short opcode0, opcode1;
228
229 /* Check for odd addresses */
230 if (addr & 0x1)
231 return false;
232
233 /* MMR region will never have instructions */
234 if (addr >= SYSMMR_BASE)
235 return false;
236
237 /* Scratchpad will never have instructions */
238 if (addr >= L1_SCRATCH_START && addr < L1_SCRATCH_START + L1_SCRATCH_LENGTH)
239 return false;
240
241 /* Data banks will never have instructions */
242 if (addr >= BOOT_ROM_START + BOOT_ROM_LENGTH && addr < L1_CODE_START)
243 return false;
244
245 if (!get_mem16(&opcode0, address))
246 return false;
247
248 /* was this a 32-bit instruction? If so, get the next 16 bits */
249 if ((opcode0 & 0xc000) == 0xc000) {
250 if (!get_mem16(&opcode1, address + 1))
251 return false;
252 *val = (opcode0 << 16) + opcode1;
253 } else
254 *val = opcode0;
255
256 return true;
257}
258
259#if defined(CONFIG_DEBUG_BFIN_HWTRACE_ON)
2a12c463
RG		 260/*
261 * decode the instruction if we are printing out the trace, as it
262 * makes things easier to follow, without running it through objdump
9a95e2f1
RG		 263 * Decode the change of flow, and the common load/store instructions
264 * which are the main cause for faults, and discontinuities in the trace
265 * buffer.
2a12c463 266 */
9a95e2f1
RG		 267
268#define ProgCtrl_opcode 0x0000
269#define ProgCtrl_poprnd_bits 0
270#define ProgCtrl_poprnd_mask 0xf
271#define ProgCtrl_prgfunc_bits 4
272#define ProgCtrl_prgfunc_mask 0xf
273#define ProgCtrl_code_bits 8
274#define ProgCtrl_code_mask 0xff
275
276static void decode_ProgCtrl_0(unsigned int opcode)
277{
278 int poprnd = ((opcode >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
279 int prgfunc = ((opcode >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
280
281 if (prgfunc == 0 && poprnd == 0)
282 pr_cont("NOP");
283 else if (prgfunc == 1 && poprnd == 0)
284 pr_cont("RTS");
285 else if (prgfunc == 1 && poprnd == 1)
286 pr_cont("RTI");
287 else if (prgfunc == 1 && poprnd == 2)
288 pr_cont("RTX");
289 else if (prgfunc == 1 && poprnd == 3)
290 pr_cont("RTN");
291 else if (prgfunc == 1 && poprnd == 4)
292 pr_cont("RTE");
293 else if (prgfunc == 2 && poprnd == 0)
294 pr_cont("IDLE");
295 else if (prgfunc == 2 && poprnd == 3)
296 pr_cont("CSYNC");
297 else if (prgfunc == 2 && poprnd == 4)
298 pr_cont("SSYNC");
299 else if (prgfunc == 2 && poprnd == 5)
300 pr_cont("EMUEXCPT");
301 else if (prgfunc == 3)
302 pr_cont("CLI R%i", poprnd);
303 else if (prgfunc == 4)
304 pr_cont("STI R%i", poprnd);
305 else if (prgfunc == 5)
306 pr_cont("JUMP (P%i)", poprnd);
307 else if (prgfunc == 6)
308 pr_cont("CALL (P%i)", poprnd);
309 else if (prgfunc == 7)
310 pr_cont("CALL (PC + P%i)", poprnd);
311 else if (prgfunc == 8)
312 pr_cont("JUMP (PC + P%i", poprnd);
313 else if (prgfunc == 9)
314 pr_cont("RAISE %i", poprnd);
315 else if (prgfunc == 10)
316 pr_cont("EXCPT %i", poprnd);
317 else
318 pr_cont("0x%04x", opcode);
319
320}
321
322#define BRCC_opcode 0x1000
323#define BRCC_offset_bits 0
324#define BRCC_offset_mask 0x3ff
325#define BRCC_B_bits 10
326#define BRCC_B_mask 0x1
327#define BRCC_T_bits 11
328#define BRCC_T_mask 0x1
329#define BRCC_code_bits 12
330#define BRCC_code_mask 0xf
331
332static void decode_BRCC_0(unsigned int opcode)
2a12c463 333{
9a95e2f1
RG		 334 int B = ((opcode >> BRCC_B_bits) & BRCC_B_mask);
335 int T = ((opcode >> BRCC_T_bits) & BRCC_T_mask);
336
337 pr_cont("IF %sCC JUMP pcrel %s", T ? "" : "!", B ? "(BP)" : "");
338}
339
340#define CALLa_opcode 0xe2000000
341#define CALLa_addr_bits 0
342#define CALLa_addr_mask 0xffffff
343#define CALLa_S_bits 24
344#define CALLa_S_mask 0x1
345#define CALLa_code_bits 25
346#define CALLa_code_mask 0x7f
347
348static void decode_CALLa_0(unsigned int opcode)
349{
350 int S = ((opcode >> (CALLa_S_bits - 16)) & CALLa_S_mask);
351
352 if (S)
353 pr_cont("CALL pcrel");
354 else
355 pr_cont("JUMP.L");
356}
357
358#define LoopSetup_opcode 0xe0800000
359#define LoopSetup_eoffset_bits 0
360#define LoopSetup_eoffset_mask 0x3ff
361#define LoopSetup_dontcare_bits 10
362#define LoopSetup_dontcare_mask 0x3
363#define LoopSetup_reg_bits 12
364#define LoopSetup_reg_mask 0xf
365#define LoopSetup_soffset_bits 16
366#define LoopSetup_soffset_mask 0xf
367#define LoopSetup_c_bits 20
368#define LoopSetup_c_mask 0x1
369#define LoopSetup_rop_bits 21
370#define LoopSetup_rop_mask 0x3
371#define LoopSetup_code_bits 23
372#define LoopSetup_code_mask 0x1ff
373
374static void decode_LoopSetup_0(unsigned int opcode)
375{
376 int c = ((opcode >> LoopSetup_c_bits) & LoopSetup_c_mask);
377 int reg = ((opcode >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
378 int rop = ((opcode >> LoopSetup_rop_bits) & LoopSetup_rop_mask);
379
380 pr_cont("LSETUP <> LC%i", c);
381 if ((rop & 1) == 1)
382 pr_cont("= P%i", reg);
383 if ((rop & 2) == 2)
384 pr_cont(" >> 0x1");
385}
386
387#define DspLDST_opcode 0x9c00
388#define DspLDST_reg_bits 0
389#define DspLDST_reg_mask 0x7
390#define DspLDST_i_bits 3
391#define DspLDST_i_mask 0x3
392#define DspLDST_m_bits 5
393#define DspLDST_m_mask 0x3
394#define DspLDST_aop_bits 7
395#define DspLDST_aop_mask 0x3
396#define DspLDST_W_bits 9
397#define DspLDST_W_mask 0x1
398#define DspLDST_code_bits 10
399#define DspLDST_code_mask 0x3f
400
401static void decode_dspLDST_0(unsigned int opcode)
402{
403 int i = ((opcode >> DspLDST_i_bits) & DspLDST_i_mask);
404 int m = ((opcode >> DspLDST_m_bits) & DspLDST_m_mask);
405 int W = ((opcode >> DspLDST_W_bits) & DspLDST_W_mask);
406 int aop = ((opcode >> DspLDST_aop_bits) & DspLDST_aop_mask);
407 int reg = ((opcode >> DspLDST_reg_bits) & DspLDST_reg_mask);
408
409 if (W == 0) {
410 pr_cont("R%i", reg);
411 switch (m) {
412 case 0:
413 pr_cont(" = ");
414 break;
415 case 1:
416 pr_cont(".L = ");
417 break;
418 case 2:
419 pr_cont(".W = ");
420 break;
421 }
422 }
423
424 pr_cont("[ I%i", i);
425
426 switch (aop) {
427 case 0:
428 pr_cont("++ ]");
429 break;
430 case 1:
431 pr_cont("-- ]");
432 break;
433 }
434
435 if (W == 1) {
436 pr_cont(" = R%i", reg);
437 switch (m) {
438 case 1:
439 pr_cont(".L = ");
440 break;
441 case 2:
442 pr_cont(".W = ");
443 break;
444 }
445 }
446}
447
448#define LDST_opcode 0x9000
449#define LDST_reg_bits 0
450#define LDST_reg_mask 0x7
451#define LDST_ptr_bits 3
452#define LDST_ptr_mask 0x7
453#define LDST_Z_bits 6
454#define LDST_Z_mask 0x1
455#define LDST_aop_bits 7
456#define LDST_aop_mask 0x3
457#define LDST_W_bits 9
458#define LDST_W_mask 0x1
459#define LDST_sz_bits 10
460#define LDST_sz_mask 0x3
461#define LDST_code_bits 12
462#define LDST_code_mask 0xf
463
464static void decode_LDST_0(unsigned int opcode)
465{
466 int Z = ((opcode >> LDST_Z_bits) & LDST_Z_mask);
467 int W = ((opcode >> LDST_W_bits) & LDST_W_mask);
468 int sz = ((opcode >> LDST_sz_bits) & LDST_sz_mask);
469 int aop = ((opcode >> LDST_aop_bits) & LDST_aop_mask);
470 int reg = ((opcode >> LDST_reg_bits) & LDST_reg_mask);
471 int ptr = ((opcode >> LDST_ptr_bits) & LDST_ptr_mask);
472
473 if (W == 0)
474 pr_cont("%s%i = ", (sz == 0 && Z == 1) ? "P" : "R", reg);
475
476 switch (sz) {
477 case 1:
478 pr_cont("W");
479 break;
480 case 2:
481 pr_cont("B");
482 break;
483 }
484
485 pr_cont("[P%i", ptr);
486
487 switch (aop) {
488 case 0:
489 pr_cont("++");
490 break;
491 case 1:
492 pr_cont("--");
493 break;
494 }
495 pr_cont("]");
496
497 if (W == 1)
498 pr_cont(" = %s%i ", (sz == 0 && Z == 1) ? "P" : "R", reg);
499
500 if (sz) {
501 if (Z)
502 pr_cont(" (X)");
503 else
504 pr_cont(" (Z)");
505 }
506}
507
508#define LDSTii_opcode 0xa000
509#define LDSTii_reg_bit 0
510#define LDSTii_reg_mask 0x7
511#define LDSTii_ptr_bit 3
512#define LDSTii_ptr_mask 0x7
513#define LDSTii_offset_bit 6
514#define LDSTii_offset_mask 0xf
515#define LDSTii_op_bit 10
516#define LDSTii_op_mask 0x3
517#define LDSTii_W_bit 12
518#define LDSTii_W_mask 0x1
519#define LDSTii_code_bit 13
520#define LDSTii_code_mask 0x7
521
522static void decode_LDSTii_0(unsigned int opcode)
523{
524 int reg = ((opcode >> LDSTii_reg_bit) & LDSTii_reg_mask);
525 int ptr = ((opcode >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
526 int offset = ((opcode >> LDSTii_offset_bit) & LDSTii_offset_mask);
527 int op = ((opcode >> LDSTii_op_bit) & LDSTii_op_mask);
528 int W = ((opcode >> LDSTii_W_bit) & LDSTii_W_mask);
529
530 if (W == 0) {
531 pr_cont("%s%i = %s[P%i + %i]", op == 3 ? "R" : "P", reg,
532 op == 1 || op == 2 ? "" : "W", ptr, offset);
533 if (op == 2)
534 pr_cont("(Z)");
535 if (op == 3)
536 pr_cont("(X)");
537 } else {
538 pr_cont("%s[P%i + %i] = %s%i", op == 0 ? "" : "W", ptr,
539 offset, op == 3 ? "P" : "R", reg);
540 }
541}
542
543#define LDSTidxI_opcode 0xe4000000
544#define LDSTidxI_offset_bits 0
545#define LDSTidxI_offset_mask 0xffff
546#define LDSTidxI_reg_bits 16
547#define LDSTidxI_reg_mask 0x7
548#define LDSTidxI_ptr_bits 19
549#define LDSTidxI_ptr_mask 0x7
550#define LDSTidxI_sz_bits 22
551#define LDSTidxI_sz_mask 0x3
552#define LDSTidxI_Z_bits 24
553#define LDSTidxI_Z_mask 0x1
554#define LDSTidxI_W_bits 25
555#define LDSTidxI_W_mask 0x1
556#define LDSTidxI_code_bits 26
557#define LDSTidxI_code_mask 0x3f
558
559static void decode_LDSTidxI_0(unsigned int opcode)
560{
561 int Z = ((opcode >> LDSTidxI_Z_bits) & LDSTidxI_Z_mask);
562 int W = ((opcode >> LDSTidxI_W_bits) & LDSTidxI_W_mask);
563 int sz = ((opcode >> LDSTidxI_sz_bits) & LDSTidxI_sz_mask);
564 int reg = ((opcode >> LDSTidxI_reg_bits) & LDSTidxI_reg_mask);
565 int ptr = ((opcode >> LDSTidxI_ptr_bits) & LDSTidxI_ptr_mask);
566 int offset = ((opcode >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
567
568 if (W == 0)
569 pr_cont("%s%i = ", sz == 0 && Z == 1 ? "P" : "R", reg);
570
571 if (sz == 1)
572 pr_cont("W");
573 if (sz == 2)
574 pr_cont("B");
575
576 pr_cont("[P%i + %s0x%x]", ptr, offset & 0x20 ? "-" : "",
577 (offset & 0x1f) << 2);
578
579 if (W == 0 && sz != 0) {
580 if (Z)
581 pr_cont("(X)");
2a12c463 582 else
9a95e2f1 583 pr_cont("(Z)");
2a12c463
RG		 584 }
585
9a95e2f1
RG		 586 if (W == 1)
587 pr_cont("= %s%i", (sz == 0 && Z == 1) ? "P" : "R", reg);
588
589}
590
591static void decode_opcode(unsigned int opcode)
592{
593#ifdef CONFIG_BUG
594 if (opcode == BFIN_BUG_OPCODE)
595 pr_cont("BUG");
596 else
597#endif
598 if ((opcode & 0xffffff00) == ProgCtrl_opcode)
599 decode_ProgCtrl_0(opcode);
600 else if ((opcode & 0xfffff000) == BRCC_opcode)
601 decode_BRCC_0(opcode);
602 else if ((opcode & 0xfffff000) == 0x2000)
603 pr_cont("JUMP.S");
604 else if ((opcode & 0xfe000000) == CALLa_opcode)
605 decode_CALLa_0(opcode);
606 else if ((opcode & 0xff8000C0) == LoopSetup_opcode)
607 decode_LoopSetup_0(opcode);
608 else if ((opcode & 0xfffffc00) == DspLDST_opcode)
609 decode_dspLDST_0(opcode);
610 else if ((opcode & 0xfffff000) == LDST_opcode)
611 decode_LDST_0(opcode);
612 else if ((opcode & 0xffffe000) == LDSTii_opcode)
613 decode_LDSTii_0(opcode);
614 else if ((opcode & 0xfc000000) == LDSTidxI_opcode)
615 decode_LDSTidxI_0(opcode);
616 else if (opcode & 0xffff0000)
617 pr_cont("0x%08x", opcode);
618 else
619 pr_cont("0x%04x", opcode);
620}
621
622#define BIT_MULTI_INS 0x08000000
623static void decode_instruction(unsigned short *address)
624{
625 unsigned int opcode;
626
627 if (!get_instruction(&opcode, address))
628 return;
629
630 decode_opcode(opcode);
631
632 /* If things are a 32-bit instruction, it has the possibility of being
633 * a multi-issue instruction (a 32-bit, and 2 16 bit instrucitions)
634 * This test collidates with the unlink instruction, so disallow that
635 */
636 if ((opcode & 0xc0000000) == 0xc0000000 &&
637 (opcode & BIT_MULTI_INS) &&
638 (opcode & 0xe8000000) != 0xe8000000) {
639 pr_cont(" || ");
640 if (!get_instruction(&opcode, address + 2))
641 return;
642 decode_opcode(opcode);
643 pr_cont(" || ");
644 if (!get_instruction(&opcode, address + 3))
645 return;
646 decode_opcode(opcode);
647 }
2a12c463
RG		 648}
649#endif
650
651void dump_bfin_trace_buffer(void)
652{
2a12c463 653#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
d60805ad 654 int tflags, i = 0, fault = 0;
2a12c463
RG		 655 char buf[150];
656 unsigned short *addr;
d60805ad 657 unsigned int cpu = raw_smp_processor_id();
2a12c463
RG		 658#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
659 int j, index;
660#endif
661
662 trace_buffer_save(tflags);
663
d28cff4b 664 pr_notice("Hardware Trace:\n");
2a12c463
RG		 665
666#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
d28cff4b 667 pr_notice("WARNING: Expanded trace turned on - can not trace exceptions\n");
2a12c463
RG		 668#endif
669
670 if (likely(bfin_read_TBUFSTAT() & TBUFCNT)) {
671 for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) {
d60805ad
RG		 672 addr = (unsigned short *)bfin_read_TBUF();
673 decode_address(buf, (unsigned long)addr);
d28cff4b 674 pr_notice("%4i Target : %s\n", i, buf);
d60805ad
RG		 675 /* Normally, the faulting instruction doesn't go into
676 * the trace buffer, (since it doesn't commit), so
677 * we print out the fault address here
678 */
a80d5f44
RG		 679 if (!fault && addr == ((unsigned short *)evt_ivhw)) {
680 addr = (unsigned short *)bfin_read_TBUF();
681 decode_address(buf, (unsigned long)addr);
682 pr_notice(" FAULT : %s ", buf);
683 decode_instruction(addr);
684 pr_cont("\n");
685 fault = 1;
686 continue;
687 }
d60805ad
RG		 688 if (!fault && addr == (unsigned short *)trap &&
689 (cpu_pda[cpu].seqstat & SEQSTAT_EXCAUSE) > VEC_EXCPT15) {
690 decode_address(buf, cpu_pda[cpu].icplb_fault_addr);
691 pr_notice(" FAULT : %s ", buf);
692 decode_instruction((unsigned short *)cpu_pda[cpu].icplb_fault_addr);
693 pr_cont("\n");
694 fault = 1;
695 }
2a12c463
RG		 696 addr = (unsigned short *)bfin_read_TBUF();
697 decode_address(buf, (unsigned long)addr);
d28cff4b 698 pr_notice(" Source : %s ", buf);
2a12c463 699 decode_instruction(addr);
d28cff4b 700 pr_cont("\n");
2a12c463
RG		 701 }
702 }
703
704#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
705 if (trace_buff_offset)
706 index = trace_buff_offset / 4;
707 else
708 index = EXPAND_LEN;
709
710 j = (1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 128;
711 while (j) {
712 decode_address(buf, software_trace_buff[index]);
d28cff4b 713 pr_notice("%4i Target : %s\n", i, buf);
2a12c463
RG		 714 index -= 1;
715 if (index < 0)
716 index = EXPAND_LEN;
717 decode_address(buf, software_trace_buff[index]);
d28cff4b 718 pr_notice(" Source : %s ", buf);
2a12c463 719 decode_instruction((unsigned short *)software_trace_buff[index]);
d28cff4b 720 pr_cont("\n");
2a12c463
RG		 721 index -= 1;
722 if (index < 0)
723 index = EXPAND_LEN;
724 j--;
725 i++;
726 }
727#endif
728
729 trace_buffer_restore(tflags);
730#endif
2a12c463
RG		 731}
732EXPORT_SYMBOL(dump_bfin_trace_buffer);
733
734void dump_bfin_process(struct pt_regs *fp)
735{
2a12c463
RG		 736 /* We should be able to look at fp->ipend, but we don't push it on the
737 * stack all the time, so do this until we fix that */
738 unsigned int context = bfin_read_IPEND();
739
740 if (oops_in_progress)
d28cff4b 741 pr_emerg("Kernel OOPS in progress\n");
2a12c463
RG		 742
743 if (context & 0x0020 && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR)
d28cff4b 744 pr_notice("HW Error context\n");
2a12c463 745 else if (context & 0x0020)
d28cff4b 746 pr_notice("Deferred Exception context\n");
2a12c463 747 else if (context & 0x3FC0)
d28cff4b 748 pr_notice("Interrupt context\n");
2a12c463 749 else if (context & 0x4000)
d28cff4b 750 pr_notice("Deferred Interrupt context\n");
2a12c463 751 else if (context & 0x8000)
d28cff4b 752 pr_notice("Kernel process context\n");
2a12c463
RG		 753
754 /* Because we are crashing, and pointers could be bad, we check things
755 * pretty closely before we use them
756 */
757 if ((unsigned long)current >= FIXED_CODE_START &&
758 !((unsigned long)current & 0x3) && current->pid) {
d28cff4b 759 pr_notice("CURRENT PROCESS:\n");
2a12c463 760 if (current->comm >= (char *)FIXED_CODE_START)
d28cff4b 761 pr_notice("COMM=%s PID=%d",
2a12c463
RG		 762 current->comm, current->pid);
763 else
d28cff4b 764 pr_notice("COMM= invalid");
2a12c463 765
d28cff4b
RG		 766 pr_cont(" CPU=%d\n", current_thread_info()->cpu);
767 if (!((unsigned long)current->mm & 0x3) &&
768 (unsigned long)current->mm >= FIXED_CODE_START) {
769 pr_notice("TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n",
2a12c463
RG		 770 (void *)current->mm->start_code,
771 (void *)current->mm->end_code,
772 (void *)current->mm->start_data,
d28cff4b
RG		 773 (void *)current->mm->end_data);
774 pr_notice(" BSS = 0x%p-0x%p USER-STACK = 0x%p\n\n",
2a12c463
RG		 775 (void *)current->mm->end_data,
776 (void *)current->mm->brk,
777 (void *)current->mm->start_stack);
d28cff4b
RG		 778 } else
779 pr_notice("invalid mm\n");
2a12c463 780 } else
d28cff4b 781 pr_notice("No Valid process in current context\n");
2a12c463
RG		 782}
783
784void dump_bfin_mem(struct pt_regs *fp)
785{
2a12c463
RG		 786 unsigned short *addr, *erraddr, val = 0, err = 0;
787 char sti = 0, buf[6];
788
789 erraddr = (void *)fp->pc;
790
d28cff4b 791 pr_notice("return address: [0x%p]; contents of:", erraddr);
2a12c463
RG		 792
793 for (addr = (unsigned short *)((unsigned long)erraddr & ~0xF) - 0x10;
794 addr < (unsigned short *)((unsigned long)erraddr & ~0xF) + 0x10;
795 addr++) {
796 if (!((unsigned long)addr & 0xF))
d28cff4b 797 pr_notice("0x%p: ", addr);
2a12c463 798
9a95e2f1 799 if (!get_mem16(&val, addr)) {
2a12c463
RG		 800 val = 0;
801 sprintf(buf, "????");
802 } else
803 sprintf(buf, "%04x", val);
804
805 if (addr == erraddr) {
d28cff4b 806 pr_cont("[%s]", buf);
2a12c463
RG		 807 err = val;
808 } else
d28cff4b 809 pr_cont(" %s ", buf);
2a12c463
RG		 810
811 /* Do any previous instructions turn on interrupts? */
812 if (addr <= erraddr && /* in the past */
813 ((val >= 0x0040 && val <= 0x0047) || /* STI instruction */
814 val == 0x017b)) /* [SP++] = RETI */
815 sti = 1;
816 }
817
d28cff4b 818 pr_cont("\n");
2a12c463
RG		 819
820 /* Hardware error interrupts can be deferred */
821 if (unlikely(sti && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR &&
822 oops_in_progress)){
d28cff4b 823 pr_notice("Looks like this was a deferred error - sorry\n");
2a12c463 824#ifndef CONFIG_DEBUG_HWERR
d28cff4b
RG		 825 pr_notice("The remaining message may be meaningless\n");
826 pr_notice("You should enable CONFIG_DEBUG_HWERR to get a better idea where it came from\n");
2a12c463
RG		 827#else
828 /* If we are handling only one peripheral interrupt
829 * and current mm and pid are valid, and the last error
830 * was in that user space process's text area
831 * print it out - because that is where the problem exists
832 */
833 if ((!(((fp)->ipend & ~0x30) & (((fp)->ipend & ~0x30) - 1))) &&
834 (current->pid && current->mm)) {
835 /* And the last RETI points to the current userspace context */
836 if ((fp + 1)->pc >= current->mm->start_code &&
837 (fp + 1)->pc <= current->mm->end_code) {
d28cff4b
RG		 838 pr_notice("It might be better to look around here :\n");
839 pr_notice("-------------------------------------------\n");
2a12c463 840 show_regs(fp + 1);
d28cff4b 841 pr_notice("-------------------------------------------\n");
2a12c463
RG		 842 }
843 }
844#endif
845 }
2a12c463
RG		 846}
847
848void show_regs(struct pt_regs *fp)
849{
2a12c463
RG		 850 char buf[150];
851 struct irqaction *action;
852 unsigned int i;
853 unsigned long flags = 0;
854 unsigned int cpu = raw_smp_processor_id();
855 unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic();
856
d28cff4b 857 pr_notice("\n");
a43cb95d
TH		 858 show_regs_print_info(KERN_NOTICE);
859
2a12c463 860 if (CPUID != bfin_cpuid())
d28cff4b 861 pr_notice("Compiled for cpu family 0x%04x (Rev %d), "
2a12c463
RG		 862 "but running on:0x%04x (Rev %d)\n",
863 CPUID, bfin_compiled_revid(), bfin_cpuid(), bfin_revid());
864
d28cff4b 865 pr_notice("ADSP-%s-0.%d",
2a12c463
RG		 866 CPU, bfin_compiled_revid());
867
868 if (bfin_compiled_revid() != bfin_revid())
d28cff4b 869 pr_cont("(Detected 0.%d)", bfin_revid());
2a12c463 870
d28cff4b 871 pr_cont(" %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n",
2a12c463
RG		 872 get_cclk()/1000000, get_sclk()/1000000,
873#ifdef CONFIG_MPU
874 "mpu on"
875#else
876 "mpu off"
877#endif
878 );
879
d28cff4b 880 pr_notice("%s", linux_banner);
2a12c463 881
d28cff4b
RG		 882 pr_notice("\nSEQUENCER STATUS:\t\t%s\n", print_tainted());
883 pr_notice(" SEQSTAT: %08lx IPEND: %04lx IMASK: %04lx SYSCFG: %04lx\n",
2a12c463
RG		 884 (long)fp->seqstat, fp->ipend, cpu_pda[raw_smp_processor_id()].ex_imask, fp->syscfg);
885 if (fp->ipend & EVT_IRPTEN)
d28cff4b 886 pr_notice(" Global Interrupts Disabled (IPEND[4])\n");
2a12c463
RG		 887 if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG13 | EVT_IVG12 | EVT_IVG11 |
888 EVT_IVG10 | EVT_IVG9 | EVT_IVG8 | EVT_IVG7 | EVT_IVTMR)))
d28cff4b 889 pr_notice(" Peripheral interrupts masked off\n");
2a12c463 890 if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG15 | EVT_IVG14)))
d28cff4b 891 pr_notice(" Kernel interrupts masked off\n");
2a12c463 892 if ((fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) {
d28cff4b 893 pr_notice(" HWERRCAUSE: 0x%lx\n",
2a12c463
RG		 894 (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14);
895#ifdef EBIU_ERRMST
896 /* If the error was from the EBIU, print it out */
897 if (bfin_read_EBIU_ERRMST() & CORE_ERROR) {
d28cff4b 898 pr_notice(" EBIU Error Reason : 0x%04x\n",
2a12c463 899 bfin_read_EBIU_ERRMST());
d28cff4b 900 pr_notice(" EBIU Error Address : 0x%08x\n",
2a12c463
RG		 901 bfin_read_EBIU_ERRADD());
902 }
903#endif
904 }
d28cff4b 905 pr_notice(" EXCAUSE : 0x%lx\n",
2a12c463
RG		 906 fp->seqstat & SEQSTAT_EXCAUSE);
907 for (i = 2; i <= 15 ; i++) {
908 if (fp->ipend & (1 << i)) {
909 if (i != 4) {
910 decode_address(buf, bfin_read32(EVT0 + 4*i));
d28cff4b 911 pr_notice(" physical IVG%i asserted : %s\n", i, buf);
2a12c463 912 } else
d28cff4b 913 pr_notice(" interrupts disabled\n");
2a12c463
RG		 914 }
915 }
916
917 /* if no interrupts are going off, don't print this out */
918 if (fp->ipend & ~0x3F) {
919 for (i = 0; i < (NR_IRQS - 1); i++) {
28a283aa 920 struct irq_desc *desc = irq_to_desc(i);
2a12c463 921 if (!in_atomic)
28a283aa 922 raw_spin_lock_irqsave(&desc->lock, flags);
2a12c463 923
28a283aa 924 action = desc->action;
2a12c463
RG		 925 if (!action)
926 goto unlock;
927
928 decode_address(buf, (unsigned int)action->handler);
d28cff4b 929 pr_notice(" logical irq %3d mapped : %s", i, buf);
2a12c463
RG		 930 for (action = action->next; action; action = action->next) {
931 decode_address(buf, (unsigned int)action->handler);
d28cff4b 932 pr_cont(", %s", buf);
2a12c463 933 }
d28cff4b 934 pr_cont("\n");
2a12c463
RG		 935unlock:
936 if (!in_atomic)
28a283aa 937 raw_spin_unlock_irqrestore(&desc->lock, flags);
2a12c463
RG		 938 }
939 }
940
941 decode_address(buf, fp->rete);
d28cff4b 942 pr_notice(" RETE: %s\n", buf);
2a12c463 943 decode_address(buf, fp->retn);
d28cff4b 944 pr_notice(" RETN: %s\n", buf);
2a12c463 945 decode_address(buf, fp->retx);
d28cff4b 946 pr_notice(" RETX: %s\n", buf);
2a12c463 947 decode_address(buf, fp->rets);
d28cff4b 948 pr_notice(" RETS: %s\n", buf);
2a12c463 949 decode_address(buf, fp->pc);
d28cff4b 950 pr_notice(" PC : %s\n", buf);
2a12c463
RG		 951
952 if (((long)fp->seqstat & SEQSTAT_EXCAUSE) &&
953 (((long)fp->seqstat & SEQSTAT_EXCAUSE) != VEC_HWERR)) {
954 decode_address(buf, cpu_pda[cpu].dcplb_fault_addr);
d28cff4b 955 pr_notice("DCPLB_FAULT_ADDR: %s\n", buf);
2a12c463 956 decode_address(buf, cpu_pda[cpu].icplb_fault_addr);
d28cff4b 957 pr_notice("ICPLB_FAULT_ADDR: %s\n", buf);
2a12c463
RG		 958 }
959
d28cff4b
RG		 960 pr_notice("PROCESSOR STATE:\n");
961 pr_notice(" R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n",
2a12c463 962 fp->r0, fp->r1, fp->r2, fp->r3);
d28cff4b 963 pr_notice(" R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n",
2a12c463 964 fp->r4, fp->r5, fp->r6, fp->r7);
d28cff4b 965 pr_notice(" P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n",
2a12c463 966 fp->p0, fp->p1, fp->p2, fp->p3);
d28cff4b 967 pr_notice(" P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n",
2a12c463 968 fp->p4, fp->p5, fp->fp, (long)fp);
d28cff4b 969 pr_notice(" LB0: %08lx LT0: %08lx LC0: %08lx\n",
2a12c463 970 fp->lb0, fp->lt0, fp->lc0);
d28cff4b 971 pr_notice(" LB1: %08lx LT1: %08lx LC1: %08lx\n",
2a12c463 972 fp->lb1, fp->lt1, fp->lc1);
d28cff4b 973 pr_notice(" B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n",
2a12c463 974 fp->b0, fp->l0, fp->m0, fp->i0);
d28cff4b 975 pr_notice(" B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n",
2a12c463 976 fp->b1, fp->l1, fp->m1, fp->i1);
d28cff4b 977 pr_notice(" B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n",
2a12c463 978 fp->b2, fp->l2, fp->m2, fp->i2);
d28cff4b 979 pr_notice(" B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n",
2a12c463 980 fp->b3, fp->l3, fp->m3, fp->i3);
d28cff4b 981 pr_notice("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
2a12c463
RG		 982 fp->a0w, fp->a0x, fp->a1w, fp->a1x);
983
d28cff4b 984 pr_notice("USP : %08lx ASTAT: %08lx\n",
2a12c463
RG		 985 rdusp(), fp->astat);
986
d28cff4b 987 pr_notice("\n");
2a12c463 988}
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