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Merge tag 'v3.2-rc2' into staging/for_v3.3
[mirror_ubuntu-artful-kernel.git] / arch / blackfin / mach-bf518 / boards / ezbrd.c
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2f6f4bcd 1/*
96f1050d
RG		 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2005 National ICT Australia (NICTA)
4 * Aidan Williams <aidan@nicta.com.au>
2f6f4bcd 5 *
96f1050d 6 * Licensed under the GPL-2 or later.
2f6f4bcd
BW		 7 */
8
9#include <linux/device.h>
8dc7a9c8 10#include <linux/export.h>
2f6f4bcd
BW		 11#include <linux/platform_device.h>
12#include <linux/mtd/mtd.h>
13#include <linux/mtd/partitions.h>
14#include <linux/mtd/physmap.h>
15#include <linux/spi/spi.h>
16#include <linux/spi/flash.h>
17
18#include <linux/i2c.h>
19#include <linux/irq.h>
20#include <linux/interrupt.h>
21#include <asm/dma.h>
22#include <asm/bfin5xx_spi.h>
23#include <asm/reboot.h>
24#include <asm/portmux.h>
25#include <asm/dpmc.h>
501674a5 26#include <asm/bfin_sdh.h>
2f6f4bcd 27#include <linux/spi/ad7877.h>
65319628 28#include <net/dsa.h>
2f6f4bcd
BW		 29
30/*
31 * Name the Board for the /proc/cpuinfo
32 */
fe85cad2 33const char bfin_board_name[] = "ADI BF518F-EZBRD";
2f6f4bcd
BW		 34
35/*
36 * Driver needs to know address, irq and flag pin.
37 */
38
39#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
40static struct mtd_partition ezbrd_partitions[] = {
41 {
42 .name = "bootloader(nor)",
43 .size = 0x40000,
44 .offset = 0,
45 }, {
46 .name = "linux kernel(nor)",
47 .size = 0x1C0000,
48 .offset = MTDPART_OFS_APPEND,
49 }, {
50 .name = "file system(nor)",
51 .size = MTDPART_SIZ_FULL,
52 .offset = MTDPART_OFS_APPEND,
53 }
54};
55
56static struct physmap_flash_data ezbrd_flash_data = {
57 .width = 2,
58 .parts = ezbrd_partitions,
59 .nr_parts = ARRAY_SIZE(ezbrd_partitions),
60};
61
62static struct resource ezbrd_flash_resource = {
63 .start = 0x20000000,
ee0263cc
GY		 64#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
65 .end = 0x202fffff,
66#else
2f6f4bcd 67 .end = 0x203fffff,
ee0263cc 68#endif
2f6f4bcd
BW		 69 .flags = IORESOURCE_MEM,
70};
71
72static struct platform_device ezbrd_flash_device = {
73 .name = "physmap-flash",
74 .id = 0,
75 .dev = {
76 .platform_data = &ezbrd_flash_data,
77 },
78 .num_resources = 1,
79 .resource = &ezbrd_flash_resource,
80};
81#endif
82
83#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
84static struct platform_device rtc_device = {
85 .name = "rtc-bfin",
86 .id = -1,
87};
88#endif
89
90#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
02460d08
SZ		 91#include <linux/bfin_mac.h>
92static const unsigned short bfin_mac_peripherals[] = {
93 P_MII0_ETxD0,
94 P_MII0_ETxD1,
95 P_MII0_ETxEN,
96 P_MII0_ERxD0,
97 P_MII0_ERxD1,
98 P_MII0_TxCLK,
99 P_MII0_PHYINT,
100 P_MII0_CRS,
101 P_MII0_MDC,
102 P_MII0_MDIO,
103 0
104};
105
106static struct bfin_phydev_platform_data bfin_phydev_data[] = {
107 {
d57bc0fe 108#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
02460d08 109 .addr = 3,
d57bc0fe
SZ		 110#else
111 .addr = 1,
112#endif
02460d08
SZ		 113 .irq = IRQ_MAC_PHYINT,
114 },
115};
116
117static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
d57bc0fe 118 .phydev_number = 1,
02460d08
SZ		 119 .phydev_data = bfin_phydev_data,
120 .phy_mode = PHY_INTERFACE_MODE_MII,
121 .mac_peripherals = bfin_mac_peripherals,
d57bc0fe
SZ		 122#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
123 .phy_mask = 0xfff7, /* Only probe the port phy connect to the on chip MAC */
124#endif
02460d08
SZ		 125};
126
65319628
GY		 127static struct platform_device bfin_mii_bus = {
128 .name = "bfin_mii_bus",
02460d08
SZ		 129 .dev = {
130 .platform_data = &bfin_mii_bus_data,
131 }
65319628
GY		 132};
133
2f6f4bcd
BW		 134static struct platform_device bfin_mac_device = {
135 .name = "bfin_mac",
02460d08
SZ		 136 .dev = {
137 .platform_data = &bfin_mii_bus,
138 }
65319628 139};
65319628
GY		 140
141#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
2780cd64 142static struct dsa_chip_data ksz8893m_switch_chip_data = {
65319628 143 .mii_bus = &bfin_mii_bus.dev,
2780cd64
MF		 144 .port_names = {
145 NULL,
146 "eth%d",
147 "eth%d",
148 "cpu",
149 },
150};
151static struct dsa_platform_data ksz8893m_switch_data = {
152 .nr_chips = 1,
65319628 153 .netdev = &bfin_mac_device.dev,
2780cd64 154 .chip = &ksz8893m_switch_chip_data,
65319628
GY		 155};
156
157static struct platform_device ksz8893m_switch_device = {
158 .name = "dsa",
159 .id = 0,
160 .num_resources = 0,
161 .dev.platform_data = &ksz8893m_switch_data,
2f6f4bcd
BW		 162};
163#endif
c19577e3 164#endif
2f6f4bcd
BW		 165
166#if defined(CONFIG_MTD_M25P80) \
167 || defined(CONFIG_MTD_M25P80_MODULE)
168static struct mtd_partition bfin_spi_flash_partitions[] = {
169 {
170 .name = "bootloader(spi)",
171 .size = 0x00040000,
172 .offset = 0,
173 .mask_flags = MTD_CAP_ROM
174 }, {
175 .name = "linux kernel(spi)",
176 .size = MTDPART_SIZ_FULL,
177 .offset = MTDPART_OFS_APPEND,
178 }
179};
180
181static struct flash_platform_data bfin_spi_flash_data = {
182 .name = "m25p80",
183 .parts = bfin_spi_flash_partitions,
184 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
185 .type = "m25p16",
186};
187
188/* SPI flash chip (m25p64) */
189static struct bfin5xx_spi_chip spi_flash_chip_info = {
190 .enable_dma = 0, /* use dma transfer with this chip*/
2f6f4bcd
BW		 191};
192#endif
193
f3f704d3
MH		 194#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
195static struct bfin5xx_spi_chip mmc_spi_chip_info = {
196 .enable_dma = 0,
2f6f4bcd
BW		 197};
198#endif
199
2f6f4bcd 200#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
2f6f4bcd
BW		 201static const struct ad7877_platform_data bfin_ad7877_ts_info = {
202 .model = 7877,
203 .vref_delay_usecs = 50, /* internal, no capacitor */
204 .x_plate_ohms = 419,
205 .y_plate_ohms = 486,
206 .pressure_max = 1000,
207 .pressure_min = 0,
208 .stopacq_polarity = 1,
209 .first_conversion_delay = 3,
210 .acquisition_time = 1,
211 .averaging = 1,
212 .pen_down_acc_interval = 1,
213};
214#endif
215
2f6f4bcd
BW		 216static struct spi_board_info bfin_spi_board_info[] __initdata = {
217#if defined(CONFIG_MTD_M25P80) \
218 || defined(CONFIG_MTD_M25P80_MODULE)
219 {
220 /* the modalias must be the same as spi device driver name */
221 .modalias = "m25p80", /* Name of spi_driver for this device */
222 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
223 .bus_num = 0, /* Framework bus number */
a427293f 224 .chip_select = 2, /* On BF518F-EZBRD it's SPI0_SSEL2 */
2f6f4bcd
BW		 225 .platform_data = &bfin_spi_flash_data,
226 .controller_data = &spi_flash_chip_info,
227 .mode = SPI_MODE_3,
228 },
229#endif
230
c19577e3 231#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628
GY		 232#if defined(CONFIG_NET_DSA_KSZ8893M) \
233 || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
234 {
235 .modalias = "ksz8893m",
236 .max_speed_hz = 5000000,
237 .bus_num = 0,
238 .chip_select = 1,
239 .platform_data = NULL,
65319628
GY		 240 .mode = SPI_MODE_3,
241 },
242#endif
c19577e3 243#endif
65319628 244
f3f704d3 245#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
2f6f4bcd 246 {
f3f704d3 247 .modalias = "mmc_spi",
2f6f4bcd
BW		 248 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
249 .bus_num = 0,
f3f704d3
MH		 250 .chip_select = 5,
251 .controller_data = &mmc_spi_chip_info,
2f6f4bcd
BW		 252 .mode = SPI_MODE_3,
253 },
254#endif
2f6f4bcd
BW		 255#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
256 {
257 .modalias = "ad7877",
258 .platform_data = &bfin_ad7877_ts_info,
259 .irq = IRQ_PF8,
260 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
261 .bus_num = 0,
262 .chip_select = 2,
2f6f4bcd
BW		 263 },
264#endif
265#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
266 && defined(CONFIG_SND_SOC_WM8731_SPI)
267 {
268 .modalias = "wm8731",
269 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
270 .bus_num = 0,
271 .chip_select = 5,
2f6f4bcd
BW		 272 .mode = SPI_MODE_0,
273 },
274#endif
275#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
276 {
277 .modalias = "spidev",
278 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
279 .bus_num = 0,
280 .chip_select = 1,
2f6f4bcd
BW		 281 },
282#endif
283#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
284 {
285 .modalias = "bfin-lq035q1-spi",
286 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
287 .bus_num = 0,
288 .chip_select = 1,
2f6f4bcd
BW		 289 .mode = SPI_CPHA | SPI_CPOL,
290 },
291#endif
292};
293
294/* SPI controller data */
295#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
296/* SPI (0) */
297static struct bfin5xx_spi_master bfin_spi0_info = {
c5af5451 298 .num_chipselect = 6,
2f6f4bcd
BW		 299 .enable_dma = 1, /* master has the ability to do dma transfer */
300 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
301};
302
303static struct resource bfin_spi0_resource[] = {
304 [0] = {
305 .start = SPI0_REGBASE,
306 .end = SPI0_REGBASE + 0xFF,
307 .flags = IORESOURCE_MEM,
308 },
309 [1] = {
310 .start = CH_SPI0,
311 .end = CH_SPI0,
53122693
YL		 312 .flags = IORESOURCE_DMA,
313 },
314 [2] = {
315 .start = IRQ_SPI0,
316 .end = IRQ_SPI0,
2f6f4bcd
BW		 317 .flags = IORESOURCE_IRQ,
318 },
319};
320
321static struct platform_device bfin_spi0_device = {
322 .name = "bfin-spi",
323 .id = 0, /* Bus number */
324 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
325 .resource = bfin_spi0_resource,
326 .dev = {
327 .platform_data = &bfin_spi0_info, /* Passed to driver */
328 },
329};
330
331/* SPI (1) */
332static struct bfin5xx_spi_master bfin_spi1_info = {
c5af5451 333 .num_chipselect = 6,
2f6f4bcd
BW		 334 .enable_dma = 1, /* master has the ability to do dma transfer */
335 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
336};
337
338static struct resource bfin_spi1_resource[] = {
339 [0] = {
340 .start = SPI1_REGBASE,
341 .end = SPI1_REGBASE + 0xFF,
342 .flags = IORESOURCE_MEM,
343 },
344 [1] = {
345 .start = CH_SPI1,
346 .end = CH_SPI1,
53122693
YL		 347 .flags = IORESOURCE_DMA,
348 },
349 [2] = {
350 .start = IRQ_SPI1,
351 .end = IRQ_SPI1,
2f6f4bcd
BW		 352 .flags = IORESOURCE_IRQ,
353 },
354};
355
356static struct platform_device bfin_spi1_device = {
357 .name = "bfin-spi",
358 .id = 1, /* Bus number */
359 .num_resources = ARRAY_SIZE(bfin_spi1_resource),
360 .resource = bfin_spi1_resource,
361 .dev = {
362 .platform_data = &bfin_spi1_info, /* Passed to driver */
363 },
364};
365#endif /* spi master and devices */
366
367#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
2f6f4bcd 368#ifdef CONFIG_SERIAL_BFIN_UART0
6bd1fbea 369static struct resource bfin_uart0_resources[] = {
2f6f4bcd 370 {
6bd1fbea
SZ		 371 .start = UART0_THR,
372 .end = UART0_GCTL+2,
2f6f4bcd
BW		 373 .flags = IORESOURCE_MEM,
374 },
edb0a640
SZ		 375 {
376 .start = IRQ_UART0_TX,
377 .end = IRQ_UART0_TX,
378 .flags = IORESOURCE_IRQ,
379 },
6bd1fbea
SZ		 380 {
381 .start = IRQ_UART0_RX,
edb0a640 382 .end = IRQ_UART0_RX,
6bd1fbea
SZ		 383 .flags = IORESOURCE_IRQ,
384 },
385 {
386 .start = IRQ_UART0_ERROR,
387 .end = IRQ_UART0_ERROR,
388 .flags = IORESOURCE_IRQ,
389 },
390 {
391 .start = CH_UART0_TX,
392 .end = CH_UART0_TX,
393 .flags = IORESOURCE_DMA,
394 },
395 {
396 .start = CH_UART0_RX,
397 .end = CH_UART0_RX,
398 .flags = IORESOURCE_DMA,
399 },
400};
401
a8b19886 402static unsigned short bfin_uart0_peripherals[] = {
6bd1fbea
SZ		 403 P_UART0_TX, P_UART0_RX, 0
404};
405
406static struct platform_device bfin_uart0_device = {
407 .name = "bfin-uart",
408 .id = 0,
409 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
410 .resource = bfin_uart0_resources,
411 .dev = {
412 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
413 },
414};
2f6f4bcd
BW		 415#endif
416#ifdef CONFIG_SERIAL_BFIN_UART1
6bd1fbea 417static struct resource bfin_uart1_resources[] = {
2f6f4bcd 418 {
6bd1fbea
SZ		 419 .start = UART1_THR,
420 .end = UART1_GCTL+2,
2f6f4bcd
BW		 421 .flags = IORESOURCE_MEM,
422 },
edb0a640
SZ		 423 {
424 .start = IRQ_UART1_TX,
425 .end = IRQ_UART1_TX,
426 .flags = IORESOURCE_IRQ,
427 },
6bd1fbea
SZ		 428 {
429 .start = IRQ_UART1_RX,
edb0a640 430 .end = IRQ_UART1_RX,
6bd1fbea
SZ		 431 .flags = IORESOURCE_IRQ,
432 },
433 {
434 .start = IRQ_UART1_ERROR,
435 .end = IRQ_UART1_ERROR,
436 .flags = IORESOURCE_IRQ,
437 },
438 {
439 .start = CH_UART1_TX,
440 .end = CH_UART1_TX,
441 .flags = IORESOURCE_DMA,
442 },
443 {
444 .start = CH_UART1_RX,
445 .end = CH_UART1_RX,
446 .flags = IORESOURCE_DMA,
447 },
2f6f4bcd
BW		 448};
449
a8b19886 450static unsigned short bfin_uart1_peripherals[] = {
6bd1fbea
SZ		 451 P_UART1_TX, P_UART1_RX, 0
452};
453
454static struct platform_device bfin_uart1_device = {
2f6f4bcd
BW		 455 .name = "bfin-uart",
456 .id = 1,
6bd1fbea
SZ		 457 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
458 .resource = bfin_uart1_resources,
459 .dev = {
460 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
461 },
2f6f4bcd
BW		 462};
463#endif
6bd1fbea 464#endif
2f6f4bcd
BW		 465
466#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
2f6f4bcd 467#ifdef CONFIG_BFIN_SIR0
42bd8bcb 468static struct resource bfin_sir0_resources[] = {
2f6f4bcd
BW		 469 {
470 .start = 0xFFC00400,
471 .end = 0xFFC004FF,
472 .flags = IORESOURCE_MEM,
473 },
42bd8bcb
GY		 474 {
475 .start = IRQ_UART0_RX,
476 .end = IRQ_UART0_RX+1,
477 .flags = IORESOURCE_IRQ,
478 },
479 {
480 .start = CH_UART0_RX,
481 .end = CH_UART0_RX+1,
482 .flags = IORESOURCE_DMA,
483 },
484};
485
486static struct platform_device bfin_sir0_device = {
487 .name = "bfin_sir",
488 .id = 0,
489 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
490 .resource = bfin_sir0_resources,
491};
2f6f4bcd
BW		 492#endif
493#ifdef CONFIG_BFIN_SIR1
42bd8bcb 494static struct resource bfin_sir1_resources[] = {
2f6f4bcd
BW		 495 {
496 .start = 0xFFC02000,
497 .end = 0xFFC020FF,
498 .flags = IORESOURCE_MEM,
499 },
42bd8bcb
GY		 500 {
501 .start = IRQ_UART1_RX,
502 .end = IRQ_UART1_RX+1,
503 .flags = IORESOURCE_IRQ,
504 },
505 {
506 .start = CH_UART1_RX,
507 .end = CH_UART1_RX+1,
508 .flags = IORESOURCE_DMA,
509 },
2f6f4bcd
BW		 510};
511
42bd8bcb 512static struct platform_device bfin_sir1_device = {
2f6f4bcd 513 .name = "bfin_sir",
42bd8bcb
GY		 514 .id = 1,
515 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
516 .resource = bfin_sir1_resources,
2f6f4bcd
BW		 517};
518#endif
42bd8bcb 519#endif
2f6f4bcd 520
97dd505c
BL		 521#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
522static struct platform_device bfin_i2s = {
523 .name = "bfin-i2s",
524 .id = CONFIG_SND_BF5XX_SPORT_NUM,
525 /* TODO: add platform data here */
526};
527#endif
528
2f6f4bcd
BW		 529#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
530static struct resource bfin_twi0_resource[] = {
531 [0] = {
532 .start = TWI0_REGBASE,
533 .end = TWI0_REGBASE,
534 .flags = IORESOURCE_MEM,
535 },
536 [1] = {
537 .start = IRQ_TWI,
538 .end = IRQ_TWI,
539 .flags = IORESOURCE_IRQ,
540 },
541};
542
543static struct platform_device i2c_bfin_twi_device = {
544 .name = "i2c-bfin-twi",
545 .id = 0,
546 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
547 .resource = bfin_twi0_resource,
548};
549#endif
550
2f6f4bcd 551static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
ebd58333 552#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
2f6f4bcd
BW		 553 {
554 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
555 },
556#endif
204844eb 557#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
2f6f4bcd
BW		 558 {
559 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
560 .irq = IRQ_PF8,
561 },
562#endif
97dd505c
BL		 563#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
564 {
565 I2C_BOARD_INFO("ssm2602", 0x1b),
566 },
567#endif
2f6f4bcd 568};
2f6f4bcd
BW		 569
570#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
df5de261
SZ		 571#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
572static struct resource bfin_sport0_uart_resources[] = {
573 {
574 .start = SPORT0_TCR1,
575 .end = SPORT0_MRCS3+4,
576 .flags = IORESOURCE_MEM,
577 },
578 {
579 .start = IRQ_SPORT0_RX,
580 .end = IRQ_SPORT0_RX+1,
581 .flags = IORESOURCE_IRQ,
582 },
583 {
584 .start = IRQ_SPORT0_ERROR,
585 .end = IRQ_SPORT0_ERROR,
586 .flags = IORESOURCE_IRQ,
587 },
588};
589
a8b19886 590static unsigned short bfin_sport0_peripherals[] = {
df5de261 591 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
e54b6730 592 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
df5de261
SZ		 593};
594
2f6f4bcd
BW		 595static struct platform_device bfin_sport0_uart_device = {
596 .name = "bfin-sport-uart",
597 .id = 0,
df5de261
SZ		 598 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
599 .resource = bfin_sport0_uart_resources,
600 .dev = {
601 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
602 },
603};
604#endif
605#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
606static struct resource bfin_sport1_uart_resources[] = {
607 {
608 .start = SPORT1_TCR1,
609 .end = SPORT1_MRCS3+4,
610 .flags = IORESOURCE_MEM,
611 },
612 {
613 .start = IRQ_SPORT1_RX,
614 .end = IRQ_SPORT1_RX+1,
615 .flags = IORESOURCE_IRQ,
616 },
617 {
618 .start = IRQ_SPORT1_ERROR,
619 .end = IRQ_SPORT1_ERROR,
620 .flags = IORESOURCE_IRQ,
621 },
622};
623
a8b19886 624static unsigned short bfin_sport1_peripherals[] = {
df5de261 625 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
e54b6730 626 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
2f6f4bcd
BW		 627};
628
629static struct platform_device bfin_sport1_uart_device = {
630 .name = "bfin-sport-uart",
631 .id = 1,
df5de261
SZ		 632 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
633 .resource = bfin_sport1_uart_resources,
634 .dev = {
635 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
636 },
2f6f4bcd
BW		 637};
638#endif
df5de261 639#endif
2f6f4bcd
BW		 640
641#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
642#include <linux/input.h>
643#include <linux/gpio_keys.h>
644
645static struct gpio_keys_button bfin_gpio_keys_table[] = {
646 {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
647 {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
648};
649
650static struct gpio_keys_platform_data bfin_gpio_keys_data = {
651 .buttons = bfin_gpio_keys_table,
652 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
653};
654
655static struct platform_device bfin_device_gpiokeys = {
656 .name = "gpio-keys",
657 .dev = {
658 .platform_data = &bfin_gpio_keys_data,
659 },
660};
661#endif
662
501674a5
CC		 663#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
664
665static struct bfin_sd_host bfin_sdh_data = {
666 .dma_chan = CH_RSI,
667 .irq_int0 = IRQ_RSI_INT0,
668 .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
669};
670
671static struct platform_device bf51x_sdh_device = {
672 .name = "bfin-sdh",
673 .id = 0,
674 .dev = {
675 .platform_data = &bfin_sdh_data,
676 },
677};
678#endif
679
2f6f4bcd
BW		 680static const unsigned int cclk_vlev_datasheet[] =
681{
682 VRPAIR(VLEV_100, 400000000),
683 VRPAIR(VLEV_105, 426000000),
684 VRPAIR(VLEV_110, 500000000),
685 VRPAIR(VLEV_115, 533000000),
686 VRPAIR(VLEV_120, 600000000),
687};
688
689static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
690 .tuple_tab = cclk_vlev_datasheet,
691 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
692 .vr_settling_time = 25 /* us */,
693};
694
695static struct platform_device bfin_dpmc = {
696 .name = "bfin dpmc",
697 .dev = {
698 .platform_data = &bfin_dmpc_vreg_data,
699 },
700};
701
702static struct platform_device *stamp_devices[] __initdata = {
703
704 &bfin_dpmc,
705
706#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
707 &rtc_device,
708#endif
709
710#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628 711 &bfin_mii_bus,
2f6f4bcd 712 &bfin_mac_device,
65319628
GY		 713#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
714 &ksz8893m_switch_device,
715#endif
c19577e3 716#endif
65319628 717
2f6f4bcd
BW		 718#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
719 &bfin_spi0_device,
720 &bfin_spi1_device,
721#endif
722
723#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
6bd1fbea
SZ		 724#ifdef CONFIG_SERIAL_BFIN_UART0
725 &bfin_uart0_device,
726#endif
727#ifdef CONFIG_SERIAL_BFIN_UART1
728 &bfin_uart1_device,
729#endif
2f6f4bcd
BW		 730#endif
731
732#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb
GY		 733#ifdef CONFIG_BFIN_SIR0
734 &bfin_sir0_device,
735#endif
736#ifdef CONFIG_BFIN_SIR1
737 &bfin_sir1_device,
738#endif
2f6f4bcd
BW		 739#endif
740
741#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
742 &i2c_bfin_twi_device,
743#endif
744
97dd505c
BL		 745#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
746 &bfin_i2s,
747#endif
748
2f6f4bcd 749#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
df5de261 750#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
2f6f4bcd 751 &bfin_sport0_uart_device,
df5de261
SZ		 752#endif
753#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
2f6f4bcd
BW		 754 &bfin_sport1_uart_device,
755#endif
df5de261 756#endif
2f6f4bcd
BW		 757
758#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
759 &bfin_device_gpiokeys,
760#endif
761
501674a5
CC		 762#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
763 &bf51x_sdh_device,
764#endif
765
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BW		 766#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
767 &ezbrd_flash_device,
768#endif
2f6f4bcd
BW		 769};
770
771static int __init ezbrd_init(void)
772{
773 printk(KERN_INFO "%s(): registering device resources\n", __func__);
2f6f4bcd
BW		 774 i2c_register_board_info(0, bfin_i2c_board_info,
775 ARRAY_SIZE(bfin_i2c_board_info));
2f6f4bcd
BW		 776 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
777 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
ee0263cc
GY		 778 /* setup BF518-EZBRD GPIO pin PG11 to AMS2, PG15 to AMS3. */
779 peripheral_request(P_AMS2, "ParaFlash");
780#if !defined(CONFIG_SPI_BFIN) && !defined(CONFIG_SPI_BFIN_MODULE)
781 peripheral_request(P_AMS3, "ParaFlash");
782#endif
2f6f4bcd
BW		 783 return 0;
784}
785
786arch_initcall(ezbrd_init);
787
c13ce9fd
SZ		 788static struct platform_device *ezbrd_early_devices[] __initdata = {
789#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
790#ifdef CONFIG_SERIAL_BFIN_UART0
791 &bfin_uart0_device,
792#endif
793#ifdef CONFIG_SERIAL_BFIN_UART1
794 &bfin_uart1_device,
795#endif
796#endif
797
798#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
799#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
800 &bfin_sport0_uart_device,
801#endif
802#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
803 &bfin_sport1_uart_device,
804#endif
805#endif
806};
807
808void __init native_machine_early_platform_add_devices(void)
809{
810 printk(KERN_INFO "register early platform devices\n");
811 early_platform_add_devices(ezbrd_early_devices,
812 ARRAY_SIZE(ezbrd_early_devices));
813}
814
2f6f4bcd
BW		 815void native_machine_restart(char *cmd)
816{
817 /* workaround reboot hang when booting from SPI */
818 if ((bfin_read_SYSCR() & 0x7) == 0x3)
b52dae31 819 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
2f6f4bcd
BW		 820}
821
822void bfin_get_ether_addr(char *addr)
823{
824 /* the MAC is stored in OTP memory page 0xDF */
825 u32 ret;
826 u64 otp_mac;
827 u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
828
829 ret = otp_read(0xDF, 0x00, &otp_mac);
830 if (!(ret & 0x1)) {
831 char *otp_mac_p = (char *)&otp_mac;
832 for (ret = 0; ret < 6; ++ret)
833 addr[ret] = otp_mac_p[5 - ret];
834 }
835}
836EXPORT_SYMBOL(bfin_get_ether_addr);
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