]>
Commit | Line | Data |
---|---|---|
5aff1642 HK |
1 | /* |
2 | * Copyright 2004-2009 Analog Devices Inc. | |
3 | * 2005 National ICT Australia (NICTA) | |
4 | * Aidan Williams <aidan@nicta.com.au> | |
5 | * | |
6 | * Licensed under the GPL-2 or later. | |
7 | */ | |
8 | ||
9 | #include <linux/device.h> | |
10 | #include <linux/etherdevice.h> | |
11 | #include <linux/platform_device.h> | |
12 | #include <linux/mtd/mtd.h> | |
13 | #include <linux/mtd/partitions.h> | |
14 | #include <linux/mtd/physmap.h> | |
15 | #include <linux/spi/spi.h> | |
16 | #include <linux/spi/flash.h> | |
17 | ||
18 | #include <linux/i2c.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <asm/dma.h> | |
22 | #include <asm/bfin5xx_spi.h> | |
23 | #include <asm/reboot.h> | |
24 | #include <asm/portmux.h> | |
25 | #include <asm/dpmc.h> | |
26 | #include <asm/bfin_sdh.h> | |
27 | #include <linux/spi/ad7877.h> | |
28 | #include <net/dsa.h> | |
29 | ||
30 | /* | |
31 | * Name the Board for the /proc/cpuinfo | |
32 | */ | |
33 | const char bfin_board_name[] = "Bluetechnix TCM-BF518"; | |
34 | ||
35 | /* | |
36 | * Driver needs to know address, irq and flag pin. | |
37 | */ | |
38 | ||
c4a2c58d | 39 | #if IS_ENABLED(CONFIG_MTD_PHYSMAP) |
5aff1642 HK |
40 | static struct mtd_partition tcm_partitions[] = { |
41 | { | |
42 | .name = "bootloader(nor)", | |
43 | .size = 0x40000, | |
44 | .offset = 0, | |
45 | }, | |
46 | { | |
47 | .name = "linux(nor)", | |
48 | .size = 0x1C0000, | |
49 | .offset = MTDPART_OFS_APPEND, | |
50 | } | |
51 | }; | |
52 | ||
53 | static struct physmap_flash_data tcm_flash_data = { | |
54 | .width = 2, | |
55 | .parts = tcm_partitions, | |
56 | .nr_parts = ARRAY_SIZE(tcm_partitions), | |
57 | }; | |
58 | ||
59 | static struct resource tcm_flash_resource = { | |
60 | .start = 0x20000000, | |
61 | .end = 0x201fffff, | |
62 | .flags = IORESOURCE_MEM, | |
63 | }; | |
64 | ||
65 | static struct platform_device tcm_flash_device = { | |
66 | .name = "physmap-flash", | |
67 | .id = 0, | |
68 | .dev = { | |
69 | .platform_data = &tcm_flash_data, | |
70 | }, | |
71 | .num_resources = 1, | |
72 | .resource = &tcm_flash_resource, | |
73 | }; | |
74 | #endif | |
75 | ||
c4a2c58d | 76 | #if IS_ENABLED(CONFIG_RTC_DRV_BFIN) |
5aff1642 HK |
77 | static struct platform_device rtc_device = { |
78 | .name = "rtc-bfin", | |
79 | .id = -1, | |
80 | }; | |
81 | #endif | |
82 | ||
c4a2c58d | 83 | #if IS_ENABLED(CONFIG_BFIN_MAC) |
02460d08 SZ |
84 | #include <linux/bfin_mac.h> |
85 | static const unsigned short bfin_mac_peripherals[] = P_MII0; | |
86 | ||
87 | static struct bfin_phydev_platform_data bfin_phydev_data[] = { | |
88 | { | |
89 | .addr = 1, | |
90 | .irq = IRQ_MAC_PHYINT, | |
91 | }, | |
92 | }; | |
93 | ||
94 | static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { | |
95 | .phydev_number = 1, | |
96 | .phydev_data = bfin_phydev_data, | |
97 | .phy_mode = PHY_INTERFACE_MODE_MII, | |
98 | .mac_peripherals = bfin_mac_peripherals, | |
99 | }; | |
100 | ||
5aff1642 HK |
101 | static struct platform_device bfin_mii_bus = { |
102 | .name = "bfin_mii_bus", | |
02460d08 SZ |
103 | .dev = { |
104 | .platform_data = &bfin_mii_bus_data, | |
105 | } | |
5aff1642 HK |
106 | }; |
107 | ||
108 | static struct platform_device bfin_mac_device = { | |
109 | .name = "bfin_mac", | |
02460d08 SZ |
110 | .dev = { |
111 | .platform_data = &bfin_mii_bus, | |
112 | } | |
5aff1642 HK |
113 | }; |
114 | #endif | |
115 | ||
c4a2c58d | 116 | #if IS_ENABLED(CONFIG_MTD_M25P80) |
5aff1642 HK |
117 | static struct mtd_partition bfin_spi_flash_partitions[] = { |
118 | { | |
119 | .name = "bootloader(spi)", | |
120 | .size = 0x00040000, | |
121 | .offset = 0, | |
122 | .mask_flags = MTD_CAP_ROM | |
123 | }, { | |
124 | .name = "linux kernel(spi)", | |
125 | .size = MTDPART_SIZ_FULL, | |
126 | .offset = MTDPART_OFS_APPEND, | |
127 | } | |
128 | }; | |
129 | ||
130 | static struct flash_platform_data bfin_spi_flash_data = { | |
131 | .name = "m25p80", | |
132 | .parts = bfin_spi_flash_partitions, | |
133 | .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), | |
134 | .type = "m25p16", | |
135 | }; | |
136 | ||
137 | /* SPI flash chip (m25p64) */ | |
138 | static struct bfin5xx_spi_chip spi_flash_chip_info = { | |
139 | .enable_dma = 0, /* use dma transfer with this chip*/ | |
5aff1642 HK |
140 | }; |
141 | #endif | |
142 | ||
c4a2c58d | 143 | #if IS_ENABLED(CONFIG_MMC_SPI) |
5aff1642 HK |
144 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { |
145 | .enable_dma = 0, | |
5aff1642 HK |
146 | }; |
147 | #endif | |
148 | ||
c4a2c58d | 149 | #if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) |
5aff1642 HK |
150 | static const struct ad7877_platform_data bfin_ad7877_ts_info = { |
151 | .model = 7877, | |
152 | .vref_delay_usecs = 50, /* internal, no capacitor */ | |
153 | .x_plate_ohms = 419, | |
154 | .y_plate_ohms = 486, | |
155 | .pressure_max = 1000, | |
156 | .pressure_min = 0, | |
157 | .stopacq_polarity = 1, | |
158 | .first_conversion_delay = 3, | |
159 | .acquisition_time = 1, | |
160 | .averaging = 1, | |
161 | .pen_down_acc_interval = 1, | |
162 | }; | |
163 | #endif | |
164 | ||
5aff1642 | 165 | static struct spi_board_info bfin_spi_board_info[] __initdata = { |
c4a2c58d | 166 | #if IS_ENABLED(CONFIG_MTD_M25P80) |
5aff1642 HK |
167 | { |
168 | /* the modalias must be the same as spi device driver name */ | |
169 | .modalias = "m25p80", /* Name of spi_driver for this device */ | |
170 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | |
171 | .bus_num = 0, /* Framework bus number */ | |
172 | .chip_select = 2, /* SPI0_SSEL2 */ | |
173 | .platform_data = &bfin_spi_flash_data, | |
174 | .controller_data = &spi_flash_chip_info, | |
175 | .mode = SPI_MODE_3, | |
176 | }, | |
177 | #endif | |
178 | ||
c4a2c58d | 179 | #if IS_ENABLED(CONFIG_MMC_SPI) |
5aff1642 HK |
180 | { |
181 | .modalias = "mmc_spi", | |
182 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ | |
183 | .bus_num = 0, | |
184 | .chip_select = 5, | |
185 | .controller_data = &mmc_spi_chip_info, | |
186 | .mode = SPI_MODE_3, | |
187 | }, | |
188 | #endif | |
c4a2c58d | 189 | #if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) |
5aff1642 HK |
190 | { |
191 | .modalias = "ad7877", | |
192 | .platform_data = &bfin_ad7877_ts_info, | |
193 | .irq = IRQ_PF8, | |
194 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | |
195 | .bus_num = 0, | |
196 | .chip_select = 2, | |
5aff1642 HK |
197 | }, |
198 | #endif | |
c4a2c58d | 199 | #if IS_ENABLED(CONFIG_SND_SOC_WM8731) \ |
5aff1642 HK |
200 | && defined(CONFIG_SND_SOC_WM8731_SPI) |
201 | { | |
202 | .modalias = "wm8731", | |
203 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | |
204 | .bus_num = 0, | |
205 | .chip_select = 5, | |
5aff1642 HK |
206 | .mode = SPI_MODE_0, |
207 | }, | |
208 | #endif | |
c4a2c58d | 209 | #if IS_ENABLED(CONFIG_SPI_SPIDEV) |
5aff1642 HK |
210 | { |
211 | .modalias = "spidev", | |
212 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | |
213 | .bus_num = 0, | |
214 | .chip_select = 1, | |
5aff1642 HK |
215 | }, |
216 | #endif | |
c4a2c58d | 217 | #if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1) |
5aff1642 HK |
218 | { |
219 | .modalias = "bfin-lq035q1-spi", | |
220 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ | |
221 | .bus_num = 0, | |
222 | .chip_select = 1, | |
5aff1642 HK |
223 | .mode = SPI_CPHA | SPI_CPOL, |
224 | }, | |
225 | #endif | |
226 | }; | |
227 | ||
228 | /* SPI controller data */ | |
c4a2c58d | 229 | #if IS_ENABLED(CONFIG_SPI_BFIN5XX) |
5aff1642 HK |
230 | /* SPI (0) */ |
231 | static struct bfin5xx_spi_master bfin_spi0_info = { | |
232 | .num_chipselect = 6, | |
233 | .enable_dma = 1, /* master has the ability to do dma transfer */ | |
234 | .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, | |
235 | }; | |
236 | ||
237 | static struct resource bfin_spi0_resource[] = { | |
238 | [0] = { | |
239 | .start = SPI0_REGBASE, | |
240 | .end = SPI0_REGBASE + 0xFF, | |
241 | .flags = IORESOURCE_MEM, | |
242 | }, | |
243 | [1] = { | |
244 | .start = CH_SPI0, | |
245 | .end = CH_SPI0, | |
246 | .flags = IORESOURCE_DMA, | |
247 | }, | |
248 | [2] = { | |
249 | .start = IRQ_SPI0, | |
250 | .end = IRQ_SPI0, | |
251 | .flags = IORESOURCE_IRQ, | |
252 | }, | |
253 | }; | |
254 | ||
255 | static struct platform_device bfin_spi0_device = { | |
256 | .name = "bfin-spi", | |
257 | .id = 0, /* Bus number */ | |
258 | .num_resources = ARRAY_SIZE(bfin_spi0_resource), | |
259 | .resource = bfin_spi0_resource, | |
260 | .dev = { | |
261 | .platform_data = &bfin_spi0_info, /* Passed to driver */ | |
262 | }, | |
263 | }; | |
264 | ||
265 | /* SPI (1) */ | |
266 | static struct bfin5xx_spi_master bfin_spi1_info = { | |
c5af5451 | 267 | .num_chipselect = 6, |
5aff1642 HK |
268 | .enable_dma = 1, /* master has the ability to do dma transfer */ |
269 | .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, | |
270 | }; | |
271 | ||
272 | static struct resource bfin_spi1_resource[] = { | |
273 | [0] = { | |
274 | .start = SPI1_REGBASE, | |
275 | .end = SPI1_REGBASE + 0xFF, | |
276 | .flags = IORESOURCE_MEM, | |
277 | }, | |
278 | [1] = { | |
279 | .start = CH_SPI1, | |
280 | .end = CH_SPI1, | |
281 | .flags = IORESOURCE_DMA, | |
282 | }, | |
283 | [2] = { | |
284 | .start = IRQ_SPI1, | |
285 | .end = IRQ_SPI1, | |
286 | .flags = IORESOURCE_IRQ, | |
287 | }, | |
288 | }; | |
289 | ||
290 | static struct platform_device bfin_spi1_device = { | |
291 | .name = "bfin-spi", | |
292 | .id = 1, /* Bus number */ | |
293 | .num_resources = ARRAY_SIZE(bfin_spi1_resource), | |
294 | .resource = bfin_spi1_resource, | |
295 | .dev = { | |
296 | .platform_data = &bfin_spi1_info, /* Passed to driver */ | |
297 | }, | |
298 | }; | |
299 | #endif /* spi master and devices */ | |
300 | ||
c4a2c58d | 301 | #if IS_ENABLED(CONFIG_SERIAL_BFIN) |
5aff1642 HK |
302 | #ifdef CONFIG_SERIAL_BFIN_UART0 |
303 | static struct resource bfin_uart0_resources[] = { | |
304 | { | |
305 | .start = UART0_THR, | |
306 | .end = UART0_GCTL+2, | |
307 | .flags = IORESOURCE_MEM, | |
308 | }, | |
edb0a640 SZ |
309 | { |
310 | .start = IRQ_UART0_TX, | |
311 | .end = IRQ_UART0_TX, | |
312 | .flags = IORESOURCE_IRQ, | |
313 | }, | |
5aff1642 HK |
314 | { |
315 | .start = IRQ_UART0_RX, | |
edb0a640 | 316 | .end = IRQ_UART0_RX, |
5aff1642 HK |
317 | .flags = IORESOURCE_IRQ, |
318 | }, | |
319 | { | |
320 | .start = IRQ_UART0_ERROR, | |
321 | .end = IRQ_UART0_ERROR, | |
322 | .flags = IORESOURCE_IRQ, | |
323 | }, | |
324 | { | |
325 | .start = CH_UART0_TX, | |
326 | .end = CH_UART0_TX, | |
327 | .flags = IORESOURCE_DMA, | |
328 | }, | |
329 | { | |
330 | .start = CH_UART0_RX, | |
331 | .end = CH_UART0_RX, | |
332 | .flags = IORESOURCE_DMA, | |
333 | }, | |
334 | }; | |
335 | ||
a8b19886 | 336 | static unsigned short bfin_uart0_peripherals[] = { |
5aff1642 HK |
337 | P_UART0_TX, P_UART0_RX, 0 |
338 | }; | |
339 | ||
340 | static struct platform_device bfin_uart0_device = { | |
341 | .name = "bfin-uart", | |
342 | .id = 0, | |
343 | .num_resources = ARRAY_SIZE(bfin_uart0_resources), | |
344 | .resource = bfin_uart0_resources, | |
345 | .dev = { | |
346 | .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ | |
347 | }, | |
348 | }; | |
349 | #endif | |
350 | #ifdef CONFIG_SERIAL_BFIN_UART1 | |
351 | static struct resource bfin_uart1_resources[] = { | |
352 | { | |
353 | .start = UART1_THR, | |
354 | .end = UART1_GCTL+2, | |
355 | .flags = IORESOURCE_MEM, | |
356 | }, | |
edb0a640 SZ |
357 | { |
358 | .start = IRQ_UART1_TX, | |
359 | .end = IRQ_UART1_TX, | |
360 | .flags = IORESOURCE_IRQ, | |
361 | }, | |
5aff1642 HK |
362 | { |
363 | .start = IRQ_UART1_RX, | |
edb0a640 | 364 | .end = IRQ_UART1_RX, |
5aff1642 HK |
365 | .flags = IORESOURCE_IRQ, |
366 | }, | |
367 | { | |
368 | .start = IRQ_UART1_ERROR, | |
369 | .end = IRQ_UART1_ERROR, | |
370 | .flags = IORESOURCE_IRQ, | |
371 | }, | |
372 | { | |
373 | .start = CH_UART1_TX, | |
374 | .end = CH_UART1_TX, | |
375 | .flags = IORESOURCE_DMA, | |
376 | }, | |
377 | { | |
378 | .start = CH_UART1_RX, | |
379 | .end = CH_UART1_RX, | |
380 | .flags = IORESOURCE_DMA, | |
381 | }, | |
382 | }; | |
383 | ||
a8b19886 | 384 | static unsigned short bfin_uart1_peripherals[] = { |
5aff1642 HK |
385 | P_UART1_TX, P_UART1_RX, 0 |
386 | }; | |
387 | ||
388 | static struct platform_device bfin_uart1_device = { | |
389 | .name = "bfin-uart", | |
390 | .id = 1, | |
391 | .num_resources = ARRAY_SIZE(bfin_uart1_resources), | |
392 | .resource = bfin_uart1_resources, | |
393 | .dev = { | |
394 | .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ | |
395 | }, | |
396 | }; | |
397 | #endif | |
398 | #endif | |
399 | ||
c4a2c58d | 400 | #if IS_ENABLED(CONFIG_BFIN_SIR) |
5aff1642 HK |
401 | #ifdef CONFIG_BFIN_SIR0 |
402 | static struct resource bfin_sir0_resources[] = { | |
403 | { | |
404 | .start = 0xFFC00400, | |
405 | .end = 0xFFC004FF, | |
406 | .flags = IORESOURCE_MEM, | |
407 | }, | |
408 | { | |
409 | .start = IRQ_UART0_RX, | |
410 | .end = IRQ_UART0_RX+1, | |
411 | .flags = IORESOURCE_IRQ, | |
412 | }, | |
413 | { | |
414 | .start = CH_UART0_RX, | |
415 | .end = CH_UART0_RX+1, | |
416 | .flags = IORESOURCE_DMA, | |
417 | }, | |
418 | }; | |
419 | ||
420 | static struct platform_device bfin_sir0_device = { | |
421 | .name = "bfin_sir", | |
422 | .id = 0, | |
423 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | |
424 | .resource = bfin_sir0_resources, | |
425 | }; | |
426 | #endif | |
427 | #ifdef CONFIG_BFIN_SIR1 | |
428 | static struct resource bfin_sir1_resources[] = { | |
429 | { | |
430 | .start = 0xFFC02000, | |
431 | .end = 0xFFC020FF, | |
432 | .flags = IORESOURCE_MEM, | |
433 | }, | |
434 | { | |
435 | .start = IRQ_UART1_RX, | |
436 | .end = IRQ_UART1_RX+1, | |
437 | .flags = IORESOURCE_IRQ, | |
438 | }, | |
439 | { | |
440 | .start = CH_UART1_RX, | |
441 | .end = CH_UART1_RX+1, | |
442 | .flags = IORESOURCE_DMA, | |
443 | }, | |
444 | }; | |
445 | ||
446 | static struct platform_device bfin_sir1_device = { | |
447 | .name = "bfin_sir", | |
448 | .id = 1, | |
449 | .num_resources = ARRAY_SIZE(bfin_sir1_resources), | |
450 | .resource = bfin_sir1_resources, | |
451 | }; | |
452 | #endif | |
453 | #endif | |
454 | ||
c4a2c58d | 455 | #if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) |
cf93feb3 SZ |
456 | static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; |
457 | ||
5aff1642 HK |
458 | static struct resource bfin_twi0_resource[] = { |
459 | [0] = { | |
460 | .start = TWI0_REGBASE, | |
461 | .end = TWI0_REGBASE, | |
462 | .flags = IORESOURCE_MEM, | |
463 | }, | |
464 | [1] = { | |
465 | .start = IRQ_TWI, | |
466 | .end = IRQ_TWI, | |
467 | .flags = IORESOURCE_IRQ, | |
468 | }, | |
469 | }; | |
470 | ||
471 | static struct platform_device i2c_bfin_twi_device = { | |
472 | .name = "i2c-bfin-twi", | |
473 | .id = 0, | |
474 | .num_resources = ARRAY_SIZE(bfin_twi0_resource), | |
475 | .resource = bfin_twi0_resource, | |
cf93feb3 SZ |
476 | .dev = { |
477 | .platform_data = &bfin_twi0_pins, | |
478 | }, | |
5aff1642 HK |
479 | }; |
480 | #endif | |
481 | ||
482 | static struct i2c_board_info __initdata bfin_i2c_board_info[] = { | |
c4a2c58d | 483 | #if IS_ENABLED(CONFIG_BFIN_TWI_LCD) |
5aff1642 HK |
484 | { |
485 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), | |
486 | }, | |
487 | #endif | |
c4a2c58d | 488 | #if IS_ENABLED(CONFIG_INPUT_PCF8574) |
5aff1642 HK |
489 | { |
490 | I2C_BOARD_INFO("pcf8574_keypad", 0x27), | |
491 | .irq = IRQ_PF8, | |
492 | }, | |
493 | #endif | |
494 | }; | |
495 | ||
c4a2c58d | 496 | #if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) |
5aff1642 HK |
497 | #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART |
498 | static struct resource bfin_sport0_uart_resources[] = { | |
499 | { | |
500 | .start = SPORT0_TCR1, | |
501 | .end = SPORT0_MRCS3+4, | |
502 | .flags = IORESOURCE_MEM, | |
503 | }, | |
504 | { | |
505 | .start = IRQ_SPORT0_RX, | |
506 | .end = IRQ_SPORT0_RX+1, | |
507 | .flags = IORESOURCE_IRQ, | |
508 | }, | |
509 | { | |
510 | .start = IRQ_SPORT0_ERROR, | |
511 | .end = IRQ_SPORT0_ERROR, | |
512 | .flags = IORESOURCE_IRQ, | |
513 | }, | |
514 | }; | |
515 | ||
a8b19886 | 516 | static unsigned short bfin_sport0_peripherals[] = { |
5aff1642 | 517 | P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, |
e54b6730 | 518 | P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 |
5aff1642 HK |
519 | }; |
520 | ||
521 | static struct platform_device bfin_sport0_uart_device = { | |
522 | .name = "bfin-sport-uart", | |
523 | .id = 0, | |
524 | .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), | |
525 | .resource = bfin_sport0_uart_resources, | |
526 | .dev = { | |
527 | .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ | |
528 | }, | |
529 | }; | |
530 | #endif | |
531 | #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART | |
532 | static struct resource bfin_sport1_uart_resources[] = { | |
533 | { | |
534 | .start = SPORT1_TCR1, | |
535 | .end = SPORT1_MRCS3+4, | |
536 | .flags = IORESOURCE_MEM, | |
537 | }, | |
538 | { | |
539 | .start = IRQ_SPORT1_RX, | |
540 | .end = IRQ_SPORT1_RX+1, | |
541 | .flags = IORESOURCE_IRQ, | |
542 | }, | |
543 | { | |
544 | .start = IRQ_SPORT1_ERROR, | |
545 | .end = IRQ_SPORT1_ERROR, | |
546 | .flags = IORESOURCE_IRQ, | |
547 | }, | |
548 | }; | |
549 | ||
a8b19886 | 550 | static unsigned short bfin_sport1_peripherals[] = { |
5aff1642 | 551 | P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, |
e54b6730 | 552 | P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 |
5aff1642 HK |
553 | }; |
554 | ||
555 | static struct platform_device bfin_sport1_uart_device = { | |
556 | .name = "bfin-sport-uart", | |
557 | .id = 1, | |
558 | .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), | |
559 | .resource = bfin_sport1_uart_resources, | |
560 | .dev = { | |
561 | .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ | |
562 | }, | |
563 | }; | |
564 | #endif | |
565 | #endif | |
566 | ||
c4a2c58d | 567 | #if IS_ENABLED(CONFIG_KEYBOARD_GPIO) |
5aff1642 HK |
568 | #include <linux/input.h> |
569 | #include <linux/gpio_keys.h> | |
570 | ||
571 | static struct gpio_keys_button bfin_gpio_keys_table[] = { | |
572 | {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"}, | |
573 | {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"}, | |
574 | }; | |
575 | ||
576 | static struct gpio_keys_platform_data bfin_gpio_keys_data = { | |
577 | .buttons = bfin_gpio_keys_table, | |
578 | .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), | |
579 | }; | |
580 | ||
581 | static struct platform_device bfin_device_gpiokeys = { | |
582 | .name = "gpio-keys", | |
583 | .dev = { | |
584 | .platform_data = &bfin_gpio_keys_data, | |
585 | }, | |
586 | }; | |
587 | #endif | |
588 | ||
c4a2c58d | 589 | #if IS_ENABLED(CONFIG_SDH_BFIN) |
5aff1642 HK |
590 | |
591 | static struct bfin_sd_host bfin_sdh_data = { | |
592 | .dma_chan = CH_RSI, | |
593 | .irq_int0 = IRQ_RSI_INT0, | |
594 | .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0}, | |
595 | }; | |
596 | ||
597 | static struct platform_device bf51x_sdh_device = { | |
598 | .name = "bfin-sdh", | |
599 | .id = 0, | |
600 | .dev = { | |
601 | .platform_data = &bfin_sdh_data, | |
602 | }, | |
603 | }; | |
604 | #endif | |
605 | ||
606 | static const unsigned int cclk_vlev_datasheet[] = | |
607 | { | |
608 | VRPAIR(VLEV_100, 400000000), | |
609 | VRPAIR(VLEV_105, 426000000), | |
610 | VRPAIR(VLEV_110, 500000000), | |
611 | VRPAIR(VLEV_115, 533000000), | |
612 | VRPAIR(VLEV_120, 600000000), | |
613 | }; | |
614 | ||
615 | static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { | |
616 | .tuple_tab = cclk_vlev_datasheet, | |
617 | .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), | |
618 | .vr_settling_time = 25 /* us */, | |
619 | }; | |
620 | ||
621 | static struct platform_device bfin_dpmc = { | |
622 | .name = "bfin dpmc", | |
623 | .dev = { | |
624 | .platform_data = &bfin_dmpc_vreg_data, | |
625 | }, | |
626 | }; | |
627 | ||
628 | static struct platform_device *tcm_devices[] __initdata = { | |
629 | ||
630 | &bfin_dpmc, | |
631 | ||
c4a2c58d | 632 | #if IS_ENABLED(CONFIG_RTC_DRV_BFIN) |
5aff1642 HK |
633 | &rtc_device, |
634 | #endif | |
635 | ||
c4a2c58d | 636 | #if IS_ENABLED(CONFIG_BFIN_MAC) |
5aff1642 HK |
637 | &bfin_mii_bus, |
638 | &bfin_mac_device, | |
639 | #endif | |
640 | ||
c4a2c58d | 641 | #if IS_ENABLED(CONFIG_SPI_BFIN5XX) |
5aff1642 HK |
642 | &bfin_spi0_device, |
643 | &bfin_spi1_device, | |
644 | #endif | |
645 | ||
c4a2c58d | 646 | #if IS_ENABLED(CONFIG_SERIAL_BFIN) |
5aff1642 HK |
647 | #ifdef CONFIG_SERIAL_BFIN_UART0 |
648 | &bfin_uart0_device, | |
649 | #endif | |
650 | #ifdef CONFIG_SERIAL_BFIN_UART1 | |
651 | &bfin_uart1_device, | |
652 | #endif | |
653 | #endif | |
654 | ||
c4a2c58d | 655 | #if IS_ENABLED(CONFIG_BFIN_SIR) |
5aff1642 HK |
656 | #ifdef CONFIG_BFIN_SIR0 |
657 | &bfin_sir0_device, | |
658 | #endif | |
659 | #ifdef CONFIG_BFIN_SIR1 | |
660 | &bfin_sir1_device, | |
661 | #endif | |
662 | #endif | |
663 | ||
c4a2c58d | 664 | #if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) |
5aff1642 HK |
665 | &i2c_bfin_twi_device, |
666 | #endif | |
667 | ||
c4a2c58d | 668 | #if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) |
5aff1642 HK |
669 | #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART |
670 | &bfin_sport0_uart_device, | |
671 | #endif | |
672 | #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART | |
673 | &bfin_sport1_uart_device, | |
674 | #endif | |
675 | #endif | |
676 | ||
c4a2c58d | 677 | #if IS_ENABLED(CONFIG_KEYBOARD_GPIO) |
5aff1642 HK |
678 | &bfin_device_gpiokeys, |
679 | #endif | |
680 | ||
c4a2c58d | 681 | #if IS_ENABLED(CONFIG_SDH_BFIN) |
5aff1642 HK |
682 | &bf51x_sdh_device, |
683 | #endif | |
684 | ||
c4a2c58d | 685 | #if IS_ENABLED(CONFIG_MTD_PHYSMAP) |
5aff1642 HK |
686 | &tcm_flash_device, |
687 | #endif | |
688 | }; | |
689 | ||
690 | static int __init tcm_init(void) | |
691 | { | |
692 | printk(KERN_INFO "%s(): registering device resources\n", __func__); | |
693 | i2c_register_board_info(0, bfin_i2c_board_info, | |
694 | ARRAY_SIZE(bfin_i2c_board_info)); | |
695 | platform_add_devices(tcm_devices, ARRAY_SIZE(tcm_devices)); | |
696 | spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); | |
697 | return 0; | |
698 | } | |
699 | ||
700 | arch_initcall(tcm_init); | |
701 | ||
702 | static struct platform_device *tcm_early_devices[] __initdata = { | |
703 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) | |
704 | #ifdef CONFIG_SERIAL_BFIN_UART0 | |
705 | &bfin_uart0_device, | |
706 | #endif | |
707 | #ifdef CONFIG_SERIAL_BFIN_UART1 | |
708 | &bfin_uart1_device, | |
709 | #endif | |
710 | #endif | |
711 | ||
712 | #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) | |
713 | #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART | |
714 | &bfin_sport0_uart_device, | |
715 | #endif | |
716 | #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART | |
717 | &bfin_sport1_uart_device, | |
718 | #endif | |
719 | #endif | |
720 | }; | |
721 | ||
722 | void __init native_machine_early_platform_add_devices(void) | |
723 | { | |
724 | printk(KERN_INFO "register early platform devices\n"); | |
725 | early_platform_add_devices(tcm_early_devices, | |
726 | ARRAY_SIZE(tcm_early_devices)); | |
727 | } | |
728 | ||
729 | void native_machine_restart(char *cmd) | |
730 | { | |
731 | /* workaround reboot hang when booting from SPI */ | |
732 | if ((bfin_read_SYSCR() & 0x7) == 0x3) | |
733 | bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); | |
734 | } | |
735 | ||
fa63c6da | 736 | int bfin_get_ether_addr(char *addr) |
5aff1642 | 737 | { |
fa63c6da | 738 | return 1; |
5aff1642 HK |
739 | } |
740 | EXPORT_SYMBOL(bfin_get_ether_addr); |