[mirror_ubuntu-zesty-kernel.git] / arch / blackfin / mach-bf518 / include / mach / defBF514.h

/*
 * Copyright 2008-2009 Analog Devices Inc.
 *
 * Licensed under the ADI BSD license or the GPL-2 (or later)
 */

#ifndef _DEF_BF514_H
#define _DEF_BF514_H

/* Include all Core registers and bit definitions */
#include <asm/def_LPBlackfin.h>

/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */

/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
#include "defBF51x_base.h"

/* The following are the #defines needed by ADSP-BF514 that are not in the common header */

/* SDH Registers */

#define SDH_PWR_CTL                    0xFFC03900 /* SDH Power Control */
#define SDH_CLK_CTL                    0xFFC03904 /* SDH Clock Control */
#define SDH_ARGUMENT                   0xFFC03908 /* SDH Argument */
#define SDH_COMMAND                    0xFFC0390C /* SDH Command */
#define SDH_RESP_CMD                   0xFFC03910 /* SDH Response Command */
#define SDH_RESPONSE0                  0xFFC03914 /* SDH Response0 */
#define SDH_RESPONSE1                  0xFFC03918 /* SDH Response1 */
#define SDH_RESPONSE2                  0xFFC0391C /* SDH Response2 */
#define SDH_RESPONSE3                  0xFFC03920 /* SDH Response3 */
#define SDH_DATA_TIMER                 0xFFC03924 /* SDH Data Timer */
#define SDH_DATA_LGTH                  0xFFC03928 /* SDH Data Length */
#define SDH_DATA_CTL                   0xFFC0392C /* SDH Data Control */
#define SDH_DATA_CNT                   0xFFC03930 /* SDH Data Counter */
#define SDH_STATUS                     0xFFC03934 /* SDH Status */
#define SDH_STATUS_CLR                 0xFFC03938 /* SDH Status Clear */
#define SDH_MASK0                      0xFFC0393C /* SDH Interrupt0 Mask */
#define SDH_MASK1                      0xFFC03940 /* SDH Interrupt1 Mask */
#define SDH_FIFO_CNT                   0xFFC03948 /* SDH FIFO Counter */
#define SDH_FIFO                       0xFFC03980 /* SDH Data FIFO */
#define SDH_E_STATUS                   0xFFC039C0 /* SDH Exception Status */
#define SDH_E_MASK                     0xFFC039C4 /* SDH Exception Mask */
#define SDH_CFG                        0xFFC039C8 /* SDH Configuration */
#define SDH_RD_WAIT_EN                 0xFFC039CC /* SDH Read Wait Enable */
#define SDH_PID0                       0xFFC039D0 /* SDH Peripheral Identification0 */
#define SDH_PID1                       0xFFC039D4 /* SDH Peripheral Identification1 */
#define SDH_PID2                       0xFFC039D8 /* SDH Peripheral Identification2 */
#define SDH_PID3                       0xFFC039DC /* SDH Peripheral Identification3 */
#define SDH_PID4                       0xFFC039E0 /* SDH Peripheral Identification4 */
#define SDH_PID5                       0xFFC039E4 /* SDH Peripheral Identification5 */
#define SDH_PID6                       0xFFC039E8 /* SDH Peripheral Identification6 */
#define SDH_PID7                       0xFFC039EC /* SDH Peripheral Identification7 */

/* Removable Storage Interface Registers */

#define RSI_PWR_CONTROL                0xFFC03800 /* RSI Power Control Register */
#define RSI_CLK_CONTROL                0xFFC03804 /* RSI Clock Control Register */
#define RSI_ARGUMENT                   0xFFC03808 /* RSI Argument Register */
#define RSI_COMMAND                    0xFFC0380C /* RSI Command Register */
#define RSI_RESP_CMD                   0xFFC03810 /* RSI Response Command Register */
#define RSI_RESPONSE0                  0xFFC03814 /* RSI Response Register */
#define RSI_RESPONSE1                  0xFFC03818 /* RSI Response Register */
#define RSI_RESPONSE2                  0xFFC0381C /* RSI Response Register */
#define RSI_RESPONSE3                  0xFFC03820 /* RSI Response Register */
#define RSI_DATA_TIMER                 0xFFC03824 /* RSI Data Timer Register */
#define RSI_DATA_LGTH                  0xFFC03828 /* RSI Data Length Register */
#define RSI_DATA_CONTROL               0xFFC0382C /* RSI Data Control Register */
#define RSI_DATA_CNT                   0xFFC03830 /* RSI Data Counter Register */
#define RSI_STATUS                     0xFFC03834 /* RSI Status Register */
#define RSI_STATUSCL                   0xFFC03838 /* RSI Status Clear Register */
#define RSI_MASK0                      0xFFC0383C /* RSI Interrupt 0 Mask Register */
#define RSI_MASK1                      0xFFC03840 /* RSI Interrupt 1 Mask Register */
#define RSI_FIFO_CNT                   0xFFC03848 /* RSI FIFO Counter Register */
#define RSI_CEATA_CONTROL              0xFFC0384C /* RSI CEATA Register */
#define RSI_FIFO                       0xFFC03880 /* RSI Data FIFO Register */
#define RSI_ESTAT                      0xFFC038C0 /* RSI Exception Status Register */
#define RSI_EMASK                      0xFFC038C4 /* RSI Exception Mask Register */
#define RSI_CONFIG                     0xFFC038C8 /* RSI Configuration Register */
#define RSI_RD_WAIT_EN                 0xFFC038CC /* RSI Read Wait Enable Register */
#define RSI_PID0                       0xFFC03FE0 /* RSI Peripheral ID Register 0 */
#define RSI_PID1                       0xFFC03FE4 /* RSI Peripheral ID Register 1 */
#define RSI_PID2                       0xFFC03FE8 /* RSI Peripheral ID Register 2 */
#define RSI_PID3                       0xFFC03FEC /* RSI Peripheral ID Register 3 */
#define RSI_PID4                       0xFFC03FF0 /* RSI Peripheral ID Register 4 */
#define RSI_PID5                       0xFFC03FF4 /* RSI Peripheral ID Register 5 */
#define RSI_PID6                       0xFFC03FF8 /* RSI Peripheral ID Register 6 */
#define RSI_PID7                       0xFFC03FFC /* RSI Peripheral ID Register 7 */

/* ********************************************************** */
/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
/*     and MULTI BIT READ MACROS                              */
/* ********************************************************** */

/* Bit masks for SDH_COMMAND */

#define                   CMD_IDX  0x3f       /* Command Index */
#define                   CMD_RSP  0x40       /* Response */
#define                 CMD_L_RSP  0x80       /* Long Response */
#define                 CMD_INT_E  0x100      /* Command Interrupt */
#define                CMD_PEND_E  0x200      /* Command Pending */
#define                     CMD_E  0x400      /* Command Enable */

/* Bit masks for SDH_PWR_CTL */

#define                    PWR_ON  0x3        /* Power On */
#if 0
#define                       TBD  0x3c       /* TBD */
#endif
#define                 SD_CMD_OD  0x40       /* Open Drain Output */
#define                   ROD_CTL  0x80       /* Rod Control */

/* Bit masks for SDH_CLK_CTL */

#define                    CLKDIV  0xff       /* MC_CLK Divisor */
#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
#define                  PWR_SV_E  0x200      /* Power Save Enable */
#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */

/* Bit masks for SDH_RESP_CMD */

#define                  RESP_CMD  0x3f       /* Response Command */

/* Bit masks for SDH_DATA_CTL */

#define                     DTX_E  0x1        /* Data Transfer Enable */
#define                   DTX_DIR  0x2        /* Data Transfer Direction */
#define                  DTX_MODE  0x4        /* Data Transfer Mode */
#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */

/* Bit masks for SDH_STATUS */

#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
#define               CMD_TIME_OUT  0x4        /* CMD Time Out */
#define               DAT_TIME_OUT  0x8        /* Data Time Out */
#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
#define                RX_OVERRUN  0x20       /* Receive Overrun */
#define              CMD_RESP_END  0x40       /* CMD Response End */
#define                  CMD_SENT  0x80       /* CMD Sent */
#define                   DAT_END  0x100      /* Data End */
#define             START_BIT_ERR  0x200      /* Start Bit Error */
#define               DAT_BLK_END  0x400      /* Data Block End */
#define                   CMD_ACT  0x800      /* CMD Active */
#define                    TX_ACT  0x1000     /* Transmit Active */
#define                    RX_ACT  0x2000     /* Receive Active */
#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */

/* Bit masks for SDH_STATUS_CLR */

#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
#define              DAT_END_STAT  0x100      /* Data End Status */
#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */

/* Bit masks for SDH_MASK0 */

#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
#define              DAT_END_MASK  0x100      /* Data End Mask */
#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */

/* Bit masks for SDH_FIFO_CNT */

#define                FIFO_COUNT  0x7fff     /* FIFO Count */

/* Bit masks for SDH_E_STATUS */

#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
#define               SD_CARD_DET  0x10       /* SD Card Detect */

/* Bit masks for SDH_E_MASK */

#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
#define                   SCD_MSK  0x40       /* Mask Card Detect */

/* Bit masks for SDH_CFG */

#define                   CLKS_EN  0x1        /* Clocks Enable */
#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
#define                       MWE  0x8        /* Moving Window Enable */
#define                    SD_RST  0x10       /* SDMMC Reset */
#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */

/* Bit masks for SDH_RD_WAIT_EN */

#define                       RWR  0x1        /* Read Wait Request */

#endif /* _DEF_BF514_H */
Commit	Line	Data
2f6f4bcd	1	/*
96f1050d	2	* Copyright 2008-2009 Analog Devices Inc.
2f6f4bcd	3	*
96f1050d	4	* Licensed under the ADI BSD license or the GPL-2 (or later)
2f6f4bcd BW	5	*/
	6
	7	#ifndef _DEF_BF514_H
	8	#define _DEF_BF514_H
	9
	10	/* Include all Core registers and bit definitions */
	11	#include <asm/def_LPBlackfin.h>
	12
	13	/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */
	14
	15	/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
	16	#include "defBF51x_base.h"
	17
	18	/* The following are the #defines needed by ADSP-BF514 that are not in the common header */
	19
	20	/* SDH Registers */
	21
	22	#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */
	23	#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */
	24	#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */
	25	#define SDH_COMMAND 0xFFC0390C /* SDH Command */
	26	#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */
	27	#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */
	28	#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */
	29	#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */
	30	#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */
	31	#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */
	32	#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */
	33	#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */
	34	#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */
	35	#define SDH_STATUS 0xFFC03934 /* SDH Status */
	36	#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */
	37	#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */
	38	#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */
	39	#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */
	40	#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */
	41	#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */
	42	#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */
	43	#define SDH_CFG 0xFFC039C8 /* SDH Configuration */
	44	#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */
	45	#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */
	46	#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */
	47	#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */
	48	#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */
	49	#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */
	50	#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */
	51	#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */
	52	#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */
	53
	54	/* Removable Storage Interface Registers */
	55
	56	#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
	57	#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
	58	#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
	59	#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
	60	#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
	61	#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
	62	#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
	63	#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
	64	#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
	65	#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
	66	#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
	67	#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
	68	#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
69	#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
70	#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
71	#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
72	#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
73	#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
74	#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
75	#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
76	#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
77	#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
78	#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
79	#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
80	#define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */
81	#define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */
82	#define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */
83	#define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */
84	#define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */
85	#define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */
86	#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */
87	#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */
88
abd750a0 CC	89	/* ********************************************************** */
	90	/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
	91	/* and MULTI BIT READ MACROS */
	92	/* ********************************************************** */
	93
	94	/* Bit masks for SDH_COMMAND */
	95
	96	#define CMD_IDX 0x3f /* Command Index */
	97	#define CMD_RSP 0x40 /* Response */
	98	#define CMD_L_RSP 0x80 /* Long Response */
	99	#define CMD_INT_E 0x100 /* Command Interrupt */
	100	#define CMD_PEND_E 0x200 /* Command Pending */
	101	#define CMD_E 0x400 /* Command Enable */
	102
	103	/* Bit masks for SDH_PWR_CTL */
	104
	105	#define PWR_ON 0x3 /* Power On */
	106	#if 0
	107	#define TBD 0x3c /* TBD */
	108	#endif
	109	#define SD_CMD_OD 0x40 /* Open Drain Output */
	110	#define ROD_CTL 0x80 /* Rod Control */
	111
	112	/* Bit masks for SDH_CLK_CTL */
	113
	114	#define CLKDIV 0xff /* MC_CLK Divisor */
	115	#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
	116	#define PWR_SV_E 0x200 /* Power Save Enable */
	117	#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
	118	#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
	119
	120	/* Bit masks for SDH_RESP_CMD */
	121
	122	#define RESP_CMD 0x3f /* Response Command */
	123
	124	/* Bit masks for SDH_DATA_CTL */
	125
	126	#define DTX_E 0x1 /* Data Transfer Enable */
	127	#define DTX_DIR 0x2 /* Data Transfer Direction */
	128	#define DTX_MODE 0x4 /* Data Transfer Mode */
	129	#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
	130	#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
	131
	132	/* Bit masks for SDH_STATUS */
	133
	134	#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
	135	#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
	136	#define CMD_TIME_OUT 0x4 /* CMD Time Out */
	137	#define DAT_TIME_OUT 0x8 /* Data Time Out */
	138	#define TX_UNDERRUN 0x10 /* Transmit Underrun */
	139	#define RX_OVERRUN 0x20 /* Receive Overrun */
	140	#define CMD_RESP_END 0x40 /* CMD Response End */
	141	#define CMD_SENT 0x80 /* CMD Sent */
	142	#define DAT_END 0x100 /* Data End */
	143	#define START_BIT_ERR 0x200 /* Start Bit Error */
	144	#define DAT_BLK_END 0x400 /* Data Block End */
	145	#define CMD_ACT 0x800 /* CMD Active */
	146	#define TX_ACT 0x1000 /* Transmit Active */
	147	#define RX_ACT 0x2000 /* Receive Active */
	148	#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
	149	#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
	150	#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
	151	#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
	152	#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
153	#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
154	#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
155	#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
156
157	/* Bit masks for SDH_STATUS_CLR */
158
159	#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
160	#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
161	#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
162	#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
163	#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
164	#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
165	#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
166	#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
167	#define DAT_END_STAT 0x100 /* Data End Status */
168	#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
169	#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
170
171	/* Bit masks for SDH_MASK0 */
172
173	#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
174	#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
175	#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
176	#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
177	#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
178	#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
179	#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
180	#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
181	#define DAT_END_MASK 0x100 /* Data End Mask */
182	#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
183	#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
184	#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
185	#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
186	#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
187	#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
188	#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
189	#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
190	#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
191	#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
192	#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
193	#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
194	#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
195
196	/* Bit masks for SDH_FIFO_CNT */
197
198	#define FIFO_COUNT 0x7fff /* FIFO Count */
199
200	/* Bit masks for SDH_E_STATUS */
201
202	#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
203	#define SD_CARD_DET 0x10 /* SD Card Detect */
204
205	/* Bit masks for SDH_E_MASK */
206
207	#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
208	#define SCD_MSK 0x40 /* Mask Card Detect */
209
210	/* Bit masks for SDH_CFG */
211
212	#define CLKS_EN 0x1 /* Clocks Enable */
213	#define SD4E 0x4 /* SDIO 4-Bit Enable */
214	#define MWE 0x8 /* Moving Window Enable */
215	#define SD_RST 0x10 /* SDMMC Reset */
216	#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
217	#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
218	#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
219
220	/* Bit masks for SDH_RD_WAIT_EN */
221
222	#define RWR 0x1 /* Read Wait Request */
223
2f6f4bcd	224	#endif /* _DEF_BF514_H */