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1394f032 | 1 | /* |
287050fe MF |
2 | * File: include/asm-blackfin/mach-bf533/anomaly.h |
3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
1394f032 | 4 | * |
c18e99cf | 5 | * Copyright (C) 2004-2009 Analog Devices Inc. |
287050fe | 6 | * Licensed under the GPL-2 or later. |
1394f032 BW |
7 | */ |
8 | ||
a413647b | 9 | /* This file should be up to date with: |
6651ece9 | 10 | * - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List |
1394f032 BW |
11 | */ |
12 | ||
13 | #ifndef _MACH_ANOMALY_H_ | |
14 | #define _MACH_ANOMALY_H_ | |
15 | ||
16 | /* We do not support 0.1 or 0.2 silicon - sorry */ | |
1aafd909 | 17 | #if __SILICON_REVISION__ < 3 |
7cc1c4b2 | 18 | # error will not work on BF533 silicon version 0.0, 0.1, or 0.2 |
1394f032 BW |
19 | #endif |
20 | ||
1aafd909 MF |
21 | #if defined(__ADSPBF531__) |
22 | # define ANOMALY_BF531 1 | |
23 | #else | |
24 | # define ANOMALY_BF531 0 | |
25 | #endif | |
26 | #if defined(__ADSPBF532__) | |
27 | # define ANOMALY_BF532 1 | |
28 | #else | |
29 | # define ANOMALY_BF532 0 | |
30 | #endif | |
31 | #if defined(__ADSPBF533__) | |
32 | # define ANOMALY_BF533 1 | |
33 | #else | |
34 | # define ANOMALY_BF533 0 | |
35 | #endif | |
1394f032 | 36 | |
a200ad22 | 37 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ |
1aafd909 MF |
38 | #define ANOMALY_05000074 (1) |
39 | /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ | |
40 | #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) | |
41 | /* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */ | |
a413647b | 42 | #define ANOMALY_05000105 (__SILICON_REVISION__ > 2) |
1aafd909 MF |
43 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ |
44 | #define ANOMALY_05000119 (1) | |
45 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | |
46 | #define ANOMALY_05000122 (1) | |
47 | /* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */ | |
48 | #define ANOMALY_05000158 (__SILICON_REVISION__ < 5) | |
a200ad22 | 49 | /* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ |
1aafd909 | 50 | #define ANOMALY_05000166 (1) |
a413647b | 51 | /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ |
1aafd909 MF |
52 | #define ANOMALY_05000167 (1) |
53 | /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ | |
54 | #define ANOMALY_05000179 (__SILICON_REVISION__ < 5) | |
55 | /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ | |
56 | #define ANOMALY_05000180 (1) | |
57 | /* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ | |
58 | #define ANOMALY_05000183 (__SILICON_REVISION__ < 4) | |
a200ad22 | 59 | /* False Protection Exceptions when Speculative Fetch Is Cancelled */ |
1aafd909 MF |
60 | #define ANOMALY_05000189 (__SILICON_REVISION__ < 4) |
61 | /* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ | |
62 | #define ANOMALY_05000193 (__SILICON_REVISION__ < 4) | |
63 | /* Restarting SPORT in Specific Modes May Cause Data Corruption */ | |
64 | #define ANOMALY_05000194 (__SILICON_REVISION__ < 4) | |
a200ad22 | 65 | /* Failing MMR Accesses when Preceding Memory Read Stalls */ |
1aafd909 MF |
66 | #define ANOMALY_05000198 (__SILICON_REVISION__ < 5) |
67 | /* Current DMA Address Shows Wrong Value During Carry Fix */ | |
68 | #define ANOMALY_05000199 (__SILICON_REVISION__ < 4) | |
69 | /* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */ | |
a413647b | 70 | #define ANOMALY_05000200 (__SILICON_REVISION__ == 3 || __SILICON_REVISION__ == 4) |
1aafd909 | 71 | /* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */ |
a413647b | 72 | #define ANOMALY_05000201 (__SILICON_REVISION__ == 3) |
1aafd909 MF |
73 | /* Possible Infinite Stall with Specific Dual-DAG Situation */ |
74 | #define ANOMALY_05000202 (__SILICON_REVISION__ < 5) | |
75 | /* Specific Sequence That Can Cause DMA Error or DMA Stopping */ | |
76 | #define ANOMALY_05000203 (__SILICON_REVISION__ < 4) | |
a200ad22 | 77 | /* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */ |
1aafd909 MF |
78 | #define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533) |
79 | /* Recovery from "Brown-Out" Condition */ | |
80 | #define ANOMALY_05000207 (__SILICON_REVISION__ < 4) | |
81 | /* VSTAT Status Bit in PLL_STAT Register Is Not Functional */ | |
82 | #define ANOMALY_05000208 (1) | |
83 | /* Speed Path in Computational Unit Affects Certain Instructions */ | |
84 | #define ANOMALY_05000209 (__SILICON_REVISION__ < 4) | |
85 | /* UART TX Interrupt Masked Erroneously */ | |
86 | #define ANOMALY_05000215 (__SILICON_REVISION__ < 5) | |
87 | /* NMI Event at Boot Time Results in Unpredictable State */ | |
88 | #define ANOMALY_05000219 (1) | |
89 | /* Incorrect Pulse-Width of UART Start Bit */ | |
90 | #define ANOMALY_05000225 (__SILICON_REVISION__ < 5) | |
91 | /* Scratchpad Memory Bank Reads May Return Incorrect Data */ | |
92 | #define ANOMALY_05000227 (__SILICON_REVISION__ < 5) | |
93 | /* SPI Slave Boot Mode Modifies Registers from Reset Value */ | |
94 | #define ANOMALY_05000229 (1) | |
95 | /* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */ | |
96 | #define ANOMALY_05000230 (__SILICON_REVISION__ < 5) | |
97 | /* UART STB Bit Incorrectly Affects Receiver Setting */ | |
98 | #define ANOMALY_05000231 (__SILICON_REVISION__ < 5) | |
99 | /* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ | |
4e8086d6 | 100 | #define ANOMALY_05000233 (__SILICON_REVISION__ < 6) |
1aafd909 MF |
101 | /* Incorrect Revision Number in DSPID Register */ |
102 | #define ANOMALY_05000234 (__SILICON_REVISION__ == 4) | |
103 | /* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ | |
4e8086d6 | 104 | #define ANOMALY_05000242 (__SILICON_REVISION__ < 5) |
1aafd909 MF |
105 | /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ |
106 | #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) | |
a413647b | 107 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ |
1aafd909 | 108 | #define ANOMALY_05000245 (1) |
a200ad22 | 109 | /* Data CPLBs Should Prevent False Hardware Errors */ |
1aafd909 MF |
110 | #define ANOMALY_05000246 (__SILICON_REVISION__ < 5) |
111 | /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ | |
112 | #define ANOMALY_05000250 (__SILICON_REVISION__ == 4) | |
113 | /* Maximum External Clock Speed for Timers */ | |
114 | #define ANOMALY_05000253 (__SILICON_REVISION__ < 5) | |
115 | /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ | |
116 | #define ANOMALY_05000254 (__SILICON_REVISION__ > 4) | |
117 | /* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ | |
118 | #define ANOMALY_05000255 (__SILICON_REVISION__ < 5) | |
119 | /* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ | |
120 | #define ANOMALY_05000257 (__SILICON_REVISION__ < 5) | |
121 | /* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ | |
122 | #define ANOMALY_05000258 (__SILICON_REVISION__ < 5) | |
123 | /* ICPLB_STATUS MMR Register May Be Corrupted */ | |
124 | #define ANOMALY_05000260 (__SILICON_REVISION__ < 5) | |
125 | /* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ | |
126 | #define ANOMALY_05000261 (__SILICON_REVISION__ < 5) | |
127 | /* Stores To Data Cache May Be Lost */ | |
128 | #define ANOMALY_05000262 (__SILICON_REVISION__ < 5) | |
129 | /* Hardware Loop Corrupted When Taking an ICPLB Exception */ | |
130 | #define ANOMALY_05000263 (__SILICON_REVISION__ < 5) | |
131 | /* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ | |
132 | #define ANOMALY_05000264 (__SILICON_REVISION__ < 5) | |
133 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ | |
4e8086d6 | 134 | #define ANOMALY_05000265 (1) |
1aafd909 MF |
135 | /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ |
136 | #define ANOMALY_05000269 (__SILICON_REVISION__ < 5) | |
137 | /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ | |
138 | #define ANOMALY_05000270 (__SILICON_REVISION__ < 5) | |
139 | /* Spontaneous Reset of Internal Voltage Regulator */ | |
a413647b | 140 | #define ANOMALY_05000271 (__SILICON_REVISION__ == 3) |
1aafd909 MF |
141 | /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ |
142 | #define ANOMALY_05000272 (1) | |
143 | /* Writes to Synchronous SDRAM Memory May Be Lost */ | |
4e8086d6 | 144 | #define ANOMALY_05000273 (__SILICON_REVISION__ < 6) |
1aafd909 MF |
145 | /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ |
146 | #define ANOMALY_05000276 (1) | |
147 | /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ | |
4e8086d6 | 148 | #define ANOMALY_05000277 (__SILICON_REVISION__ < 6) |
1aafd909 | 149 | /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ |
4e8086d6 | 150 | #define ANOMALY_05000278 (__SILICON_REVISION__ < 6) |
a200ad22 | 151 | /* False Hardware Error Exception when ISR Context Is Not Restored */ |
4e8086d6 | 152 | #define ANOMALY_05000281 (__SILICON_REVISION__ < 6) |
1aafd909 | 153 | /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ |
4e8086d6 | 154 | #define ANOMALY_05000282 (__SILICON_REVISION__ < 6) |
a200ad22 | 155 | /* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ |
4e8086d6 | 156 | #define ANOMALY_05000283 (__SILICON_REVISION__ < 6) |
1aafd909 | 157 | /* SPORTs May Receive Bad Data If FIFOs Fill Up */ |
4e8086d6 | 158 | #define ANOMALY_05000288 (__SILICON_REVISION__ < 6) |
1aafd909 | 159 | /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ |
4e8086d6 | 160 | #define ANOMALY_05000301 (__SILICON_REVISION__ < 6) |
a200ad22 | 161 | /* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */ |
1aafd909 | 162 | #define ANOMALY_05000302 (__SILICON_REVISION__ < 5) |
c18e99cf | 163 | /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ |
1aafd909 | 164 | #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) |
a200ad22 | 165 | /* ALT_TIMING Bit in PPI_CONTROL Register Is Not Functional */ |
1aafd909 | 166 | #define ANOMALY_05000306 (__SILICON_REVISION__ < 5) |
4e8086d6 | 167 | /* SCKELOW Bit Does Not Maintain State Through Hibernate */ |
a413647b | 168 | #define ANOMALY_05000307 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ |
1aafd909 MF |
169 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ |
170 | #define ANOMALY_05000310 (1) | |
171 | /* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ | |
4e8086d6 | 172 | #define ANOMALY_05000311 (__SILICON_REVISION__ < 6) |
a200ad22 | 173 | /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ |
4e8086d6 | 174 | #define ANOMALY_05000312 (__SILICON_REVISION__ < 6) |
a413647b | 175 | /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ |
4e8086d6 | 176 | #define ANOMALY_05000313 (__SILICON_REVISION__ < 6) |
a200ad22 | 177 | /* Killed System MMR Write Completes Erroneously on Next System MMR Access */ |
4e8086d6 | 178 | #define ANOMALY_05000315 (__SILICON_REVISION__ < 6) |
1aafd909 | 179 | /* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ |
4e8086d6 | 180 | #define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6) |
a70ce072 | 181 | /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ |
4e8086d6 | 182 | #define ANOMALY_05000357 (__SILICON_REVISION__ < 6) |
a70ce072 MF |
183 | /* UART Break Signal Issues */ |
184 | #define ANOMALY_05000363 (__SILICON_REVISION__ < 5) | |
185 | /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ | |
186 | #define ANOMALY_05000366 (1) | |
187 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ | |
4e8086d6 | 188 | #define ANOMALY_05000371 (__SILICON_REVISION__ < 6) |
a70ce072 | 189 | /* PPI Does Not Start Properly In Specific Mode */ |
4e8086d6 | 190 | #define ANOMALY_05000400 (__SILICON_REVISION__ == 5) |
a70ce072 | 191 | /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ |
4e8086d6 | 192 | #define ANOMALY_05000402 (__SILICON_REVISION__ == 5) |
a70ce072 MF |
193 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ |
194 | #define ANOMALY_05000403 (1) | |
4e8086d6 MF |
195 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ |
196 | #define ANOMALY_05000416 (1) | |
6651ece9 MF |
197 | /* Multichannel SPORT Channel Misalignment Under Specific Configuration */ |
198 | #define ANOMALY_05000425 (1) | |
199 | /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ | |
200 | #define ANOMALY_05000426 (1) | |
3529e041 MF |
201 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ |
202 | #define ANOMALY_05000443 (1) | |
a200ad22 | 203 | /* False Hardware Error when RETI Points to Invalid Memory */ |
a413647b | 204 | #define ANOMALY_05000461 (1) |
1394f032 | 205 | |
1aafd909 MF |
206 | /* These anomalies have been "phased" out of analog.com anomaly sheets and are |
207 | * here to show running on older silicon just isn't feasible. | |
208 | */ | |
1394f032 | 209 | |
a413647b MF |
210 | /* Internal voltage regulator can't be modified via register writes */ |
211 | #define ANOMALY_05000066 (__SILICON_REVISION__ < 2) | |
1aafd909 MF |
212 | /* Watchpoints (Hardware Breakpoints) are not supported */ |
213 | #define ANOMALY_05000067 (__SILICON_REVISION__ < 3) | |
a413647b MF |
214 | /* SDRAM PSSE bit cannot be set again after SDRAM Powerup */ |
215 | #define ANOMALY_05000070 (__SILICON_REVISION__ < 2) | |
216 | /* Writing FIO_DIR can corrupt a programmable flag's data */ | |
217 | #define ANOMALY_05000079 (__SILICON_REVISION__ < 2) | |
a200ad22 | 218 | /* Timer Auto-Baud Mode requires the UART clock to be enabled. */ |
a413647b MF |
219 | #define ANOMALY_05000086 (__SILICON_REVISION__ < 2) |
220 | /* Internal Clocking Modes on SPORT0 not supported */ | |
221 | #define ANOMALY_05000088 (__SILICON_REVISION__ < 2) | |
222 | /* Internal voltage regulator does not wake up from an RTC wakeup */ | |
223 | #define ANOMALY_05000092 (__SILICON_REVISION__ < 2) | |
a200ad22 | 224 | /* The IFLUSH Instruction Must Be Preceded by a CSYNC Instruction */ |
a413647b | 225 | #define ANOMALY_05000093 (__SILICON_REVISION__ < 2) |
a200ad22 | 226 | /* Vectoring to instruction that is being filled into the i-cache may cause erroneous behavior */ |
a413647b | 227 | #define ANOMALY_05000095 (__SILICON_REVISION__ < 2) |
a200ad22 | 228 | /* PREFETCH, FLUSH, and FLUSHINV Instructions Must Be Followed by a CSYNC Instruction */ |
a413647b MF |
229 | #define ANOMALY_05000096 (__SILICON_REVISION__ < 2) |
230 | /* Performance Monitor 0 and 1 are swapped when monitoring memory events */ | |
231 | #define ANOMALY_05000097 (__SILICON_REVISION__ < 2) | |
232 | /* 32-bit SPORT DMA will be word reversed */ | |
233 | #define ANOMALY_05000098 (__SILICON_REVISION__ < 2) | |
234 | /* Incorrect status in the UART_IIR register */ | |
235 | #define ANOMALY_05000100 (__SILICON_REVISION__ < 2) | |
236 | /* Reading X_MODIFY or Y_MODIFY while DMA channel is active */ | |
237 | #define ANOMALY_05000101 (__SILICON_REVISION__ < 2) | |
a200ad22 | 238 | /* Descriptor MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */ |
a413647b | 239 | #define ANOMALY_05000102 (__SILICON_REVISION__ < 2) |
a200ad22 | 240 | /* Incorrect Value Written to the Cycle Counters */ |
a413647b | 241 | #define ANOMALY_05000103 (__SILICON_REVISION__ < 2) |
a200ad22 | 242 | /* Stores to L1 Data Memory Incorrect when a Specific Sequence Is Followed */ |
a413647b MF |
243 | #define ANOMALY_05000104 (__SILICON_REVISION__ < 2) |
244 | /* Programmable Flag (PF3) functionality not supported in all PPI modes */ | |
245 | #define ANOMALY_05000106 (__SILICON_REVISION__ < 2) | |
246 | /* Data store can be lost when targeting a cache line fill */ | |
247 | #define ANOMALY_05000107 (__SILICON_REVISION__ < 2) | |
a200ad22 | 248 | /* Reserved Bits in SYSCFG Register Not Set at Power-On */ |
1aafd909 | 249 | #define ANOMALY_05000109 (__SILICON_REVISION__ < 3) |
a413647b MF |
250 | /* Infinite Core Stall */ |
251 | #define ANOMALY_05000114 (__SILICON_REVISION__ < 2) | |
a200ad22 | 252 | /* PPI_FSx may glitch when generated by the on chip Timers. */ |
a413647b | 253 | #define ANOMALY_05000115 (__SILICON_REVISION__ < 2) |
a200ad22 | 254 | /* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ |
1aafd909 | 255 | #define ANOMALY_05000116 (__SILICON_REVISION__ < 3) |
a413647b MF |
256 | /* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */ |
257 | #define ANOMALY_05000117 (__SILICON_REVISION__ < 2) | |
258 | /* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */ | |
259 | #define ANOMALY_05000118 (__SILICON_REVISION__ < 2) | |
a200ad22 | 260 | /* DTEST_COMMAND Initiated Memory Access May Be Incorrect If Data Cache or DMA Is Active */ |
1aafd909 MF |
261 | #define ANOMALY_05000123 (__SILICON_REVISION__ < 3) |
262 | /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ | |
263 | #define ANOMALY_05000124 (__SILICON_REVISION__ < 3) | |
a200ad22 | 264 | /* Erroneous Exception when Enabling Cache */ |
1aafd909 MF |
265 | #define ANOMALY_05000125 (__SILICON_REVISION__ < 3) |
266 | /* SPI clock polarity and phase bits incorrect during booting */ | |
267 | #define ANOMALY_05000126 (__SILICON_REVISION__ < 3) | |
a200ad22 | 268 | /* DMEM_CONTROL<12> Is Not Set on Reset */ |
1aafd909 MF |
269 | #define ANOMALY_05000137 (__SILICON_REVISION__ < 3) |
270 | /* SPI boot will not complete if there is a zero fill block in the loader file */ | |
a413647b | 271 | #define ANOMALY_05000138 (__SILICON_REVISION__ == 2) |
a200ad22 | 272 | /* TIMERx_CONFIG[5] must be set for PPI in GP output mode with internal Frame Syncs */ |
a413647b | 273 | #define ANOMALY_05000139 (__SILICON_REVISION__ < 2) |
1aafd909 MF |
274 | /* Allowing the SPORT RX FIFO to fill will cause an overflow */ |
275 | #define ANOMALY_05000140 (__SILICON_REVISION__ < 3) | |
a200ad22 | 276 | /* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ |
1aafd909 MF |
277 | #define ANOMALY_05000141 (__SILICON_REVISION__ < 3) |
278 | /* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ | |
279 | #define ANOMALY_05000142 (__SILICON_REVISION__ < 3) | |
280 | /* A read from external memory may return a wrong value with data cache enabled */ | |
281 | #define ANOMALY_05000143 (__SILICON_REVISION__ < 3) | |
282 | /* DMA and TESTSET conflict when both are accessing external memory */ | |
283 | #define ANOMALY_05000144 (__SILICON_REVISION__ < 3) | |
284 | /* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */ | |
285 | #define ANOMALY_05000145 (__SILICON_REVISION__ < 3) | |
286 | /* MDMA may lose the first few words of a descriptor chain */ | |
287 | #define ANOMALY_05000146 (__SILICON_REVISION__ < 3) | |
a413647b | 288 | /* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ |
1aafd909 | 289 | #define ANOMALY_05000147 (__SILICON_REVISION__ < 3) |
a200ad22 | 290 | /* When booting from 16-bit asynchronous memory, the upper 8 bits of each word must be 0x00 */ |
1aafd909 MF |
291 | #define ANOMALY_05000148 (__SILICON_REVISION__ < 3) |
292 | /* Frame Delay in SPORT Multichannel Mode */ | |
293 | #define ANOMALY_05000153 (__SILICON_REVISION__ < 3) | |
a413647b | 294 | /* SPORT TFS signal stays active in multichannel mode outside of valid channels */ |
1aafd909 MF |
295 | #define ANOMALY_05000154 (__SILICON_REVISION__ < 3) |
296 | /* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */ | |
297 | #define ANOMALY_05000155 (__SILICON_REVISION__ < 3) | |
a200ad22 | 298 | /* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ |
1aafd909 | 299 | #define ANOMALY_05000157 (__SILICON_REVISION__ < 3) |
a200ad22 | 300 | /* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ |
1aafd909 | 301 | #define ANOMALY_05000163 (__SILICON_REVISION__ < 3) |
a200ad22 | 302 | /* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */ |
1aafd909 | 303 | #define ANOMALY_05000168 (__SILICON_REVISION__ < 3) |
a200ad22 | 304 | /* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */ |
1aafd909 MF |
305 | #define ANOMALY_05000169 (__SILICON_REVISION__ < 3) |
306 | /* DMA vs Core accesses to external memory */ | |
307 | #define ANOMALY_05000173 (__SILICON_REVISION__ < 3) | |
308 | /* Cache Fill Buffer Data lost */ | |
309 | #define ANOMALY_05000174 (__SILICON_REVISION__ < 3) | |
310 | /* Overlapping Sequencer and Memory Stalls */ | |
311 | #define ANOMALY_05000175 (__SILICON_REVISION__ < 3) | |
a200ad22 | 312 | /* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */ |
1aafd909 | 313 | #define ANOMALY_05000176 (__SILICON_REVISION__ < 3) |
a200ad22 | 314 | /* Disabling the PPI Resets the PPI Configuration Registers */ |
1aafd909 | 315 | #define ANOMALY_05000181 (__SILICON_REVISION__ < 3) |
a200ad22 | 316 | /* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */ |
1aafd909 MF |
317 | #define ANOMALY_05000185 (__SILICON_REVISION__ < 3) |
318 | /* PPI does not invert the Driving PPICLK edge in Transmit Modes */ | |
319 | #define ANOMALY_05000191 (__SILICON_REVISION__ < 3) | |
a200ad22 | 320 | /* In PPI Transmit Modes with External Frame Syncs POLC bit must be set to 1 */ |
1aafd909 MF |
321 | #define ANOMALY_05000192 (__SILICON_REVISION__ < 3) |
322 | /* Internal Voltage Regulator may not start up */ | |
323 | #define ANOMALY_05000206 (__SILICON_REVISION__ < 3) | |
4bf3f3cb | 324 | |
1aafd909 | 325 | /* Anomalies that don't exist on this proc */ |
a413647b MF |
326 | #define ANOMALY_05000120 (0) |
327 | #define ANOMALY_05000149 (0) | |
328 | #define ANOMALY_05000171 (0) | |
a200ad22 | 329 | #define ANOMALY_05000182 (0) |
a413647b MF |
330 | #define ANOMALY_05000220 (0) |
331 | #define ANOMALY_05000248 (0) | |
1aafd909 | 332 | #define ANOMALY_05000266 (0) |
a413647b MF |
333 | #define ANOMALY_05000274 (0) |
334 | #define ANOMALY_05000287 (0) | |
2b39331a | 335 | #define ANOMALY_05000323 (0) |
4e8086d6 | 336 | #define ANOMALY_05000353 (1) |
a413647b | 337 | #define ANOMALY_05000362 (1) |
976119bc | 338 | #define ANOMALY_05000364 (0) |
ee554be9 | 339 | #define ANOMALY_05000380 (0) |
4e8086d6 | 340 | #define ANOMALY_05000386 (1) |
a413647b | 341 | #define ANOMALY_05000389 (0) |
6651ece9 | 342 | #define ANOMALY_05000412 (0) |
a413647b | 343 | #define ANOMALY_05000430 (0) |
6651ece9 | 344 | #define ANOMALY_05000432 (0) |
94b28211 | 345 | #define ANOMALY_05000435 (0) |
7dbc3f6e MF |
346 | #define ANOMALY_05000447 (0) |
347 | #define ANOMALY_05000448 (0) | |
a413647b MF |
348 | #define ANOMALY_05000456 (0) |
349 | #define ANOMALY_05000450 (0) | |
a200ad22 MF |
350 | #define ANOMALY_05000465 (0) |
351 | #define ANOMALY_05000467 (0) | |
4bf3f3cb | 352 | |
1394f032 | 353 | #endif |