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1394f032 BW |
1 | /* |
2 | * File: arch/blackfin/mach-bf537/boards/cm_bf537.c | |
3 | * Based on: arch/blackfin/mach-bf533/boards/ezkit.c | |
4 | * Author: Aidan Williams <aidan@nicta.com.au> | |
5 | * | |
6 | * Created: 2005 | |
7 | * Description: Board description file | |
8 | * | |
9 | * Modified: | |
10 | * Copyright 2005 National ICT Australia (NICTA) | |
11 | * Copyright 2004-2006 Analog Devices Inc. | |
12 | * | |
13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, see the file COPYING, or write | |
27 | * to the Free Software Foundation, Inc., | |
28 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
29 | */ | |
30 | ||
31 | #include <linux/device.h> | |
43f73fef | 32 | #include <linux/etherdevice.h> |
1394f032 BW |
33 | #include <linux/platform_device.h> |
34 | #include <linux/mtd/mtd.h> | |
35 | #include <linux/mtd/partitions.h> | |
8ea89497 | 36 | #include <linux/mtd/physmap.h> |
1394f032 BW |
37 | #include <linux/spi/spi.h> |
38 | #include <linux/spi/flash.h> | |
b964c592 | 39 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) |
f02bcec5 | 40 | #include <linux/usb/isp1362.h> |
b964c592 | 41 | #endif |
0a87e3e9 | 42 | #include <linux/ata_platform.h> |
1f83b8f1 | 43 | #include <linux/irq.h> |
c6c4d7bb | 44 | #include <asm/dma.h> |
1394f032 | 45 | #include <asm/bfin5xx_spi.h> |
5d448dd5 | 46 | #include <asm/portmux.h> |
14b03204 | 47 | #include <asm/dpmc.h> |
1394f032 BW |
48 | |
49 | /* | |
50 | * Name the Board for the /proc/cpuinfo | |
51 | */ | |
066954a3 | 52 | const char bfin_board_name[] = "Bluetechnix CM BF537"; |
1394f032 BW |
53 | |
54 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | |
55 | /* all SPI peripherals info goes here */ | |
56 | ||
57 | #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) | |
58 | static struct mtd_partition bfin_spi_flash_partitions[] = { | |
59 | { | |
aa582977 | 60 | .name = "bootloader(spi)", |
1394f032 BW |
61 | .size = 0x00020000, |
62 | .offset = 0, | |
63 | .mask_flags = MTD_CAP_ROM | |
1f83b8f1 | 64 | }, { |
aa582977 | 65 | .name = "linux kernel(spi)", |
1394f032 BW |
66 | .size = 0xe0000, |
67 | .offset = 0x20000 | |
1f83b8f1 | 68 | }, { |
aa582977 | 69 | .name = "file system(spi)", |
1394f032 BW |
70 | .size = 0x700000, |
71 | .offset = 0x00100000, | |
72 | } | |
73 | }; | |
74 | ||
75 | static struct flash_platform_data bfin_spi_flash_data = { | |
76 | .name = "m25p80", | |
77 | .parts = bfin_spi_flash_partitions, | |
78 | .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), | |
79 | .type = "m25p64", | |
80 | }; | |
81 | ||
82 | /* SPI flash chip (m25p64) */ | |
83 | static struct bfin5xx_spi_chip spi_flash_chip_info = { | |
84 | .enable_dma = 0, /* use dma transfer with this chip*/ | |
85 | .bits_per_word = 8, | |
86 | }; | |
87 | #endif | |
88 | ||
89 | #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) | |
90 | /* SPI ADC chip */ | |
91 | static struct bfin5xx_spi_chip spi_adc_chip_info = { | |
92 | .enable_dma = 1, /* use dma transfer with this chip*/ | |
93 | .bits_per_word = 16, | |
94 | }; | |
95 | #endif | |
96 | ||
97 | #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | |
98 | static struct bfin5xx_spi_chip ad1836_spi_chip_info = { | |
99 | .enable_dma = 0, | |
100 | .bits_per_word = 16, | |
101 | }; | |
102 | #endif | |
103 | ||
104 | #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) | |
105 | static struct bfin5xx_spi_chip ad9960_spi_chip_info = { | |
106 | .enable_dma = 0, | |
107 | .bits_per_word = 16, | |
108 | }; | |
109 | #endif | |
110 | ||
f3f704d3 MH |
111 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
112 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { | |
113 | .enable_dma = 0, | |
1394f032 BW |
114 | .bits_per_word = 8, |
115 | }; | |
116 | #endif | |
117 | ||
118 | static struct spi_board_info bfin_spi_board_info[] __initdata = { | |
119 | #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) | |
120 | { | |
121 | /* the modalias must be the same as spi device driver name */ | |
122 | .modalias = "m25p80", /* Name of spi_driver for this device */ | |
123 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | |
c6c4d7bb | 124 | .bus_num = 0, /* Framework bus number */ |
1394f032 BW |
125 | .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ |
126 | .platform_data = &bfin_spi_flash_data, | |
127 | .controller_data = &spi_flash_chip_info, | |
128 | .mode = SPI_MODE_3, | |
129 | }, | |
130 | #endif | |
131 | ||
132 | #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) | |
133 | { | |
134 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ | |
135 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ | |
c6c4d7bb | 136 | .bus_num = 0, /* Framework bus number */ |
1394f032 BW |
137 | .chip_select = 1, /* Framework chip select. */ |
138 | .platform_data = NULL, /* No spi_driver specific config */ | |
139 | .controller_data = &spi_adc_chip_info, | |
140 | }, | |
141 | #endif | |
142 | ||
143 | #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | |
144 | { | |
145 | .modalias = "ad1836-spi", | |
146 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | |
c6c4d7bb | 147 | .bus_num = 0, |
1394f032 BW |
148 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, |
149 | .controller_data = &ad1836_spi_chip_info, | |
150 | }, | |
151 | #endif | |
152 | ||
153 | #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) | |
154 | { | |
155 | .modalias = "ad9960-spi", | |
156 | .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */ | |
c6c4d7bb | 157 | .bus_num = 0, |
1394f032 BW |
158 | .chip_select = 1, |
159 | .controller_data = &ad9960_spi_chip_info, | |
160 | }, | |
161 | #endif | |
162 | ||
f3f704d3 | 163 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
1394f032 | 164 | { |
f3f704d3 MH |
165 | .modalias = "mmc_spi", |
166 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ | |
c6c4d7bb | 167 | .bus_num = 0, |
f3f704d3 MH |
168 | .chip_select = 1, |
169 | .controller_data = &mmc_spi_chip_info, | |
1394f032 BW |
170 | .mode = SPI_MODE_3, |
171 | }, | |
172 | #endif | |
173 | }; | |
174 | ||
c6c4d7bb BW |
175 | /* SPI (0) */ |
176 | static struct resource bfin_spi0_resource[] = { | |
177 | [0] = { | |
178 | .start = SPI0_REGBASE, | |
179 | .end = SPI0_REGBASE + 0xFF, | |
180 | .flags = IORESOURCE_MEM, | |
181 | }, | |
182 | [1] = { | |
183 | .start = CH_SPI, | |
184 | .end = CH_SPI, | |
185 | .flags = IORESOURCE_IRQ, | |
186 | } | |
187 | }; | |
188 | ||
1394f032 | 189 | /* SPI controller data */ |
c6c4d7bb | 190 | static struct bfin5xx_spi_master bfin_spi0_info = { |
1394f032 BW |
191 | .num_chipselect = 8, |
192 | .enable_dma = 1, /* master has the ability to do dma transfer */ | |
5d448dd5 | 193 | .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, |
1394f032 BW |
194 | }; |
195 | ||
c6c4d7bb BW |
196 | static struct platform_device bfin_spi0_device = { |
197 | .name = "bfin-spi", | |
198 | .id = 0, /* Bus number */ | |
199 | .num_resources = ARRAY_SIZE(bfin_spi0_resource), | |
200 | .resource = bfin_spi0_resource, | |
1394f032 | 201 | .dev = { |
c6c4d7bb | 202 | .platform_data = &bfin_spi0_info, /* Passed to driver */ |
1394f032 BW |
203 | }, |
204 | }; | |
205 | #endif /* spi master and devices */ | |
206 | ||
207 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) | |
208 | static struct platform_device rtc_device = { | |
209 | .name = "rtc-bfin", | |
210 | .id = -1, | |
211 | }; | |
212 | #endif | |
213 | ||
0d4a89bb MH |
214 | #if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE) |
215 | static struct platform_device hitachi_fb_device = { | |
216 | .name = "hitachi-tx09", | |
217 | }; | |
218 | #endif | |
219 | ||
1394f032 BW |
220 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
221 | static struct resource smc91x_resources[] = { | |
222 | { | |
223 | .start = 0x20200300, | |
224 | .end = 0x20200300 + 16, | |
225 | .flags = IORESOURCE_MEM, | |
1f83b8f1 | 226 | }, { |
1394f032 BW |
227 | .start = IRQ_PF14, |
228 | .end = IRQ_PF14, | |
229 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
230 | }, | |
231 | }; | |
232 | ||
233 | static struct platform_device smc91x_device = { | |
234 | .name = "smc91x", | |
235 | .id = 0, | |
236 | .num_resources = ARRAY_SIZE(smc91x_resources), | |
237 | .resource = smc91x_resources, | |
238 | }; | |
239 | #endif | |
240 | ||
241 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) | |
242 | static struct resource isp1362_hcd_resources[] = { | |
243 | { | |
244 | .start = 0x20308000, | |
245 | .end = 0x20308000, | |
246 | .flags = IORESOURCE_MEM, | |
1f83b8f1 | 247 | }, { |
1394f032 BW |
248 | .start = 0x20308004, |
249 | .end = 0x20308004, | |
250 | .flags = IORESOURCE_MEM, | |
1f83b8f1 | 251 | }, { |
1394f032 BW |
252 | .start = IRQ_PG15, |
253 | .end = IRQ_PG15, | |
254 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
255 | }, | |
256 | }; | |
257 | ||
258 | static struct isp1362_platform_data isp1362_priv = { | |
259 | .sel15Kres = 1, | |
260 | .clknotstop = 0, | |
261 | .oc_enable = 0, | |
262 | .int_act_high = 0, | |
263 | .int_edge_triggered = 0, | |
264 | .remote_wakeup_connected = 0, | |
265 | .no_power_switching = 1, | |
266 | .power_switching_mode = 0, | |
267 | }; | |
268 | ||
269 | static struct platform_device isp1362_hcd_device = { | |
270 | .name = "isp1362-hcd", | |
271 | .id = 0, | |
272 | .dev = { | |
273 | .platform_data = &isp1362_priv, | |
274 | }, | |
275 | .num_resources = ARRAY_SIZE(isp1362_hcd_resources), | |
276 | .resource = isp1362_hcd_resources, | |
277 | }; | |
278 | #endif | |
279 | ||
280 | #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) | |
281 | static struct resource net2272_bfin_resources[] = { | |
282 | { | |
283 | .start = 0x20200000, | |
284 | .end = 0x20200000 + 0x100, | |
285 | .flags = IORESOURCE_MEM, | |
1f83b8f1 | 286 | }, { |
8ecc7368 MH |
287 | .start = IRQ_PH14, |
288 | .end = IRQ_PH14, | |
1394f032 BW |
289 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, |
290 | }, | |
291 | }; | |
292 | ||
293 | static struct platform_device net2272_bfin_device = { | |
294 | .name = "net2272", | |
295 | .id = -1, | |
296 | .num_resources = ARRAY_SIZE(net2272_bfin_resources), | |
297 | .resource = net2272_bfin_resources, | |
298 | }; | |
299 | #endif | |
300 | ||
c97618d3 MF |
301 | static struct resource bfin_gpios_resources = { |
302 | .start = 0, | |
303 | .end = MAX_BLACKFIN_GPIOS - 1, | |
304 | .flags = IORESOURCE_IRQ, | |
305 | }; | |
306 | ||
307 | static struct platform_device bfin_gpios_device = { | |
308 | .name = "simple-gpio", | |
309 | .id = -1, | |
310 | .num_resources = 1, | |
311 | .resource = &bfin_gpios_resources, | |
312 | }; | |
313 | ||
8ea89497 MF |
314 | #if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE) |
315 | static struct mtd_partition cm_partitions[] = { | |
316 | { | |
317 | .name = "bootloader(nor)", | |
318 | .size = 0x40000, | |
319 | .offset = 0, | |
320 | }, { | |
321 | .name = "linux kernel(nor)", | |
322 | .size = 0xE0000, | |
323 | .offset = MTDPART_OFS_APPEND, | |
324 | }, { | |
325 | .name = "file system(nor)", | |
326 | .size = MTDPART_SIZ_FULL, | |
327 | .offset = MTDPART_OFS_APPEND, | |
328 | } | |
329 | }; | |
330 | ||
331 | static struct physmap_flash_data cm_flash_data = { | |
332 | .width = 2, | |
333 | .parts = cm_partitions, | |
334 | .nr_parts = ARRAY_SIZE(cm_partitions), | |
335 | }; | |
336 | ||
337 | static unsigned cm_flash_gpios[] = { GPIO_PF4 }; | |
338 | ||
339 | static struct resource cm_flash_resource[] = { | |
340 | { | |
341 | .name = "cfi_probe", | |
342 | .start = 0x20000000, | |
343 | .end = 0x201fffff, | |
344 | .flags = IORESOURCE_MEM, | |
345 | }, { | |
346 | .start = (unsigned long)cm_flash_gpios, | |
347 | .end = ARRAY_SIZE(cm_flash_gpios), | |
348 | .flags = IORESOURCE_IRQ, | |
349 | } | |
350 | }; | |
351 | ||
352 | static struct platform_device cm_flash_device = { | |
353 | .name = "gpio-addr-flash", | |
354 | .id = 0, | |
355 | .dev = { | |
356 | .platform_data = &cm_flash_data, | |
357 | }, | |
358 | .num_resources = ARRAY_SIZE(cm_flash_resource), | |
359 | .resource = cm_flash_resource, | |
360 | }; | |
361 | #endif | |
362 | ||
1394f032 BW |
363 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) |
364 | static struct resource bfin_uart_resources[] = { | |
365 | { | |
366 | .start = 0xFFC00400, | |
367 | .end = 0xFFC004FF, | |
368 | .flags = IORESOURCE_MEM, | |
1f83b8f1 | 369 | }, { |
1394f032 BW |
370 | .start = 0xFFC02000, |
371 | .end = 0xFFC020FF, | |
372 | .flags = IORESOURCE_MEM, | |
373 | }, | |
374 | }; | |
375 | ||
376 | static struct platform_device bfin_uart_device = { | |
377 | .name = "bfin-uart", | |
378 | .id = 1, | |
379 | .num_resources = ARRAY_SIZE(bfin_uart_resources), | |
380 | .resource = bfin_uart_resources, | |
381 | }; | |
382 | #endif | |
383 | ||
5be36d22 | 384 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
5be36d22 | 385 | #ifdef CONFIG_BFIN_SIR0 |
42bd8bcb | 386 | static struct resource bfin_sir0_resources[] = { |
5be36d22 GY |
387 | { |
388 | .start = 0xFFC00400, | |
389 | .end = 0xFFC004FF, | |
390 | .flags = IORESOURCE_MEM, | |
391 | }, | |
42bd8bcb GY |
392 | { |
393 | .start = IRQ_UART0_RX, | |
394 | .end = IRQ_UART0_RX+1, | |
395 | .flags = IORESOURCE_IRQ, | |
396 | }, | |
397 | { | |
398 | .start = CH_UART0_RX, | |
399 | .end = CH_UART0_RX+1, | |
400 | .flags = IORESOURCE_DMA, | |
401 | }, | |
402 | }; | |
403 | static struct platform_device bfin_sir0_device = { | |
404 | .name = "bfin_sir", | |
405 | .id = 0, | |
406 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | |
407 | .resource = bfin_sir0_resources, | |
408 | }; | |
5be36d22 GY |
409 | #endif |
410 | #ifdef CONFIG_BFIN_SIR1 | |
42bd8bcb | 411 | static struct resource bfin_sir1_resources[] = { |
5be36d22 GY |
412 | { |
413 | .start = 0xFFC02000, | |
414 | .end = 0xFFC020FF, | |
415 | .flags = IORESOURCE_MEM, | |
416 | }, | |
42bd8bcb GY |
417 | { |
418 | .start = IRQ_UART1_RX, | |
419 | .end = IRQ_UART1_RX+1, | |
420 | .flags = IORESOURCE_IRQ, | |
421 | }, | |
422 | { | |
423 | .start = CH_UART1_RX, | |
424 | .end = CH_UART1_RX+1, | |
425 | .flags = IORESOURCE_DMA, | |
426 | }, | |
5be36d22 | 427 | }; |
42bd8bcb | 428 | static struct platform_device bfin_sir1_device = { |
5be36d22 | 429 | .name = "bfin_sir", |
42bd8bcb GY |
430 | .id = 1, |
431 | .num_resources = ARRAY_SIZE(bfin_sir1_resources), | |
432 | .resource = bfin_sir1_resources, | |
5be36d22 GY |
433 | }; |
434 | #endif | |
42bd8bcb | 435 | #endif |
5be36d22 | 436 | |
56ce835b MF |
437 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) |
438 | static struct resource bfin_twi0_resource[] = { | |
439 | [0] = { | |
440 | .start = TWI0_REGBASE, | |
441 | .end = TWI0_REGBASE, | |
442 | .flags = IORESOURCE_MEM, | |
443 | }, | |
444 | [1] = { | |
445 | .start = IRQ_TWI, | |
446 | .end = IRQ_TWI, | |
447 | .flags = IORESOURCE_IRQ, | |
448 | }, | |
449 | }; | |
450 | ||
451 | static struct platform_device i2c_bfin_twi_device = { | |
452 | .name = "i2c-bfin-twi", | |
453 | .id = 0, | |
454 | .num_resources = ARRAY_SIZE(bfin_twi0_resource), | |
455 | .resource = bfin_twi0_resource, | |
456 | }; | |
457 | #endif | |
458 | ||
1394f032 BW |
459 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) |
460 | static struct platform_device bfin_sport0_uart_device = { | |
461 | .name = "bfin-sport-uart", | |
462 | .id = 0, | |
463 | }; | |
464 | ||
465 | static struct platform_device bfin_sport1_uart_device = { | |
466 | .name = "bfin-sport-uart", | |
467 | .id = 1, | |
468 | }; | |
469 | #endif | |
470 | ||
471 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) | |
65319628 GY |
472 | static struct platform_device bfin_mii_bus = { |
473 | .name = "bfin_mii_bus", | |
474 | }; | |
475 | ||
1394f032 BW |
476 | static struct platform_device bfin_mac_device = { |
477 | .name = "bfin_mac", | |
65319628 | 478 | .dev.platform_data = &bfin_mii_bus, |
1394f032 BW |
479 | }; |
480 | #endif | |
481 | ||
c6c4d7bb | 482 | #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) |
fe5aeb93 | 483 | #define PATA_INT IRQ_PF14 |
c6c4d7bb BW |
484 | |
485 | static struct pata_platform_info bfin_pata_platform_data = { | |
486 | .ioport_shift = 2, | |
487 | .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED, | |
488 | }; | |
489 | ||
490 | static struct resource bfin_pata_resources[] = { | |
491 | { | |
492 | .start = 0x2030C000, | |
493 | .end = 0x2030C01F, | |
494 | .flags = IORESOURCE_MEM, | |
495 | }, | |
496 | { | |
497 | .start = 0x2030D018, | |
498 | .end = 0x2030D01B, | |
499 | .flags = IORESOURCE_MEM, | |
500 | }, | |
501 | { | |
502 | .start = PATA_INT, | |
503 | .end = PATA_INT, | |
504 | .flags = IORESOURCE_IRQ, | |
505 | }, | |
506 | }; | |
507 | ||
508 | static struct platform_device bfin_pata_device = { | |
509 | .name = "pata_platform", | |
510 | .id = -1, | |
511 | .num_resources = ARRAY_SIZE(bfin_pata_resources), | |
512 | .resource = bfin_pata_resources, | |
513 | .dev = { | |
514 | .platform_data = &bfin_pata_platform_data, | |
515 | } | |
516 | }; | |
517 | #endif | |
518 | ||
14b03204 MH |
519 | static const unsigned int cclk_vlev_datasheet[] = |
520 | { | |
521 | VRPAIR(VLEV_085, 250000000), | |
522 | VRPAIR(VLEV_090, 376000000), | |
523 | VRPAIR(VLEV_095, 426000000), | |
524 | VRPAIR(VLEV_100, 426000000), | |
525 | VRPAIR(VLEV_105, 476000000), | |
526 | VRPAIR(VLEV_110, 476000000), | |
527 | VRPAIR(VLEV_115, 476000000), | |
528 | VRPAIR(VLEV_120, 500000000), | |
529 | VRPAIR(VLEV_125, 533000000), | |
530 | VRPAIR(VLEV_130, 600000000), | |
531 | }; | |
532 | ||
533 | static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { | |
534 | .tuple_tab = cclk_vlev_datasheet, | |
535 | .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), | |
536 | .vr_settling_time = 25 /* us */, | |
537 | }; | |
538 | ||
539 | static struct platform_device bfin_dpmc = { | |
540 | .name = "bfin dpmc", | |
541 | .dev = { | |
542 | .platform_data = &bfin_dmpc_vreg_data, | |
543 | }, | |
544 | }; | |
545 | ||
1394f032 | 546 | static struct platform_device *cm_bf537_devices[] __initdata = { |
14b03204 MH |
547 | |
548 | &bfin_dpmc, | |
549 | ||
0d4a89bb MH |
550 | #if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE) |
551 | &hitachi_fb_device, | |
552 | #endif | |
553 | ||
1394f032 BW |
554 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) |
555 | &rtc_device, | |
556 | #endif | |
557 | ||
558 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) | |
559 | &bfin_uart_device, | |
560 | #endif | |
561 | ||
5be36d22 | 562 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
42bd8bcb GY |
563 | #ifdef CONFIG_BFIN_SIR0 |
564 | &bfin_sir0_device, | |
565 | #endif | |
566 | #ifdef CONFIG_BFIN_SIR1 | |
567 | &bfin_sir1_device, | |
568 | #endif | |
5be36d22 GY |
569 | #endif |
570 | ||
56ce835b MF |
571 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) |
572 | &i2c_bfin_twi_device, | |
573 | #endif | |
574 | ||
1394f032 BW |
575 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) |
576 | &bfin_sport0_uart_device, | |
577 | &bfin_sport1_uart_device, | |
578 | #endif | |
579 | ||
580 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) | |
581 | &isp1362_hcd_device, | |
582 | #endif | |
583 | ||
584 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | |
585 | &smc91x_device, | |
586 | #endif | |
587 | ||
588 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) | |
65319628 | 589 | &bfin_mii_bus, |
1394f032 BW |
590 | &bfin_mac_device, |
591 | #endif | |
592 | ||
593 | #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) | |
594 | &net2272_bfin_device, | |
595 | #endif | |
596 | ||
597 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | |
c6c4d7bb BW |
598 | &bfin_spi0_device, |
599 | #endif | |
600 | ||
601 | #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) | |
602 | &bfin_pata_device, | |
1394f032 | 603 | #endif |
8ea89497 MF |
604 | |
605 | #if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE) | |
606 | &cm_flash_device, | |
607 | #endif | |
c97618d3 MF |
608 | |
609 | &bfin_gpios_device, | |
1394f032 BW |
610 | }; |
611 | ||
612 | static int __init cm_bf537_init(void) | |
613 | { | |
b85d858b | 614 | printk(KERN_INFO "%s(): registering device resources\n", __func__); |
1394f032 BW |
615 | platform_add_devices(cm_bf537_devices, ARRAY_SIZE(cm_bf537_devices)); |
616 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | |
617 | spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); | |
618 | #endif | |
c6c4d7bb BW |
619 | |
620 | #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) | |
621 | irq_desc[PATA_INT].status |= IRQ_NOAUTOEN; | |
622 | #endif | |
1394f032 BW |
623 | return 0; |
624 | } | |
625 | ||
626 | arch_initcall(cm_bf537_init); | |
137b1529 | 627 | |
9862cc52 | 628 | void bfin_get_ether_addr(char *addr) |
137b1529 MF |
629 | { |
630 | random_ether_addr(addr); | |
631 | printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__); | |
632 | } | |
9862cc52 | 633 | EXPORT_SYMBOL(bfin_get_ether_addr); |