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Merge branch 'tip/perf/core' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt...
[mirror_ubuntu-eoan-kernel.git] / arch / blackfin / mach-bf537 / boards / cm_bf537u.c
CommitLineData
1394f032 1/*
96f1050d
RG		 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2008-2009 Bluetechnix
4 * 2005 National ICT Australia (NICTA)
5 * Aidan Williams <aidan@nicta.com.au>
1394f032 6 *
96f1050d 7 * Licensed under the GPL-2 or later.
1394f032
BW		 8 */
9
10#include <linux/device.h>
43f73fef 11#include <linux/etherdevice.h>
90590543 12#include <linux/export.h>
1394f032
BW		 13#include <linux/platform_device.h>
14#include <linux/mtd/mtd.h>
15#include <linux/mtd/partitions.h>
8ea89497 16#include <linux/mtd/physmap.h>
1394f032
BW		 17#include <linux/spi/spi.h>
18#include <linux/spi/flash.h>
b964c592 19#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
f02bcec5 20#include <linux/usb/isp1362.h>
b964c592 21#endif
0a87e3e9 22#include <linux/ata_platform.h>
1f83b8f1 23#include <linux/irq.h>
c6c4d7bb 24#include <asm/dma.h>
1394f032 25#include <asm/bfin5xx_spi.h>
5d448dd5 26#include <asm/portmux.h>
14b03204 27#include <asm/dpmc.h>
60584344 28#include <linux/spi/mmc_spi.h>
1394f032
BW		 29
30/*
31 * Name the Board for the /proc/cpuinfo
32 */
60584344 33const char bfin_board_name[] = "Bluetechnix CM BF537U";
1394f032
BW		 34
35#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
36/* all SPI peripherals info goes here */
37
38#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
39static struct mtd_partition bfin_spi_flash_partitions[] = {
40 {
aa582977 41 .name = "bootloader(spi)",
1394f032
BW		 42 .size = 0x00020000,
43 .offset = 0,
44 .mask_flags = MTD_CAP_ROM
1f83b8f1 45 }, {
aa582977 46 .name = "linux kernel(spi)",
1394f032
BW		 47 .size = 0xe0000,
48 .offset = 0x20000
1f83b8f1 49 }, {
aa582977 50 .name = "file system(spi)",
1394f032
BW		 51 .size = 0x700000,
52 .offset = 0x00100000,
53 }
54};
55
56static struct flash_platform_data bfin_spi_flash_data = {
57 .name = "m25p80",
58 .parts = bfin_spi_flash_partitions,
59 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
60 .type = "m25p64",
61};
62
63/* SPI flash chip (m25p64) */
64static struct bfin5xx_spi_chip spi_flash_chip_info = {
65 .enable_dma = 0, /* use dma transfer with this chip*/
1394f032
BW		 66};
67#endif
68
f3f704d3
MH		 69#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
70static struct bfin5xx_spi_chip mmc_spi_chip_info = {
71 .enable_dma = 0,
1394f032
BW		 72};
73#endif
74
75static struct spi_board_info bfin_spi_board_info[] __initdata = {
76#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
77 {
78 /* the modalias must be the same as spi device driver name */
79 .modalias = "m25p80", /* Name of spi_driver for this device */
80 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 81 .bus_num = 0, /* Framework bus number */
1394f032
BW		 82 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
83 .platform_data = &bfin_spi_flash_data,
84 .controller_data = &spi_flash_chip_info,
85 .mode = SPI_MODE_3,
86 },
87#endif
88
7ba80063 89#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
1394f032 90 {
7ba80063 91 .modalias = "ad183x",
1394f032 92 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 93 .bus_num = 0,
7ba80063 94 .chip_select = 4,
1394f032
BW		 95 },
96#endif
97
f3f704d3 98#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
1394f032 99 {
f3f704d3
MH		 100 .modalias = "mmc_spi",
101 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 102 .bus_num = 0,
f3f704d3
MH		 103 .chip_select = 1,
104 .controller_data = &mmc_spi_chip_info,
1394f032
BW		 105 .mode = SPI_MODE_3,
106 },
107#endif
108};
109
c6c4d7bb
BW		 110/* SPI (0) */
111static struct resource bfin_spi0_resource[] = {
112 [0] = {
113 .start = SPI0_REGBASE,
114 .end = SPI0_REGBASE + 0xFF,
115 .flags = IORESOURCE_MEM,
116 },
117 [1] = {
118 .start = CH_SPI,
119 .end = CH_SPI,
53122693
YL		 120 .flags = IORESOURCE_DMA,
121 },
122 [2] = {
123 .start = IRQ_SPI,
124 .end = IRQ_SPI,
c6c4d7bb 125 .flags = IORESOURCE_IRQ,
53122693 126 },
c6c4d7bb
BW		 127};
128
1394f032 129/* SPI controller data */
c6c4d7bb 130static struct bfin5xx_spi_master bfin_spi0_info = {
1394f032
BW		 131 .num_chipselect = 8,
132 .enable_dma = 1, /* master has the ability to do dma transfer */
5d448dd5 133 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1394f032
BW		 134};
135
c6c4d7bb
BW		 136static struct platform_device bfin_spi0_device = {
137 .name = "bfin-spi",
138 .id = 0, /* Bus number */
139 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
140 .resource = bfin_spi0_resource,
1394f032 141 .dev = {
c6c4d7bb 142 .platform_data = &bfin_spi0_info, /* Passed to driver */
1394f032
BW		 143 },
144};
145#endif /* spi master and devices */
146
147#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
148static struct platform_device rtc_device = {
149 .name = "rtc-bfin",
150 .id = -1,
151};
152#endif
153
0d4a89bb
MH		 154#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
155static struct platform_device hitachi_fb_device = {
156 .name = "hitachi-tx09",
157};
158#endif
159
1394f032 160#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
61f09b5a
MH		 161#include <linux/smc91x.h>
162
163static struct smc91x_platdata smc91x_info = {
164 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
165 .leda = RPC_LED_100_10,
166 .ledb = RPC_LED_TX_RX,
167};
168
1394f032
BW		 169static struct resource smc91x_resources[] = {
170 {
171 .start = 0x20200300,
172 .end = 0x20200300 + 16,
173 .flags = IORESOURCE_MEM,
1f83b8f1 174 }, {
1394f032
BW		 175 .start = IRQ_PF14,
176 .end = IRQ_PF14,
177 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
178 },
179};
180
181static struct platform_device smc91x_device = {
182 .name = "smc91x",
183 .id = 0,
184 .num_resources = ARRAY_SIZE(smc91x_resources),
185 .resource = smc91x_resources,
61f09b5a
MH		 186 .dev = {
187 .platform_data = &smc91x_info,
188 },
1394f032
BW		 189};
190#endif
191
192#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
193static struct resource isp1362_hcd_resources[] = {
194 {
195 .start = 0x20308000,
196 .end = 0x20308000,
197 .flags = IORESOURCE_MEM,
1f83b8f1 198 }, {
1394f032
BW		 199 .start = 0x20308004,
200 .end = 0x20308004,
201 .flags = IORESOURCE_MEM,
1f83b8f1 202 }, {
1394f032
BW		 203 .start = IRQ_PG15,
204 .end = IRQ_PG15,
9e75894c 205 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
1394f032
BW		 206 },
207};
208
209static struct isp1362_platform_data isp1362_priv = {
210 .sel15Kres = 1,
211 .clknotstop = 0,
212 .oc_enable = 0,
213 .int_act_high = 0,
214 .int_edge_triggered = 0,
215 .remote_wakeup_connected = 0,
216 .no_power_switching = 1,
217 .power_switching_mode = 0,
218};
219
220static struct platform_device isp1362_hcd_device = {
221 .name = "isp1362-hcd",
222 .id = 0,
223 .dev = {
224 .platform_data = &isp1362_priv,
225 },
226 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
227 .resource = isp1362_hcd_resources,
228};
229#endif
230
231#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
232static struct resource net2272_bfin_resources[] = {
233 {
234 .start = 0x20200000,
235 .end = 0x20200000 + 0x100,
236 .flags = IORESOURCE_MEM,
1f83b8f1 237 }, {
8ecc7368
MH		 238 .start = IRQ_PH14,
239 .end = IRQ_PH14,
1394f032
BW		 240 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
241 },
242};
243
244static struct platform_device net2272_bfin_device = {
245 .name = "net2272",
246 .id = -1,
247 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
248 .resource = net2272_bfin_resources,
249};
250#endif
251
8ea89497
MF		 252#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
253static struct mtd_partition cm_partitions[] = {
254 {
255 .name = "bootloader(nor)",
256 .size = 0x40000,
257 .offset = 0,
258 }, {
259 .name = "linux kernel(nor)",
60584344 260 .size = 0x100000,
8ea89497
MF		 261 .offset = MTDPART_OFS_APPEND,
262 }, {
263 .name = "file system(nor)",
264 .size = MTDPART_SIZ_FULL,
265 .offset = MTDPART_OFS_APPEND,
266 }
267};
268
269static struct physmap_flash_data cm_flash_data = {
270 .width = 2,
271 .parts = cm_partitions,
272 .nr_parts = ARRAY_SIZE(cm_partitions),
273};
274
60584344 275static unsigned cm_flash_gpios[] = { GPIO_PH0 };
8ea89497
MF		 276
277static struct resource cm_flash_resource[] = {
278 {
279 .name = "cfi_probe",
280 .start = 0x20000000,
281 .end = 0x201fffff,
282 .flags = IORESOURCE_MEM,
283 }, {
284 .start = (unsigned long)cm_flash_gpios,
285 .end = ARRAY_SIZE(cm_flash_gpios),
286 .flags = IORESOURCE_IRQ,
287 }
288};
289
290static struct platform_device cm_flash_device = {
291 .name = "gpio-addr-flash",
292 .id = 0,
293 .dev = {
294 .platform_data = &cm_flash_data,
295 },
296 .num_resources = ARRAY_SIZE(cm_flash_resource),
297 .resource = cm_flash_resource,
298};
299#endif
300
1394f032 301#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
6bd1fbea
SZ		 302#ifdef CONFIG_SERIAL_BFIN_UART0
303static struct resource bfin_uart0_resources[] = {
1394f032 304 {
6bd1fbea
SZ		 305 .start = UART0_THR,
306 .end = UART0_GCTL+2,
1394f032 307 .flags = IORESOURCE_MEM,
6bd1fbea 308 },
edb0a640
SZ		 309 {
310 .start = IRQ_UART0_TX,
311 .end = IRQ_UART0_TX,
312 .flags = IORESOURCE_IRQ,
313 },
6bd1fbea
SZ		 314 {
315 .start = IRQ_UART0_RX,
edb0a640 316 .end = IRQ_UART0_RX,
6bd1fbea
SZ		 317 .flags = IORESOURCE_IRQ,
318 },
319 {
320 .start = IRQ_UART0_ERROR,
321 .end = IRQ_UART0_ERROR,
322 .flags = IORESOURCE_IRQ,
323 },
324 {
325 .start = CH_UART0_TX,
326 .end = CH_UART0_TX,
327 .flags = IORESOURCE_DMA,
328 },
329 {
330 .start = CH_UART0_RX,
331 .end = CH_UART0_RX,
332 .flags = IORESOURCE_DMA,
333 },
334};
335
a8b19886 336static unsigned short bfin_uart0_peripherals[] = {
6bd1fbea
SZ		 337 P_UART0_TX, P_UART0_RX, 0
338};
339
340static struct platform_device bfin_uart0_device = {
341 .name = "bfin-uart",
342 .id = 0,
343 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
344 .resource = bfin_uart0_resources,
345 .dev = {
346 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
347 },
348};
349#endif
350#ifdef CONFIG_SERIAL_BFIN_UART1
351static struct resource bfin_uart1_resources[] = {
352 {
353 .start = UART1_THR,
354 .end = UART1_GCTL+2,
1394f032
BW		 355 .flags = IORESOURCE_MEM,
356 },
edb0a640
SZ		 357 {
358 .start = IRQ_UART1_TX,
359 .end = IRQ_UART1_TX,
360 .flags = IORESOURCE_IRQ,
361 },
6bd1fbea
SZ		 362 {
363 .start = IRQ_UART1_RX,
edb0a640 364 .end = IRQ_UART1_RX,
6bd1fbea
SZ		 365 .flags = IORESOURCE_IRQ,
366 },
367 {
368 .start = IRQ_UART1_ERROR,
369 .end = IRQ_UART1_ERROR,
370 .flags = IORESOURCE_IRQ,
371 },
372 {
373 .start = CH_UART1_TX,
374 .end = CH_UART1_TX,
375 .flags = IORESOURCE_DMA,
376 },
377 {
378 .start = CH_UART1_RX,
379 .end = CH_UART1_RX,
380 .flags = IORESOURCE_DMA,
381 },
1394f032
BW		 382};
383
a8b19886 384static unsigned short bfin_uart1_peripherals[] = {
6bd1fbea
SZ		 385 P_UART1_TX, P_UART1_RX, 0
386};
387
388static struct platform_device bfin_uart1_device = {
1394f032
BW		 389 .name = "bfin-uart",
390 .id = 1,
6bd1fbea
SZ		 391 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
392 .resource = bfin_uart1_resources,
393 .dev = {
394 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
395 },
1394f032
BW		 396};
397#endif
6bd1fbea 398#endif
1394f032 399
5be36d22 400#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
5be36d22 401#ifdef CONFIG_BFIN_SIR0
42bd8bcb 402static struct resource bfin_sir0_resources[] = {
5be36d22
GY		 403 {
404 .start = 0xFFC00400,
405 .end = 0xFFC004FF,
406 .flags = IORESOURCE_MEM,
407 },
42bd8bcb
GY		 408 {
409 .start = IRQ_UART0_RX,
410 .end = IRQ_UART0_RX+1,
411 .flags = IORESOURCE_IRQ,
412 },
413 {
414 .start = CH_UART0_RX,
415 .end = CH_UART0_RX+1,
416 .flags = IORESOURCE_DMA,
417 },
418};
419static struct platform_device bfin_sir0_device = {
420 .name = "bfin_sir",
421 .id = 0,
422 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
423 .resource = bfin_sir0_resources,
424};
5be36d22
GY		 425#endif
426#ifdef CONFIG_BFIN_SIR1
42bd8bcb 427static struct resource bfin_sir1_resources[] = {
5be36d22
GY		 428 {
429 .start = 0xFFC02000,
430 .end = 0xFFC020FF,
431 .flags = IORESOURCE_MEM,
432 },
42bd8bcb
GY		 433 {
434 .start = IRQ_UART1_RX,
435 .end = IRQ_UART1_RX+1,
436 .flags = IORESOURCE_IRQ,
437 },
438 {
439 .start = CH_UART1_RX,
440 .end = CH_UART1_RX+1,
441 .flags = IORESOURCE_DMA,
442 },
5be36d22 443};
42bd8bcb 444static struct platform_device bfin_sir1_device = {
5be36d22 445 .name = "bfin_sir",
42bd8bcb
GY		 446 .id = 1,
447 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
448 .resource = bfin_sir1_resources,
5be36d22
GY		 449};
450#endif
42bd8bcb 451#endif
5be36d22 452
56ce835b
MF		 453#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
454static struct resource bfin_twi0_resource[] = {
455 [0] = {
456 .start = TWI0_REGBASE,
457 .end = TWI0_REGBASE,
458 .flags = IORESOURCE_MEM,
459 },
460 [1] = {
461 .start = IRQ_TWI,
462 .end = IRQ_TWI,
463 .flags = IORESOURCE_IRQ,
464 },
465};
466
467static struct platform_device i2c_bfin_twi_device = {
468 .name = "i2c-bfin-twi",
469 .id = 0,
470 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
471 .resource = bfin_twi0_resource,
472};
473#endif
474
1394f032 475#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
df5de261
SZ		 476#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
477static struct resource bfin_sport0_uart_resources[] = {
478 {
479 .start = SPORT0_TCR1,
480 .end = SPORT0_MRCS3+4,
481 .flags = IORESOURCE_MEM,
482 },
483 {
484 .start = IRQ_SPORT0_RX,
485 .end = IRQ_SPORT0_RX+1,
486 .flags = IORESOURCE_IRQ,
487 },
488 {
489 .start = IRQ_SPORT0_ERROR,
490 .end = IRQ_SPORT0_ERROR,
491 .flags = IORESOURCE_IRQ,
492 },
493};
494
a8b19886 495static unsigned short bfin_sport0_peripherals[] = {
df5de261 496 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
e54b6730 497 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
df5de261
SZ		 498};
499
1394f032
BW		 500static struct platform_device bfin_sport0_uart_device = {
501 .name = "bfin-sport-uart",
502 .id = 0,
df5de261
SZ		 503 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
504 .resource = bfin_sport0_uart_resources,
505 .dev = {
506 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
507 },
508};
509#endif
510#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
511static struct resource bfin_sport1_uart_resources[] = {
512 {
513 .start = SPORT1_TCR1,
514 .end = SPORT1_MRCS3+4,
515 .flags = IORESOURCE_MEM,
516 },
517 {
518 .start = IRQ_SPORT1_RX,
519 .end = IRQ_SPORT1_RX+1,
520 .flags = IORESOURCE_IRQ,
521 },
522 {
523 .start = IRQ_SPORT1_ERROR,
524 .end = IRQ_SPORT1_ERROR,
525 .flags = IORESOURCE_IRQ,
526 },
527};
528
a8b19886 529static unsigned short bfin_sport1_peripherals[] = {
df5de261 530 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
e54b6730 531 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
1394f032
BW		 532};
533
534static struct platform_device bfin_sport1_uart_device = {
535 .name = "bfin-sport-uart",
536 .id = 1,
df5de261
SZ		 537 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
538 .resource = bfin_sport1_uart_resources,
539 .dev = {
540 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
541 },
1394f032
BW		 542};
543#endif
df5de261 544#endif
1394f032
BW		 545
546#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
02460d08
SZ		 547#include <linux/bfin_mac.h>
548static const unsigned short bfin_mac_peripherals[] = P_MII0;
549
550static struct bfin_phydev_platform_data bfin_phydev_data[] = {
551 {
552 .addr = 1,
553 .irq = IRQ_MAC_PHYINT,
554 },
555};
556
557static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
558 .phydev_number = 1,
559 .phydev_data = bfin_phydev_data,
560 .phy_mode = PHY_INTERFACE_MODE_MII,
561 .mac_peripherals = bfin_mac_peripherals,
562};
563
65319628
GY		 564static struct platform_device bfin_mii_bus = {
565 .name = "bfin_mii_bus",
02460d08
SZ		 566 .dev = {
567 .platform_data = &bfin_mii_bus_data,
568 }
65319628
GY		 569};
570
1394f032
BW		 571static struct platform_device bfin_mac_device = {
572 .name = "bfin_mac",
02460d08
SZ		 573 .dev = {
574 .platform_data = &bfin_mii_bus,
575 }
1394f032
BW		 576};
577#endif
578
c6c4d7bb 579#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
fe5aeb93 580#define PATA_INT IRQ_PF14
c6c4d7bb
BW		 581
582static struct pata_platform_info bfin_pata_platform_data = {
583 .ioport_shift = 2,
7832bb5d 584 .irq_type = IRQF_TRIGGER_HIGH,
c6c4d7bb
BW		 585};
586
587static struct resource bfin_pata_resources[] = {
588 {
589 .start = 0x2030C000,
590 .end = 0x2030C01F,
591 .flags = IORESOURCE_MEM,
592 },
593 {
594 .start = 0x2030D018,
595 .end = 0x2030D01B,
596 .flags = IORESOURCE_MEM,
597 },
598 {
599 .start = PATA_INT,
600 .end = PATA_INT,
601 .flags = IORESOURCE_IRQ,
602 },
603};
604
605static struct platform_device bfin_pata_device = {
606 .name = "pata_platform",
607 .id = -1,
608 .num_resources = ARRAY_SIZE(bfin_pata_resources),
609 .resource = bfin_pata_resources,
610 .dev = {
611 .platform_data = &bfin_pata_platform_data,
612 }
613};
614#endif
615
14b03204
MH		 616static const unsigned int cclk_vlev_datasheet[] =
617{
618 VRPAIR(VLEV_085, 250000000),
619 VRPAIR(VLEV_090, 376000000),
620 VRPAIR(VLEV_095, 426000000),
621 VRPAIR(VLEV_100, 426000000),
622 VRPAIR(VLEV_105, 476000000),
623 VRPAIR(VLEV_110, 476000000),
624 VRPAIR(VLEV_115, 476000000),
625 VRPAIR(VLEV_120, 500000000),
626 VRPAIR(VLEV_125, 533000000),
627 VRPAIR(VLEV_130, 600000000),
628};
629
630static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
631 .tuple_tab = cclk_vlev_datasheet,
632 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
633 .vr_settling_time = 25 /* us */,
634};
635
636static struct platform_device bfin_dpmc = {
637 .name = "bfin dpmc",
638 .dev = {
639 .platform_data = &bfin_dmpc_vreg_data,
640 },
641};
642
60584344 643static struct platform_device *cm_bf537u_devices[] __initdata = {
14b03204
MH		 644
645 &bfin_dpmc,
646
0d4a89bb
MH		 647#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
648 &hitachi_fb_device,
649#endif
650
1394f032
BW		 651#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
652 &rtc_device,
653#endif
654
655#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
6bd1fbea
SZ		 656#ifdef CONFIG_SERIAL_BFIN_UART0
657 &bfin_uart0_device,
658#endif
659#ifdef CONFIG_SERIAL_BFIN_UART1
660 &bfin_uart1_device,
661#endif
1394f032
BW		 662#endif
663
5be36d22 664#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb
GY		 665#ifdef CONFIG_BFIN_SIR0
666 &bfin_sir0_device,
667#endif
668#ifdef CONFIG_BFIN_SIR1
669 &bfin_sir1_device,
670#endif
5be36d22
GY		 671#endif
672
56ce835b
MF		 673#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
674 &i2c_bfin_twi_device,
675#endif
676
1394f032 677#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
df5de261 678#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1394f032 679 &bfin_sport0_uart_device,
df5de261
SZ		 680#endif
681#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1394f032
BW		 682 &bfin_sport1_uart_device,
683#endif
df5de261 684#endif
1394f032
BW		 685
686#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
687 &isp1362_hcd_device,
688#endif
689
690#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
691 &smc91x_device,
692#endif
693
694#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628 695 &bfin_mii_bus,
1394f032
BW		 696 &bfin_mac_device,
697#endif
698
699#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
700 &net2272_bfin_device,
701#endif
702
703#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
c6c4d7bb
BW		 704 &bfin_spi0_device,
705#endif
706
707#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
708 &bfin_pata_device,
1394f032 709#endif
8ea89497
MF		 710
711#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
712 &cm_flash_device,
713#endif
1394f032
BW		 714};
715
9be8631b
MF		 716static int __init net2272_init(void)
717{
718#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
719 int ret;
720
721 ret = gpio_request(GPIO_PH15, driver_name);
722 if (ret)
723 return ret;
724
725 ret = gpio_request(GPIO_PH13, "net2272");
726 if (ret) {
727 gpio_free(GPIO_PH15);
728 return ret;
729 }
730
731 /* Set PH15 Low make /AMS2 work properly */
732 gpio_direction_output(GPIO_PH15, 0);
733
734 /* enable CLKBUF output */
735 bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
736
737 /* Reset the USB chip */
738 gpio_direction_output(GPIO_PH13, 0);
739 mdelay(2);
740 gpio_set_value(GPIO_PH13, 1);
741#endif
742
743 return 0;
744}
745
60584344 746static int __init cm_bf537u_init(void)
1394f032 747{
b85d858b 748 printk(KERN_INFO "%s(): registering device resources\n", __func__);
60584344 749 platform_add_devices(cm_bf537u_devices, ARRAY_SIZE(cm_bf537u_devices));
1394f032
BW		 750#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
751 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
752#endif
c6c4d7bb
BW		 753
754#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
bc2f6bd8 755 irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
c6c4d7bb 756#endif
9be8631b
MF		 757
758 if (net2272_init())
759 pr_warning("unable to configure net2272; it probably won't work\n");
760
1394f032
BW		 761 return 0;
762}
763
60584344 764arch_initcall(cm_bf537u_init);
137b1529 765
c13ce9fd
SZ		 766static struct platform_device *cm_bf537u_early_devices[] __initdata = {
767#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
768#ifdef CONFIG_SERIAL_BFIN_UART0
769 &bfin_uart0_device,
770#endif
771#ifdef CONFIG_SERIAL_BFIN_UART1
772 &bfin_uart1_device,
773#endif
774#endif
775
776#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
777#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
778 &bfin_sport0_uart_device,
779#endif
780#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
781 &bfin_sport1_uart_device,
782#endif
783#endif
784};
785
786void __init native_machine_early_platform_add_devices(void)
787{
788 printk(KERN_INFO "register early platform devices\n");
789 early_platform_add_devices(cm_bf537u_early_devices,
790 ARRAY_SIZE(cm_bf537u_early_devices));
791}
792
9862cc52 793void bfin_get_ether_addr(char *addr)
137b1529
MF		 794{
795 random_ether_addr(addr);
796 printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__);
797}
9862cc52 798EXPORT_SYMBOL(bfin_get_ether_addr);
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