[mirror_ubuntu-bionic-kernel.git] / arch / blackfin / mach-bf537 / boards / pnav10.c

/*
 * Copyright 2004-2009 Analog Devices Inc.
 *                2005 National ICT Australia (NICTA)
 *                      Aidan Williams <aidan@nicta.com.au>
 *
 * Licensed under the GPL-2 or later.
 */

#include <linux/device.h>
#include <linux/etherdevice.h>
#include <linux/export.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <linux/irq.h>
#include <asm/dma.h>
#include <asm/bfin5xx_spi.h>
#include <asm/portmux.h>

#include <linux/spi/ad7877.h>

/*
 * Name the Board for the /proc/cpuinfo
 */
const char bfin_board_name[] = "ADI PNAV-1.0";

/*
 *  Driver needs to know address, irq and flag pin.
 */

#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
static struct resource bfin_pcmcia_cf_resources[] = {
	{
		.start = 0x20310000, /* IO PORT */
		.end = 0x20312000,
		.flags = IORESOURCE_MEM,
	}, {
		.start = 0x20311000, /* Attribute Memory */
		.end = 0x20311FFF,
		.flags = IORESOURCE_MEM,
	}, {
		.start = IRQ_PF4,
		.end = IRQ_PF4,
		.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
	}, {
		.start = 6, /* Card Detect PF6 */
		.end = 6,
		.flags = IORESOURCE_IRQ,
	},
};

static struct platform_device bfin_pcmcia_cf_device = {
	.name = "bfin_cf_pcmcia",
	.id = -1,
	.num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
	.resource = bfin_pcmcia_cf_resources,
};
#endif

#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
static struct platform_device rtc_device = {
	.name = "rtc-bfin",
	.id   = -1,
};
#endif

#if IS_ENABLED(CONFIG_SMC91X)
#include <linux/smc91x.h>

static struct smc91x_platdata smc91x_info = {
	.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
	.leda = RPC_LED_100_10,
	.ledb = RPC_LED_TX_RX,
};

static struct resource smc91x_resources[] = {
	{
		.name = "smc91x-regs",
		.start = 0x20300300,
		.end = 0x20300300 + 16,
		.flags = IORESOURCE_MEM,
	}, {

		.start = IRQ_PF7,
		.end = IRQ_PF7,
		.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
	},
};
static struct platform_device smc91x_device = {
	.name = "smc91x",
	.id = 0,
	.num_resources = ARRAY_SIZE(smc91x_resources),
	.resource = smc91x_resources,
	.dev	= {
		.platform_data	= &smc91x_info,
	},
};
#endif

#if IS_ENABLED(CONFIG_BFIN_MAC)
#include <linux/bfin_mac.h>
static const unsigned short bfin_mac_peripherals[] = P_RMII0;

static struct bfin_phydev_platform_data bfin_phydev_data[] = {
	{
		.addr = 1,
		.irq = IRQ_MAC_PHYINT,
	},
};

static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
	.phydev_number = 1,
	.phydev_data = bfin_phydev_data,
	.phy_mode = PHY_INTERFACE_MODE_RMII,
	.mac_peripherals = bfin_mac_peripherals,
};

static struct platform_device bfin_mii_bus = {
	.name = "bfin_mii_bus",
	.dev = {
		.platform_data = &bfin_mii_bus_data,
	}
};

static struct platform_device bfin_mac_device = {
	.name = "bfin_mac",
	.dev = {
		.platform_data = &bfin_mii_bus,
	}
};
#endif

#if IS_ENABLED(CONFIG_USB_NET2272)
static struct resource net2272_bfin_resources[] = {
	{
		.start = 0x20300000,
		.end = 0x20300000 + 0x100,
		.flags = IORESOURCE_MEM,
	}, {
		.start = IRQ_PF7,
		.end = IRQ_PF7,
		.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
	},
};

static struct platform_device net2272_bfin_device = {
	.name = "net2272",
	.id = -1,
	.num_resources = ARRAY_SIZE(net2272_bfin_resources),
	.resource = net2272_bfin_resources,
};
#endif

#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
/* all SPI peripherals info goes here */

#if IS_ENABLED(CONFIG_MTD_M25P80)
static struct mtd_partition bfin_spi_flash_partitions[] = {
	{
		.name = "bootloader(spi)",
		.size = 0x00020000,
		.offset = 0,
		.mask_flags = MTD_CAP_ROM
	}, {
		.name = "linux kernel(spi)",
		.size = 0xe0000,
		.offset = 0x20000
	}, {
		.name = "file system(spi)",
		.size = 0x700000,
		.offset = 0x00100000,
	}
};

static struct flash_platform_data bfin_spi_flash_data = {
	.name = "m25p80",
	.parts = bfin_spi_flash_partitions,
	.nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
	.type = "m25p64",
};

/* SPI flash chip (m25p64) */
static struct bfin5xx_spi_chip spi_flash_chip_info = {
	.enable_dma = 0,         /* use dma transfer with this chip*/
};
#endif

#if IS_ENABLED(CONFIG_MMC_SPI)
static struct bfin5xx_spi_chip mmc_spi_chip_info = {
	.enable_dma = 0,
};
#endif

#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
static const struct ad7877_platform_data bfin_ad7877_ts_info = {
	.model			= 7877,
	.vref_delay_usecs	= 50,	/* internal, no capacitor */
	.x_plate_ohms		= 419,
	.y_plate_ohms		= 486,
	.pressure_max		= 1000,
	.pressure_min		= 0,
	.stopacq_polarity 	= 1,
	.first_conversion_delay = 3,
	.acquisition_time 	= 1,
	.averaging 		= 1,
	.pen_down_acc_interval 	= 1,
};
#endif

static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if IS_ENABLED(CONFIG_MTD_M25P80)
	{
		/* the modalias must be the same as spi device driver name */
		.modalias = "m25p80", /* Name of spi_driver for this device */
		.max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
		.bus_num = 0, /* Framework bus number */
		.chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
		.platform_data = &bfin_spi_flash_data,
		.controller_data = &spi_flash_chip_info,
		.mode = SPI_MODE_3,
	},
#endif

#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
	{
		.modalias = "ad183x",
		.max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
		.bus_num = 0,
		.chip_select = 4,
	},
#endif
#if IS_ENABLED(CONFIG_MMC_SPI)
	{
		.modalias = "mmc_spi",
		.max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
		.bus_num = 0,
		.chip_select = 5,
		.controller_data = &mmc_spi_chip_info,
		.mode = SPI_MODE_3,
	},
#endif
#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
{
	.modalias		= "ad7877",
	.platform_data		= &bfin_ad7877_ts_info,
	.irq			= IRQ_PF2,
	.max_speed_hz		= 12500000,     /* max spi clock (SCK) speed in HZ */
	.bus_num		= 0,
	.chip_select  		= 5,
},
#endif

};

/* SPI (0) */
static struct resource bfin_spi0_resource[] = {
	[0] = {
		.start = SPI0_REGBASE,
		.end   = SPI0_REGBASE + 0xFF,
		.flags = IORESOURCE_MEM,
		},
	[1] = {
		.start = CH_SPI,
		.end   = CH_SPI,
		.flags = IORESOURCE_DMA,
	},
	[2] = {
		.start = IRQ_SPI,
		.end   = IRQ_SPI,
		.flags = IORESOURCE_IRQ,
	},
};

/* SPI controller data */
static struct bfin5xx_spi_master bfin_spi0_info = {
	.num_chipselect = 8,
	.enable_dma = 1,  /* master has the ability to do dma transfer */
	.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
};

static struct platform_device bfin_spi0_device = {
	.name = "bfin-spi",
	.id = 0, /* Bus number */
	.num_resources = ARRAY_SIZE(bfin_spi0_resource),
	.resource = bfin_spi0_resource,
	.dev = {
		.platform_data = &bfin_spi0_info, /* Passed to driver */
	},
};
#endif  /* spi master and devices */

#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
static struct platform_device bfin_fb_device = {
	.name = "bf537-lq035",
};
#endif

#if IS_ENABLED(CONFIG_SERIAL_BFIN)
#ifdef CONFIG_SERIAL_BFIN_UART0
static struct resource bfin_uart0_resources[] = {
	{
		.start = UART0_THR,
		.end = UART0_GCTL+2,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = IRQ_UART0_TX,
		.end = IRQ_UART0_TX,
		.flags = IORESOURCE_IRQ,
	},
	{
		.start = IRQ_UART0_RX,
		.end = IRQ_UART0_RX,
		.flags = IORESOURCE_IRQ,
	},
	{
		.start = IRQ_UART0_ERROR,
		.end = IRQ_UART0_ERROR,
		.flags = IORESOURCE_IRQ,
	},
	{
		.start = CH_UART0_TX,
		.end = CH_UART0_TX,
		.flags = IORESOURCE_DMA,
	},
	{
		.start = CH_UART0_RX,
		.end = CH_UART0_RX,
		.flags = IORESOURCE_DMA,
	},
};

static unsigned short bfin_uart0_peripherals[] = {
	P_UART0_TX, P_UART0_RX, 0
};

static struct platform_device bfin_uart0_device = {
	.name = "bfin-uart",
	.id = 0,
	.num_resources = ARRAY_SIZE(bfin_uart0_resources),
	.resource = bfin_uart0_resources,
	.dev = {
		.platform_data = &bfin_uart0_peripherals, /* Passed to driver */
	},
};
#endif
#ifdef CONFIG_SERIAL_BFIN_UART1
static struct resource bfin_uart1_resources[] = {
	{
		.start = UART1_THR,
		.end = UART1_GCTL+2,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = IRQ_UART1_TX,
		.end = IRQ_UART1_TX,
		.flags = IORESOURCE_IRQ,
	},
	{
		.start = IRQ_UART1_RX,
		.end = IRQ_UART1_RX,
		.flags = IORESOURCE_IRQ,
	},
	{
		.start = IRQ_UART1_ERROR,
		.end = IRQ_UART1_ERROR,
		.flags = IORESOURCE_IRQ,
	},
	{
		.start = CH_UART1_TX,
		.end = CH_UART1_TX,
		.flags = IORESOURCE_DMA,
	},
	{
		.start = CH_UART1_RX,
		.end = CH_UART1_RX,
		.flags = IORESOURCE_DMA,
	},
};

static unsigned short bfin_uart1_peripherals[] = {
	P_UART1_TX, P_UART1_RX, 0
};

static struct platform_device bfin_uart1_device = {
	.name = "bfin-uart",
	.id = 1,
	.num_resources = ARRAY_SIZE(bfin_uart1_resources),
	.resource = bfin_uart1_resources,
	.dev = {
		.platform_data = &bfin_uart1_peripherals, /* Passed to driver */
	},
};
#endif
#endif

#if IS_ENABLED(CONFIG_BFIN_SIR)
#ifdef CONFIG_BFIN_SIR0
static struct resource bfin_sir0_resources[] = {
	{
		.start = 0xFFC00400,
		.end = 0xFFC004FF,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = IRQ_UART0_RX,
		.end = IRQ_UART0_RX+1,
		.flags = IORESOURCE_IRQ,
	},
	{
		.start = CH_UART0_RX,
		.end = CH_UART0_RX+1,
		.flags = IORESOURCE_DMA,
	},
};

static struct platform_device bfin_sir0_device = {
	.name = "bfin_sir",
	.id = 0,
	.num_resources = ARRAY_SIZE(bfin_sir0_resources),
	.resource = bfin_sir0_resources,
};
#endif
#ifdef CONFIG_BFIN_SIR1
static struct resource bfin_sir1_resources[] = {
	{
		.start = 0xFFC02000,
		.end = 0xFFC020FF,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = IRQ_UART1_RX,
		.end = IRQ_UART1_RX+1,
		.flags = IORESOURCE_IRQ,
	},
	{
		.start = CH_UART1_RX,
		.end = CH_UART1_RX+1,
		.flags = IORESOURCE_DMA,
	},
};

static struct platform_device bfin_sir1_device = {
	.name = "bfin_sir",
	.id = 1,
	.num_resources = ARRAY_SIZE(bfin_sir1_resources),
	.resource = bfin_sir1_resources,
};
#endif
#endif

static struct platform_device *stamp_devices[] __initdata = {
#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
	&bfin_pcmcia_cf_device,
#endif

#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
	&rtc_device,
#endif

#if IS_ENABLED(CONFIG_SMC91X)
	&smc91x_device,
#endif

#if IS_ENABLED(CONFIG_BFIN_MAC)
	&bfin_mii_bus,
	&bfin_mac_device,
#endif

#if IS_ENABLED(CONFIG_USB_NET2272)
	&net2272_bfin_device,
#endif

#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
	&bfin_spi0_device,
#endif

#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
	&bfin_fb_device,
#endif

#if IS_ENABLED(CONFIG_SERIAL_BFIN)
#ifdef CONFIG_SERIAL_BFIN_UART0
	&bfin_uart0_device,
#endif
#ifdef CONFIG_SERIAL_BFIN_UART1
	&bfin_uart1_device,
#endif
#endif

#if IS_ENABLED(CONFIG_BFIN_SIR)
#ifdef CONFIG_BFIN_SIR0
	&bfin_sir0_device,
#endif
#ifdef CONFIG_BFIN_SIR1
	&bfin_sir1_device,
#endif
#endif
};

static int __init pnav_init(void)
{
	printk(KERN_INFO "%s(): registering device resources\n", __func__);
	platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
	spi_register_board_info(bfin_spi_board_info,
				ARRAY_SIZE(bfin_spi_board_info));
#endif
	return 0;
}

arch_initcall(pnav_init);

static struct platform_device *stamp_early_devices[] __initdata = {
#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
#ifdef CONFIG_SERIAL_BFIN_UART0
	&bfin_uart0_device,
#endif
#ifdef CONFIG_SERIAL_BFIN_UART1
	&bfin_uart1_device,
#endif
#endif
};

void __init native_machine_early_platform_add_devices(void)
{
	printk(KERN_INFO "register early platform devices\n");
	early_platform_add_devices(stamp_early_devices,
		ARRAY_SIZE(stamp_early_devices));
}

int bfin_get_ether_addr(char *addr)
{
	return 1;
}
EXPORT_SYMBOL(bfin_get_ether_addr);
Commit	Line	Data
1394f032	1	/*
96f1050d RG	2	* Copyright 2004-2009 Analog Devices Inc.
	3	* 2005 National ICT Australia (NICTA)
	4	* Aidan Williams <aidan@nicta.com.au>
1394f032	5	*
96f1050d	6	* Licensed under the GPL-2 or later.
1394f032 BW	7	*/
	8
	9	#include <linux/device.h>
43f73fef	10	#include <linux/etherdevice.h>
90590543	11	#include <linux/export.h>
1394f032 BW	12	#include <linux/platform_device.h>
	13	#include <linux/mtd/mtd.h>
	14	#include <linux/mtd/partitions.h>
	15	#include <linux/spi/spi.h>
	16	#include <linux/spi/flash.h>
1f83b8f1	17	#include <linux/irq.h>
c6c4d7bb	18	#include <asm/dma.h>
1394f032	19	#include <asm/bfin5xx_spi.h>
5d448dd5	20	#include <asm/portmux.h>
1394f032 BW	21
	22	#include <linux/spi/ad7877.h>
	23
	24	/*
	25	* Name the Board for the /proc/cpuinfo
	26	*/
fe85cad2	27	const char bfin_board_name[] = "ADI PNAV-1.0";
1394f032 BW	28
	29	/*
	30	* Driver needs to know address, irq and flag pin.
	31	*/
	32
c4a2c58d	33	#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
1394f032 BW	34	static struct resource bfin_pcmcia_cf_resources[] = {
	35	{
	36	.start = 0x20310000, /* IO PORT */
	37	.end = 0x20312000,
	38	.flags = IORESOURCE_MEM,
1f83b8f1	39	}, {
d2d50aa9	40	.start = 0x20311000, /* Attribute Memory */
1394f032 BW	41	.end = 0x20311FFF,
1394f032 BW	42	.flags = IORESOURCE_MEM,
1f83b8f1	43	}, {
1394f032 BW	44	.start = IRQ_PF4,
	45	.end = IRQ_PF4,
	46	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_LOWLEVEL,
1f83b8f1	47	}, {
1394f032 BW	48	.start = 6, /* Card Detect PF6 */
	49	.end = 6,
	50	.flags = IORESOURCE_IRQ,
	51	},
	52	};
	53
	54	static struct platform_device bfin_pcmcia_cf_device = {
	55	.name = "bfin_cf_pcmcia",
	56	.id = -1,
	57	.num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
	58	.resource = bfin_pcmcia_cf_resources,
	59	};
	60	#endif
	61
c4a2c58d	62	#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
1394f032 BW	63	static struct platform_device rtc_device = {
	64	.name = "rtc-bfin",
	65	.id = -1,
	66	};
	67	#endif
	68
c4a2c58d	69	#if IS_ENABLED(CONFIG_SMC91X)
61f09b5a MH	70	#include <linux/smc91x.h>
	71
	72	static struct smc91x_platdata smc91x_info = {
	73	.flags = SMC91X_USE_16BIT \| SMC91X_NOWAIT,
	74	.leda = RPC_LED_100_10,
	75	.ledb = RPC_LED_TX_RX,
	76	};
	77
1394f032 BW	78	static struct resource smc91x_resources[] = {
	79	{
	80	.name = "smc91x-regs",
	81	.start = 0x20300300,
	82	.end = 0x20300300 + 16,
	83	.flags = IORESOURCE_MEM,
1f83b8f1	84	}, {
1394f032 BW	85
	86	.start = IRQ_PF7,
	87	.end = IRQ_PF7,
	88	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHLEVEL,
	89	},
	90	};
	91	static struct platform_device smc91x_device = {
	92	.name = "smc91x",
	93	.id = 0,
	94	.num_resources = ARRAY_SIZE(smc91x_resources),
	95	.resource = smc91x_resources,
61f09b5a MH	96	.dev = {
	97	.platform_data = &smc91x_info,
	98	},
1394f032 BW	99	};
	100	#endif
	101
c4a2c58d	102	#if IS_ENABLED(CONFIG_BFIN_MAC)
02460d08 SZ	103	#include <linux/bfin_mac.h>
	104	static const unsigned short bfin_mac_peripherals[] = P_RMII0;
	105
	106	static struct bfin_phydev_platform_data bfin_phydev_data[] = {
	107	{
	108	.addr = 1,
	109	.irq = IRQ_MAC_PHYINT,
	110	},
	111	};
	112
	113	static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
	114	.phydev_number = 1,
	115	.phydev_data = bfin_phydev_data,
	116	.phy_mode = PHY_INTERFACE_MODE_RMII,
	117	.mac_peripherals = bfin_mac_peripherals,
	118	};
	119
65319628 GY	120	static struct platform_device bfin_mii_bus = {
65319628 GY	121	.name = "bfin_mii_bus",
02460d08 SZ	122	.dev = {
	123	.platform_data = &bfin_mii_bus_data,
	124	}
65319628 GY	125	};
65319628 GY	126
1394f032 BW	127	static struct platform_device bfin_mac_device = {
1394f032 BW	128	.name = "bfin_mac",
02460d08 SZ	129	.dev = {
	130	.platform_data = &bfin_mii_bus,
	131	}
1394f032 BW	132	};
	133	#endif
	134
c4a2c58d	135	#if IS_ENABLED(CONFIG_USB_NET2272)
1394f032 BW	136	static struct resource net2272_bfin_resources[] = {
	137	{
	138	.start = 0x20300000,
	139	.end = 0x20300000 + 0x100,
	140	.flags = IORESOURCE_MEM,
1f83b8f1	141	}, {
1394f032 BW	142	.start = IRQ_PF7,
	143	.end = IRQ_PF7,
	144	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHLEVEL,
	145	},
	146	};
	147
	148	static struct platform_device net2272_bfin_device = {
	149	.name = "net2272",
	150	.id = -1,
	151	.num_resources = ARRAY_SIZE(net2272_bfin_resources),
	152	.resource = net2272_bfin_resources,
	153	};
	154	#endif
	155
c4a2c58d	156	#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
1394f032 BW	157	/* all SPI peripherals info goes here */
1394f032 BW	158
c4a2c58d	159	#if IS_ENABLED(CONFIG_MTD_M25P80)
1394f032 BW	160	static struct mtd_partition bfin_spi_flash_partitions[] = {
1394f032 BW	161	{
aa582977	162	.name = "bootloader(spi)",
1394f032 BW	163	.size = 0x00020000,
	164	.offset = 0,
	165	.mask_flags = MTD_CAP_ROM
1f83b8f1	166	}, {
aa582977	167	.name = "linux kernel(spi)",
1394f032 BW	168	.size = 0xe0000,
1394f032 BW	169	.offset = 0x20000
1f83b8f1	170	}, {
aa582977	171	.name = "file system(spi)",
1394f032 BW	172	.size = 0x700000,
	173	.offset = 0x00100000,
	174	}
	175	};
	176
	177	static struct flash_platform_data bfin_spi_flash_data = {
	178	.name = "m25p80",
	179	.parts = bfin_spi_flash_partitions,
	180	.nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
	181	.type = "m25p64",
	182	};
	183
	184	/* SPI flash chip (m25p64) */
	185	static struct bfin5xx_spi_chip spi_flash_chip_info = {
	186	.enable_dma = 0, /* use dma transfer with this chip*/
1394f032 BW	187	};
	188	#endif
	189
c4a2c58d	190	#if IS_ENABLED(CONFIG_MMC_SPI)
f3f704d3 MH	191	static struct bfin5xx_spi_chip mmc_spi_chip_info = {
f3f704d3 MH	192	.enable_dma = 0,
1394f032 BW	193	};
	194	#endif
	195
c4a2c58d	196	#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
1394f032 BW	197	static const struct ad7877_platform_data bfin_ad7877_ts_info = {
	198	.model = 7877,
	199	.vref_delay_usecs = 50, /* internal, no capacitor */
	200	.x_plate_ohms = 419,
	201	.y_plate_ohms = 486,
	202	.pressure_max = 1000,
	203	.pressure_min = 0,
	204	.stopacq_polarity = 1,
	205	.first_conversion_delay = 3,
	206	.acquisition_time = 1,
	207	.averaging = 1,
	208	.pen_down_acc_interval = 1,
	209	};
	210	#endif
	211
	212	static struct spi_board_info bfin_spi_board_info[] __initdata = {
c4a2c58d	213	#if IS_ENABLED(CONFIG_MTD_M25P80)
1394f032 BW	214	{
	215	/* the modalias must be the same as spi device driver name */
	216	.modalias = "m25p80", /* Name of spi_driver for this device */
	217	.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb	218	.bus_num = 0, /* Framework bus number */
1394f032 BW	219	.chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
	220	.platform_data = &bfin_spi_flash_data,
	221	.controller_data = &spi_flash_chip_info,
	222	.mode = SPI_MODE_3,
	223	},
	224	#endif
	225
c4a2c58d	226	#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
1394f032	227	{
7ba80063	228	.modalias = "ad183x",
1394f032	229	.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb	230	.bus_num = 0,
7ba80063	231	.chip_select = 4,
1394f032 BW	232	},
1394f032 BW	233	#endif
c4a2c58d	234	#if IS_ENABLED(CONFIG_MMC_SPI)
1394f032	235	{
f3f704d3	236	.modalias = "mmc_spi",
1394f032	237	.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb	238	.bus_num = 0,
f3f704d3 MH	239	.chip_select = 5,
f3f704d3 MH	240	.controller_data = &mmc_spi_chip_info,
1394f032 BW	241	.mode = SPI_MODE_3,
	242	},
	243	#endif
c4a2c58d	244	#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
1394f032 BW	245	{
	246	.modalias = "ad7877",
	247	.platform_data = &bfin_ad7877_ts_info,
	248	.irq = IRQ_PF2,
	249	.max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
c7d48966	250	.bus_num = 0,
1394f032	251	.chip_select = 5,
1394f032 BW	252	},
	253	#endif
	254
	255	};
	256
c6c4d7bb BW	257	/* SPI (0) */
	258	static struct resource bfin_spi0_resource[] = {
	259	[0] = {
	260	.start = SPI0_REGBASE,
	261	.end = SPI0_REGBASE + 0xFF,
	262	.flags = IORESOURCE_MEM,
	263	},
	264	[1] = {
	265	.start = CH_SPI,
	266	.end = CH_SPI,
53122693 YL	267	.flags = IORESOURCE_DMA,
	268	},
	269	[2] = {
	270	.start = IRQ_SPI,
	271	.end = IRQ_SPI,
c6c4d7bb	272	.flags = IORESOURCE_IRQ,
53122693	273	},
c6c4d7bb BW	274	};
c6c4d7bb BW	275
1394f032	276	/* SPI controller data */
c6c4d7bb	277	static struct bfin5xx_spi_master bfin_spi0_info = {
1394f032 BW	278	.num_chipselect = 8,
1394f032 BW	279	.enable_dma = 1, /* master has the ability to do dma transfer */
5d448dd5	280	.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1394f032 BW	281	};
1394f032 BW	282
c6c4d7bb BW	283	static struct platform_device bfin_spi0_device = {
	284	.name = "bfin-spi",
	285	.id = 0, /* Bus number */
	286	.num_resources = ARRAY_SIZE(bfin_spi0_resource),
	287	.resource = bfin_spi0_resource,
1394f032	288	.dev = {
c6c4d7bb	289	.platform_data = &bfin_spi0_info, /* Passed to driver */
1394f032 BW	290	},
	291	};
	292	#endif /* spi master and devices */
	293
c4a2c58d	294	#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
1394f032	295	static struct platform_device bfin_fb_device = {
c6c4d7bb	296	.name = "bf537-lq035",
1394f032 BW	297	};
	298	#endif
	299
c4a2c58d	300	#if IS_ENABLED(CONFIG_SERIAL_BFIN)
6bd1fbea SZ	301	#ifdef CONFIG_SERIAL_BFIN_UART0
6bd1fbea SZ	302	static struct resource bfin_uart0_resources[] = {
1394f032	303	{
6bd1fbea SZ	304	.start = UART0_THR,
6bd1fbea SZ	305	.end = UART0_GCTL+2,
1394f032	306	.flags = IORESOURCE_MEM,
6bd1fbea	307	},
edb0a640 SZ	308	{
	309	.start = IRQ_UART0_TX,
	310	.end = IRQ_UART0_TX,
	311	.flags = IORESOURCE_IRQ,
	312	},
6bd1fbea SZ	313	{
6bd1fbea SZ	314	.start = IRQ_UART0_RX,
edb0a640	315	.end = IRQ_UART0_RX,
6bd1fbea SZ	316	.flags = IORESOURCE_IRQ,
	317	},
	318	{
	319	.start = IRQ_UART0_ERROR,
	320	.end = IRQ_UART0_ERROR,
	321	.flags = IORESOURCE_IRQ,
	322	},
	323	{
	324	.start = CH_UART0_TX,
	325	.end = CH_UART0_TX,
	326	.flags = IORESOURCE_DMA,
	327	},
	328	{
	329	.start = CH_UART0_RX,
	330	.end = CH_UART0_RX,
	331	.flags = IORESOURCE_DMA,
	332	},
	333	};
	334
a8b19886	335	static unsigned short bfin_uart0_peripherals[] = {
6bd1fbea SZ	336	P_UART0_TX, P_UART0_RX, 0
	337	};
	338
	339	static struct platform_device bfin_uart0_device = {
	340	.name = "bfin-uart",
	341	.id = 0,
	342	.num_resources = ARRAY_SIZE(bfin_uart0_resources),
	343	.resource = bfin_uart0_resources,
	344	.dev = {
	345	.platform_data = &bfin_uart0_peripherals, /* Passed to driver */
	346	},
	347	};
	348	#endif
	349	#ifdef CONFIG_SERIAL_BFIN_UART1
	350	static struct resource bfin_uart1_resources[] = {
	351	{
	352	.start = UART1_THR,
	353	.end = UART1_GCTL+2,
1394f032 BW	354	.flags = IORESOURCE_MEM,
1394f032 BW	355	},
edb0a640 SZ	356	{
	357	.start = IRQ_UART1_TX,
	358	.end = IRQ_UART1_TX,
	359	.flags = IORESOURCE_IRQ,
	360	},
6bd1fbea SZ	361	{
6bd1fbea SZ	362	.start = IRQ_UART1_RX,
edb0a640	363	.end = IRQ_UART1_RX,
6bd1fbea SZ	364	.flags = IORESOURCE_IRQ,
	365	},
	366	{
	367	.start = IRQ_UART1_ERROR,
	368	.end = IRQ_UART1_ERROR,
	369	.flags = IORESOURCE_IRQ,
	370	},
	371	{
	372	.start = CH_UART1_TX,
	373	.end = CH_UART1_TX,
	374	.flags = IORESOURCE_DMA,
	375	},
	376	{
	377	.start = CH_UART1_RX,
	378	.end = CH_UART1_RX,
	379	.flags = IORESOURCE_DMA,
	380	},
1394f032 BW	381	};
1394f032 BW	382
a8b19886	383	static unsigned short bfin_uart1_peripherals[] = {
6bd1fbea SZ	384	P_UART1_TX, P_UART1_RX, 0
	385	};
	386
	387	static struct platform_device bfin_uart1_device = {
1394f032 BW	388	.name = "bfin-uart",
1394f032 BW	389	.id = 1,
6bd1fbea SZ	390	.num_resources = ARRAY_SIZE(bfin_uart1_resources),
	391	.resource = bfin_uart1_resources,
	392	.dev = {
	393	.platform_data = &bfin_uart1_peripherals, /* Passed to driver */
	394	},
1394f032 BW	395	};
1394f032 BW	396	#endif
6bd1fbea	397	#endif
1394f032	398
c4a2c58d	399	#if IS_ENABLED(CONFIG_BFIN_SIR)
5be36d22	400	#ifdef CONFIG_BFIN_SIR0
42bd8bcb	401	static struct resource bfin_sir0_resources[] = {
5be36d22 GY	402	{
	403	.start = 0xFFC00400,
	404	.end = 0xFFC004FF,
	405	.flags = IORESOURCE_MEM,
	406	},
42bd8bcb GY	407	{
	408	.start = IRQ_UART0_RX,
	409	.end = IRQ_UART0_RX+1,
	410	.flags = IORESOURCE_IRQ,
	411	},
	412	{
	413	.start = CH_UART0_RX,
	414	.end = CH_UART0_RX+1,
	415	.flags = IORESOURCE_DMA,
	416	},
	417	};
	418
	419	static struct platform_device bfin_sir0_device = {
	420	.name = "bfin_sir",
	421	.id = 0,
	422	.num_resources = ARRAY_SIZE(bfin_sir0_resources),
	423	.resource = bfin_sir0_resources,
	424	};
5be36d22 GY	425	#endif
5be36d22 GY	426	#ifdef CONFIG_BFIN_SIR1
42bd8bcb	427	static struct resource bfin_sir1_resources[] = {
5be36d22 GY	428	{
	429	.start = 0xFFC02000,
	430	.end = 0xFFC020FF,
	431	.flags = IORESOURCE_MEM,
	432	},
42bd8bcb GY	433	{
	434	.start = IRQ_UART1_RX,
	435	.end = IRQ_UART1_RX+1,
	436	.flags = IORESOURCE_IRQ,
	437	},
	438	{
	439	.start = CH_UART1_RX,
	440	.end = CH_UART1_RX+1,
	441	.flags = IORESOURCE_DMA,
	442	},
5be36d22 GY	443	};
5be36d22 GY	444
42bd8bcb	445	static struct platform_device bfin_sir1_device = {
5be36d22	446	.name = "bfin_sir",
42bd8bcb GY	447	.id = 1,
	448	.num_resources = ARRAY_SIZE(bfin_sir1_resources),
	449	.resource = bfin_sir1_resources,
5be36d22 GY	450	};
5be36d22 GY	451	#endif
42bd8bcb	452	#endif
1394f032 BW	453
1394f032 BW	454	static struct platform_device *stamp_devices[] __initdata = {
c4a2c58d	455	#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
1394f032 BW	456	&bfin_pcmcia_cf_device,
	457	#endif
	458
c4a2c58d	459	#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
1394f032 BW	460	&rtc_device,
	461	#endif
	462
c4a2c58d	463	#if IS_ENABLED(CONFIG_SMC91X)
1394f032 BW	464	&smc91x_device,
	465	#endif
	466
c4a2c58d	467	#if IS_ENABLED(CONFIG_BFIN_MAC)
65319628	468	&bfin_mii_bus,
1394f032 BW	469	&bfin_mac_device,
	470	#endif
	471
c4a2c58d	472	#if IS_ENABLED(CONFIG_USB_NET2272)
1394f032 BW	473	&net2272_bfin_device,
	474	#endif
	475
c4a2c58d	476	#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
c6c4d7bb	477	&bfin_spi0_device,
1394f032 BW	478	#endif
1394f032 BW	479
c4a2c58d	480	#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
1394f032 BW	481	&bfin_fb_device,
	482	#endif
	483
c4a2c58d	484	#if IS_ENABLED(CONFIG_SERIAL_BFIN)
6bd1fbea SZ	485	#ifdef CONFIG_SERIAL_BFIN_UART0
	486	&bfin_uart0_device,
	487	#endif
	488	#ifdef CONFIG_SERIAL_BFIN_UART1
	489	&bfin_uart1_device,
	490	#endif
1394f032	491	#endif
5be36d22	492
c4a2c58d	493	#if IS_ENABLED(CONFIG_BFIN_SIR)
42bd8bcb GY	494	#ifdef CONFIG_BFIN_SIR0
	495	&bfin_sir0_device,
	496	#endif
	497	#ifdef CONFIG_BFIN_SIR1
	498	&bfin_sir1_device,
	499	#endif
5be36d22	500	#endif
1394f032 BW	501	};
1394f032 BW	502
7f6678c5	503	static int __init pnav_init(void)
1394f032	504	{
b85d858b	505	printk(KERN_INFO "%s(): registering device resources\n", __func__);
1394f032	506	platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
c4a2c58d	507	#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
1394f032 BW	508	spi_register_board_info(bfin_spi_board_info,
	509	ARRAY_SIZE(bfin_spi_board_info));
	510	#endif
	511	return 0;
	512	}
	513
7f6678c5	514	arch_initcall(pnav_init);
137b1529	515
c13ce9fd SZ	516	static struct platform_device *stamp_early_devices[] __initdata = {
	517	#if defined(CONFIG_SERIAL_BFIN_CONSOLE) \|\| defined(CONFIG_EARLY_PRINTK)
	518	#ifdef CONFIG_SERIAL_BFIN_UART0
	519	&bfin_uart0_device,
	520	#endif
	521	#ifdef CONFIG_SERIAL_BFIN_UART1
	522	&bfin_uart1_device,
	523	#endif
	524	#endif
	525	};
	526
	527	void __init native_machine_early_platform_add_devices(void)
	528	{
	529	printk(KERN_INFO "register early platform devices\n");
	530	early_platform_add_devices(stamp_early_devices,
	531	ARRAY_SIZE(stamp_early_devices));
	532	}
	533
0eceb82f	534	int bfin_get_ether_addr(char *addr)
137b1529	535	{
0eceb82f	536	return 1;
137b1529	537	}
9862cc52	538	EXPORT_SYMBOL(bfin_get_ether_addr);