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Merge branch 'tip/perf/core' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt...
[mirror_ubuntu-eoan-kernel.git] / arch / blackfin / mach-bf537 / boards / tcm_bf537.c
CommitLineData
b9da3b92 1/*
96f1050d
RG		 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2008-2009 Bluetechnix
4 * 2005 National ICT Australia (NICTA)
5 * Aidan Williams <aidan@nicta.com.au>
b9da3b92 6 *
96f1050d 7 * Licensed under the GPL-2 or later.
b9da3b92
MF		 8 */
9
10#include <linux/device.h>
11#include <linux/etherdevice.h>
90590543 12#include <linux/export.h>
b9da3b92
MF		 13#include <linux/platform_device.h>
14#include <linux/mtd/mtd.h>
15#include <linux/mtd/partitions.h>
16#include <linux/mtd/physmap.h>
17#include <linux/spi/spi.h>
18#include <linux/spi/flash.h>
19#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
20#include <linux/usb/isp1362.h>
21#endif
22#include <linux/ata_platform.h>
23#include <linux/irq.h>
24#include <asm/dma.h>
25#include <asm/bfin5xx_spi.h>
26#include <asm/portmux.h>
27#include <asm/dpmc.h>
9c21453e 28#include <linux/spi/mmc_spi.h>
b9da3b92
MF		 29
30/*
31 * Name the Board for the /proc/cpuinfo
32 */
33const char bfin_board_name[] = "Bluetechnix TCM BF537";
34
35#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
36/* all SPI peripherals info goes here */
37
38#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
39static struct mtd_partition bfin_spi_flash_partitions[] = {
40 {
41 .name = "bootloader(spi)",
42 .size = 0x00020000,
43 .offset = 0,
44 .mask_flags = MTD_CAP_ROM
45 }, {
46 .name = "linux kernel(spi)",
47 .size = 0xe0000,
48 .offset = 0x20000
49 }, {
50 .name = "file system(spi)",
51 .size = 0x700000,
52 .offset = 0x00100000,
53 }
54};
55
56static struct flash_platform_data bfin_spi_flash_data = {
57 .name = "m25p80",
58 .parts = bfin_spi_flash_partitions,
59 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
60 .type = "m25p64",
61};
62
63/* SPI flash chip (m25p64) */
64static struct bfin5xx_spi_chip spi_flash_chip_info = {
65 .enable_dma = 0, /* use dma transfer with this chip*/
b9da3b92
MF		 66};
67#endif
68
f3f704d3
MH		 69#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
70static struct bfin5xx_spi_chip mmc_spi_chip_info = {
71 .enable_dma = 0,
b9da3b92
MF		 72};
73#endif
74
75static struct spi_board_info bfin_spi_board_info[] __initdata = {
76#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
77 {
78 /* the modalias must be the same as spi device driver name */
79 .modalias = "m25p80", /* Name of spi_driver for this device */
80 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
81 .bus_num = 0, /* Framework bus number */
82 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
83 .platform_data = &bfin_spi_flash_data,
84 .controller_data = &spi_flash_chip_info,
85 .mode = SPI_MODE_3,
86 },
87#endif
88
7ba80063 89#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
b9da3b92 90 {
7ba80063 91 .modalias = "ad183x",
b9da3b92
MF		 92 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
93 .bus_num = 0,
7ba80063 94 .chip_select = 4,
b9da3b92
MF		 95 },
96#endif
97
f3f704d3 98#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
b9da3b92 99 {
f3f704d3 100 .modalias = "mmc_spi",
b9da3b92
MF		 101 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
102 .bus_num = 0,
9c21453e 103 .chip_select = 1,
f3f704d3 104 .controller_data = &mmc_spi_chip_info,
b9da3b92
MF		 105 .mode = SPI_MODE_3,
106 },
107#endif
108};
109
110/* SPI (0) */
111static struct resource bfin_spi0_resource[] = {
112 [0] = {
113 .start = SPI0_REGBASE,
114 .end = SPI0_REGBASE + 0xFF,
115 .flags = IORESOURCE_MEM,
116 },
117 [1] = {
118 .start = CH_SPI,
119 .end = CH_SPI,
53122693
YL		 120 .flags = IORESOURCE_DMA,
121 },
122 [2] = {
123 .start = IRQ_SPI,
124 .end = IRQ_SPI,
b9da3b92
MF		 125 .flags = IORESOURCE_IRQ,
126 }
127};
128
129/* SPI controller data */
130static struct bfin5xx_spi_master bfin_spi0_info = {
131 .num_chipselect = 8,
132 .enable_dma = 1, /* master has the ability to do dma transfer */
133 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
134};
135
136static struct platform_device bfin_spi0_device = {
137 .name = "bfin-spi",
138 .id = 0, /* Bus number */
139 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
140 .resource = bfin_spi0_resource,
141 .dev = {
142 .platform_data = &bfin_spi0_info, /* Passed to driver */
143 },
144};
145#endif /* spi master and devices */
146
147#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
148static struct platform_device rtc_device = {
149 .name = "rtc-bfin",
150 .id = -1,
151};
152#endif
153
154#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
155static struct platform_device hitachi_fb_device = {
156 .name = "hitachi-tx09",
157};
158#endif
159
160#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
61f09b5a
MH		 161#include <linux/smc91x.h>
162
163static struct smc91x_platdata smc91x_info = {
164 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
165 .leda = RPC_LED_100_10,
166 .ledb = RPC_LED_TX_RX,
167};
168
b9da3b92
MF		 169static struct resource smc91x_resources[] = {
170 {
171 .start = 0x20200300,
172 .end = 0x20200300 + 16,
173 .flags = IORESOURCE_MEM,
174 }, {
175 .start = IRQ_PF14,
176 .end = IRQ_PF14,
177 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
178 },
179};
180
181static struct platform_device smc91x_device = {
182 .name = "smc91x",
183 .id = 0,
184 .num_resources = ARRAY_SIZE(smc91x_resources),
185 .resource = smc91x_resources,
61f09b5a
MH		 186 .dev = {
187 .platform_data = &smc91x_info,
188 },
b9da3b92
MF		 189};
190#endif
191
192#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
193static struct resource isp1362_hcd_resources[] = {
194 {
195 .start = 0x20308000,
196 .end = 0x20308000,
197 .flags = IORESOURCE_MEM,
198 }, {
199 .start = 0x20308004,
200 .end = 0x20308004,
201 .flags = IORESOURCE_MEM,
202 }, {
203 .start = IRQ_PG15,
204 .end = IRQ_PG15,
9e75894c 205 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
b9da3b92
MF		 206 },
207};
208
209static struct isp1362_platform_data isp1362_priv = {
210 .sel15Kres = 1,
211 .clknotstop = 0,
212 .oc_enable = 0,
213 .int_act_high = 0,
214 .int_edge_triggered = 0,
215 .remote_wakeup_connected = 0,
216 .no_power_switching = 1,
217 .power_switching_mode = 0,
218};
219
220static struct platform_device isp1362_hcd_device = {
221 .name = "isp1362-hcd",
222 .id = 0,
223 .dev = {
224 .platform_data = &isp1362_priv,
225 },
226 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
227 .resource = isp1362_hcd_resources,
228};
229#endif
230
231#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
232static struct resource net2272_bfin_resources[] = {
233 {
9c21453e
HK		 234 .start = 0x20300000,
235 .end = 0x20300000 + 0x100,
b9da3b92
MF		 236 .flags = IORESOURCE_MEM,
237 }, {
9c21453e
HK		 238 .start = IRQ_PG13,
239 .end = IRQ_PG13,
b9da3b92
MF		 240 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
241 },
242};
243
244static struct platform_device net2272_bfin_device = {
245 .name = "net2272",
246 .id = -1,
247 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
248 .resource = net2272_bfin_resources,
249};
250#endif
251
252#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
253static struct mtd_partition cm_partitions[] = {
254 {
255 .name = "bootloader(nor)",
256 .size = 0x40000,
257 .offset = 0,
258 }, {
259 .name = "linux kernel(nor)",
9c21453e 260 .size = 0x100000,
b9da3b92
MF		 261 .offset = MTDPART_OFS_APPEND,
262 }, {
263 .name = "file system(nor)",
264 .size = MTDPART_SIZ_FULL,
265 .offset = MTDPART_OFS_APPEND,
266 }
267};
268
269static struct physmap_flash_data cm_flash_data = {
270 .width = 2,
271 .parts = cm_partitions,
272 .nr_parts = ARRAY_SIZE(cm_partitions),
273};
274
275static unsigned cm_flash_gpios[] = { GPIO_PF4, GPIO_PF5 };
276
277static struct resource cm_flash_resource[] = {
278 {
279 .name = "cfi_probe",
280 .start = 0x20000000,
281 .end = 0x201fffff,
282 .flags = IORESOURCE_MEM,
283 }, {
284 .start = (unsigned long)cm_flash_gpios,
285 .end = ARRAY_SIZE(cm_flash_gpios),
286 .flags = IORESOURCE_IRQ,
287 }
288};
289
290static struct platform_device cm_flash_device = {
291 .name = "gpio-addr-flash",
292 .id = 0,
293 .dev = {
294 .platform_data = &cm_flash_data,
295 },
296 .num_resources = ARRAY_SIZE(cm_flash_resource),
297 .resource = cm_flash_resource,
298};
299#endif
300
301#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
6bd1fbea
SZ		 302#ifdef CONFIG_SERIAL_BFIN_UART0
303static struct resource bfin_uart0_resources[] = {
b9da3b92 304 {
6bd1fbea
SZ		 305 .start = UART0_THR,
306 .end = UART0_GCTL+2,
b9da3b92 307 .flags = IORESOURCE_MEM,
6bd1fbea 308 },
edb0a640
SZ		 309 {
310 .start = IRQ_UART0_TX,
311 .end = IRQ_UART0_TX,
312 .flags = IORESOURCE_IRQ,
313 },
6bd1fbea
SZ		 314 {
315 .start = IRQ_UART0_RX,
edb0a640 316 .end = IRQ_UART0_RX,
6bd1fbea
SZ		 317 .flags = IORESOURCE_IRQ,
318 },
319 {
320 .start = IRQ_UART0_ERROR,
321 .end = IRQ_UART0_ERROR,
322 .flags = IORESOURCE_IRQ,
323 },
324 {
325 .start = CH_UART0_TX,
326 .end = CH_UART0_TX,
327 .flags = IORESOURCE_DMA,
328 },
329 {
330 .start = CH_UART0_RX,
331 .end = CH_UART0_RX,
332 .flags = IORESOURCE_DMA,
333 },
334};
335
a8b19886 336static unsigned short bfin_uart0_peripherals[] = {
6bd1fbea
SZ		 337 P_UART0_TX, P_UART0_RX, 0
338};
339
340static struct platform_device bfin_uart0_device = {
341 .name = "bfin-uart",
342 .id = 0,
343 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
344 .resource = bfin_uart0_resources,
345 .dev = {
346 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
347 },
348};
349#endif
350#ifdef CONFIG_SERIAL_BFIN_UART1
351static struct resource bfin_uart1_resources[] = {
352 {
353 .start = UART1_THR,
354 .end = UART1_GCTL+2,
b9da3b92
MF		 355 .flags = IORESOURCE_MEM,
356 },
edb0a640
SZ		 357 {
358 .start = IRQ_UART1_TX,
359 .end = IRQ_UART1_TX,
360 .flags = IORESOURCE_IRQ,
361 },
6bd1fbea
SZ		 362 {
363 .start = IRQ_UART1_RX,
edb0a640 364 .end = IRQ_UART1_RX,
6bd1fbea
SZ		 365 .flags = IORESOURCE_IRQ,
366 },
367 {
368 .start = IRQ_UART1_ERROR,
369 .end = IRQ_UART1_ERROR,
370 .flags = IORESOURCE_IRQ,
371 },
372 {
373 .start = CH_UART1_TX,
374 .end = CH_UART1_TX,
375 .flags = IORESOURCE_DMA,
376 },
377 {
378 .start = CH_UART1_RX,
379 .end = CH_UART1_RX,
380 .flags = IORESOURCE_DMA,
381 },
b9da3b92
MF		 382};
383
a8b19886 384static unsigned short bfin_uart1_peripherals[] = {
6bd1fbea
SZ		 385 P_UART1_TX, P_UART1_RX, 0
386};
387
388static struct platform_device bfin_uart1_device = {
b9da3b92
MF		 389 .name = "bfin-uart",
390 .id = 1,
6bd1fbea
SZ		 391 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
392 .resource = bfin_uart1_resources,
393 .dev = {
394 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
395 },
b9da3b92
MF		 396};
397#endif
6bd1fbea 398#endif
b9da3b92
MF		 399
400#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
b9da3b92 401#ifdef CONFIG_BFIN_SIR0
42bd8bcb 402static struct resource bfin_sir0_resources[] = {
b9da3b92
MF		 403 {
404 .start = 0xFFC00400,
405 .end = 0xFFC004FF,
406 .flags = IORESOURCE_MEM,
407 },
42bd8bcb
GY		 408 {
409 .start = IRQ_UART0_RX,
410 .end = IRQ_UART0_RX+1,
411 .flags = IORESOURCE_IRQ,
412 },
413 {
414 .start = CH_UART0_RX,
415 .end = CH_UART0_RX+1,
416 .flags = IORESOURCE_DMA,
417 },
418};
419
420static struct platform_device bfin_sir0_device = {
421 .name = "bfin_sir",
422 .id = 0,
423 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
424 .resource = bfin_sir0_resources,
425};
b9da3b92
MF		 426#endif
427#ifdef CONFIG_BFIN_SIR1
42bd8bcb 428static struct resource bfin_sir1_resources[] = {
b9da3b92
MF		 429 {
430 .start = 0xFFC02000,
431 .end = 0xFFC020FF,
432 .flags = IORESOURCE_MEM,
433 },
42bd8bcb
GY		 434 {
435 .start = IRQ_UART1_RX,
436 .end = IRQ_UART1_RX+1,
437 .flags = IORESOURCE_IRQ,
438 },
439 {
440 .start = CH_UART1_RX,
441 .end = CH_UART1_RX+1,
442 .flags = IORESOURCE_DMA,
443 },
b9da3b92
MF		 444};
445
42bd8bcb 446static struct platform_device bfin_sir1_device = {
b9da3b92 447 .name = "bfin_sir",
42bd8bcb
GY		 448 .id = 1,
449 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
450 .resource = bfin_sir1_resources,
b9da3b92
MF		 451};
452#endif
42bd8bcb 453#endif
b9da3b92
MF		 454
455#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
456static struct resource bfin_twi0_resource[] = {
457 [0] = {
458 .start = TWI0_REGBASE,
459 .end = TWI0_REGBASE,
460 .flags = IORESOURCE_MEM,
461 },
462 [1] = {
463 .start = IRQ_TWI,
464 .end = IRQ_TWI,
465 .flags = IORESOURCE_IRQ,
466 },
467};
468
469static struct platform_device i2c_bfin_twi_device = {
470 .name = "i2c-bfin-twi",
471 .id = 0,
472 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
473 .resource = bfin_twi0_resource,
474};
475#endif
476
477#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
df5de261
SZ		 478#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
479static struct resource bfin_sport0_uart_resources[] = {
480 {
481 .start = SPORT0_TCR1,
482 .end = SPORT0_MRCS3+4,
483 .flags = IORESOURCE_MEM,
484 },
485 {
486 .start = IRQ_SPORT0_RX,
487 .end = IRQ_SPORT0_RX+1,
488 .flags = IORESOURCE_IRQ,
489 },
490 {
491 .start = IRQ_SPORT0_ERROR,
492 .end = IRQ_SPORT0_ERROR,
493 .flags = IORESOURCE_IRQ,
494 },
495};
496
a8b19886 497static unsigned short bfin_sport0_peripherals[] = {
df5de261 498 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
e54b6730 499 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
df5de261
SZ		 500};
501
b9da3b92
MF		 502static struct platform_device bfin_sport0_uart_device = {
503 .name = "bfin-sport-uart",
504 .id = 0,
df5de261
SZ		 505 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
506 .resource = bfin_sport0_uart_resources,
507 .dev = {
508 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
509 },
510};
511#endif
512#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
513static struct resource bfin_sport1_uart_resources[] = {
514 {
515 .start = SPORT1_TCR1,
516 .end = SPORT1_MRCS3+4,
517 .flags = IORESOURCE_MEM,
518 },
519 {
520 .start = IRQ_SPORT1_RX,
521 .end = IRQ_SPORT1_RX+1,
522 .flags = IORESOURCE_IRQ,
523 },
524 {
525 .start = IRQ_SPORT1_ERROR,
526 .end = IRQ_SPORT1_ERROR,
527 .flags = IORESOURCE_IRQ,
528 },
529};
530
a8b19886 531static unsigned short bfin_sport1_peripherals[] = {
df5de261 532 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
e54b6730 533 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
b9da3b92
MF		 534};
535
536static struct platform_device bfin_sport1_uart_device = {
537 .name = "bfin-sport-uart",
538 .id = 1,
df5de261
SZ		 539 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
540 .resource = bfin_sport1_uart_resources,
541 .dev = {
542 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
543 },
b9da3b92
MF		 544};
545#endif
df5de261 546#endif
b9da3b92
MF		 547
548#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
02460d08
SZ		 549#include <linux/bfin_mac.h>
550static const unsigned short bfin_mac_peripherals[] = P_MII0;
551
552static struct bfin_phydev_platform_data bfin_phydev_data[] = {
553 {
554 .addr = 1,
555 .irq = IRQ_MAC_PHYINT,
556 },
557};
558
559static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
560 .phydev_number = 1,
561 .phydev_data = bfin_phydev_data,
562 .phy_mode = PHY_INTERFACE_MODE_MII,
563 .mac_peripherals = bfin_mac_peripherals,
564};
565
65319628
GY		 566static struct platform_device bfin_mii_bus = {
567 .name = "bfin_mii_bus",
02460d08
SZ		 568 .dev = {
569 .platform_data = &bfin_mii_bus_data,
570 }
65319628
GY		 571};
572
b9da3b92
MF		 573static struct platform_device bfin_mac_device = {
574 .name = "bfin_mac",
02460d08
SZ		 575 .dev = {
576 .platform_data = &bfin_mii_bus,
577 }
b9da3b92
MF		 578};
579#endif
580
581#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
fe5aeb93 582#define PATA_INT IRQ_PF14
b9da3b92
MF		 583
584static struct pata_platform_info bfin_pata_platform_data = {
585 .ioport_shift = 2,
7832bb5d 586 .irq_type = IRQF_TRIGGER_HIGH,
b9da3b92
MF		 587};
588
589static struct resource bfin_pata_resources[] = {
590 {
591 .start = 0x2030C000,
592 .end = 0x2030C01F,
593 .flags = IORESOURCE_MEM,
594 },
595 {
596 .start = 0x2030D018,
597 .end = 0x2030D01B,
598 .flags = IORESOURCE_MEM,
599 },
600 {
601 .start = PATA_INT,
602 .end = PATA_INT,
603 .flags = IORESOURCE_IRQ,
604 },
605};
606
607static struct platform_device bfin_pata_device = {
608 .name = "pata_platform",
609 .id = -1,
610 .num_resources = ARRAY_SIZE(bfin_pata_resources),
611 .resource = bfin_pata_resources,
612 .dev = {
613 .platform_data = &bfin_pata_platform_data,
614 }
615};
616#endif
617
618static const unsigned int cclk_vlev_datasheet[] =
619{
620 VRPAIR(VLEV_085, 250000000),
621 VRPAIR(VLEV_090, 376000000),
622 VRPAIR(VLEV_095, 426000000),
623 VRPAIR(VLEV_100, 426000000),
624 VRPAIR(VLEV_105, 476000000),
625 VRPAIR(VLEV_110, 476000000),
626 VRPAIR(VLEV_115, 476000000),
627 VRPAIR(VLEV_120, 500000000),
628 VRPAIR(VLEV_125, 533000000),
629 VRPAIR(VLEV_130, 600000000),
630};
631
632static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
633 .tuple_tab = cclk_vlev_datasheet,
634 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
635 .vr_settling_time = 25 /* us */,
636};
637
638static struct platform_device bfin_dpmc = {
639 .name = "bfin dpmc",
640 .dev = {
641 .platform_data = &bfin_dmpc_vreg_data,
642 },
643};
644
645static struct platform_device *cm_bf537_devices[] __initdata = {
646
647 &bfin_dpmc,
648
649#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
650 &hitachi_fb_device,
651#endif
652
653#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
654 &rtc_device,
655#endif
656
657#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
6bd1fbea
SZ		 658#ifdef CONFIG_SERIAL_BFIN_UART0
659 &bfin_uart0_device,
660#endif
661#ifdef CONFIG_SERIAL_BFIN_UART1
662 &bfin_uart1_device,
663#endif
b9da3b92
MF		 664#endif
665
666#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb
GY		 667#ifdef CONFIG_BFIN_SIR0
668 &bfin_sir0_device,
669#endif
670#ifdef CONFIG_BFIN_SIR1
671 &bfin_sir1_device,
672#endif
b9da3b92
MF		 673#endif
674
675#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
676 &i2c_bfin_twi_device,
677#endif
678
679#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
df5de261 680#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
b9da3b92 681 &bfin_sport0_uart_device,
df5de261
SZ		 682#endif
683#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
b9da3b92
MF		 684 &bfin_sport1_uart_device,
685#endif
df5de261 686#endif
b9da3b92
MF		 687
688#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
689 &isp1362_hcd_device,
690#endif
691
692#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
693 &smc91x_device,
694#endif
695
696#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628 697 &bfin_mii_bus,
b9da3b92
MF		 698 &bfin_mac_device,
699#endif
700
701#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
702 &net2272_bfin_device,
703#endif
704
705#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
706 &bfin_spi0_device,
707#endif
708
709#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
710 &bfin_pata_device,
711#endif
712
713#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
714 &cm_flash_device,
715#endif
716};
717
9be8631b
MF		 718static int __init net2272_init(void)
719{
720#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
721 int ret;
722
723 ret = gpio_request(GPIO_PG14, "net2272");
724 if (ret)
725 return ret;
726
727 /* Reset USB Chip, PG14 */
728 gpio_direction_output(GPIO_PG14, 0);
729 mdelay(2);
730 gpio_set_value(GPIO_PG14, 1);
731#endif
732
733 return 0;
734}
735
7f6678c5 736static int __init tcm_bf537_init(void)
b9da3b92
MF		 737{
738 printk(KERN_INFO "%s(): registering device resources\n", __func__);
739 platform_add_devices(cm_bf537_devices, ARRAY_SIZE(cm_bf537_devices));
740#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
741 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
742#endif
743
744#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
bc2f6bd8 745 irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
b9da3b92 746#endif
9be8631b
MF		 747
748 if (net2272_init())
749 pr_warning("unable to configure net2272; it probably won't work\n");
750
b9da3b92
MF		 751 return 0;
752}
753
7f6678c5 754arch_initcall(tcm_bf537_init);
b9da3b92 755
c13ce9fd
SZ		 756static struct platform_device *cm_bf537_early_devices[] __initdata = {
757#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
758#ifdef CONFIG_SERIAL_BFIN_UART0
759 &bfin_uart0_device,
760#endif
761#ifdef CONFIG_SERIAL_BFIN_UART1
762 &bfin_uart1_device,
763#endif
764#endif
765
766#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
767#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
768 &bfin_sport0_uart_device,
769#endif
770#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
771 &bfin_sport1_uart_device,
772#endif
773#endif
774};
775
776void __init native_machine_early_platform_add_devices(void)
777{
778 printk(KERN_INFO "register early platform devices\n");
779 early_platform_add_devices(cm_bf537_early_devices,
780 ARRAY_SIZE(cm_bf537_early_devices));
781}
782
b9da3b92
MF		 783void bfin_get_ether_addr(char *addr)
784{
785 random_ether_addr(addr);
786 printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__);
787}
788EXPORT_SYMBOL(bfin_get_ether_addr);
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