[mirror_ubuntu-bionic-kernel.git] / arch / blackfin / mach-bf538 / include / mach / anomaly.h

/*
 * DO NOT EDIT THIS FILE
 * This file is under version control at
 *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
 * and can be replaced with that version at any time
 * DO NOT EDIT THIS FILE
 *
 * Copyright 2004-2011 Analog Devices Inc.
 * Licensed under the ADI BSD license.
 *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
 */

/* This file should be up to date with:
 *  - Revision I, 05/25/2010; ADSP-BF538/BF538F Blackfin Processor Anomaly List
 *  - Revision N, 05/25/2010; ADSP-BF539/BF539F Blackfin Processor Anomaly List
 */

#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_

/* We do not support old silicon - sorry */
#if __SILICON_REVISION__ < 4
# error will not work on BF538/BF539 silicon version 0.0, 0.1, 0.2, or 0.3
#endif

#if defined(__ADSPBF538__)
# define ANOMALY_BF538 1
#else
# define ANOMALY_BF538 0
#endif
#if defined(__ADSPBF539__)
# define ANOMALY_BF539 1
#else
# define ANOMALY_BF539 0
#endif

/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
#define ANOMALY_05000166 (1)
/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
#define ANOMALY_05000179 (1)
/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
#define ANOMALY_05000180 (1)
/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
#define ANOMALY_05000193 (1)
/* Current DMA Address Shows Wrong Value During Carry Fix */
#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
/* NMI Event at Boot Time Results in Unpredictable State */
#define ANOMALY_05000219 (1)
/* SPI Slave Boot Mode Modifies Registers from Reset Value */
#define ANOMALY_05000229 (1)
/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
#define ANOMALY_05000233 (1)
/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1)
/* Maximum External Clock Speed for Timers */
#define ANOMALY_05000253 (1)
/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
#define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
#define ANOMALY_05000272 (1)
/* Writes to Synchronous SDRAM Memory May Be Lost */
#define ANOMALY_05000273 (__SILICON_REVISION__ < 4)
/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
#define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
#define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
/* False Hardware Error Exception when ISR Context Is Not Restored */
#define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
#define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
#define ANOMALY_05000283 (__SILICON_REVISION__ < 4)
/* SPORTs May Receive Bad Data If FIFOs Fill Up */
#define ANOMALY_05000288 (__SILICON_REVISION__ < 4)
/* Reads from CAN Mailbox and Acceptance Mask Area Can Fail */
#define ANOMALY_05000291 (__SILICON_REVISION__ < 4)
/* Hibernate Leakage Current Is Higher Than Specified */
#define ANOMALY_05000293 (__SILICON_REVISION__ < 4)
/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
#define ANOMALY_05000294 (1)
/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
#define ANOMALY_05000301 (__SILICON_REVISION__ < 4)
/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
#define ANOMALY_05000304 (__SILICON_REVISION__ < 4)
/* SCKELOW Bit Does Not Maintain State Through Hibernate */
#define ANOMALY_05000307 (__SILICON_REVISION__ < 4)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1)
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (__SILICON_REVISION__ < 5)
/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
#define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
#define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
#define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4)
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
#define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
#define ANOMALY_05000357 (__SILICON_REVISION__ < 5)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (__SILICON_REVISION__ < 5)
/* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */
#define ANOMALY_05000374 (__SILICON_REVISION__ == 4)
/* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */
#define ANOMALY_05000375 (__SILICON_REVISION__ < 4)
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
#define ANOMALY_05000402 (__SILICON_REVISION__ == 3)
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (1)
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
#define ANOMALY_05000416 (1)
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
#define ANOMALY_05000425 (1)
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
#define ANOMALY_05000426 (1)
/* Specific GPIO Pins May Change State when Entering Hibernate */
#define ANOMALY_05000436 (__SILICON_REVISION__ > 3)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
/* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1)
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
#define ANOMALY_05000462 (1)
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
#define ANOMALY_05000473 (1)
/* Possible Lockup Condition whem Modifying PLL from External Memory */
#define ANOMALY_05000475 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
/* IFLUSH sucks at life */
#define ANOMALY_05000491 (1)

/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
#define ANOMALY_05000120 (0)
#define ANOMALY_05000125 (0)
#define ANOMALY_05000149 (0)
#define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0)
#define ANOMALY_05000182 (0)
#define ANOMALY_05000189 (0)
#define ANOMALY_05000198 (0)
#define ANOMALY_05000202 (0)
#define ANOMALY_05000215 (0)
#define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0)
#define ANOMALY_05000234 (0)
#define ANOMALY_05000242 (0)
#define ANOMALY_05000248 (0)
#define ANOMALY_05000250 (0)
#define ANOMALY_05000254 (0)
#define ANOMALY_05000257 (0)
#define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000274 (0)
#define ANOMALY_05000287 (0)
#define ANOMALY_05000305 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000353 (1)
#define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0)
#define ANOMALY_05000364 (0)
#define ANOMALY_05000380 (0)
#define ANOMALY_05000383 (0)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000430 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
#define ANOMALY_05000440 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
#define ANOMALY_05000450 (0)
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
#define ANOMALY_05000480 (0)
#define ANOMALY_05000485 (0)

#endif
Commit	Line	Data
dc26aec2	1	/*
af5d7fc7 MF	2	* DO NOT EDIT THIS FILE
	3	* This file is under version control at
	4	* svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
	5	* and can be replaced with that version at any time
	6	* DO NOT EDIT THIS FILE
dc26aec2	7	*
93f1742c	8	* Copyright 2004-2011 Analog Devices Inc.
af5d7fc7 MF	9	* Licensed under the ADI BSD license.
af5d7fc7 MF	10	* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
dc26aec2 MH	11	*/
dc26aec2 MH	12
a413647b	13	/* This file should be up to date with:
93f1742c MF	14	* - Revision I, 05/25/2010; ADSP-BF538/BF538F Blackfin Processor Anomaly List
93f1742c MF	15	* - Revision N, 05/25/2010; ADSP-BF539/BF539F Blackfin Processor Anomaly List
dc26aec2 MH	16	*/
	17
	18	#ifndef _MACH_ANOMALY_H_
	19	#define _MACH_ANOMALY_H_
	20
a413647b	21	/* We do not support old silicon - sorry */
dc26aec2	22	#if __SILICON_REVISION__ < 4
a413647b	23	# error will not work on BF538/BF539 silicon version 0.0, 0.1, 0.2, or 0.3
dc26aec2 MH	24	#endif
dc26aec2 MH	25
a413647b MF	26	#if defined(__ADSPBF538__)
	27	# define ANOMALY_BF538 1
	28	#else
	29	# define ANOMALY_BF538 0
	30	#endif
	31	#if defined(__ADSPBF539__)
	32	# define ANOMALY_BF539 1
	33	#else
	34	# define ANOMALY_BF539 0
	35	#endif
	36
a200ad22	37	/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
dc26aec2 MH	38	#define ANOMALY_05000074 (1)
	39	/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
	40	#define ANOMALY_05000119 (1)
	41	/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
	42	#define ANOMALY_05000122 (1)
a200ad22	43	/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
dc26aec2 MH	44	#define ANOMALY_05000166 (1)
	45	/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
	46	#define ANOMALY_05000179 (1)
	47	/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
	48	#define ANOMALY_05000180 (1)
	49	/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
	50	#define ANOMALY_05000193 (1)
	51	/* Current DMA Address Shows Wrong Value During Carry Fix */
	52	#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
	53	/* NMI Event at Boot Time Results in Unpredictable State */
	54	#define ANOMALY_05000219 (1)
	55	/* SPI Slave Boot Mode Modifies Registers from Reset Value */
	56	#define ANOMALY_05000229 (1)
	57	/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
	58	#define ANOMALY_05000233 (1)
a413647b	59	/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
dc26aec2	60	#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
a413647b	61	/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
dc26aec2 MH	62	#define ANOMALY_05000245 (1)
	63	/* Maximum External Clock Speed for Timers */
	64	#define ANOMALY_05000253 (1)
a413647b	65	/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
dc26aec2 MH	66	#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
	67	/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
	68	#define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
	69	/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
	70	#define ANOMALY_05000272 (1)
	71	/* Writes to Synchronous SDRAM Memory May Be Lost */
	72	#define ANOMALY_05000273 (__SILICON_REVISION__ < 4)
	73	/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
	74	#define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
	75	/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
	76	#define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
a200ad22	77	/* False Hardware Error Exception when ISR Context Is Not Restored */
dc26aec2 MH	78	#define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
	79	/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
	80	#define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
a200ad22	81	/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
dc26aec2 MH	82	#define ANOMALY_05000283 (__SILICON_REVISION__ < 4)
	83	/* SPORTs May Receive Bad Data If FIFOs Fill Up */
	84	#define ANOMALY_05000288 (__SILICON_REVISION__ < 4)
	85	/* Reads from CAN Mailbox and Acceptance Mask Area Can Fail */
	86	#define ANOMALY_05000291 (__SILICON_REVISION__ < 4)
	87	/* Hibernate Leakage Current Is Higher Than Specified */
	88	#define ANOMALY_05000293 (__SILICON_REVISION__ < 4)
	89	/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
	90	#define ANOMALY_05000294 (1)
	91	/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
	92	#define ANOMALY_05000301 (__SILICON_REVISION__ < 4)
	93	/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
	94	#define ANOMALY_05000304 (__SILICON_REVISION__ < 4)
	95	/* SCKELOW Bit Does Not Maintain State Through Hibernate */
	96	#define ANOMALY_05000307 (__SILICON_REVISION__ < 4)
	97	/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
	98	#define ANOMALY_05000310 (1)
a200ad22	99	/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
dc26aec2	100	#define ANOMALY_05000312 (__SILICON_REVISION__ < 5)
a413647b	101	/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
dc26aec2	102	#define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
a200ad22	103	/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
dc26aec2 MH	104	#define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
dc26aec2 MH	105	/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
a413647b	106	#define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4)
dc26aec2 MH	107	/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
	108	#define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
	109	/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
	110	#define ANOMALY_05000357 (__SILICON_REVISION__ < 5)
	111	/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
	112	#define ANOMALY_05000366 (1)
	113	/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
	114	#define ANOMALY_05000371 (__SILICON_REVISION__ < 5)
	115	/* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */
	116	#define ANOMALY_05000374 (__SILICON_REVISION__ == 4)
a200ad22	117	/* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */
dc26aec2 MH	118	#define ANOMALY_05000375 (__SILICON_REVISION__ < 4)
dc26aec2 MH	119	/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
bd411b15	120	#define ANOMALY_05000402 (__SILICON_REVISION__ == 3)
dc26aec2 MH	121	/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
	122	#define ANOMALY_05000403 (1)
	123	/* Speculative Fetches Can Cause Undesired External FIFO Operations */
	124	#define ANOMALY_05000416 (1)
6651ece9 MF	125	/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
	126	#define ANOMALY_05000425 (1)
	127	/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
	128	#define ANOMALY_05000426 (1)
	129	/* Specific GPIO Pins May Change State when Entering Hibernate */
	130	#define ANOMALY_05000436 (__SILICON_REVISION__ > 3)
3529e041 MF	131	/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
3529e041 MF	132	#define ANOMALY_05000443 (1)
a200ad22	133	/* False Hardware Error when RETI Points to Invalid Memory */
a413647b	134	#define ANOMALY_05000461 (1)
dc7101bb MF	135	/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
dc7101bb MF	136	#define ANOMALY_05000462 (1)
af5d7fc7 MF	137	/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
af5d7fc7 MF	138	#define ANOMALY_05000473 (1)
dc7101bb MF	139	/* Possible Lockup Condition whem Modifying PLL from External Memory */
dc7101bb MF	140	#define ANOMALY_05000475 (1)
af5d7fc7 MF	141	/* TESTSET Instruction Cannot Be Interrupted */
af5d7fc7 MF	142	#define ANOMALY_05000477 (1)
dc7101bb MF	143	/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
	144	#define ANOMALY_05000481 (1)
	145	/* IFLUSH sucks at life */
	146	#define ANOMALY_05000491 (1)
dc26aec2 MH	147
dc26aec2 MH	148	/* Anomalies that don't exist on this proc */
a413647b MF	149	#define ANOMALY_05000099 (0)
a413647b MF	150	#define ANOMALY_05000120 (0)
a200ad22	151	#define ANOMALY_05000125 (0)
a413647b	152	#define ANOMALY_05000149 (0)
dc26aec2	153	#define ANOMALY_05000158 (0)
a413647b	154	#define ANOMALY_05000171 (0)
a200ad22	155	#define ANOMALY_05000182 (0)
976119bc	156	#define ANOMALY_05000189 (0)
3529e041	157	#define ANOMALY_05000198 (0)
a200ad22	158	#define ANOMALY_05000202 (0)
a413647b MF	159	#define ANOMALY_05000215 (0)
	160	#define ANOMALY_05000220 (0)
	161	#define ANOMALY_05000227 (0)
3529e041	162	#define ANOMALY_05000230 (0)
a413647b	163	#define ANOMALY_05000231 (0)
a200ad22	164	#define ANOMALY_05000234 (0)
a413647b MF	165	#define ANOMALY_05000242 (0)
	166	#define ANOMALY_05000248 (0)
	167	#define ANOMALY_05000250 (0)
	168	#define ANOMALY_05000254 (0)
a200ad22	169	#define ANOMALY_05000257 (0)
3529e041	170	#define ANOMALY_05000263 (0)
a200ad22	171	#define ANOMALY_05000266 (0)
a413647b MF	172	#define ANOMALY_05000274 (0)
a413647b MF	173	#define ANOMALY_05000287 (0)
c18e99cf	174	#define ANOMALY_05000305 (0)
dc26aec2 MH	175	#define ANOMALY_05000311 (0)
dc26aec2 MH	176	#define ANOMALY_05000323 (0)
3529e041	177	#define ANOMALY_05000353 (1)
a413647b	178	#define ANOMALY_05000362 (1)
dc26aec2	179	#define ANOMALY_05000363 (0)
976119bc	180	#define ANOMALY_05000364 (0)
ee554be9	181	#define ANOMALY_05000380 (0)
93f1742c	182	#define ANOMALY_05000383 (0)
3529e041	183	#define ANOMALY_05000386 (1)
a413647b MF	184	#define ANOMALY_05000389 (0)
a413647b MF	185	#define ANOMALY_05000400 (0)
6651ece9	186	#define ANOMALY_05000412 (0)
a413647b	187	#define ANOMALY_05000430 (0)
6651ece9	188	#define ANOMALY_05000432 (0)
94b28211	189	#define ANOMALY_05000435 (0)
93f1742c	190	#define ANOMALY_05000440 (0)
7dbc3f6e MF	191	#define ANOMALY_05000447 (0)
7dbc3f6e MF	192	#define ANOMALY_05000448 (0)
a413647b MF	193	#define ANOMALY_05000456 (0)
a413647b MF	194	#define ANOMALY_05000450 (0)
a200ad22 MF	195	#define ANOMALY_05000465 (0)
a200ad22 MF	196	#define ANOMALY_05000467 (0)
af5d7fc7	197	#define ANOMALY_05000474 (0)
93f1742c	198	#define ANOMALY_05000480 (0)
dc7101bb	199	#define ANOMALY_05000485 (0)
dc26aec2 MH	200
dc26aec2 MH	201	#endif