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1 | /* |
2 | * File: arch/blackfin/mach-bf538/ints-priority.c | |
3 | * Based on: arch/blackfin/mach-bf533/ints-priority.c | |
4 | * Author: Michael Hennerich | |
5 | * | |
6 | * Created: | |
7 | * Description: Set up the interrupt priorities | |
8 | * | |
9 | * Modified: | |
10 | * Copyright 2008 Analog Devices Inc. | |
11 | * | |
12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or | |
17 | * (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, see the file COPYING, or write | |
26 | * to the Free Software Foundation, Inc., | |
27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
28 | */ | |
29 | ||
30 | #include <linux/module.h> | |
31 | #include <linux/irq.h> | |
32 | #include <asm/blackfin.h> | |
33 | ||
34 | void __init program_IAR(void) | |
35 | { | |
36 | ||
37 | /* Program the IAR0 Register with the configured priority */ | |
38 | bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) | | |
39 | ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) | | |
40 | ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) | | |
41 | ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) | | |
42 | ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) | | |
43 | ((CONFIG_IRQ_SPI0_ERROR - 7) << IRQ_SPI0_ERROR_POS) | | |
44 | ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) | | |
45 | ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS)); | |
46 | ||
47 | bfin_write_SIC_IAR1(((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS) | | |
48 | ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) | | |
49 | ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) | | |
50 | ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) | | |
51 | ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) | | |
52 | ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) | | |
53 | ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) | | |
54 | ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS)); | |
55 | ||
56 | bfin_write_SIC_IAR2(((CONFIG_IRQ_TMR0 - 7) << IRQ_TMR0_POS) | | |
57 | ((CONFIG_IRQ_TMR1 - 7) << IRQ_TMR1_POS) | | |
58 | ((CONFIG_IRQ_TMR2 - 7) << IRQ_TMR2_POS) | | |
59 | ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) | | |
60 | ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) | | |
61 | ((CONFIG_IRQ_MEM0_DMA0 - 7) << IRQ_MEM0_DMA0_POS) | | |
62 | ((CONFIG_IRQ_MEM0_DMA1 - 7) << IRQ_MEM0_DMA1_POS) | | |
63 | ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS)); | |
64 | ||
65 | bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) | | |
66 | ((CONFIG_IRQ_SPORT2_ERROR - 7) << IRQ_SPORT2_ERROR_POS) | | |
67 | ((CONFIG_IRQ_SPORT3_ERROR - 7) << IRQ_SPORT3_ERROR_POS) | | |
68 | ((CONFIG_IRQ_SPI1_ERROR - 7) << IRQ_SPI1_ERROR_POS) | | |
69 | ((CONFIG_IRQ_SPI2_ERROR - 7) << IRQ_SPI2_ERROR_POS) | | |
70 | ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) | | |
71 | ((CONFIG_IRQ_UART2_ERROR - 7) << IRQ_UART2_ERROR_POS)); | |
72 | ||
73 | bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN_ERROR - 7) << IRQ_CAN_ERROR_POS) | | |
74 | ((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) | | |
75 | ((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) | | |
76 | ((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) | | |
77 | ((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) | | |
78 | ((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS)); | |
79 | ||
80 | bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) | | |
81 | ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) | | |
82 | ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) | | |
83 | ((CONFIG_IRQ_UART2_RX - 7) << IRQ_UART2_RX_POS) | | |
84 | ((CONFIG_IRQ_UART2_TX - 7) << IRQ_UART2_TX_POS) | | |
85 | ((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) | | |
86 | ((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) | | |
87 | ((CONFIG_IRQ_CAN_RX - 7) << IRQ_CAN_RX_POS)); | |
88 | ||
89 | bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) | | |
90 | ((CONFIG_IRQ_MEM1_DMA0 - 7) << IRQ_MEM1_DMA0_POS) | | |
91 | ((CONFIG_IRQ_MEM1_DMA1 - 7) << IRQ_MEM1_DMA1_POS)); | |
92 | ||
93 | SSYNC(); | |
94 | } |