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Blackfin: SMP: fix hotplug building after irq header shuffle
[mirror_ubuntu-zesty-kernel.git] / arch / blackfin / mach-bf548 / boards / ezkit.c
CommitLineData
24a07a12 1/*
96f1050d
RG		 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2005 National ICT Australia (NICTA)
4 * Aidan Williams <aidan@nicta.com.au>
24a07a12 5 *
96f1050d 6 * Licensed under the GPL-2 or later.
24a07a12
RH		 7 */
8
9#include <linux/device.h>
10#include <linux/platform_device.h>
11#include <linux/mtd/mtd.h>
12#include <linux/mtd/partitions.h>
de8c43f2 13#include <linux/mtd/physmap.h>
24a07a12
RH		 14#include <linux/spi/spi.h>
15#include <linux/spi/flash.h>
1f83b8f1 16#include <linux/irq.h>
81d9c7f2 17#include <linux/i2c.h>
24a07a12 18#include <linux/interrupt.h>
c6c4d7bb 19#include <linux/usb/musb.h>
24a07a12 20#include <asm/bfin5xx_spi.h>
c6c4d7bb
BW		 21#include <asm/dma.h>
22#include <asm/gpio.h>
23#include <asm/nand.h>
14b03204 24#include <asm/dpmc.h>
5d448dd5 25#include <asm/portmux.h>
501674a5 26#include <asm/bfin_sdh.h>
639f6571 27#include <mach/bf54x_keys.h>
c6c4d7bb
BW		 28#include <linux/input.h>
29#include <linux/spi/ad7877.h>
24a07a12
RH		 30
31/*
32 * Name the Board for the /proc/cpuinfo
33 */
fe85cad2 34const char bfin_board_name[] = "ADI BF548-EZKIT";
24a07a12
RH		 35
36/*
37 * Driver needs to know address, irq and flag pin.
38 */
39
0a6304a9 40#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
3f375690
MH		 41#include <linux/usb/isp1760.h>
42static struct resource bfin_isp1760_resources[] = {
0a6304a9 43 [0] = {
0a6304a9
MH		 44 .start = 0x2C0C0000,
45 .end = 0x2C0C0000 + 0xfffff,
46 .flags = IORESOURCE_MEM,
47 },
48 [1] = {
49 .start = IRQ_PG7,
50 .end = IRQ_PG7,
51 .flags = IORESOURCE_IRQ,
52 },
53};
54
3f375690
MH		 55static struct isp1760_platform_data isp1760_priv = {
56 .is_isp1761 = 0,
3f375690
MH		 57 .bus_width_16 = 1,
58 .port1_otg = 0,
59 .analog_oc = 0,
60 .dack_polarity_high = 0,
61 .dreq_polarity_high = 0,
0a6304a9
MH		 62};
63
3f375690 64static struct platform_device bfin_isp1760_device = {
c6feb768 65 .name = "isp1760",
3f375690
MH		 66 .id = 0,
67 .dev = {
68 .platform_data = &isp1760_priv,
69 },
70 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
71 .resource = bfin_isp1760_resources,
0a6304a9 72};
0a6304a9
MH		 73#endif
74
c6c4d7bb
BW		 75#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
76
639f6571 77#include <mach/bf54x-lq043.h>
c6c4d7bb
BW		 78
79static struct bfin_bf54xfb_mach_info bf54x_lq043_data = {
0e101ec1
SP		 80 .width = 95,
81 .height = 54,
c6c4d7bb
BW		 82 .xres = {480, 480, 480},
83 .yres = {272, 272, 272},
84 .bpp = {24, 24, 24},
85 .disp = GPIO_PE3,
86};
87
88static struct resource bf54x_lq043_resources[] = {
89 {
90 .start = IRQ_EPPI0_ERR,
91 .end = IRQ_EPPI0_ERR,
92 .flags = IORESOURCE_IRQ,
93 },
94};
95
96static struct platform_device bf54x_lq043_device = {
97 .name = "bf54x-lq043",
98 .id = -1,
99 .num_resources = ARRAY_SIZE(bf54x_lq043_resources),
100 .resource = bf54x_lq043_resources,
101 .dev = {
102 .platform_data = &bf54x_lq043_data,
103 },
104};
105#endif
106
107#if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE)
8f740ef3 108static const unsigned int bf548_keymap[] = {
c6c4d7bb
BW		 109 KEYVAL(0, 0, KEY_ENTER),
110 KEYVAL(0, 1, KEY_HELP),
111 KEYVAL(0, 2, KEY_0),
112 KEYVAL(0, 3, KEY_BACKSPACE),
113 KEYVAL(1, 0, KEY_TAB),
114 KEYVAL(1, 1, KEY_9),
115 KEYVAL(1, 2, KEY_8),
116 KEYVAL(1, 3, KEY_7),
117 KEYVAL(2, 0, KEY_DOWN),
118 KEYVAL(2, 1, KEY_6),
119 KEYVAL(2, 2, KEY_5),
120 KEYVAL(2, 3, KEY_4),
121 KEYVAL(3, 0, KEY_UP),
122 KEYVAL(3, 1, KEY_3),
123 KEYVAL(3, 2, KEY_2),
124 KEYVAL(3, 3, KEY_1),
125};
126
127static struct bfin_kpad_platform_data bf54x_kpad_data = {
128 .rows = 4,
129 .cols = 4,
8f740ef3
MH		 130 .keymap = bf548_keymap,
131 .keymapsize = ARRAY_SIZE(bf548_keymap),
c6c4d7bb
BW		 132 .repeat = 0,
133 .debounce_time = 5000, /* ns (5ms) */
134 .coldrive_time = 1000, /* ns (1ms) */
135 .keyup_test_interval = 50, /* ms (50ms) */
136};
137
138static struct resource bf54x_kpad_resources[] = {
139 {
140 .start = IRQ_KEY,
141 .end = IRQ_KEY,
142 .flags = IORESOURCE_IRQ,
143 },
144};
145
146static struct platform_device bf54x_kpad_device = {
147 .name = "bf54x-keys",
148 .id = -1,
149 .num_resources = ARRAY_SIZE(bf54x_kpad_resources),
150 .resource = bf54x_kpad_resources,
151 .dev = {
152 .platform_data = &bf54x_kpad_data,
153 },
154};
155#endif
156
adfc0467 157#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
aca5e4aa
MH		 158#include <asm/bfin_rotary.h>
159
160static struct bfin_rotary_platform_data bfin_rotary_data = {
161 /*.rotary_up_key = KEY_UP,*/
162 /*.rotary_down_key = KEY_DOWN,*/
163 .rotary_rel_code = REL_WHEEL,
164 .rotary_button_key = KEY_ENTER,
165 .debounce = 10, /* 0..17 */
166 .mode = ROT_QUAD_ENC | ROT_DEBE,
167};
168
169static struct resource bfin_rotary_resources[] = {
170 {
171 .start = IRQ_CNT,
172 .end = IRQ_CNT,
173 .flags = IORESOURCE_IRQ,
174 },
175};
176
177static struct platform_device bfin_rotary_device = {
178 .name = "bfin-rotary",
179 .id = -1,
180 .num_resources = ARRAY_SIZE(bfin_rotary_resources),
181 .resource = bfin_rotary_resources,
182 .dev = {
183 .platform_data = &bfin_rotary_data,
184 },
185};
186#endif
187
ffc4d8bc 188#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
57af8edf 189#include <linux/input/adxl34x.h>
ffc4d8bc
MH		 190static const struct adxl34x_platform_data adxl34x_info = {
191 .x_axis_offset = 0,
192 .y_axis_offset = 0,
193 .z_axis_offset = 0,
194 .tap_threshold = 0x31,
195 .tap_duration = 0x10,
196 .tap_latency = 0x60,
197 .tap_window = 0xF0,
198 .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
199 .act_axis_control = 0xFF,
200 .activity_threshold = 5,
201 .inactivity_threshold = 3,
202 .inactivity_time = 4,
203 .free_fall_threshold = 0x7,
204 .free_fall_time = 0x20,
205 .data_rate = 0x8,
206 .data_range = ADXL_FULL_RES,
207
208 .ev_type = EV_ABS,
209 .ev_code_x = ABS_X, /* EV_REL */
210 .ev_code_y = ABS_Y, /* EV_REL */
211 .ev_code_z = ABS_Z, /* EV_REL */
212
57af8edf 213 .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
ffc4d8bc
MH		 214
215/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
216/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
217 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
218 .fifo_mode = ADXL_FIFO_STREAM,
5db4036b
MH		 219 .orientation_enable = ADXL_EN_ORIENTATION_3D,
220 .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
221 .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
222 /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
223 .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
ffc4d8bc
MH		 224};
225#endif
226
24a07a12
RH		 227#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
228static struct platform_device rtc_device = {
229 .name = "rtc-bfin",
230 .id = -1,
231};
232#endif
233
234#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
24a07a12 235#ifdef CONFIG_SERIAL_BFIN_UART0
6bd1fbea 236static struct resource bfin_uart0_resources[] = {
24a07a12 237 {
6bd1fbea
SZ		 238 .start = UART0_DLL,
239 .end = UART0_RBR+2,
24a07a12
RH		 240 .flags = IORESOURCE_MEM,
241 },
6bd1fbea
SZ		 242 {
243 .start = IRQ_UART0_RX,
244 .end = IRQ_UART0_RX+1,
245 .flags = IORESOURCE_IRQ,
246 },
247 {
248 .start = IRQ_UART0_ERROR,
249 .end = IRQ_UART0_ERROR,
250 .flags = IORESOURCE_IRQ,
251 },
252 {
253 .start = CH_UART0_TX,
254 .end = CH_UART0_TX,
255 .flags = IORESOURCE_DMA,
256 },
257 {
258 .start = CH_UART0_RX,
259 .end = CH_UART0_RX,
260 .flags = IORESOURCE_DMA,
261 },
262};
263
264unsigned short bfin_uart0_peripherals[] = {
265 P_UART0_TX, P_UART0_RX, 0
266};
267
268static struct platform_device bfin_uart0_device = {
269 .name = "bfin-uart",
270 .id = 0,
271 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
272 .resource = bfin_uart0_resources,
273 .dev = {
274 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
275 },
276};
24a07a12
RH		 277#endif
278#ifdef CONFIG_SERIAL_BFIN_UART1
6bd1fbea 279static struct resource bfin_uart1_resources[] = {
24a07a12 280 {
6bd1fbea
SZ		 281 .start = UART1_DLL,
282 .end = UART1_RBR+2,
24a07a12
RH		 283 .flags = IORESOURCE_MEM,
284 },
6bd1fbea
SZ		 285 {
286 .start = IRQ_UART1_RX,
287 .end = IRQ_UART1_RX+1,
288 .flags = IORESOURCE_IRQ,
289 },
290 {
291 .start = IRQ_UART1_ERROR,
292 .end = IRQ_UART1_ERROR,
293 .flags = IORESOURCE_IRQ,
294 },
295 {
296 .start = CH_UART1_TX,
297 .end = CH_UART1_TX,
298 .flags = IORESOURCE_DMA,
299 },
300 {
301 .start = CH_UART1_RX,
302 .end = CH_UART1_RX,
303 .flags = IORESOURCE_DMA,
304 },
305#ifdef CONFIG_BFIN_UART1_CTSRTS
306 { /* CTS pin -- 0 means not supported */
307 .start = GPIO_PE10,
308 .end = GPIO_PE10,
309 .flags = IORESOURCE_IO,
310 },
311 { /* RTS pin -- 0 means not supported */
312 .start = GPIO_PE9,
313 .end = GPIO_PE9,
314 .flags = IORESOURCE_IO,
315 },
316#endif
317};
318
319unsigned short bfin_uart1_peripherals[] = {
320 P_UART1_TX, P_UART1_RX,
321#ifdef CONFIG_BFIN_UART1_CTSRTS
322 P_UART1_RTS, P_UART1_CTS,
323#endif
324 0
325};
326
327static struct platform_device bfin_uart1_device = {
328 .name = "bfin-uart",
329 .id = 1,
330 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
331 .resource = bfin_uart1_resources,
332 .dev = {
333 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
334 },
335};
24a07a12
RH		 336#endif
337#ifdef CONFIG_SERIAL_BFIN_UART2
6bd1fbea 338static struct resource bfin_uart2_resources[] = {
24a07a12 339 {
6bd1fbea
SZ		 340 .start = UART2_DLL,
341 .end = UART2_RBR+2,
24a07a12
RH		 342 .flags = IORESOURCE_MEM,
343 },
6bd1fbea
SZ		 344 {
345 .start = IRQ_UART2_RX,
346 .end = IRQ_UART2_RX+1,
347 .flags = IORESOURCE_IRQ,
348 },
349 {
350 .start = IRQ_UART2_ERROR,
351 .end = IRQ_UART2_ERROR,
352 .flags = IORESOURCE_IRQ,
353 },
354 {
355 .start = CH_UART2_TX,
356 .end = CH_UART2_TX,
357 .flags = IORESOURCE_DMA,
358 },
359 {
360 .start = CH_UART2_RX,
361 .end = CH_UART2_RX,
362 .flags = IORESOURCE_DMA,
363 },
364};
365
366unsigned short bfin_uart2_peripherals[] = {
367 P_UART2_TX, P_UART2_RX, 0
368};
369
370static struct platform_device bfin_uart2_device = {
371 .name = "bfin-uart",
372 .id = 2,
373 .num_resources = ARRAY_SIZE(bfin_uart2_resources),
374 .resource = bfin_uart2_resources,
375 .dev = {
376 .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
377 },
378};
24a07a12
RH		 379#endif
380#ifdef CONFIG_SERIAL_BFIN_UART3
6bd1fbea 381static struct resource bfin_uart3_resources[] = {
24a07a12 382 {
6bd1fbea
SZ		 383 .start = UART3_DLL,
384 .end = UART3_RBR+2,
cc2e16bd 385 .flags = IORESOURCE_MEM,
24a07a12 386 },
6bd1fbea
SZ		 387 {
388 .start = IRQ_UART3_RX,
389 .end = IRQ_UART3_RX+1,
390 .flags = IORESOURCE_IRQ,
391 },
392 {
393 .start = IRQ_UART3_ERROR,
394 .end = IRQ_UART3_ERROR,
395 .flags = IORESOURCE_IRQ,
396 },
397 {
398 .start = CH_UART3_TX,
399 .end = CH_UART3_TX,
400 .flags = IORESOURCE_DMA,
401 },
402 {
403 .start = CH_UART3_RX,
404 .end = CH_UART3_RX,
405 .flags = IORESOURCE_DMA,
406 },
407#ifdef CONFIG_BFIN_UART3_CTSRTS
408 { /* CTS pin -- 0 means not supported */
409 .start = GPIO_PB3,
410 .end = GPIO_PB3,
411 .flags = IORESOURCE_IO,
412 },
413 { /* RTS pin -- 0 means not supported */
414 .start = GPIO_PB2,
415 .end = GPIO_PB2,
416 .flags = IORESOURCE_IO,
417 },
24a07a12
RH		 418#endif
419};
420
6bd1fbea
SZ		 421unsigned short bfin_uart3_peripherals[] = {
422 P_UART3_TX, P_UART3_RX,
423#ifdef CONFIG_BFIN_UART3_CTSRTS
424 P_UART3_RTS, P_UART3_CTS,
425#endif
426 0
427};
428
429static struct platform_device bfin_uart3_device = {
24a07a12 430 .name = "bfin-uart",
6bd1fbea
SZ		 431 .id = 3,
432 .num_resources = ARRAY_SIZE(bfin_uart3_resources),
433 .resource = bfin_uart3_resources,
434 .dev = {
435 .platform_data = &bfin_uart3_peripherals, /* Passed to driver */
436 },
24a07a12
RH		 437};
438#endif
6bd1fbea 439#endif
24a07a12 440
5be36d22 441#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
5be36d22 442#ifdef CONFIG_BFIN_SIR0
42bd8bcb 443static struct resource bfin_sir0_resources[] = {
5be36d22
GY		 444 {
445 .start = 0xFFC00400,
446 .end = 0xFFC004FF,
447 .flags = IORESOURCE_MEM,
448 },
42bd8bcb
GY		 449 {
450 .start = IRQ_UART0_RX,
451 .end = IRQ_UART0_RX+1,
452 .flags = IORESOURCE_IRQ,
453 },
454 {
455 .start = CH_UART0_RX,
456 .end = CH_UART0_RX+1,
457 .flags = IORESOURCE_DMA,
458 },
459};
460static struct platform_device bfin_sir0_device = {
461 .name = "bfin_sir",
462 .id = 0,
463 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
464 .resource = bfin_sir0_resources,
465};
5be36d22
GY		 466#endif
467#ifdef CONFIG_BFIN_SIR1
42bd8bcb 468static struct resource bfin_sir1_resources[] = {
5be36d22
GY		 469 {
470 .start = 0xFFC02000,
471 .end = 0xFFC020FF,
472 .flags = IORESOURCE_MEM,
473 },
42bd8bcb
GY		 474 {
475 .start = IRQ_UART1_RX,
476 .end = IRQ_UART1_RX+1,
477 .flags = IORESOURCE_IRQ,
478 },
479 {
480 .start = CH_UART1_RX,
481 .end = CH_UART1_RX+1,
482 .flags = IORESOURCE_DMA,
483 },
484};
485static struct platform_device bfin_sir1_device = {
486 .name = "bfin_sir",
487 .id = 1,
488 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
489 .resource = bfin_sir1_resources,
490};
5be36d22
GY		 491#endif
492#ifdef CONFIG_BFIN_SIR2
42bd8bcb 493static struct resource bfin_sir2_resources[] = {
5be36d22
GY		 494 {
495 .start = 0xFFC02100,
496 .end = 0xFFC021FF,
497 .flags = IORESOURCE_MEM,
498 },
42bd8bcb
GY		 499 {
500 .start = IRQ_UART2_RX,
501 .end = IRQ_UART2_RX+1,
502 .flags = IORESOURCE_IRQ,
503 },
504 {
505 .start = CH_UART2_RX,
506 .end = CH_UART2_RX+1,
507 .flags = IORESOURCE_DMA,
508 },
509};
510static struct platform_device bfin_sir2_device = {
511 .name = "bfin_sir",
512 .id = 2,
513 .num_resources = ARRAY_SIZE(bfin_sir2_resources),
514 .resource = bfin_sir2_resources,
515};
5be36d22
GY		 516#endif
517#ifdef CONFIG_BFIN_SIR3
42bd8bcb 518static struct resource bfin_sir3_resources[] = {
5be36d22
GY		 519 {
520 .start = 0xFFC03100,
521 .end = 0xFFC031FF,
522 .flags = IORESOURCE_MEM,
523 },
42bd8bcb
GY		 524 {
525 .start = IRQ_UART3_RX,
526 .end = IRQ_UART3_RX+1,
527 .flags = IORESOURCE_IRQ,
528 },
529 {
530 .start = CH_UART3_RX,
531 .end = CH_UART3_RX+1,
532 .flags = IORESOURCE_DMA,
533 },
5be36d22 534};
42bd8bcb 535static struct platform_device bfin_sir3_device = {
5be36d22 536 .name = "bfin_sir",
42bd8bcb
GY		 537 .id = 3,
538 .num_resources = ARRAY_SIZE(bfin_sir3_resources),
539 .resource = bfin_sir3_resources,
5be36d22
GY		 540};
541#endif
42bd8bcb 542#endif
5be36d22 543
c6c4d7bb 544#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
7a8b71db
MF		 545#include <linux/smsc911x.h>
546
c6c4d7bb
BW		 547static struct resource smsc911x_resources[] = {
548 {
549 .name = "smsc911x-memory",
550 .start = 0x24000000,
551 .end = 0x24000000 + 0xFF,
552 .flags = IORESOURCE_MEM,
553 },
554 {
555 .start = IRQ_PE8,
556 .end = IRQ_PE8,
557 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
558 },
559};
7a8b71db
MF		 560
561static struct smsc911x_platform_config smsc911x_config = {
562 .flags = SMSC911X_USE_32BIT,
563 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
564 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
565 .phy_interface = PHY_INTERFACE_MODE_MII,
566};
567
c6c4d7bb
BW		 568static struct platform_device smsc911x_device = {
569 .name = "smsc911x",
570 .id = 0,
571 .num_resources = ARRAY_SIZE(smsc911x_resources),
572 .resource = smsc911x_resources,
7a8b71db
MF		 573 .dev = {
574 .platform_data = &smsc911x_config,
575 },
c6c4d7bb
BW		 576};
577#endif
578
c6c4d7bb
BW		 579#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
580static struct resource musb_resources[] = {
581 [0] = {
582 .start = 0xFFC03C00,
583 .end = 0xFFC040FF,
584 .flags = IORESOURCE_MEM,
585 },
586 [1] = { /* general IRQ */
587 .start = IRQ_USB_INT0,
588 .end = IRQ_USB_INT0,
589 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
fcf173e4 590 .name = "mc"
c6c4d7bb
BW		 591 },
592 [2] = { /* DMA IRQ */
593 .start = IRQ_USB_DMA,
594 .end = IRQ_USB_DMA,
595 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
fcf173e4 596 .name = "dma"
c6c4d7bb
BW		 597 },
598};
599
50041acb
BW		 600static struct musb_hdrc_config musb_config = {
601 .multipoint = 0,
602 .dyn_fifo = 0,
603 .soft_con = 1,
604 .dma = 1,
fea05dac
BW		 605 .num_eps = 8,
606 .dma_channels = 8,
50041acb 607 .gpio_vrsel = GPIO_PE7,
85eb0e4b
CC		 608 /* Some custom boards need to be active low, just set it to "0"
609 * if it is the case.
610 */
611 .gpio_vrsel_active = 1,
50041acb
BW		 612};
613
c6c4d7bb 614static struct musb_hdrc_platform_data musb_plat = {
2935077e 615#if defined(CONFIG_USB_MUSB_OTG)
c6c4d7bb 616 .mode = MUSB_OTG,
2935077e 617#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
c6c4d7bb 618 .mode = MUSB_HOST,
2935077e 619#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
c6c4d7bb
BW		 620 .mode = MUSB_PERIPHERAL,
621#endif
50041acb 622 .config = &musb_config,
c6c4d7bb
BW		 623};
624
625static u64 musb_dmamask = ~(u32)0;
626
627static struct platform_device musb_device = {
9cb0308e 628 .name = "musb-blackfin",
c6c4d7bb
BW		 629 .id = 0,
630 .dev = {
631 .dma_mask = &musb_dmamask,
632 .coherent_dma_mask = 0xffffffff,
633 .platform_data = &musb_plat,
634 },
635 .num_resources = ARRAY_SIZE(musb_resources),
636 .resource = musb_resources,
637};
638#endif
639
df5de261
SZ		 640#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
641#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
642static struct resource bfin_sport0_uart_resources[] = {
643 {
644 .start = SPORT0_TCR1,
645 .end = SPORT0_MRCS3+4,
646 .flags = IORESOURCE_MEM,
647 },
648 {
649 .start = IRQ_SPORT0_RX,
650 .end = IRQ_SPORT0_RX+1,
651 .flags = IORESOURCE_IRQ,
652 },
653 {
654 .start = IRQ_SPORT0_ERROR,
655 .end = IRQ_SPORT0_ERROR,
656 .flags = IORESOURCE_IRQ,
657 },
658};
659
660unsigned short bfin_sport0_peripherals[] = {
661 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
662 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
663};
664
665static struct platform_device bfin_sport0_uart_device = {
666 .name = "bfin-sport-uart",
667 .id = 0,
668 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
669 .resource = bfin_sport0_uart_resources,
670 .dev = {
671 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
672 },
673};
674#endif
675#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
676static struct resource bfin_sport1_uart_resources[] = {
677 {
678 .start = SPORT1_TCR1,
679 .end = SPORT1_MRCS3+4,
680 .flags = IORESOURCE_MEM,
681 },
682 {
683 .start = IRQ_SPORT1_RX,
684 .end = IRQ_SPORT1_RX+1,
685 .flags = IORESOURCE_IRQ,
686 },
687 {
688 .start = IRQ_SPORT1_ERROR,
689 .end = IRQ_SPORT1_ERROR,
690 .flags = IORESOURCE_IRQ,
691 },
692};
693
694unsigned short bfin_sport1_peripherals[] = {
695 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
696 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
697};
698
699static struct platform_device bfin_sport1_uart_device = {
700 .name = "bfin-sport-uart",
701 .id = 1,
702 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
703 .resource = bfin_sport1_uart_resources,
704 .dev = {
705 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
706 },
707};
708#endif
709#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
710static struct resource bfin_sport2_uart_resources[] = {
711 {
712 .start = SPORT2_TCR1,
713 .end = SPORT2_MRCS3+4,
714 .flags = IORESOURCE_MEM,
715 },
716 {
717 .start = IRQ_SPORT2_RX,
718 .end = IRQ_SPORT2_RX+1,
719 .flags = IORESOURCE_IRQ,
720 },
721 {
722 .start = IRQ_SPORT2_ERROR,
723 .end = IRQ_SPORT2_ERROR,
724 .flags = IORESOURCE_IRQ,
725 },
726};
727
728unsigned short bfin_sport2_peripherals[] = {
729 P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
730 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
731};
732
733static struct platform_device bfin_sport2_uart_device = {
734 .name = "bfin-sport-uart",
735 .id = 2,
736 .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
737 .resource = bfin_sport2_uart_resources,
738 .dev = {
739 .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
740 },
741};
742#endif
743#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
744static struct resource bfin_sport3_uart_resources[] = {
745 {
746 .start = SPORT3_TCR1,
747 .end = SPORT3_MRCS3+4,
748 .flags = IORESOURCE_MEM,
749 },
750 {
751 .start = IRQ_SPORT3_RX,
752 .end = IRQ_SPORT3_RX+1,
753 .flags = IORESOURCE_IRQ,
754 },
755 {
756 .start = IRQ_SPORT3_ERROR,
757 .end = IRQ_SPORT3_ERROR,
758 .flags = IORESOURCE_IRQ,
759 },
760};
761
762unsigned short bfin_sport3_peripherals[] = {
763 P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
764 P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
765};
766
767static struct platform_device bfin_sport3_uart_device = {
768 .name = "bfin-sport-uart",
769 .id = 3,
770 .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources),
771 .resource = bfin_sport3_uart_resources,
772 .dev = {
773 .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
774 },
775};
776#endif
777#endif
778
706a01b1
BS		 779#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
780unsigned short bfin_can_peripherals[] = {
781 P_CAN0_RX, P_CAN0_TX, 0
782};
783
784static struct resource bfin_can_resources[] = {
785 {
786 .start = 0xFFC02A00,
787 .end = 0xFFC02FFF,
788 .flags = IORESOURCE_MEM,
789 },
790 {
791 .start = IRQ_CAN0_RX,
792 .end = IRQ_CAN0_RX,
793 .flags = IORESOURCE_IRQ,
794 },
795 {
796 .start = IRQ_CAN0_TX,
797 .end = IRQ_CAN0_TX,
798 .flags = IORESOURCE_IRQ,
799 },
800 {
801 .start = IRQ_CAN0_ERROR,
802 .end = IRQ_CAN0_ERROR,
803 .flags = IORESOURCE_IRQ,
804 },
805};
806
807static struct platform_device bfin_can_device = {
808 .name = "bfin_can",
809 .num_resources = ARRAY_SIZE(bfin_can_resources),
810 .resource = bfin_can_resources,
811 .dev = {
812 .platform_data = &bfin_can_peripherals, /* Passed to driver */
813 },
814};
815#endif
816
c6c4d7bb
BW		 817#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
818static struct resource bfin_atapi_resources[] = {
819 {
820 .start = 0xFFC03800,
821 .end = 0xFFC0386F,
822 .flags = IORESOURCE_MEM,
823 },
824 {
825 .start = IRQ_ATAPI_ERR,
826 .end = IRQ_ATAPI_ERR,
827 .flags = IORESOURCE_IRQ,
828 },
829};
830
831static struct platform_device bfin_atapi_device = {
832 .name = "pata-bf54x",
833 .id = -1,
834 .num_resources = ARRAY_SIZE(bfin_atapi_resources),
835 .resource = bfin_atapi_resources,
836};
837#endif
838
839#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
840static struct mtd_partition partition_info[] = {
841 {
73775b89 842 .name = "bootloader(nand)",
c6c4d7bb 843 .offset = 0,
73775b89
MF		 844 .size = 0x80000,
845 }, {
846 .name = "linux kernel(nand)",
847 .offset = MTDPART_OFS_APPEND,
f4585a08 848 .size = 4 * 1024 * 1024,
c6c4d7bb
BW		 849 },
850 {
aa582977 851 .name = "file system(nand)",
edf05641
MF		 852 .offset = MTDPART_OFS_APPEND,
853 .size = MTDPART_SIZ_FULL,
c6c4d7bb
BW		 854 },
855};
856
857static struct bf5xx_nand_platform bf5xx_nand_platform = {
c6c4d7bb
BW		 858 .data_width = NFC_NWIDTH_8,
859 .partitions = partition_info,
860 .nr_partitions = ARRAY_SIZE(partition_info),
861 .rd_dly = 3,
862 .wr_dly = 3,
863};
864
865static struct resource bf5xx_nand_resources[] = {
866 {
867 .start = 0xFFC03B00,
868 .end = 0xFFC03B4F,
869 .flags = IORESOURCE_MEM,
870 },
871 {
872 .start = CH_NFC,
873 .end = CH_NFC,
874 .flags = IORESOURCE_IRQ,
875 },
876};
877
878static struct platform_device bf5xx_nand_device = {
879 .name = "bf5xx-nand",
880 .id = 0,
881 .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
882 .resource = bf5xx_nand_resources,
883 .dev = {
884 .platform_data = &bf5xx_nand_platform,
885 },
886};
887#endif
888
3d7e6cf8 889#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
501674a5
CC		 890
891static struct bfin_sd_host bfin_sdh_data = {
892 .dma_chan = CH_SDH,
893 .irq_int0 = IRQ_SDH_MASK0,
894 .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0},
895};
896
c6c4d7bb
BW		 897static struct platform_device bf54x_sdh_device = {
898 .name = "bfin-sdh",
899 .id = 0,
501674a5
CC		 900 .dev = {
901 .platform_data = &bfin_sdh_data,
902 },
c6c4d7bb
BW		 903};
904#endif
905
793dc27b 906#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2
MF		 907static struct mtd_partition ezkit_partitions[] = {
908 {
aa582977 909 .name = "bootloader(nor)",
73775b89 910 .size = 0x80000,
de8c43f2
MF		 911 .offset = 0,
912 }, {
aa582977 913 .name = "linux kernel(nor)",
664d0403 914 .size = 0x400000,
de8c43f2
MF		 915 .offset = MTDPART_OFS_APPEND,
916 }, {
aa582977 917 .name = "file system(nor)",
de8c43f2
MF		 918 .size = MTDPART_SIZ_FULL,
919 .offset = MTDPART_OFS_APPEND,
920 }
921};
922
923static struct physmap_flash_data ezkit_flash_data = {
924 .width = 2,
925 .parts = ezkit_partitions,
926 .nr_parts = ARRAY_SIZE(ezkit_partitions),
927};
928
929static struct resource ezkit_flash_resource = {
930 .start = 0x20000000,
664d0403 931 .end = 0x21ffffff,
de8c43f2
MF		 932 .flags = IORESOURCE_MEM,
933};
934
935static struct platform_device ezkit_flash_device = {
936 .name = "physmap-flash",
937 .id = 0,
938 .dev = {
939 .platform_data = &ezkit_flash_data,
940 },
941 .num_resources = 1,
942 .resource = &ezkit_flash_resource,
943};
793dc27b 944#endif
de8c43f2 945
c6c4d7bb
BW		 946#if defined(CONFIG_MTD_M25P80) \
947 || defined(CONFIG_MTD_M25P80_MODULE)
948/* SPI flash chip (m25p16) */
949static struct mtd_partition bfin_spi_flash_partitions[] = {
950 {
aa582977 951 .name = "bootloader(spi)",
73775b89 952 .size = 0x00080000,
c6c4d7bb
BW		 953 .offset = 0,
954 .mask_flags = MTD_CAP_ROM
955 }, {
aa582977 956 .name = "linux kernel(spi)",
edf05641
MF		 957 .size = MTDPART_SIZ_FULL,
958 .offset = MTDPART_OFS_APPEND,
c6c4d7bb
BW		 959 }
960};
961
962static struct flash_platform_data bfin_spi_flash_data = {
963 .name = "m25p80",
964 .parts = bfin_spi_flash_partitions,
965 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
966 .type = "m25p16",
967};
968
969static struct bfin5xx_spi_chip spi_flash_chip_info = {
970 .enable_dma = 0, /* use dma transfer with this chip*/
971 .bits_per_word = 8,
c6c4d7bb
BW		 972};
973#endif
974
7ba80063
BS		 975#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
976 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
37fa2421
BS		 977static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
978 .enable_dma = 0,
979 .bits_per_word = 16,
980};
981#endif
982
c6c4d7bb
BW		 983#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
984static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
c6c4d7bb
BW		 985 .enable_dma = 0,
986 .bits_per_word = 16,
987};
988
989static const struct ad7877_platform_data bfin_ad7877_ts_info = {
990 .model = 7877,
991 .vref_delay_usecs = 50, /* internal, no capacitor */
992 .x_plate_ohms = 419,
993 .y_plate_ohms = 486,
994 .pressure_max = 1000,
995 .pressure_min = 0,
996 .stopacq_polarity = 1,
997 .first_conversion_delay = 3,
998 .acquisition_time = 1,
999 .averaging = 1,
1000 .pen_down_acc_interval = 1,
1001};
1002#endif
1003
6e668936
MH		 1004#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
1005static struct bfin5xx_spi_chip spidev_chip_info = {
1006 .enable_dma = 0,
1007 .bits_per_word = 8,
1008};
1009#endif
1010
ffc4d8bc
MH		 1011#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
1012static struct bfin5xx_spi_chip spi_adxl34x_chip_info = {
1013 .enable_dma = 0, /* use dma transfer with this chip*/
1014 .bits_per_word = 8,
ffc4d8bc
MH		 1015};
1016#endif
1017
5bda2723 1018static struct spi_board_info bfin_spi_board_info[] __initdata = {
c6c4d7bb
BW		 1019#if defined(CONFIG_MTD_M25P80) \
1020 || defined(CONFIG_MTD_M25P80_MODULE)
1021 {
1022 /* the modalias must be the same as spi device driver name */
1023 .modalias = "m25p80", /* Name of spi_driver for this device */
1024 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
1025 .bus_num = 0, /* Framework bus number */
1026 .chip_select = 1, /* SPI_SSEL1*/
1027 .platform_data = &bfin_spi_flash_data,
1028 .controller_data = &spi_flash_chip_info,
1029 .mode = SPI_MODE_3,
1030 },
1031#endif
7ba80063
BS		 1032#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
1033 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
37fa2421 1034 {
7ba80063 1035 .modalias = "ad183x",
37fa2421
BS		 1036 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1037 .bus_num = 1,
7ba80063 1038 .chip_select = 4,
37fa2421
BS		 1039 .controller_data = &ad1836_spi_chip_info,
1040 },
1041#endif
c6c4d7bb 1042#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
ffc4d8bc
MH		 1043 {
1044 .modalias = "ad7877",
1045 .platform_data = &bfin_ad7877_ts_info,
1046 .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */
1047 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
1048 .bus_num = 0,
1049 .chip_select = 2,
1050 .controller_data = &spi_ad7877_chip_info,
1051 },
c6c4d7bb 1052#endif
6e668936
MH		 1053#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
1054 {
1055 .modalias = "spidev",
1056 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1057 .bus_num = 0,
1058 .chip_select = 1,
1059 .controller_data = &spidev_chip_info,
1060 },
1061#endif
ffc4d8bc
MH		 1062#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
1063 {
1064 .modalias = "adxl34x",
1065 .platform_data = &adxl34x_info,
1066 .irq = IRQ_PC5,
1067 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
1068 .bus_num = 1,
1069 .chip_select = 2,
1070 .controller_data = &spi_adxl34x_chip_info,
1071 .mode = SPI_MODE_3,
1072 },
1073#endif
c6c4d7bb 1074};
5bda2723 1075#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
c6c4d7bb
BW		 1076/* SPI (0) */
1077static struct resource bfin_spi0_resource[] = {
1078 [0] = {
1079 .start = SPI0_REGBASE,
1080 .end = SPI0_REGBASE + 0xFF,
1081 .flags = IORESOURCE_MEM,
1082 },
1083 [1] = {
1084 .start = CH_SPI0,
1085 .end = CH_SPI0,
53122693
YL		 1086 .flags = IORESOURCE_DMA,
1087 },
1088 [2] = {
1089 .start = IRQ_SPI0,
1090 .end = IRQ_SPI0,
c6c4d7bb
BW		 1091 .flags = IORESOURCE_IRQ,
1092 }
1093};
1094
1095/* SPI (1) */
1096static struct resource bfin_spi1_resource[] = {
1097 [0] = {
1098 .start = SPI1_REGBASE,
1099 .end = SPI1_REGBASE + 0xFF,
1100 .flags = IORESOURCE_MEM,
1101 },
1102 [1] = {
1103 .start = CH_SPI1,
1104 .end = CH_SPI1,
53122693
YL		 1105 .flags = IORESOURCE_DMA,
1106 },
1107 [2] = {
1108 .start = IRQ_SPI1,
1109 .end = IRQ_SPI1,
c6c4d7bb
BW		 1110 .flags = IORESOURCE_IRQ,
1111 }
1112};
1113
1114/* SPI controller data */
5d448dd5 1115static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
c5af5451 1116 .num_chipselect = 4,
c6c4d7bb 1117 .enable_dma = 1, /* master has the ability to do dma transfer */
5d448dd5 1118 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
c6c4d7bb
BW		 1119};
1120
1121static struct platform_device bf54x_spi_master0 = {
1122 .name = "bfin-spi",
1123 .id = 0, /* Bus number */
1124 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
1125 .resource = bfin_spi0_resource,
1126 .dev = {
5d448dd5 1127 .platform_data = &bf54x_spi_master_info0, /* Passed to driver */
c6c4d7bb
BW		 1128 },
1129};
1130
5d448dd5 1131static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
c5af5451 1132 .num_chipselect = 4,
5d448dd5
BW		 1133 .enable_dma = 1, /* master has the ability to do dma transfer */
1134 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
1135};
1136
c6c4d7bb
BW		 1137static struct platform_device bf54x_spi_master1 = {
1138 .name = "bfin-spi",
1139 .id = 1, /* Bus number */
1140 .num_resources = ARRAY_SIZE(bfin_spi1_resource),
1141 .resource = bfin_spi1_resource,
1142 .dev = {
5d448dd5 1143 .platform_data = &bf54x_spi_master_info1, /* Passed to driver */
c6c4d7bb
BW		 1144 },
1145};
1146#endif /* spi master and devices */
1147
1148#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1149static struct resource bfin_twi0_resource[] = {
1150 [0] = {
1151 .start = TWI0_REGBASE,
1152 .end = TWI0_REGBASE + 0xFF,
1153 .flags = IORESOURCE_MEM,
1154 },
1155 [1] = {
1156 .start = IRQ_TWI0,
1157 .end = IRQ_TWI0,
1158 .flags = IORESOURCE_IRQ,
1159 },
1160};
1161
1162static struct platform_device i2c_bfin_twi0_device = {
1163 .name = "i2c-bfin-twi",
1164 .id = 0,
1165 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1166 .resource = bfin_twi0_resource,
1167};
1168
7160e950 1169#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
c6c4d7bb
BW		 1170static struct resource bfin_twi1_resource[] = {
1171 [0] = {
1172 .start = TWI1_REGBASE,
1173 .end = TWI1_REGBASE + 0xFF,
1174 .flags = IORESOURCE_MEM,
1175 },
1176 [1] = {
1177 .start = IRQ_TWI1,
1178 .end = IRQ_TWI1,
1179 .flags = IORESOURCE_IRQ,
1180 },
1181};
1182
1183static struct platform_device i2c_bfin_twi1_device = {
1184 .name = "i2c-bfin-twi",
1185 .id = 1,
1186 .num_resources = ARRAY_SIZE(bfin_twi1_resource),
1187 .resource = bfin_twi1_resource,
1188};
1189#endif
7160e950 1190#endif
c6c4d7bb 1191
81d9c7f2
BW		 1192static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
1193};
1194
1195#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
1196static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
ebd58333 1197#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
81d9c7f2
BW		 1198 {
1199 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
81d9c7f2
BW		 1200 },
1201#endif
204844eb 1202#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
81d9c7f2
BW		 1203 {
1204 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
81d9c7f2
BW		 1205 .irq = 212,
1206 },
1207#endif
ffc4d8bc
MH		 1208#if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
1209 {
1210 I2C_BOARD_INFO("adxl34x", 0x53),
1211 .irq = IRQ_PC5,
1212 .platform_data = (void *)&adxl34x_info,
1213 },
1214#endif
39d3c1ca 1215#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
1216 {
1217 I2C_BOARD_INFO("ad5252", 0x2f),
1218 },
1219#endif
81d9c7f2
BW		 1220};
1221#endif
81d9c7f2 1222
2463ef22
MH		 1223#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1224#include <linux/gpio_keys.h>
1225
1226static struct gpio_keys_button bfin_gpio_keys_table[] = {
1227 {BTN_0, GPIO_PB8, 1, "gpio-keys: BTN0"},
1228 {BTN_1, GPIO_PB9, 1, "gpio-keys: BTN1"},
1229 {BTN_2, GPIO_PB10, 1, "gpio-keys: BTN2"},
1230 {BTN_3, GPIO_PB11, 1, "gpio-keys: BTN3"},
1231};
1232
1233static struct gpio_keys_platform_data bfin_gpio_keys_data = {
1234 .buttons = bfin_gpio_keys_table,
1235 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
1236};
1237
1238static struct platform_device bfin_device_gpiokeys = {
1239 .name = "gpio-keys",
1240 .dev = {
1241 .platform_data = &bfin_gpio_keys_data,
1242 },
1243};
1244#endif
1245
14b03204
MH		 1246static const unsigned int cclk_vlev_datasheet[] =
1247{
1248/*
1249 * Internal VLEV BF54XSBBC1533
1250 ****temporarily using these values until data sheet is updated
1251 */
1252 VRPAIR(VLEV_085, 150000000),
1253 VRPAIR(VLEV_090, 250000000),
1254 VRPAIR(VLEV_110, 276000000),
1255 VRPAIR(VLEV_115, 301000000),
1256 VRPAIR(VLEV_120, 525000000),
1257 VRPAIR(VLEV_125, 550000000),
1258 VRPAIR(VLEV_130, 600000000),
1259};
1260
1261static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
1262 .tuple_tab = cclk_vlev_datasheet,
1263 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
1264 .vr_settling_time = 25 /* us */,
1265};
1266
1267static struct platform_device bfin_dpmc = {
1268 .name = "bfin dpmc",
1269 .dev = {
1270 .platform_data = &bfin_dmpc_vreg_data,
1271 },
1272};
1273
439b4867
BS		 1274#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
1275static struct platform_device bfin_i2s = {
1276 .name = "bfin-i2s",
1277 .id = CONFIG_SND_BF5XX_SPORT_NUM,
1278 /* TODO: add platform data here */
1279};
1280#endif
1281
1282#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
1283static struct platform_device bfin_tdm = {
1284 .name = "bfin-tdm",
1285 .id = CONFIG_SND_BF5XX_SPORT_NUM,
1286 /* TODO: add platform data here */
1287};
1288#endif
1289
1290#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
1291static struct platform_device bfin_ac97 = {
1292 .name = "bfin-ac97",
1293 .id = CONFIG_SND_BF5XX_SPORT_NUM,
1294 /* TODO: add platform data here */
1295};
1296#endif
1297
24a07a12 1298static struct platform_device *ezkit_devices[] __initdata = {
14b03204
MH		 1299
1300 &bfin_dpmc,
1301
24a07a12
RH		 1302#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
1303 &rtc_device,
1304#endif
1305
1306#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
6bd1fbea
SZ		 1307#ifdef CONFIG_SERIAL_BFIN_UART0
1308 &bfin_uart0_device,
1309#endif
1310#ifdef CONFIG_SERIAL_BFIN_UART1
1311 &bfin_uart1_device,
1312#endif
1313#ifdef CONFIG_SERIAL_BFIN_UART2
1314 &bfin_uart2_device,
1315#endif
1316#ifdef CONFIG_SERIAL_BFIN_UART3
1317 &bfin_uart3_device,
1318#endif
24a07a12 1319#endif
c6c4d7bb 1320
5be36d22 1321#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb
GY		 1322#ifdef CONFIG_BFIN_SIR0
1323 &bfin_sir0_device,
1324#endif
1325#ifdef CONFIG_BFIN_SIR1
1326 &bfin_sir1_device,
1327#endif
1328#ifdef CONFIG_BFIN_SIR2
1329 &bfin_sir2_device,
1330#endif
1331#ifdef CONFIG_BFIN_SIR3
1332 &bfin_sir3_device,
1333#endif
5be36d22
GY		 1334#endif
1335
c6c4d7bb
BW		 1336#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
1337 &bf54x_lq043_device,
1338#endif
1339
1340#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
1341 &smsc911x_device,
1342#endif
1343
c6c4d7bb
BW		 1344#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
1345 &musb_device,
1346#endif
1347
3f375690
MH		 1348#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
1349 &bfin_isp1760_device,
1350#endif
1351
df5de261
SZ		 1352#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
1353#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1354 &bfin_sport0_uart_device,
1355#endif
1356#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1357 &bfin_sport1_uart_device,
1358#endif
1359#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1360 &bfin_sport2_uart_device,
1361#endif
1362#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
1363 &bfin_sport3_uart_device,
1364#endif
1365#endif
1366
706a01b1
BS		 1367#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
1368 &bfin_can_device,
1369#endif
1370
c6c4d7bb
BW		 1371#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
1372 &bfin_atapi_device,
1373#endif
1374
1375#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
1376 &bf5xx_nand_device,
1377#endif
1378
3d7e6cf8 1379#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
c6c4d7bb
BW		 1380 &bf54x_sdh_device,
1381#endif
1382
1383#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
1384 &bf54x_spi_master0,
d4b1d273 1385 &bf54x_spi_master1,
c6c4d7bb
BW		 1386#endif
1387
1388#if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE)
1389 &bf54x_kpad_device,
1390#endif
1391
adfc0467 1392#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
aca5e4aa
MH		 1393 &bfin_rotary_device,
1394#endif
1395
c6c4d7bb
BW		 1396#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1397 &i2c_bfin_twi0_device,
7160e950 1398#if !defined(CONFIG_BF542)
c6c4d7bb
BW		 1399 &i2c_bfin_twi1_device,
1400#endif
7160e950 1401#endif
2463ef22
MH		 1402
1403#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1404 &bfin_device_gpiokeys,
1405#endif
cad2ab65 1406
793dc27b 1407#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2 1408 &ezkit_flash_device,
793dc27b 1409#endif
439b4867
BS		 1410
1411#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
1412 &bfin_i2s,
1413#endif
1414
1415#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
1416 &bfin_tdm,
1417#endif
1418
1419#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
1420 &bfin_ac97,
1421#endif
24a07a12
RH		 1422};
1423
a01d7a76 1424static int __init ezkit_init(void)
24a07a12 1425{
b85d858b 1426 printk(KERN_INFO "%s(): registering device resources\n", __func__);
81d9c7f2 1427
81d9c7f2
BW		 1428 i2c_register_board_info(0, bfin_i2c_board_info0,
1429 ARRAY_SIZE(bfin_i2c_board_info0));
1430#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
1431 i2c_register_board_info(1, bfin_i2c_board_info1,
1432 ARRAY_SIZE(bfin_i2c_board_info1));
81d9c7f2
BW		 1433#endif
1434
24a07a12 1435 platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
c6c4d7bb 1436
5bda2723 1437 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
c6c4d7bb 1438
24a07a12
RH		 1439 return 0;
1440}
1441
a01d7a76 1442arch_initcall(ezkit_init);
c13ce9fd
SZ		 1443
1444static struct platform_device *ezkit_early_devices[] __initdata = {
1445#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
1446#ifdef CONFIG_SERIAL_BFIN_UART0
1447 &bfin_uart0_device,
1448#endif
1449#ifdef CONFIG_SERIAL_BFIN_UART1
1450 &bfin_uart1_device,
1451#endif
1452#ifdef CONFIG_SERIAL_BFIN_UART2
1453 &bfin_uart2_device,
1454#endif
1455#ifdef CONFIG_SERIAL_BFIN_UART3
1456 &bfin_uart3_device,
1457#endif
1458#endif
1459
1460#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
1461#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1462 &bfin_sport0_uart_device,
1463#endif
1464#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1465 &bfin_sport1_uart_device,
1466#endif
1467#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1468 &bfin_sport2_uart_device,
1469#endif
1470#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
1471 &bfin_sport3_uart_device,
1472#endif
1473#endif
1474};
1475
1476void __init native_machine_early_platform_add_devices(void)
1477{
1478 printk(KERN_INFO "register early platform devices\n");
1479 early_platform_add_devices(ezkit_early_devices,
1480 ARRAY_SIZE(ezkit_early_devices));
1481}
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