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blackfin: bf561: forgot CSYNC in get_core_lock_noflush
[mirror_ubuntu-zesty-kernel.git] / arch / blackfin / mach-bf548 / boards / ezkit.c
CommitLineData
24a07a12 1/*
96f1050d
RG		 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2005 National ICT Australia (NICTA)
4 * Aidan Williams <aidan@nicta.com.au>
24a07a12 5 *
96f1050d 6 * Licensed under the GPL-2 or later.
24a07a12
RH		 7 */
8
9#include <linux/device.h>
10#include <linux/platform_device.h>
11#include <linux/mtd/mtd.h>
12#include <linux/mtd/partitions.h>
de8c43f2 13#include <linux/mtd/physmap.h>
24a07a12
RH		 14#include <linux/spi/spi.h>
15#include <linux/spi/flash.h>
1f83b8f1 16#include <linux/irq.h>
81d9c7f2 17#include <linux/i2c.h>
24a07a12 18#include <linux/interrupt.h>
c6c4d7bb 19#include <linux/usb/musb.h>
24a07a12 20#include <asm/bfin5xx_spi.h>
c6c4d7bb
BW		 21#include <asm/dma.h>
22#include <asm/gpio.h>
23#include <asm/nand.h>
14b03204 24#include <asm/dpmc.h>
6f53dbbb 25#include <asm/bfin_sport.h>
5d448dd5 26#include <asm/portmux.h>
501674a5 27#include <asm/bfin_sdh.h>
639f6571 28#include <mach/bf54x_keys.h>
c6c4d7bb
BW		 29#include <linux/input.h>
30#include <linux/spi/ad7877.h>
24a07a12
RH		 31
32/*
33 * Name the Board for the /proc/cpuinfo
34 */
fe85cad2 35const char bfin_board_name[] = "ADI BF548-EZKIT";
24a07a12
RH		 36
37/*
38 * Driver needs to know address, irq and flag pin.
39 */
40
0a6304a9 41#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
3f375690
MH		 42#include <linux/usb/isp1760.h>
43static struct resource bfin_isp1760_resources[] = {
0a6304a9 44 [0] = {
0a6304a9
MH		 45 .start = 0x2C0C0000,
46 .end = 0x2C0C0000 + 0xfffff,
47 .flags = IORESOURCE_MEM,
48 },
49 [1] = {
50 .start = IRQ_PG7,
51 .end = IRQ_PG7,
52 .flags = IORESOURCE_IRQ,
53 },
54};
55
3f375690
MH		 56static struct isp1760_platform_data isp1760_priv = {
57 .is_isp1761 = 0,
3f375690
MH		 58 .bus_width_16 = 1,
59 .port1_otg = 0,
60 .analog_oc = 0,
61 .dack_polarity_high = 0,
62 .dreq_polarity_high = 0,
0a6304a9
MH		 63};
64
3f375690 65static struct platform_device bfin_isp1760_device = {
c6feb768 66 .name = "isp1760",
3f375690
MH		 67 .id = 0,
68 .dev = {
69 .platform_data = &isp1760_priv,
70 },
71 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
72 .resource = bfin_isp1760_resources,
0a6304a9 73};
0a6304a9
MH		 74#endif
75
c6c4d7bb
BW		 76#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
77
639f6571 78#include <mach/bf54x-lq043.h>
c6c4d7bb
BW		 79
80static struct bfin_bf54xfb_mach_info bf54x_lq043_data = {
0e101ec1
SP		 81 .width = 95,
82 .height = 54,
c6c4d7bb
BW		 83 .xres = {480, 480, 480},
84 .yres = {272, 272, 272},
85 .bpp = {24, 24, 24},
86 .disp = GPIO_PE3,
87};
88
89static struct resource bf54x_lq043_resources[] = {
90 {
91 .start = IRQ_EPPI0_ERR,
92 .end = IRQ_EPPI0_ERR,
93 .flags = IORESOURCE_IRQ,
94 },
95};
96
97static struct platform_device bf54x_lq043_device = {
98 .name = "bf54x-lq043",
99 .id = -1,
100 .num_resources = ARRAY_SIZE(bf54x_lq043_resources),
101 .resource = bf54x_lq043_resources,
102 .dev = {
103 .platform_data = &bf54x_lq043_data,
104 },
105};
106#endif
107
108#if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE)
8f740ef3 109static const unsigned int bf548_keymap[] = {
c6c4d7bb
BW		 110 KEYVAL(0, 0, KEY_ENTER),
111 KEYVAL(0, 1, KEY_HELP),
112 KEYVAL(0, 2, KEY_0),
113 KEYVAL(0, 3, KEY_BACKSPACE),
114 KEYVAL(1, 0, KEY_TAB),
115 KEYVAL(1, 1, KEY_9),
116 KEYVAL(1, 2, KEY_8),
117 KEYVAL(1, 3, KEY_7),
118 KEYVAL(2, 0, KEY_DOWN),
119 KEYVAL(2, 1, KEY_6),
120 KEYVAL(2, 2, KEY_5),
121 KEYVAL(2, 3, KEY_4),
122 KEYVAL(3, 0, KEY_UP),
123 KEYVAL(3, 1, KEY_3),
124 KEYVAL(3, 2, KEY_2),
125 KEYVAL(3, 3, KEY_1),
126};
127
128static struct bfin_kpad_platform_data bf54x_kpad_data = {
129 .rows = 4,
130 .cols = 4,
8f740ef3
MH		 131 .keymap = bf548_keymap,
132 .keymapsize = ARRAY_SIZE(bf548_keymap),
c6c4d7bb
BW		 133 .repeat = 0,
134 .debounce_time = 5000, /* ns (5ms) */
135 .coldrive_time = 1000, /* ns (1ms) */
136 .keyup_test_interval = 50, /* ms (50ms) */
137};
138
139static struct resource bf54x_kpad_resources[] = {
140 {
141 .start = IRQ_KEY,
142 .end = IRQ_KEY,
143 .flags = IORESOURCE_IRQ,
144 },
145};
146
147static struct platform_device bf54x_kpad_device = {
148 .name = "bf54x-keys",
149 .id = -1,
150 .num_resources = ARRAY_SIZE(bf54x_kpad_resources),
151 .resource = bf54x_kpad_resources,
152 .dev = {
153 .platform_data = &bf54x_kpad_data,
154 },
155};
156#endif
157
adfc0467 158#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
aca5e4aa
MH		 159#include <asm/bfin_rotary.h>
160
161static struct bfin_rotary_platform_data bfin_rotary_data = {
162 /*.rotary_up_key = KEY_UP,*/
163 /*.rotary_down_key = KEY_DOWN,*/
164 .rotary_rel_code = REL_WHEEL,
165 .rotary_button_key = KEY_ENTER,
166 .debounce = 10, /* 0..17 */
167 .mode = ROT_QUAD_ENC | ROT_DEBE,
168};
169
170static struct resource bfin_rotary_resources[] = {
171 {
172 .start = IRQ_CNT,
173 .end = IRQ_CNT,
174 .flags = IORESOURCE_IRQ,
175 },
176};
177
178static struct platform_device bfin_rotary_device = {
179 .name = "bfin-rotary",
180 .id = -1,
181 .num_resources = ARRAY_SIZE(bfin_rotary_resources),
182 .resource = bfin_rotary_resources,
183 .dev = {
184 .platform_data = &bfin_rotary_data,
185 },
186};
187#endif
188
ffc4d8bc 189#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
57af8edf 190#include <linux/input/adxl34x.h>
ffc4d8bc
MH		 191static const struct adxl34x_platform_data adxl34x_info = {
192 .x_axis_offset = 0,
193 .y_axis_offset = 0,
194 .z_axis_offset = 0,
195 .tap_threshold = 0x31,
196 .tap_duration = 0x10,
197 .tap_latency = 0x60,
198 .tap_window = 0xF0,
199 .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
200 .act_axis_control = 0xFF,
201 .activity_threshold = 5,
202 .inactivity_threshold = 3,
203 .inactivity_time = 4,
204 .free_fall_threshold = 0x7,
205 .free_fall_time = 0x20,
206 .data_rate = 0x8,
207 .data_range = ADXL_FULL_RES,
208
209 .ev_type = EV_ABS,
210 .ev_code_x = ABS_X, /* EV_REL */
211 .ev_code_y = ABS_Y, /* EV_REL */
212 .ev_code_z = ABS_Z, /* EV_REL */
213
57af8edf 214 .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
ffc4d8bc
MH		 215
216/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
217/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
218 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
219 .fifo_mode = ADXL_FIFO_STREAM,
5db4036b
MH		 220 .orientation_enable = ADXL_EN_ORIENTATION_3D,
221 .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
222 .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
223 /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
224 .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
ffc4d8bc
MH		 225};
226#endif
227
24a07a12
RH		 228#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
229static struct platform_device rtc_device = {
230 .name = "rtc-bfin",
231 .id = -1,
232};
233#endif
234
235#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
24a07a12 236#ifdef CONFIG_SERIAL_BFIN_UART0
6bd1fbea 237static struct resource bfin_uart0_resources[] = {
24a07a12 238 {
6bd1fbea
SZ		 239 .start = UART0_DLL,
240 .end = UART0_RBR+2,
24a07a12
RH		 241 .flags = IORESOURCE_MEM,
242 },
edb0a640
SZ		 243 {
244 .start = IRQ_UART0_TX,
245 .end = IRQ_UART0_TX,
246 .flags = IORESOURCE_IRQ,
247 },
6bd1fbea
SZ		 248 {
249 .start = IRQ_UART0_RX,
edb0a640 250 .end = IRQ_UART0_RX,
6bd1fbea
SZ		 251 .flags = IORESOURCE_IRQ,
252 },
253 {
254 .start = IRQ_UART0_ERROR,
255 .end = IRQ_UART0_ERROR,
256 .flags = IORESOURCE_IRQ,
257 },
258 {
259 .start = CH_UART0_TX,
260 .end = CH_UART0_TX,
261 .flags = IORESOURCE_DMA,
262 },
263 {
264 .start = CH_UART0_RX,
265 .end = CH_UART0_RX,
266 .flags = IORESOURCE_DMA,
267 },
268};
269
a8b19886 270static unsigned short bfin_uart0_peripherals[] = {
6bd1fbea
SZ		 271 P_UART0_TX, P_UART0_RX, 0
272};
273
274static struct platform_device bfin_uart0_device = {
275 .name = "bfin-uart",
276 .id = 0,
277 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
278 .resource = bfin_uart0_resources,
279 .dev = {
280 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
281 },
282};
24a07a12
RH		 283#endif
284#ifdef CONFIG_SERIAL_BFIN_UART1
6bd1fbea 285static struct resource bfin_uart1_resources[] = {
24a07a12 286 {
6bd1fbea
SZ		 287 .start = UART1_DLL,
288 .end = UART1_RBR+2,
24a07a12
RH		 289 .flags = IORESOURCE_MEM,
290 },
edb0a640
SZ		 291 {
292 .start = IRQ_UART1_TX,
293 .end = IRQ_UART1_TX,
294 .flags = IORESOURCE_IRQ,
295 },
6bd1fbea
SZ		 296 {
297 .start = IRQ_UART1_RX,
edb0a640 298 .end = IRQ_UART1_RX,
6bd1fbea
SZ		 299 .flags = IORESOURCE_IRQ,
300 },
301 {
302 .start = IRQ_UART1_ERROR,
303 .end = IRQ_UART1_ERROR,
304 .flags = IORESOURCE_IRQ,
305 },
306 {
307 .start = CH_UART1_TX,
308 .end = CH_UART1_TX,
309 .flags = IORESOURCE_DMA,
310 },
311 {
312 .start = CH_UART1_RX,
313 .end = CH_UART1_RX,
314 .flags = IORESOURCE_DMA,
315 },
316#ifdef CONFIG_BFIN_UART1_CTSRTS
317 { /* CTS pin -- 0 means not supported */
318 .start = GPIO_PE10,
319 .end = GPIO_PE10,
320 .flags = IORESOURCE_IO,
321 },
322 { /* RTS pin -- 0 means not supported */
323 .start = GPIO_PE9,
324 .end = GPIO_PE9,
325 .flags = IORESOURCE_IO,
326 },
327#endif
328};
329
a8b19886 330static unsigned short bfin_uart1_peripherals[] = {
6bd1fbea
SZ		 331 P_UART1_TX, P_UART1_RX,
332#ifdef CONFIG_BFIN_UART1_CTSRTS
333 P_UART1_RTS, P_UART1_CTS,
334#endif
335 0
336};
337
338static struct platform_device bfin_uart1_device = {
339 .name = "bfin-uart",
340 .id = 1,
341 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
342 .resource = bfin_uart1_resources,
343 .dev = {
344 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
345 },
346};
24a07a12
RH		 347#endif
348#ifdef CONFIG_SERIAL_BFIN_UART2
6bd1fbea 349static struct resource bfin_uart2_resources[] = {
24a07a12 350 {
6bd1fbea
SZ		 351 .start = UART2_DLL,
352 .end = UART2_RBR+2,
24a07a12
RH		 353 .flags = IORESOURCE_MEM,
354 },
edb0a640
SZ		 355 {
356 .start = IRQ_UART2_TX,
357 .end = IRQ_UART2_TX,
358 .flags = IORESOURCE_IRQ,
359 },
6bd1fbea
SZ		 360 {
361 .start = IRQ_UART2_RX,
edb0a640 362 .end = IRQ_UART2_RX,
6bd1fbea
SZ		 363 .flags = IORESOURCE_IRQ,
364 },
365 {
366 .start = IRQ_UART2_ERROR,
367 .end = IRQ_UART2_ERROR,
368 .flags = IORESOURCE_IRQ,
369 },
370 {
371 .start = CH_UART2_TX,
372 .end = CH_UART2_TX,
373 .flags = IORESOURCE_DMA,
374 },
375 {
376 .start = CH_UART2_RX,
377 .end = CH_UART2_RX,
378 .flags = IORESOURCE_DMA,
379 },
380};
381
a8b19886 382static unsigned short bfin_uart2_peripherals[] = {
6bd1fbea
SZ		 383 P_UART2_TX, P_UART2_RX, 0
384};
385
386static struct platform_device bfin_uart2_device = {
387 .name = "bfin-uart",
388 .id = 2,
389 .num_resources = ARRAY_SIZE(bfin_uart2_resources),
390 .resource = bfin_uart2_resources,
391 .dev = {
392 .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
393 },
394};
24a07a12
RH		 395#endif
396#ifdef CONFIG_SERIAL_BFIN_UART3
6bd1fbea 397static struct resource bfin_uart3_resources[] = {
24a07a12 398 {
6bd1fbea
SZ		 399 .start = UART3_DLL,
400 .end = UART3_RBR+2,
cc2e16bd 401 .flags = IORESOURCE_MEM,
24a07a12 402 },
edb0a640
SZ		 403 {
404 .start = IRQ_UART3_TX,
405 .end = IRQ_UART3_TX,
406 .flags = IORESOURCE_IRQ,
407 },
6bd1fbea
SZ		 408 {
409 .start = IRQ_UART3_RX,
edb0a640 410 .end = IRQ_UART3_RX,
6bd1fbea
SZ		 411 .flags = IORESOURCE_IRQ,
412 },
413 {
414 .start = IRQ_UART3_ERROR,
415 .end = IRQ_UART3_ERROR,
416 .flags = IORESOURCE_IRQ,
417 },
418 {
419 .start = CH_UART3_TX,
420 .end = CH_UART3_TX,
421 .flags = IORESOURCE_DMA,
422 },
423 {
424 .start = CH_UART3_RX,
425 .end = CH_UART3_RX,
426 .flags = IORESOURCE_DMA,
427 },
428#ifdef CONFIG_BFIN_UART3_CTSRTS
429 { /* CTS pin -- 0 means not supported */
430 .start = GPIO_PB3,
431 .end = GPIO_PB3,
432 .flags = IORESOURCE_IO,
433 },
434 { /* RTS pin -- 0 means not supported */
435 .start = GPIO_PB2,
436 .end = GPIO_PB2,
437 .flags = IORESOURCE_IO,
438 },
24a07a12
RH		 439#endif
440};
441
a8b19886 442static unsigned short bfin_uart3_peripherals[] = {
6bd1fbea
SZ		 443 P_UART3_TX, P_UART3_RX,
444#ifdef CONFIG_BFIN_UART3_CTSRTS
445 P_UART3_RTS, P_UART3_CTS,
446#endif
447 0
448};
449
450static struct platform_device bfin_uart3_device = {
24a07a12 451 .name = "bfin-uart",
6bd1fbea
SZ		 452 .id = 3,
453 .num_resources = ARRAY_SIZE(bfin_uart3_resources),
454 .resource = bfin_uart3_resources,
455 .dev = {
456 .platform_data = &bfin_uart3_peripherals, /* Passed to driver */
457 },
24a07a12
RH		 458};
459#endif
6bd1fbea 460#endif
24a07a12 461
5be36d22 462#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
5be36d22 463#ifdef CONFIG_BFIN_SIR0
42bd8bcb 464static struct resource bfin_sir0_resources[] = {
5be36d22
GY		 465 {
466 .start = 0xFFC00400,
467 .end = 0xFFC004FF,
468 .flags = IORESOURCE_MEM,
469 },
42bd8bcb
GY		 470 {
471 .start = IRQ_UART0_RX,
472 .end = IRQ_UART0_RX+1,
473 .flags = IORESOURCE_IRQ,
474 },
475 {
476 .start = CH_UART0_RX,
477 .end = CH_UART0_RX+1,
478 .flags = IORESOURCE_DMA,
479 },
480};
481static struct platform_device bfin_sir0_device = {
482 .name = "bfin_sir",
483 .id = 0,
484 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
485 .resource = bfin_sir0_resources,
486};
5be36d22
GY		 487#endif
488#ifdef CONFIG_BFIN_SIR1
42bd8bcb 489static struct resource bfin_sir1_resources[] = {
5be36d22
GY		 490 {
491 .start = 0xFFC02000,
492 .end = 0xFFC020FF,
493 .flags = IORESOURCE_MEM,
494 },
42bd8bcb
GY		 495 {
496 .start = IRQ_UART1_RX,
497 .end = IRQ_UART1_RX+1,
498 .flags = IORESOURCE_IRQ,
499 },
500 {
501 .start = CH_UART1_RX,
502 .end = CH_UART1_RX+1,
503 .flags = IORESOURCE_DMA,
504 },
505};
506static struct platform_device bfin_sir1_device = {
507 .name = "bfin_sir",
508 .id = 1,
509 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
510 .resource = bfin_sir1_resources,
511};
5be36d22
GY		 512#endif
513#ifdef CONFIG_BFIN_SIR2
42bd8bcb 514static struct resource bfin_sir2_resources[] = {
5be36d22
GY		 515 {
516 .start = 0xFFC02100,
517 .end = 0xFFC021FF,
518 .flags = IORESOURCE_MEM,
519 },
42bd8bcb
GY		 520 {
521 .start = IRQ_UART2_RX,
522 .end = IRQ_UART2_RX+1,
523 .flags = IORESOURCE_IRQ,
524 },
525 {
526 .start = CH_UART2_RX,
527 .end = CH_UART2_RX+1,
528 .flags = IORESOURCE_DMA,
529 },
530};
531static struct platform_device bfin_sir2_device = {
532 .name = "bfin_sir",
533 .id = 2,
534 .num_resources = ARRAY_SIZE(bfin_sir2_resources),
535 .resource = bfin_sir2_resources,
536};
5be36d22
GY		 537#endif
538#ifdef CONFIG_BFIN_SIR3
42bd8bcb 539static struct resource bfin_sir3_resources[] = {
5be36d22
GY		 540 {
541 .start = 0xFFC03100,
542 .end = 0xFFC031FF,
543 .flags = IORESOURCE_MEM,
544 },
42bd8bcb
GY		 545 {
546 .start = IRQ_UART3_RX,
547 .end = IRQ_UART3_RX+1,
548 .flags = IORESOURCE_IRQ,
549 },
550 {
551 .start = CH_UART3_RX,
552 .end = CH_UART3_RX+1,
553 .flags = IORESOURCE_DMA,
554 },
5be36d22 555};
42bd8bcb 556static struct platform_device bfin_sir3_device = {
5be36d22 557 .name = "bfin_sir",
42bd8bcb
GY		 558 .id = 3,
559 .num_resources = ARRAY_SIZE(bfin_sir3_resources),
560 .resource = bfin_sir3_resources,
5be36d22
GY		 561};
562#endif
42bd8bcb 563#endif
5be36d22 564
c6c4d7bb 565#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
7a8b71db
MF		 566#include <linux/smsc911x.h>
567
c6c4d7bb
BW		 568static struct resource smsc911x_resources[] = {
569 {
570 .name = "smsc911x-memory",
571 .start = 0x24000000,
572 .end = 0x24000000 + 0xFF,
573 .flags = IORESOURCE_MEM,
574 },
575 {
576 .start = IRQ_PE8,
577 .end = IRQ_PE8,
578 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
579 },
580};
7a8b71db
MF		 581
582static struct smsc911x_platform_config smsc911x_config = {
583 .flags = SMSC911X_USE_32BIT,
584 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
585 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
586 .phy_interface = PHY_INTERFACE_MODE_MII,
587};
588
c6c4d7bb
BW		 589static struct platform_device smsc911x_device = {
590 .name = "smsc911x",
591 .id = 0,
592 .num_resources = ARRAY_SIZE(smsc911x_resources),
593 .resource = smsc911x_resources,
7a8b71db
MF		 594 .dev = {
595 .platform_data = &smsc911x_config,
596 },
c6c4d7bb
BW		 597};
598#endif
599
c6c4d7bb
BW		 600#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
601static struct resource musb_resources[] = {
602 [0] = {
603 .start = 0xFFC03C00,
604 .end = 0xFFC040FF,
605 .flags = IORESOURCE_MEM,
606 },
607 [1] = { /* general IRQ */
608 .start = IRQ_USB_INT0,
609 .end = IRQ_USB_INT0,
610 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
fcf173e4 611 .name = "mc"
c6c4d7bb
BW		 612 },
613 [2] = { /* DMA IRQ */
614 .start = IRQ_USB_DMA,
615 .end = IRQ_USB_DMA,
616 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
fcf173e4 617 .name = "dma"
c6c4d7bb
BW		 618 },
619};
620
50041acb
BW		 621static struct musb_hdrc_config musb_config = {
622 .multipoint = 0,
623 .dyn_fifo = 0,
624 .soft_con = 1,
625 .dma = 1,
fea05dac
BW		 626 .num_eps = 8,
627 .dma_channels = 8,
50041acb 628 .gpio_vrsel = GPIO_PE7,
85eb0e4b
CC		 629 /* Some custom boards need to be active low, just set it to "0"
630 * if it is the case.
631 */
632 .gpio_vrsel_active = 1,
759a3f3f 633 .clkin = 24, /* musb CLKIN in MHZ */
50041acb
BW		 634};
635
c6c4d7bb 636static struct musb_hdrc_platform_data musb_plat = {
2935077e 637#if defined(CONFIG_USB_MUSB_OTG)
c6c4d7bb 638 .mode = MUSB_OTG,
2935077e 639#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
c6c4d7bb 640 .mode = MUSB_HOST,
2935077e 641#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
c6c4d7bb
BW		 642 .mode = MUSB_PERIPHERAL,
643#endif
50041acb 644 .config = &musb_config,
c6c4d7bb
BW		 645};
646
647static u64 musb_dmamask = ~(u32)0;
648
649static struct platform_device musb_device = {
9cb0308e 650 .name = "musb-blackfin",
c6c4d7bb
BW		 651 .id = 0,
652 .dev = {
653 .dma_mask = &musb_dmamask,
654 .coherent_dma_mask = 0xffffffff,
655 .platform_data = &musb_plat,
656 },
657 .num_resources = ARRAY_SIZE(musb_resources),
658 .resource = musb_resources,
659};
660#endif
661
df5de261
SZ		 662#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
663#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
664static struct resource bfin_sport0_uart_resources[] = {
665 {
666 .start = SPORT0_TCR1,
667 .end = SPORT0_MRCS3+4,
668 .flags = IORESOURCE_MEM,
669 },
670 {
671 .start = IRQ_SPORT0_RX,
672 .end = IRQ_SPORT0_RX+1,
673 .flags = IORESOURCE_IRQ,
674 },
675 {
676 .start = IRQ_SPORT0_ERROR,
677 .end = IRQ_SPORT0_ERROR,
678 .flags = IORESOURCE_IRQ,
679 },
680};
681
a8b19886 682static unsigned short bfin_sport0_peripherals[] = {
df5de261 683 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
e54b6730 684 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
df5de261
SZ		 685};
686
687static struct platform_device bfin_sport0_uart_device = {
688 .name = "bfin-sport-uart",
689 .id = 0,
690 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
691 .resource = bfin_sport0_uart_resources,
692 .dev = {
693 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
694 },
695};
696#endif
697#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
698static struct resource bfin_sport1_uart_resources[] = {
699 {
700 .start = SPORT1_TCR1,
701 .end = SPORT1_MRCS3+4,
702 .flags = IORESOURCE_MEM,
703 },
704 {
705 .start = IRQ_SPORT1_RX,
706 .end = IRQ_SPORT1_RX+1,
707 .flags = IORESOURCE_IRQ,
708 },
709 {
710 .start = IRQ_SPORT1_ERROR,
711 .end = IRQ_SPORT1_ERROR,
712 .flags = IORESOURCE_IRQ,
713 },
714};
715
a8b19886 716static unsigned short bfin_sport1_peripherals[] = {
df5de261 717 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
e54b6730 718 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
df5de261
SZ		 719};
720
721static struct platform_device bfin_sport1_uart_device = {
722 .name = "bfin-sport-uart",
723 .id = 1,
724 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
725 .resource = bfin_sport1_uart_resources,
726 .dev = {
727 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
728 },
729};
730#endif
731#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
732static struct resource bfin_sport2_uart_resources[] = {
733 {
734 .start = SPORT2_TCR1,
735 .end = SPORT2_MRCS3+4,
736 .flags = IORESOURCE_MEM,
737 },
738 {
739 .start = IRQ_SPORT2_RX,
740 .end = IRQ_SPORT2_RX+1,
741 .flags = IORESOURCE_IRQ,
742 },
743 {
744 .start = IRQ_SPORT2_ERROR,
745 .end = IRQ_SPORT2_ERROR,
746 .flags = IORESOURCE_IRQ,
747 },
748};
749
a8b19886 750static unsigned short bfin_sport2_peripherals[] = {
df5de261
SZ		 751 P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
752 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
753};
754
755static struct platform_device bfin_sport2_uart_device = {
756 .name = "bfin-sport-uart",
757 .id = 2,
758 .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
759 .resource = bfin_sport2_uart_resources,
760 .dev = {
761 .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
762 },
763};
764#endif
765#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
766static struct resource bfin_sport3_uart_resources[] = {
767 {
768 .start = SPORT3_TCR1,
769 .end = SPORT3_MRCS3+4,
770 .flags = IORESOURCE_MEM,
771 },
772 {
773 .start = IRQ_SPORT3_RX,
774 .end = IRQ_SPORT3_RX+1,
775 .flags = IORESOURCE_IRQ,
776 },
777 {
778 .start = IRQ_SPORT3_ERROR,
779 .end = IRQ_SPORT3_ERROR,
780 .flags = IORESOURCE_IRQ,
781 },
782};
783
a8b19886 784static unsigned short bfin_sport3_peripherals[] = {
df5de261
SZ		 785 P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
786 P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
787};
788
789static struct platform_device bfin_sport3_uart_device = {
790 .name = "bfin-sport-uart",
791 .id = 3,
792 .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources),
793 .resource = bfin_sport3_uart_resources,
794 .dev = {
795 .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
796 },
797};
798#endif
799#endif
800
706a01b1 801#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
4c131c8c
AW		 802
803static unsigned short bfin_can0_peripherals[] = {
706a01b1
BS		 804 P_CAN0_RX, P_CAN0_TX, 0
805};
806
4c131c8c 807static struct resource bfin_can0_resources[] = {
706a01b1
BS		 808 {
809 .start = 0xFFC02A00,
810 .end = 0xFFC02FFF,
811 .flags = IORESOURCE_MEM,
812 },
813 {
814 .start = IRQ_CAN0_RX,
815 .end = IRQ_CAN0_RX,
816 .flags = IORESOURCE_IRQ,
817 },
818 {
819 .start = IRQ_CAN0_TX,
820 .end = IRQ_CAN0_TX,
821 .flags = IORESOURCE_IRQ,
822 },
823 {
824 .start = IRQ_CAN0_ERROR,
825 .end = IRQ_CAN0_ERROR,
826 .flags = IORESOURCE_IRQ,
827 },
828};
829
4c131c8c 830static struct platform_device bfin_can0_device = {
706a01b1 831 .name = "bfin_can",
4c131c8c
AW		 832 .id = 0,
833 .num_resources = ARRAY_SIZE(bfin_can0_resources),
834 .resource = bfin_can0_resources,
706a01b1 835 .dev = {
4c131c8c 836 .platform_data = &bfin_can0_peripherals, /* Passed to driver */
706a01b1
BS		 837 },
838};
4c131c8c
AW		 839
840static unsigned short bfin_can1_peripherals[] = {
841 P_CAN1_RX, P_CAN1_TX, 0
842};
843
844static struct resource bfin_can1_resources[] = {
845 {
846 .start = 0xFFC03200,
847 .end = 0xFFC037FF,
848 .flags = IORESOURCE_MEM,
849 },
850 {
851 .start = IRQ_CAN1_RX,
852 .end = IRQ_CAN1_RX,
853 .flags = IORESOURCE_IRQ,
854 },
855 {
856 .start = IRQ_CAN1_TX,
857 .end = IRQ_CAN1_TX,
858 .flags = IORESOURCE_IRQ,
859 },
860 {
861 .start = IRQ_CAN1_ERROR,
862 .end = IRQ_CAN1_ERROR,
863 .flags = IORESOURCE_IRQ,
864 },
865};
866
867static struct platform_device bfin_can1_device = {
868 .name = "bfin_can",
869 .id = 1,
870 .num_resources = ARRAY_SIZE(bfin_can1_resources),
871 .resource = bfin_can1_resources,
872 .dev = {
873 .platform_data = &bfin_can1_peripherals, /* Passed to driver */
874 },
875};
876
706a01b1
BS		 877#endif
878
c6c4d7bb
BW		 879#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
880static struct resource bfin_atapi_resources[] = {
881 {
882 .start = 0xFFC03800,
883 .end = 0xFFC0386F,
884 .flags = IORESOURCE_MEM,
885 },
886 {
887 .start = IRQ_ATAPI_ERR,
888 .end = IRQ_ATAPI_ERR,
889 .flags = IORESOURCE_IRQ,
890 },
891};
892
893static struct platform_device bfin_atapi_device = {
894 .name = "pata-bf54x",
895 .id = -1,
896 .num_resources = ARRAY_SIZE(bfin_atapi_resources),
897 .resource = bfin_atapi_resources,
898};
899#endif
900
901#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
902static struct mtd_partition partition_info[] = {
903 {
73775b89 904 .name = "bootloader(nand)",
c6c4d7bb 905 .offset = 0,
73775b89
MF		 906 .size = 0x80000,
907 }, {
908 .name = "linux kernel(nand)",
909 .offset = MTDPART_OFS_APPEND,
f4585a08 910 .size = 4 * 1024 * 1024,
c6c4d7bb
BW		 911 },
912 {
aa582977 913 .name = "file system(nand)",
edf05641
MF		 914 .offset = MTDPART_OFS_APPEND,
915 .size = MTDPART_SIZ_FULL,
c6c4d7bb
BW		 916 },
917};
918
919static struct bf5xx_nand_platform bf5xx_nand_platform = {
c6c4d7bb
BW		 920 .data_width = NFC_NWIDTH_8,
921 .partitions = partition_info,
922 .nr_partitions = ARRAY_SIZE(partition_info),
923 .rd_dly = 3,
924 .wr_dly = 3,
925};
926
927static struct resource bf5xx_nand_resources[] = {
928 {
929 .start = 0xFFC03B00,
930 .end = 0xFFC03B4F,
931 .flags = IORESOURCE_MEM,
932 },
933 {
934 .start = CH_NFC,
935 .end = CH_NFC,
936 .flags = IORESOURCE_IRQ,
937 },
938};
939
940static struct platform_device bf5xx_nand_device = {
941 .name = "bf5xx-nand",
942 .id = 0,
943 .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
944 .resource = bf5xx_nand_resources,
945 .dev = {
946 .platform_data = &bf5xx_nand_platform,
947 },
948};
949#endif
950
3d7e6cf8 951#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
501674a5
CC		 952
953static struct bfin_sd_host bfin_sdh_data = {
954 .dma_chan = CH_SDH,
955 .irq_int0 = IRQ_SDH_MASK0,
956 .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0},
957};
958
c6c4d7bb
BW		 959static struct platform_device bf54x_sdh_device = {
960 .name = "bfin-sdh",
961 .id = 0,
501674a5
CC		 962 .dev = {
963 .platform_data = &bfin_sdh_data,
964 },
c6c4d7bb
BW		 965};
966#endif
967
793dc27b 968#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2
MF		 969static struct mtd_partition ezkit_partitions[] = {
970 {
aa582977 971 .name = "bootloader(nor)",
73775b89 972 .size = 0x80000,
de8c43f2
MF		 973 .offset = 0,
974 }, {
aa582977 975 .name = "linux kernel(nor)",
664d0403 976 .size = 0x400000,
de8c43f2
MF		 977 .offset = MTDPART_OFS_APPEND,
978 }, {
aa582977 979 .name = "file system(nor)",
56072047
MF		 980 .size = 0x1000000 - 0x80000 - 0x400000 - 0x8000 * 4,
981 .offset = MTDPART_OFS_APPEND,
982 }, {
983 .name = "config(nor)",
984 .size = 0x8000 * 3,
985 .offset = MTDPART_OFS_APPEND,
986 }, {
987 .name = "u-boot env(nor)",
988 .size = 0x8000,
de8c43f2
MF		 989 .offset = MTDPART_OFS_APPEND,
990 }
991};
992
993static struct physmap_flash_data ezkit_flash_data = {
994 .width = 2,
995 .parts = ezkit_partitions,
996 .nr_parts = ARRAY_SIZE(ezkit_partitions),
997};
998
999static struct resource ezkit_flash_resource = {
1000 .start = 0x20000000,
664d0403 1001 .end = 0x21ffffff,
de8c43f2
MF		 1002 .flags = IORESOURCE_MEM,
1003};
1004
1005static struct platform_device ezkit_flash_device = {
1006 .name = "physmap-flash",
1007 .id = 0,
1008 .dev = {
1009 .platform_data = &ezkit_flash_data,
1010 },
1011 .num_resources = 1,
1012 .resource = &ezkit_flash_resource,
1013};
793dc27b 1014#endif
de8c43f2 1015
c6c4d7bb
BW		 1016#if defined(CONFIG_MTD_M25P80) \
1017 || defined(CONFIG_MTD_M25P80_MODULE)
1018/* SPI flash chip (m25p16) */
1019static struct mtd_partition bfin_spi_flash_partitions[] = {
1020 {
aa582977 1021 .name = "bootloader(spi)",
73775b89 1022 .size = 0x00080000,
c6c4d7bb
BW		 1023 .offset = 0,
1024 .mask_flags = MTD_CAP_ROM
1025 }, {
aa582977 1026 .name = "linux kernel(spi)",
edf05641
MF		 1027 .size = MTDPART_SIZ_FULL,
1028 .offset = MTDPART_OFS_APPEND,
c6c4d7bb
BW		 1029 }
1030};
1031
1032static struct flash_platform_data bfin_spi_flash_data = {
1033 .name = "m25p80",
1034 .parts = bfin_spi_flash_partitions,
1035 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
1036 .type = "m25p16",
1037};
1038
1039static struct bfin5xx_spi_chip spi_flash_chip_info = {
1040 .enable_dma = 0, /* use dma transfer with this chip*/
37fa2421
BS		 1041};
1042#endif
1043
c6c4d7bb 1044#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
c6c4d7bb
BW		 1045static const struct ad7877_platform_data bfin_ad7877_ts_info = {
1046 .model = 7877,
1047 .vref_delay_usecs = 50, /* internal, no capacitor */
1048 .x_plate_ohms = 419,
1049 .y_plate_ohms = 486,
1050 .pressure_max = 1000,
1051 .pressure_min = 0,
1052 .stopacq_polarity = 1,
1053 .first_conversion_delay = 3,
1054 .acquisition_time = 1,
1055 .averaging = 1,
1056 .pen_down_acc_interval = 1,
1057};
1058#endif
1059
5bda2723 1060static struct spi_board_info bfin_spi_board_info[] __initdata = {
c6c4d7bb
BW		 1061#if defined(CONFIG_MTD_M25P80) \
1062 || defined(CONFIG_MTD_M25P80_MODULE)
1063 {
1064 /* the modalias must be the same as spi device driver name */
1065 .modalias = "m25p80", /* Name of spi_driver for this device */
1066 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
1067 .bus_num = 0, /* Framework bus number */
1068 .chip_select = 1, /* SPI_SSEL1*/
1069 .platform_data = &bfin_spi_flash_data,
1070 .controller_data = &spi_flash_chip_info,
1071 .mode = SPI_MODE_3,
1072 },
1073#endif
7ba80063
BS		 1074#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
1075 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
37fa2421 1076 {
7ba80063 1077 .modalias = "ad183x",
37fa2421
BS		 1078 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1079 .bus_num = 1,
7ba80063 1080 .chip_select = 4,
37fa2421
BS		 1081 },
1082#endif
c6c4d7bb 1083#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
ffc4d8bc
MH		 1084 {
1085 .modalias = "ad7877",
1086 .platform_data = &bfin_ad7877_ts_info,
1087 .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */
1088 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
1089 .bus_num = 0,
1090 .chip_select = 2,
ffc4d8bc 1091 },
c6c4d7bb 1092#endif
6e668936
MH		 1093#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
1094 {
1095 .modalias = "spidev",
1096 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1097 .bus_num = 0,
1098 .chip_select = 1,
6e668936
MH		 1099 },
1100#endif
ffc4d8bc
MH		 1101#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
1102 {
1103 .modalias = "adxl34x",
1104 .platform_data = &adxl34x_info,
1105 .irq = IRQ_PC5,
1106 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
1107 .bus_num = 1,
1108 .chip_select = 2,
ffc4d8bc
MH		 1109 .mode = SPI_MODE_3,
1110 },
1111#endif
c6c4d7bb 1112};
7d157fb0 1113#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
c6c4d7bb
BW		 1114/* SPI (0) */
1115static struct resource bfin_spi0_resource[] = {
1116 [0] = {
1117 .start = SPI0_REGBASE,
1118 .end = SPI0_REGBASE + 0xFF,
1119 .flags = IORESOURCE_MEM,
1120 },
1121 [1] = {
1122 .start = CH_SPI0,
1123 .end = CH_SPI0,
53122693
YL		 1124 .flags = IORESOURCE_DMA,
1125 },
1126 [2] = {
1127 .start = IRQ_SPI0,
1128 .end = IRQ_SPI0,
c6c4d7bb
BW		 1129 .flags = IORESOURCE_IRQ,
1130 }
1131};
1132
1133/* SPI (1) */
1134static struct resource bfin_spi1_resource[] = {
1135 [0] = {
1136 .start = SPI1_REGBASE,
1137 .end = SPI1_REGBASE + 0xFF,
1138 .flags = IORESOURCE_MEM,
1139 },
1140 [1] = {
1141 .start = CH_SPI1,
1142 .end = CH_SPI1,
53122693
YL		 1143 .flags = IORESOURCE_DMA,
1144 },
1145 [2] = {
1146 .start = IRQ_SPI1,
1147 .end = IRQ_SPI1,
c6c4d7bb
BW		 1148 .flags = IORESOURCE_IRQ,
1149 }
1150};
1151
1152/* SPI controller data */
5d448dd5 1153static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
c5af5451 1154 .num_chipselect = 4,
c6c4d7bb 1155 .enable_dma = 1, /* master has the ability to do dma transfer */
5d448dd5 1156 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
c6c4d7bb
BW		 1157};
1158
1159static struct platform_device bf54x_spi_master0 = {
1160 .name = "bfin-spi",
1161 .id = 0, /* Bus number */
1162 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
1163 .resource = bfin_spi0_resource,
1164 .dev = {
5d448dd5 1165 .platform_data = &bf54x_spi_master_info0, /* Passed to driver */
c6c4d7bb
BW		 1166 },
1167};
1168
5d448dd5 1169static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
c5af5451 1170 .num_chipselect = 4,
5d448dd5
BW		 1171 .enable_dma = 1, /* master has the ability to do dma transfer */
1172 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
1173};
1174
c6c4d7bb
BW		 1175static struct platform_device bf54x_spi_master1 = {
1176 .name = "bfin-spi",
1177 .id = 1, /* Bus number */
1178 .num_resources = ARRAY_SIZE(bfin_spi1_resource),
1179 .resource = bfin_spi1_resource,
1180 .dev = {
5d448dd5 1181 .platform_data = &bf54x_spi_master_info1, /* Passed to driver */
c6c4d7bb
BW		 1182 },
1183};
1184#endif /* spi master and devices */
1185
df864c30
SJ		 1186#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
1187 || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
1188#include <linux/videodev2.h>
1189#include <media/blackfin/bfin_capture.h>
1190#include <media/blackfin/ppi.h>
1191
1192static const unsigned short ppi_req[] = {
1193 P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3,
1194 P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7,
1195 P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2,
1196 0,
1197};
1198
1199static const struct ppi_info ppi_info = {
1200 .type = PPI_TYPE_EPPI,
1201 .dma_ch = CH_EPPI1,
1202 .irq_err = IRQ_EPPI1_ERROR,
1203 .base = (void __iomem *)EPPI1_STATUS,
1204 .pin_req = ppi_req,
1205};
1206
1207#if defined(CONFIG_VIDEO_VS6624) \
1208 || defined(CONFIG_VIDEO_VS6624_MODULE)
1209static struct v4l2_input vs6624_inputs[] = {
1210 {
1211 .index = 0,
1212 .name = "Camera",
1213 .type = V4L2_INPUT_TYPE_CAMERA,
1214 .std = V4L2_STD_UNKNOWN,
1215 },
1216};
1217
1218static struct bcap_route vs6624_routes[] = {
1219 {
1220 .input = 0,
1221 .output = 0,
1222 },
1223};
1224
1225static const unsigned vs6624_ce_pin = GPIO_PG6;
1226
1227static struct bfin_capture_config bfin_capture_data = {
1228 .card_name = "BF548",
1229 .inputs = vs6624_inputs,
1230 .num_inputs = ARRAY_SIZE(vs6624_inputs),
1231 .routes = vs6624_routes,
1232 .i2c_adapter_id = 0,
1233 .board_info = {
1234 .type = "vs6624",
1235 .addr = 0x10,
1236 .platform_data = (void *)&vs6624_ce_pin,
1237 },
1238 .ppi_info = &ppi_info,
1239 .ppi_control = (POLC | PACKEN | DLEN_8 | XFR_TYPE | 0x20),
1240};
1241#endif
1242
1243static struct platform_device bfin_capture_device = {
1244 .name = "bfin_capture",
1245 .dev = {
1246 .platform_data = &bfin_capture_data,
1247 },
1248};
1249#endif
1250
c6c4d7bb
BW		 1251#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1252static struct resource bfin_twi0_resource[] = {
1253 [0] = {
1254 .start = TWI0_REGBASE,
1255 .end = TWI0_REGBASE + 0xFF,
1256 .flags = IORESOURCE_MEM,
1257 },
1258 [1] = {
1259 .start = IRQ_TWI0,
1260 .end = IRQ_TWI0,
1261 .flags = IORESOURCE_IRQ,
1262 },
1263};
1264
1265static struct platform_device i2c_bfin_twi0_device = {
1266 .name = "i2c-bfin-twi",
1267 .id = 0,
1268 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1269 .resource = bfin_twi0_resource,
1270};
1271
7160e950 1272#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
c6c4d7bb
BW		 1273static struct resource bfin_twi1_resource[] = {
1274 [0] = {
1275 .start = TWI1_REGBASE,
1276 .end = TWI1_REGBASE + 0xFF,
1277 .flags = IORESOURCE_MEM,
1278 },
1279 [1] = {
1280 .start = IRQ_TWI1,
1281 .end = IRQ_TWI1,
1282 .flags = IORESOURCE_IRQ,
1283 },
1284};
1285
1286static struct platform_device i2c_bfin_twi1_device = {
1287 .name = "i2c-bfin-twi",
1288 .id = 1,
1289 .num_resources = ARRAY_SIZE(bfin_twi1_resource),
1290 .resource = bfin_twi1_resource,
1291};
1292#endif
7160e950 1293#endif
c6c4d7bb 1294
81d9c7f2
BW		 1295static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
1296};
1297
1298#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
1299static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
ebd58333 1300#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
81d9c7f2
BW		 1301 {
1302 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
81d9c7f2
BW		 1303 },
1304#endif
204844eb 1305#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
81d9c7f2
BW		 1306 {
1307 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
81d9c7f2
BW		 1308 .irq = 212,
1309 },
1310#endif
ffc4d8bc
MH		 1311#if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
1312 {
1313 I2C_BOARD_INFO("adxl34x", 0x53),
1314 .irq = IRQ_PC5,
1315 .platform_data = (void *)&adxl34x_info,
1316 },
1317#endif
39d3c1ca 1318#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
1319 {
1320 I2C_BOARD_INFO("ad5252", 0x2f),
1321 },
1322#endif
81d9c7f2
BW		 1323};
1324#endif
81d9c7f2 1325
2463ef22
MH		 1326#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1327#include <linux/gpio_keys.h>
1328
1329static struct gpio_keys_button bfin_gpio_keys_table[] = {
1330 {BTN_0, GPIO_PB8, 1, "gpio-keys: BTN0"},
1331 {BTN_1, GPIO_PB9, 1, "gpio-keys: BTN1"},
1332 {BTN_2, GPIO_PB10, 1, "gpio-keys: BTN2"},
1333 {BTN_3, GPIO_PB11, 1, "gpio-keys: BTN3"},
1334};
1335
1336static struct gpio_keys_platform_data bfin_gpio_keys_data = {
1337 .buttons = bfin_gpio_keys_table,
1338 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
1339};
1340
1341static struct platform_device bfin_device_gpiokeys = {
1342 .name = "gpio-keys",
1343 .dev = {
1344 .platform_data = &bfin_gpio_keys_data,
1345 },
1346};
1347#endif
1348
14b03204
MH		 1349static const unsigned int cclk_vlev_datasheet[] =
1350{
1351/*
1352 * Internal VLEV BF54XSBBC1533
1353 ****temporarily using these values until data sheet is updated
1354 */
1355 VRPAIR(VLEV_085, 150000000),
1356 VRPAIR(VLEV_090, 250000000),
1357 VRPAIR(VLEV_110, 276000000),
1358 VRPAIR(VLEV_115, 301000000),
1359 VRPAIR(VLEV_120, 525000000),
1360 VRPAIR(VLEV_125, 550000000),
1361 VRPAIR(VLEV_130, 600000000),
1362};
1363
1364static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
1365 .tuple_tab = cclk_vlev_datasheet,
1366 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
1367 .vr_settling_time = 25 /* us */,
1368};
1369
1370static struct platform_device bfin_dpmc = {
1371 .name = "bfin dpmc",
1372 .dev = {
1373 .platform_data = &bfin_dmpc_vreg_data,
1374 },
1375};
1376
6f53dbbb
SJ		 1377#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
1378 defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
1379 defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
1380
1381#define SPORT_REQ(x) \
1382 [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
1383 P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
1384
1385static const u16 bfin_snd_pin[][7] = {
1386 SPORT_REQ(0),
1387 SPORT_REQ(1),
1388};
1389
1390static struct bfin_snd_platform_data bfin_snd_data[] = {
1391 {
1392 .pin_req = &bfin_snd_pin[0][0],
1393 },
1394 {
1395 .pin_req = &bfin_snd_pin[1][0],
1396 },
1397};
1398
1399#define BFIN_SND_RES(x) \
1400 [x] = { \
1401 { \
1402 .start = SPORT##x##_TCR1, \
1403 .end = SPORT##x##_TCR1, \
1404 .flags = IORESOURCE_MEM \
1405 }, \
1406 { \
1407 .start = CH_SPORT##x##_RX, \
1408 .end = CH_SPORT##x##_RX, \
1409 .flags = IORESOURCE_DMA, \
1410 }, \
1411 { \
1412 .start = CH_SPORT##x##_TX, \
1413 .end = CH_SPORT##x##_TX, \
1414 .flags = IORESOURCE_DMA, \
1415 }, \
1416 { \
1417 .start = IRQ_SPORT##x##_ERROR, \
1418 .end = IRQ_SPORT##x##_ERROR, \
1419 .flags = IORESOURCE_IRQ, \
1420 } \
1421 }
1422
1423static struct resource bfin_snd_resources[][4] = {
1424 BFIN_SND_RES(0),
1425 BFIN_SND_RES(1),
1426};
1427
1428static struct platform_device bfin_pcm = {
1429 .name = "bfin-pcm-audio",
1430 .id = -1,
1431};
1432#endif
1433
1434#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
1435static struct platform_device bfin_ad73311_codec_device = {
1436 .name = "ad73311",
1437 .id = -1,
1438};
1439#endif
1440
1441#if defined(CONFIG_SND_BF5XX_SOC_AD1980) || defined(CONFIG_SND_BF5XX_SOC_AD1980_MODULE)
1442static struct platform_device bfin_ad1980_codec_device = {
1443 .name = "ad1980",
1444 .id = -1,
1445};
1446#endif
1447
1448#if defined(CONFIG_SND_BF5XX_SOC_I2S) || defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE)
439b4867
BS		 1449static struct platform_device bfin_i2s = {
1450 .name = "bfin-i2s",
1451 .id = CONFIG_SND_BF5XX_SPORT_NUM,
6f53dbbb
SJ		 1452 .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
1453 .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
1454 .dev = {
1455 .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
1456 },
439b4867
BS		 1457};
1458#endif
1459
6f53dbbb 1460#if defined(CONFIG_SND_BF5XX_SOC_TDM) || defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE)
439b4867
BS		 1461static struct platform_device bfin_tdm = {
1462 .name = "bfin-tdm",
1463 .id = CONFIG_SND_BF5XX_SPORT_NUM,
6f53dbbb
SJ		 1464 .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
1465 .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
1466 .dev = {
1467 .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
1468 },
439b4867
BS		 1469};
1470#endif
1471
6f53dbbb 1472#if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
439b4867
BS		 1473static struct platform_device bfin_ac97 = {
1474 .name = "bfin-ac97",
1475 .id = CONFIG_SND_BF5XX_SPORT_NUM,
6f53dbbb
SJ		 1476 .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
1477 .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
1478 .dev = {
1479 .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
1480 },
439b4867
BS		 1481};
1482#endif
1483
24a07a12 1484static struct platform_device *ezkit_devices[] __initdata = {
14b03204
MH		 1485
1486 &bfin_dpmc,
1487
24a07a12
RH		 1488#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
1489 &rtc_device,
1490#endif
1491
1492#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
6bd1fbea
SZ		 1493#ifdef CONFIG_SERIAL_BFIN_UART0
1494 &bfin_uart0_device,
1495#endif
1496#ifdef CONFIG_SERIAL_BFIN_UART1
1497 &bfin_uart1_device,
1498#endif
1499#ifdef CONFIG_SERIAL_BFIN_UART2
1500 &bfin_uart2_device,
1501#endif
1502#ifdef CONFIG_SERIAL_BFIN_UART3
1503 &bfin_uart3_device,
1504#endif
24a07a12 1505#endif
c6c4d7bb 1506
5be36d22 1507#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb
GY		 1508#ifdef CONFIG_BFIN_SIR0
1509 &bfin_sir0_device,
1510#endif
1511#ifdef CONFIG_BFIN_SIR1
1512 &bfin_sir1_device,
1513#endif
1514#ifdef CONFIG_BFIN_SIR2
1515 &bfin_sir2_device,
1516#endif
1517#ifdef CONFIG_BFIN_SIR3
1518 &bfin_sir3_device,
1519#endif
5be36d22
GY		 1520#endif
1521
c6c4d7bb
BW		 1522#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
1523 &bf54x_lq043_device,
1524#endif
1525
1526#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
1527 &smsc911x_device,
1528#endif
1529
c6c4d7bb
BW		 1530#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
1531 &musb_device,
1532#endif
1533
3f375690
MH		 1534#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
1535 &bfin_isp1760_device,
1536#endif
1537
df5de261
SZ		 1538#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
1539#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1540 &bfin_sport0_uart_device,
1541#endif
1542#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1543 &bfin_sport1_uart_device,
1544#endif
1545#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1546 &bfin_sport2_uart_device,
1547#endif
1548#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
1549 &bfin_sport3_uart_device,
1550#endif
1551#endif
1552
706a01b1 1553#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
4c131c8c
AW		 1554 &bfin_can0_device,
1555 &bfin_can1_device,
706a01b1
BS		 1556#endif
1557
c6c4d7bb
BW		 1558#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
1559 &bfin_atapi_device,
1560#endif
1561
1562#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
1563 &bf5xx_nand_device,
1564#endif
1565
3d7e6cf8 1566#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
c6c4d7bb
BW		 1567 &bf54x_sdh_device,
1568#endif
1569
7d157fb0 1570#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
c6c4d7bb 1571 &bf54x_spi_master0,
d4b1d273 1572 &bf54x_spi_master1,
c6c4d7bb 1573#endif
df864c30
SJ		 1574#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
1575 || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
1576 &bfin_capture_device,
1577#endif
c6c4d7bb
BW		 1578
1579#if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE)
1580 &bf54x_kpad_device,
1581#endif
1582
adfc0467 1583#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
aca5e4aa
MH		 1584 &bfin_rotary_device,
1585#endif
1586
c6c4d7bb
BW		 1587#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1588 &i2c_bfin_twi0_device,
7160e950 1589#if !defined(CONFIG_BF542)
c6c4d7bb
BW		 1590 &i2c_bfin_twi1_device,
1591#endif
7160e950 1592#endif
2463ef22
MH		 1593
1594#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1595 &bfin_device_gpiokeys,
1596#endif
cad2ab65 1597
793dc27b 1598#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2 1599 &ezkit_flash_device,
793dc27b 1600#endif
439b4867 1601
6f53dbbb
SJ		 1602#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
1603 defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
1604 defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
1605 &bfin_pcm,
1606#endif
1607
1608#if defined(CONFIG_SND_BF5XX_SOC_AD1980) || defined(CONFIG_SND_BF5XX_SOC_AD1980_MODULE)
1609 &bfin_ad1980_codec_device,
1610#endif
1611
439b4867
BS		 1612#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
1613 &bfin_i2s,
1614#endif
1615
1616#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
1617 &bfin_tdm,
1618#endif
1619
1620#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
1621 &bfin_ac97,
1622#endif
24a07a12
RH		 1623};
1624
a01d7a76 1625static int __init ezkit_init(void)
24a07a12 1626{
b85d858b 1627 printk(KERN_INFO "%s(): registering device resources\n", __func__);
81d9c7f2 1628
81d9c7f2
BW		 1629 i2c_register_board_info(0, bfin_i2c_board_info0,
1630 ARRAY_SIZE(bfin_i2c_board_info0));
1631#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
1632 i2c_register_board_info(1, bfin_i2c_board_info1,
1633 ARRAY_SIZE(bfin_i2c_board_info1));
81d9c7f2
BW		 1634#endif
1635
24a07a12 1636 platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
c6c4d7bb 1637
5bda2723 1638 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
c6c4d7bb 1639
24a07a12
RH		 1640 return 0;
1641}
1642
a01d7a76 1643arch_initcall(ezkit_init);
c13ce9fd
SZ		 1644
1645static struct platform_device *ezkit_early_devices[] __initdata = {
1646#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
1647#ifdef CONFIG_SERIAL_BFIN_UART0
1648 &bfin_uart0_device,
1649#endif
1650#ifdef CONFIG_SERIAL_BFIN_UART1
1651 &bfin_uart1_device,
1652#endif
1653#ifdef CONFIG_SERIAL_BFIN_UART2
1654 &bfin_uart2_device,
1655#endif
1656#ifdef CONFIG_SERIAL_BFIN_UART3
1657 &bfin_uart3_device,
1658#endif
1659#endif
1660
1661#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
1662#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1663 &bfin_sport0_uart_device,
1664#endif
1665#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1666 &bfin_sport1_uart_device,
1667#endif
1668#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1669 &bfin_sport2_uart_device,
1670#endif
1671#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
1672 &bfin_sport3_uart_device,
1673#endif
1674#endif
1675};
1676
1677void __init native_machine_early_platform_add_devices(void)
1678{
1679 printk(KERN_INFO "register early platform devices\n");
1680 early_platform_add_devices(ezkit_early_devices,
1681 ARRAY_SIZE(ezkit_early_devices));
1682}
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