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Blackfin: tll6527m: fix spelling in unused code (struct name)
[mirror_ubuntu-zesty-kernel.git] / arch / blackfin / mach-bf548 / boards / ezkit.c
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24a07a12 1/*
96f1050d
RG		 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2005 National ICT Australia (NICTA)
4 * Aidan Williams <aidan@nicta.com.au>
24a07a12 5 *
96f1050d 6 * Licensed under the GPL-2 or later.
24a07a12
RH		 7 */
8
9#include <linux/device.h>
10#include <linux/platform_device.h>
11#include <linux/mtd/mtd.h>
12#include <linux/mtd/partitions.h>
de8c43f2 13#include <linux/mtd/physmap.h>
24a07a12
RH		 14#include <linux/spi/spi.h>
15#include <linux/spi/flash.h>
1f83b8f1 16#include <linux/irq.h>
81d9c7f2 17#include <linux/i2c.h>
24a07a12 18#include <linux/interrupt.h>
c6c4d7bb 19#include <linux/usb/musb.h>
24a07a12 20#include <asm/bfin5xx_spi.h>
c6c4d7bb
BW		 21#include <asm/dma.h>
22#include <asm/gpio.h>
23#include <asm/nand.h>
14b03204 24#include <asm/dpmc.h>
5d448dd5 25#include <asm/portmux.h>
501674a5 26#include <asm/bfin_sdh.h>
639f6571 27#include <mach/bf54x_keys.h>
c6c4d7bb
BW		 28#include <linux/input.h>
29#include <linux/spi/ad7877.h>
24a07a12
RH		 30
31/*
32 * Name the Board for the /proc/cpuinfo
33 */
fe85cad2 34const char bfin_board_name[] = "ADI BF548-EZKIT";
24a07a12
RH		 35
36/*
37 * Driver needs to know address, irq and flag pin.
38 */
39
0a6304a9 40#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
3f375690
MH		 41#include <linux/usb/isp1760.h>
42static struct resource bfin_isp1760_resources[] = {
0a6304a9 43 [0] = {
0a6304a9
MH		 44 .start = 0x2C0C0000,
45 .end = 0x2C0C0000 + 0xfffff,
46 .flags = IORESOURCE_MEM,
47 },
48 [1] = {
49 .start = IRQ_PG7,
50 .end = IRQ_PG7,
51 .flags = IORESOURCE_IRQ,
52 },
53};
54
3f375690
MH		 55static struct isp1760_platform_data isp1760_priv = {
56 .is_isp1761 = 0,
3f375690
MH		 57 .bus_width_16 = 1,
58 .port1_otg = 0,
59 .analog_oc = 0,
60 .dack_polarity_high = 0,
61 .dreq_polarity_high = 0,
0a6304a9
MH		 62};
63
3f375690 64static struct platform_device bfin_isp1760_device = {
c6feb768 65 .name = "isp1760",
3f375690
MH		 66 .id = 0,
67 .dev = {
68 .platform_data = &isp1760_priv,
69 },
70 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
71 .resource = bfin_isp1760_resources,
0a6304a9 72};
0a6304a9
MH		 73#endif
74
c6c4d7bb
BW		 75#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
76
639f6571 77#include <mach/bf54x-lq043.h>
c6c4d7bb
BW		 78
79static struct bfin_bf54xfb_mach_info bf54x_lq043_data = {
0e101ec1
SP		 80 .width = 95,
81 .height = 54,
c6c4d7bb
BW		 82 .xres = {480, 480, 480},
83 .yres = {272, 272, 272},
84 .bpp = {24, 24, 24},
85 .disp = GPIO_PE3,
86};
87
88static struct resource bf54x_lq043_resources[] = {
89 {
90 .start = IRQ_EPPI0_ERR,
91 .end = IRQ_EPPI0_ERR,
92 .flags = IORESOURCE_IRQ,
93 },
94};
95
96static struct platform_device bf54x_lq043_device = {
97 .name = "bf54x-lq043",
98 .id = -1,
99 .num_resources = ARRAY_SIZE(bf54x_lq043_resources),
100 .resource = bf54x_lq043_resources,
101 .dev = {
102 .platform_data = &bf54x_lq043_data,
103 },
104};
105#endif
106
107#if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE)
8f740ef3 108static const unsigned int bf548_keymap[] = {
c6c4d7bb
BW		 109 KEYVAL(0, 0, KEY_ENTER),
110 KEYVAL(0, 1, KEY_HELP),
111 KEYVAL(0, 2, KEY_0),
112 KEYVAL(0, 3, KEY_BACKSPACE),
113 KEYVAL(1, 0, KEY_TAB),
114 KEYVAL(1, 1, KEY_9),
115 KEYVAL(1, 2, KEY_8),
116 KEYVAL(1, 3, KEY_7),
117 KEYVAL(2, 0, KEY_DOWN),
118 KEYVAL(2, 1, KEY_6),
119 KEYVAL(2, 2, KEY_5),
120 KEYVAL(2, 3, KEY_4),
121 KEYVAL(3, 0, KEY_UP),
122 KEYVAL(3, 1, KEY_3),
123 KEYVAL(3, 2, KEY_2),
124 KEYVAL(3, 3, KEY_1),
125};
126
127static struct bfin_kpad_platform_data bf54x_kpad_data = {
128 .rows = 4,
129 .cols = 4,
8f740ef3
MH		 130 .keymap = bf548_keymap,
131 .keymapsize = ARRAY_SIZE(bf548_keymap),
c6c4d7bb
BW		 132 .repeat = 0,
133 .debounce_time = 5000, /* ns (5ms) */
134 .coldrive_time = 1000, /* ns (1ms) */
135 .keyup_test_interval = 50, /* ms (50ms) */
136};
137
138static struct resource bf54x_kpad_resources[] = {
139 {
140 .start = IRQ_KEY,
141 .end = IRQ_KEY,
142 .flags = IORESOURCE_IRQ,
143 },
144};
145
146static struct platform_device bf54x_kpad_device = {
147 .name = "bf54x-keys",
148 .id = -1,
149 .num_resources = ARRAY_SIZE(bf54x_kpad_resources),
150 .resource = bf54x_kpad_resources,
151 .dev = {
152 .platform_data = &bf54x_kpad_data,
153 },
154};
155#endif
156
adfc0467 157#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
aca5e4aa
MH		 158#include <asm/bfin_rotary.h>
159
160static struct bfin_rotary_platform_data bfin_rotary_data = {
161 /*.rotary_up_key = KEY_UP,*/
162 /*.rotary_down_key = KEY_DOWN,*/
163 .rotary_rel_code = REL_WHEEL,
164 .rotary_button_key = KEY_ENTER,
165 .debounce = 10, /* 0..17 */
166 .mode = ROT_QUAD_ENC | ROT_DEBE,
167};
168
169static struct resource bfin_rotary_resources[] = {
170 {
171 .start = IRQ_CNT,
172 .end = IRQ_CNT,
173 .flags = IORESOURCE_IRQ,
174 },
175};
176
177static struct platform_device bfin_rotary_device = {
178 .name = "bfin-rotary",
179 .id = -1,
180 .num_resources = ARRAY_SIZE(bfin_rotary_resources),
181 .resource = bfin_rotary_resources,
182 .dev = {
183 .platform_data = &bfin_rotary_data,
184 },
185};
186#endif
187
ffc4d8bc 188#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
57af8edf 189#include <linux/input/adxl34x.h>
ffc4d8bc
MH		 190static const struct adxl34x_platform_data adxl34x_info = {
191 .x_axis_offset = 0,
192 .y_axis_offset = 0,
193 .z_axis_offset = 0,
194 .tap_threshold = 0x31,
195 .tap_duration = 0x10,
196 .tap_latency = 0x60,
197 .tap_window = 0xF0,
198 .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
199 .act_axis_control = 0xFF,
200 .activity_threshold = 5,
201 .inactivity_threshold = 3,
202 .inactivity_time = 4,
203 .free_fall_threshold = 0x7,
204 .free_fall_time = 0x20,
205 .data_rate = 0x8,
206 .data_range = ADXL_FULL_RES,
207
208 .ev_type = EV_ABS,
209 .ev_code_x = ABS_X, /* EV_REL */
210 .ev_code_y = ABS_Y, /* EV_REL */
211 .ev_code_z = ABS_Z, /* EV_REL */
212
57af8edf 213 .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
ffc4d8bc
MH		 214
215/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
216/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
217 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
218 .fifo_mode = ADXL_FIFO_STREAM,
5db4036b
MH		 219 .orientation_enable = ADXL_EN_ORIENTATION_3D,
220 .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
221 .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
222 /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
223 .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
ffc4d8bc
MH		 224};
225#endif
226
24a07a12
RH		 227#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
228static struct platform_device rtc_device = {
229 .name = "rtc-bfin",
230 .id = -1,
231};
232#endif
233
234#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
24a07a12 235#ifdef CONFIG_SERIAL_BFIN_UART0
6bd1fbea 236static struct resource bfin_uart0_resources[] = {
24a07a12 237 {
6bd1fbea
SZ		 238 .start = UART0_DLL,
239 .end = UART0_RBR+2,
24a07a12
RH		 240 .flags = IORESOURCE_MEM,
241 },
6bd1fbea
SZ		 242 {
243 .start = IRQ_UART0_RX,
244 .end = IRQ_UART0_RX+1,
245 .flags = IORESOURCE_IRQ,
246 },
247 {
248 .start = IRQ_UART0_ERROR,
249 .end = IRQ_UART0_ERROR,
250 .flags = IORESOURCE_IRQ,
251 },
252 {
253 .start = CH_UART0_TX,
254 .end = CH_UART0_TX,
255 .flags = IORESOURCE_DMA,
256 },
257 {
258 .start = CH_UART0_RX,
259 .end = CH_UART0_RX,
260 .flags = IORESOURCE_DMA,
261 },
262};
263
264unsigned short bfin_uart0_peripherals[] = {
265 P_UART0_TX, P_UART0_RX, 0
266};
267
268static struct platform_device bfin_uart0_device = {
269 .name = "bfin-uart",
270 .id = 0,
271 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
272 .resource = bfin_uart0_resources,
273 .dev = {
274 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
275 },
276};
24a07a12
RH		 277#endif
278#ifdef CONFIG_SERIAL_BFIN_UART1
6bd1fbea 279static struct resource bfin_uart1_resources[] = {
24a07a12 280 {
6bd1fbea
SZ		 281 .start = UART1_DLL,
282 .end = UART1_RBR+2,
24a07a12
RH		 283 .flags = IORESOURCE_MEM,
284 },
6bd1fbea
SZ		 285 {
286 .start = IRQ_UART1_RX,
287 .end = IRQ_UART1_RX+1,
288 .flags = IORESOURCE_IRQ,
289 },
290 {
291 .start = IRQ_UART1_ERROR,
292 .end = IRQ_UART1_ERROR,
293 .flags = IORESOURCE_IRQ,
294 },
295 {
296 .start = CH_UART1_TX,
297 .end = CH_UART1_TX,
298 .flags = IORESOURCE_DMA,
299 },
300 {
301 .start = CH_UART1_RX,
302 .end = CH_UART1_RX,
303 .flags = IORESOURCE_DMA,
304 },
305#ifdef CONFIG_BFIN_UART1_CTSRTS
306 { /* CTS pin -- 0 means not supported */
307 .start = GPIO_PE10,
308 .end = GPIO_PE10,
309 .flags = IORESOURCE_IO,
310 },
311 { /* RTS pin -- 0 means not supported */
312 .start = GPIO_PE9,
313 .end = GPIO_PE9,
314 .flags = IORESOURCE_IO,
315 },
316#endif
317};
318
319unsigned short bfin_uart1_peripherals[] = {
320 P_UART1_TX, P_UART1_RX,
321#ifdef CONFIG_BFIN_UART1_CTSRTS
322 P_UART1_RTS, P_UART1_CTS,
323#endif
324 0
325};
326
327static struct platform_device bfin_uart1_device = {
328 .name = "bfin-uart",
329 .id = 1,
330 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
331 .resource = bfin_uart1_resources,
332 .dev = {
333 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
334 },
335};
24a07a12
RH		 336#endif
337#ifdef CONFIG_SERIAL_BFIN_UART2
6bd1fbea 338static struct resource bfin_uart2_resources[] = {
24a07a12 339 {
6bd1fbea
SZ		 340 .start = UART2_DLL,
341 .end = UART2_RBR+2,
24a07a12
RH		 342 .flags = IORESOURCE_MEM,
343 },
6bd1fbea
SZ		 344 {
345 .start = IRQ_UART2_RX,
346 .end = IRQ_UART2_RX+1,
347 .flags = IORESOURCE_IRQ,
348 },
349 {
350 .start = IRQ_UART2_ERROR,
351 .end = IRQ_UART2_ERROR,
352 .flags = IORESOURCE_IRQ,
353 },
354 {
355 .start = CH_UART2_TX,
356 .end = CH_UART2_TX,
357 .flags = IORESOURCE_DMA,
358 },
359 {
360 .start = CH_UART2_RX,
361 .end = CH_UART2_RX,
362 .flags = IORESOURCE_DMA,
363 },
364};
365
366unsigned short bfin_uart2_peripherals[] = {
367 P_UART2_TX, P_UART2_RX, 0
368};
369
370static struct platform_device bfin_uart2_device = {
371 .name = "bfin-uart",
372 .id = 2,
373 .num_resources = ARRAY_SIZE(bfin_uart2_resources),
374 .resource = bfin_uart2_resources,
375 .dev = {
376 .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
377 },
378};
24a07a12
RH		 379#endif
380#ifdef CONFIG_SERIAL_BFIN_UART3
6bd1fbea 381static struct resource bfin_uart3_resources[] = {
24a07a12 382 {
6bd1fbea
SZ		 383 .start = UART3_DLL,
384 .end = UART3_RBR+2,
cc2e16bd 385 .flags = IORESOURCE_MEM,
24a07a12 386 },
6bd1fbea
SZ		 387 {
388 .start = IRQ_UART3_RX,
389 .end = IRQ_UART3_RX+1,
390 .flags = IORESOURCE_IRQ,
391 },
392 {
393 .start = IRQ_UART3_ERROR,
394 .end = IRQ_UART3_ERROR,
395 .flags = IORESOURCE_IRQ,
396 },
397 {
398 .start = CH_UART3_TX,
399 .end = CH_UART3_TX,
400 .flags = IORESOURCE_DMA,
401 },
402 {
403 .start = CH_UART3_RX,
404 .end = CH_UART3_RX,
405 .flags = IORESOURCE_DMA,
406 },
407#ifdef CONFIG_BFIN_UART3_CTSRTS
408 { /* CTS pin -- 0 means not supported */
409 .start = GPIO_PB3,
410 .end = GPIO_PB3,
411 .flags = IORESOURCE_IO,
412 },
413 { /* RTS pin -- 0 means not supported */
414 .start = GPIO_PB2,
415 .end = GPIO_PB2,
416 .flags = IORESOURCE_IO,
417 },
24a07a12
RH		 418#endif
419};
420
6bd1fbea
SZ		 421unsigned short bfin_uart3_peripherals[] = {
422 P_UART3_TX, P_UART3_RX,
423#ifdef CONFIG_BFIN_UART3_CTSRTS
424 P_UART3_RTS, P_UART3_CTS,
425#endif
426 0
427};
428
429static struct platform_device bfin_uart3_device = {
24a07a12 430 .name = "bfin-uart",
6bd1fbea
SZ		 431 .id = 3,
432 .num_resources = ARRAY_SIZE(bfin_uart3_resources),
433 .resource = bfin_uart3_resources,
434 .dev = {
435 .platform_data = &bfin_uart3_peripherals, /* Passed to driver */
436 },
24a07a12
RH		 437};
438#endif
6bd1fbea 439#endif
24a07a12 440
5be36d22 441#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
5be36d22 442#ifdef CONFIG_BFIN_SIR0
42bd8bcb 443static struct resource bfin_sir0_resources[] = {
5be36d22
GY		 444 {
445 .start = 0xFFC00400,
446 .end = 0xFFC004FF,
447 .flags = IORESOURCE_MEM,
448 },
42bd8bcb
GY		 449 {
450 .start = IRQ_UART0_RX,
451 .end = IRQ_UART0_RX+1,
452 .flags = IORESOURCE_IRQ,
453 },
454 {
455 .start = CH_UART0_RX,
456 .end = CH_UART0_RX+1,
457 .flags = IORESOURCE_DMA,
458 },
459};
460static struct platform_device bfin_sir0_device = {
461 .name = "bfin_sir",
462 .id = 0,
463 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
464 .resource = bfin_sir0_resources,
465};
5be36d22
GY		 466#endif
467#ifdef CONFIG_BFIN_SIR1
42bd8bcb 468static struct resource bfin_sir1_resources[] = {
5be36d22
GY		 469 {
470 .start = 0xFFC02000,
471 .end = 0xFFC020FF,
472 .flags = IORESOURCE_MEM,
473 },
42bd8bcb
GY		 474 {
475 .start = IRQ_UART1_RX,
476 .end = IRQ_UART1_RX+1,
477 .flags = IORESOURCE_IRQ,
478 },
479 {
480 .start = CH_UART1_RX,
481 .end = CH_UART1_RX+1,
482 .flags = IORESOURCE_DMA,
483 },
484};
485static struct platform_device bfin_sir1_device = {
486 .name = "bfin_sir",
487 .id = 1,
488 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
489 .resource = bfin_sir1_resources,
490};
5be36d22
GY		 491#endif
492#ifdef CONFIG_BFIN_SIR2
42bd8bcb 493static struct resource bfin_sir2_resources[] = {
5be36d22
GY		 494 {
495 .start = 0xFFC02100,
496 .end = 0xFFC021FF,
497 .flags = IORESOURCE_MEM,
498 },
42bd8bcb
GY		 499 {
500 .start = IRQ_UART2_RX,
501 .end = IRQ_UART2_RX+1,
502 .flags = IORESOURCE_IRQ,
503 },
504 {
505 .start = CH_UART2_RX,
506 .end = CH_UART2_RX+1,
507 .flags = IORESOURCE_DMA,
508 },
509};
510static struct platform_device bfin_sir2_device = {
511 .name = "bfin_sir",
512 .id = 2,
513 .num_resources = ARRAY_SIZE(bfin_sir2_resources),
514 .resource = bfin_sir2_resources,
515};
5be36d22
GY		 516#endif
517#ifdef CONFIG_BFIN_SIR3
42bd8bcb 518static struct resource bfin_sir3_resources[] = {
5be36d22
GY		 519 {
520 .start = 0xFFC03100,
521 .end = 0xFFC031FF,
522 .flags = IORESOURCE_MEM,
523 },
42bd8bcb
GY		 524 {
525 .start = IRQ_UART3_RX,
526 .end = IRQ_UART3_RX+1,
527 .flags = IORESOURCE_IRQ,
528 },
529 {
530 .start = CH_UART3_RX,
531 .end = CH_UART3_RX+1,
532 .flags = IORESOURCE_DMA,
533 },
5be36d22 534};
42bd8bcb 535static struct platform_device bfin_sir3_device = {
5be36d22 536 .name = "bfin_sir",
42bd8bcb
GY		 537 .id = 3,
538 .num_resources = ARRAY_SIZE(bfin_sir3_resources),
539 .resource = bfin_sir3_resources,
5be36d22
GY		 540};
541#endif
42bd8bcb 542#endif
5be36d22 543
c6c4d7bb 544#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
7a8b71db
MF		 545#include <linux/smsc911x.h>
546
c6c4d7bb
BW		 547static struct resource smsc911x_resources[] = {
548 {
549 .name = "smsc911x-memory",
550 .start = 0x24000000,
551 .end = 0x24000000 + 0xFF,
552 .flags = IORESOURCE_MEM,
553 },
554 {
555 .start = IRQ_PE8,
556 .end = IRQ_PE8,
557 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
558 },
559};
7a8b71db
MF		 560
561static struct smsc911x_platform_config smsc911x_config = {
562 .flags = SMSC911X_USE_32BIT,
563 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
564 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
565 .phy_interface = PHY_INTERFACE_MODE_MII,
566};
567
c6c4d7bb
BW		 568static struct platform_device smsc911x_device = {
569 .name = "smsc911x",
570 .id = 0,
571 .num_resources = ARRAY_SIZE(smsc911x_resources),
572 .resource = smsc911x_resources,
7a8b71db
MF		 573 .dev = {
574 .platform_data = &smsc911x_config,
575 },
c6c4d7bb
BW		 576};
577#endif
578
c6c4d7bb
BW		 579#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
580static struct resource musb_resources[] = {
581 [0] = {
582 .start = 0xFFC03C00,
583 .end = 0xFFC040FF,
584 .flags = IORESOURCE_MEM,
585 },
586 [1] = { /* general IRQ */
587 .start = IRQ_USB_INT0,
588 .end = IRQ_USB_INT0,
589 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
fcf173e4 590 .name = "mc"
c6c4d7bb
BW		 591 },
592 [2] = { /* DMA IRQ */
593 .start = IRQ_USB_DMA,
594 .end = IRQ_USB_DMA,
595 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
fcf173e4 596 .name = "dma"
c6c4d7bb
BW		 597 },
598};
599
50041acb
BW		 600static struct musb_hdrc_config musb_config = {
601 .multipoint = 0,
602 .dyn_fifo = 0,
603 .soft_con = 1,
604 .dma = 1,
fea05dac
BW		 605 .num_eps = 8,
606 .dma_channels = 8,
50041acb 607 .gpio_vrsel = GPIO_PE7,
85eb0e4b
CC		 608 /* Some custom boards need to be active low, just set it to "0"
609 * if it is the case.
610 */
611 .gpio_vrsel_active = 1,
759a3f3f 612 .clkin = 24, /* musb CLKIN in MHZ */
50041acb
BW		 613};
614
c6c4d7bb 615static struct musb_hdrc_platform_data musb_plat = {
2935077e 616#if defined(CONFIG_USB_MUSB_OTG)
c6c4d7bb 617 .mode = MUSB_OTG,
2935077e 618#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
c6c4d7bb 619 .mode = MUSB_HOST,
2935077e 620#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
c6c4d7bb
BW		 621 .mode = MUSB_PERIPHERAL,
622#endif
50041acb 623 .config = &musb_config,
c6c4d7bb
BW		 624};
625
626static u64 musb_dmamask = ~(u32)0;
627
628static struct platform_device musb_device = {
9cb0308e 629 .name = "musb-blackfin",
c6c4d7bb
BW		 630 .id = 0,
631 .dev = {
632 .dma_mask = &musb_dmamask,
633 .coherent_dma_mask = 0xffffffff,
634 .platform_data = &musb_plat,
635 },
636 .num_resources = ARRAY_SIZE(musb_resources),
637 .resource = musb_resources,
638};
639#endif
640
df5de261
SZ		 641#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
642#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
643static struct resource bfin_sport0_uart_resources[] = {
644 {
645 .start = SPORT0_TCR1,
646 .end = SPORT0_MRCS3+4,
647 .flags = IORESOURCE_MEM,
648 },
649 {
650 .start = IRQ_SPORT0_RX,
651 .end = IRQ_SPORT0_RX+1,
652 .flags = IORESOURCE_IRQ,
653 },
654 {
655 .start = IRQ_SPORT0_ERROR,
656 .end = IRQ_SPORT0_ERROR,
657 .flags = IORESOURCE_IRQ,
658 },
659};
660
661unsigned short bfin_sport0_peripherals[] = {
662 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
663 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
664};
665
666static struct platform_device bfin_sport0_uart_device = {
667 .name = "bfin-sport-uart",
668 .id = 0,
669 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
670 .resource = bfin_sport0_uart_resources,
671 .dev = {
672 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
673 },
674};
675#endif
676#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
677static struct resource bfin_sport1_uart_resources[] = {
678 {
679 .start = SPORT1_TCR1,
680 .end = SPORT1_MRCS3+4,
681 .flags = IORESOURCE_MEM,
682 },
683 {
684 .start = IRQ_SPORT1_RX,
685 .end = IRQ_SPORT1_RX+1,
686 .flags = IORESOURCE_IRQ,
687 },
688 {
689 .start = IRQ_SPORT1_ERROR,
690 .end = IRQ_SPORT1_ERROR,
691 .flags = IORESOURCE_IRQ,
692 },
693};
694
695unsigned short bfin_sport1_peripherals[] = {
696 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
697 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
698};
699
700static struct platform_device bfin_sport1_uart_device = {
701 .name = "bfin-sport-uart",
702 .id = 1,
703 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
704 .resource = bfin_sport1_uart_resources,
705 .dev = {
706 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
707 },
708};
709#endif
710#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
711static struct resource bfin_sport2_uart_resources[] = {
712 {
713 .start = SPORT2_TCR1,
714 .end = SPORT2_MRCS3+4,
715 .flags = IORESOURCE_MEM,
716 },
717 {
718 .start = IRQ_SPORT2_RX,
719 .end = IRQ_SPORT2_RX+1,
720 .flags = IORESOURCE_IRQ,
721 },
722 {
723 .start = IRQ_SPORT2_ERROR,
724 .end = IRQ_SPORT2_ERROR,
725 .flags = IORESOURCE_IRQ,
726 },
727};
728
729unsigned short bfin_sport2_peripherals[] = {
730 P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
731 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
732};
733
734static struct platform_device bfin_sport2_uart_device = {
735 .name = "bfin-sport-uart",
736 .id = 2,
737 .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
738 .resource = bfin_sport2_uart_resources,
739 .dev = {
740 .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
741 },
742};
743#endif
744#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
745static struct resource bfin_sport3_uart_resources[] = {
746 {
747 .start = SPORT3_TCR1,
748 .end = SPORT3_MRCS3+4,
749 .flags = IORESOURCE_MEM,
750 },
751 {
752 .start = IRQ_SPORT3_RX,
753 .end = IRQ_SPORT3_RX+1,
754 .flags = IORESOURCE_IRQ,
755 },
756 {
757 .start = IRQ_SPORT3_ERROR,
758 .end = IRQ_SPORT3_ERROR,
759 .flags = IORESOURCE_IRQ,
760 },
761};
762
763unsigned short bfin_sport3_peripherals[] = {
764 P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
765 P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
766};
767
768static struct platform_device bfin_sport3_uart_device = {
769 .name = "bfin-sport-uart",
770 .id = 3,
771 .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources),
772 .resource = bfin_sport3_uart_resources,
773 .dev = {
774 .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
775 },
776};
777#endif
778#endif
779
706a01b1
BS		 780#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
781unsigned short bfin_can_peripherals[] = {
782 P_CAN0_RX, P_CAN0_TX, 0
783};
784
785static struct resource bfin_can_resources[] = {
786 {
787 .start = 0xFFC02A00,
788 .end = 0xFFC02FFF,
789 .flags = IORESOURCE_MEM,
790 },
791 {
792 .start = IRQ_CAN0_RX,
793 .end = IRQ_CAN0_RX,
794 .flags = IORESOURCE_IRQ,
795 },
796 {
797 .start = IRQ_CAN0_TX,
798 .end = IRQ_CAN0_TX,
799 .flags = IORESOURCE_IRQ,
800 },
801 {
802 .start = IRQ_CAN0_ERROR,
803 .end = IRQ_CAN0_ERROR,
804 .flags = IORESOURCE_IRQ,
805 },
806};
807
808static struct platform_device bfin_can_device = {
809 .name = "bfin_can",
810 .num_resources = ARRAY_SIZE(bfin_can_resources),
811 .resource = bfin_can_resources,
812 .dev = {
813 .platform_data = &bfin_can_peripherals, /* Passed to driver */
814 },
815};
816#endif
817
c6c4d7bb
BW		 818#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
819static struct resource bfin_atapi_resources[] = {
820 {
821 .start = 0xFFC03800,
822 .end = 0xFFC0386F,
823 .flags = IORESOURCE_MEM,
824 },
825 {
826 .start = IRQ_ATAPI_ERR,
827 .end = IRQ_ATAPI_ERR,
828 .flags = IORESOURCE_IRQ,
829 },
830};
831
832static struct platform_device bfin_atapi_device = {
833 .name = "pata-bf54x",
834 .id = -1,
835 .num_resources = ARRAY_SIZE(bfin_atapi_resources),
836 .resource = bfin_atapi_resources,
837};
838#endif
839
840#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
841static struct mtd_partition partition_info[] = {
842 {
73775b89 843 .name = "bootloader(nand)",
c6c4d7bb 844 .offset = 0,
73775b89
MF		 845 .size = 0x80000,
846 }, {
847 .name = "linux kernel(nand)",
848 .offset = MTDPART_OFS_APPEND,
f4585a08 849 .size = 4 * 1024 * 1024,
c6c4d7bb
BW		 850 },
851 {
aa582977 852 .name = "file system(nand)",
edf05641
MF		 853 .offset = MTDPART_OFS_APPEND,
854 .size = MTDPART_SIZ_FULL,
c6c4d7bb
BW		 855 },
856};
857
858static struct bf5xx_nand_platform bf5xx_nand_platform = {
c6c4d7bb
BW		 859 .data_width = NFC_NWIDTH_8,
860 .partitions = partition_info,
861 .nr_partitions = ARRAY_SIZE(partition_info),
862 .rd_dly = 3,
863 .wr_dly = 3,
864};
865
866static struct resource bf5xx_nand_resources[] = {
867 {
868 .start = 0xFFC03B00,
869 .end = 0xFFC03B4F,
870 .flags = IORESOURCE_MEM,
871 },
872 {
873 .start = CH_NFC,
874 .end = CH_NFC,
875 .flags = IORESOURCE_IRQ,
876 },
877};
878
879static struct platform_device bf5xx_nand_device = {
880 .name = "bf5xx-nand",
881 .id = 0,
882 .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
883 .resource = bf5xx_nand_resources,
884 .dev = {
885 .platform_data = &bf5xx_nand_platform,
886 },
887};
888#endif
889
3d7e6cf8 890#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
501674a5
CC		 891
892static struct bfin_sd_host bfin_sdh_data = {
893 .dma_chan = CH_SDH,
894 .irq_int0 = IRQ_SDH_MASK0,
895 .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0},
896};
897
c6c4d7bb
BW		 898static struct platform_device bf54x_sdh_device = {
899 .name = "bfin-sdh",
900 .id = 0,
501674a5
CC		 901 .dev = {
902 .platform_data = &bfin_sdh_data,
903 },
c6c4d7bb
BW		 904};
905#endif
906
793dc27b 907#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2
MF		 908static struct mtd_partition ezkit_partitions[] = {
909 {
aa582977 910 .name = "bootloader(nor)",
73775b89 911 .size = 0x80000,
de8c43f2
MF		 912 .offset = 0,
913 }, {
aa582977 914 .name = "linux kernel(nor)",
664d0403 915 .size = 0x400000,
de8c43f2
MF		 916 .offset = MTDPART_OFS_APPEND,
917 }, {
aa582977 918 .name = "file system(nor)",
de8c43f2
MF		 919 .size = MTDPART_SIZ_FULL,
920 .offset = MTDPART_OFS_APPEND,
921 }
922};
923
924static struct physmap_flash_data ezkit_flash_data = {
925 .width = 2,
926 .parts = ezkit_partitions,
927 .nr_parts = ARRAY_SIZE(ezkit_partitions),
928};
929
930static struct resource ezkit_flash_resource = {
931 .start = 0x20000000,
664d0403 932 .end = 0x21ffffff,
de8c43f2
MF		 933 .flags = IORESOURCE_MEM,
934};
935
936static struct platform_device ezkit_flash_device = {
937 .name = "physmap-flash",
938 .id = 0,
939 .dev = {
940 .platform_data = &ezkit_flash_data,
941 },
942 .num_resources = 1,
943 .resource = &ezkit_flash_resource,
944};
793dc27b 945#endif
de8c43f2 946
c6c4d7bb
BW		 947#if defined(CONFIG_MTD_M25P80) \
948 || defined(CONFIG_MTD_M25P80_MODULE)
949/* SPI flash chip (m25p16) */
950static struct mtd_partition bfin_spi_flash_partitions[] = {
951 {
aa582977 952 .name = "bootloader(spi)",
73775b89 953 .size = 0x00080000,
c6c4d7bb
BW		 954 .offset = 0,
955 .mask_flags = MTD_CAP_ROM
956 }, {
aa582977 957 .name = "linux kernel(spi)",
edf05641
MF		 958 .size = MTDPART_SIZ_FULL,
959 .offset = MTDPART_OFS_APPEND,
c6c4d7bb
BW		 960 }
961};
962
963static struct flash_platform_data bfin_spi_flash_data = {
964 .name = "m25p80",
965 .parts = bfin_spi_flash_partitions,
966 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
967 .type = "m25p16",
968};
969
970static struct bfin5xx_spi_chip spi_flash_chip_info = {
971 .enable_dma = 0, /* use dma transfer with this chip*/
972 .bits_per_word = 8,
c6c4d7bb
BW		 973};
974#endif
975
7ba80063
BS		 976#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
977 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
37fa2421
BS		 978static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
979 .enable_dma = 0,
980 .bits_per_word = 16,
981};
982#endif
983
c6c4d7bb
BW		 984#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
985static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
c6c4d7bb
BW		 986 .enable_dma = 0,
987 .bits_per_word = 16,
988};
989
990static const struct ad7877_platform_data bfin_ad7877_ts_info = {
991 .model = 7877,
992 .vref_delay_usecs = 50, /* internal, no capacitor */
993 .x_plate_ohms = 419,
994 .y_plate_ohms = 486,
995 .pressure_max = 1000,
996 .pressure_min = 0,
997 .stopacq_polarity = 1,
998 .first_conversion_delay = 3,
999 .acquisition_time = 1,
1000 .averaging = 1,
1001 .pen_down_acc_interval = 1,
1002};
1003#endif
1004
6e668936
MH		 1005#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
1006static struct bfin5xx_spi_chip spidev_chip_info = {
1007 .enable_dma = 0,
1008 .bits_per_word = 8,
1009};
1010#endif
1011
ffc4d8bc
MH		 1012#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
1013static struct bfin5xx_spi_chip spi_adxl34x_chip_info = {
1014 .enable_dma = 0, /* use dma transfer with this chip*/
1015 .bits_per_word = 8,
ffc4d8bc
MH		 1016};
1017#endif
1018
5bda2723 1019static struct spi_board_info bfin_spi_board_info[] __initdata = {
c6c4d7bb
BW		 1020#if defined(CONFIG_MTD_M25P80) \
1021 || defined(CONFIG_MTD_M25P80_MODULE)
1022 {
1023 /* the modalias must be the same as spi device driver name */
1024 .modalias = "m25p80", /* Name of spi_driver for this device */
1025 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
1026 .bus_num = 0, /* Framework bus number */
1027 .chip_select = 1, /* SPI_SSEL1*/
1028 .platform_data = &bfin_spi_flash_data,
1029 .controller_data = &spi_flash_chip_info,
1030 .mode = SPI_MODE_3,
1031 },
1032#endif
7ba80063
BS		 1033#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
1034 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
37fa2421 1035 {
7ba80063 1036 .modalias = "ad183x",
37fa2421
BS		 1037 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1038 .bus_num = 1,
7ba80063 1039 .chip_select = 4,
37fa2421
BS		 1040 .controller_data = &ad1836_spi_chip_info,
1041 },
1042#endif
c6c4d7bb 1043#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
ffc4d8bc
MH		 1044 {
1045 .modalias = "ad7877",
1046 .platform_data = &bfin_ad7877_ts_info,
1047 .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */
1048 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
1049 .bus_num = 0,
1050 .chip_select = 2,
1051 .controller_data = &spi_ad7877_chip_info,
1052 },
c6c4d7bb 1053#endif
6e668936
MH		 1054#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
1055 {
1056 .modalias = "spidev",
1057 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1058 .bus_num = 0,
1059 .chip_select = 1,
1060 .controller_data = &spidev_chip_info,
1061 },
1062#endif
ffc4d8bc
MH		 1063#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
1064 {
1065 .modalias = "adxl34x",
1066 .platform_data = &adxl34x_info,
1067 .irq = IRQ_PC5,
1068 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
1069 .bus_num = 1,
1070 .chip_select = 2,
1071 .controller_data = &spi_adxl34x_chip_info,
1072 .mode = SPI_MODE_3,
1073 },
1074#endif
c6c4d7bb 1075};
5bda2723 1076#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
c6c4d7bb
BW		 1077/* SPI (0) */
1078static struct resource bfin_spi0_resource[] = {
1079 [0] = {
1080 .start = SPI0_REGBASE,
1081 .end = SPI0_REGBASE + 0xFF,
1082 .flags = IORESOURCE_MEM,
1083 },
1084 [1] = {
1085 .start = CH_SPI0,
1086 .end = CH_SPI0,
53122693
YL		 1087 .flags = IORESOURCE_DMA,
1088 },
1089 [2] = {
1090 .start = IRQ_SPI0,
1091 .end = IRQ_SPI0,
c6c4d7bb
BW		 1092 .flags = IORESOURCE_IRQ,
1093 }
1094};
1095
1096/* SPI (1) */
1097static struct resource bfin_spi1_resource[] = {
1098 [0] = {
1099 .start = SPI1_REGBASE,
1100 .end = SPI1_REGBASE + 0xFF,
1101 .flags = IORESOURCE_MEM,
1102 },
1103 [1] = {
1104 .start = CH_SPI1,
1105 .end = CH_SPI1,
53122693
YL		 1106 .flags = IORESOURCE_DMA,
1107 },
1108 [2] = {
1109 .start = IRQ_SPI1,
1110 .end = IRQ_SPI1,
c6c4d7bb
BW		 1111 .flags = IORESOURCE_IRQ,
1112 }
1113};
1114
1115/* SPI controller data */
5d448dd5 1116static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
c5af5451 1117 .num_chipselect = 4,
c6c4d7bb 1118 .enable_dma = 1, /* master has the ability to do dma transfer */
5d448dd5 1119 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
c6c4d7bb
BW		 1120};
1121
1122static struct platform_device bf54x_spi_master0 = {
1123 .name = "bfin-spi",
1124 .id = 0, /* Bus number */
1125 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
1126 .resource = bfin_spi0_resource,
1127 .dev = {
5d448dd5 1128 .platform_data = &bf54x_spi_master_info0, /* Passed to driver */
c6c4d7bb
BW		 1129 },
1130};
1131
5d448dd5 1132static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
c5af5451 1133 .num_chipselect = 4,
5d448dd5
BW		 1134 .enable_dma = 1, /* master has the ability to do dma transfer */
1135 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
1136};
1137
c6c4d7bb
BW		 1138static struct platform_device bf54x_spi_master1 = {
1139 .name = "bfin-spi",
1140 .id = 1, /* Bus number */
1141 .num_resources = ARRAY_SIZE(bfin_spi1_resource),
1142 .resource = bfin_spi1_resource,
1143 .dev = {
5d448dd5 1144 .platform_data = &bf54x_spi_master_info1, /* Passed to driver */
c6c4d7bb
BW		 1145 },
1146};
1147#endif /* spi master and devices */
1148
1149#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1150static struct resource bfin_twi0_resource[] = {
1151 [0] = {
1152 .start = TWI0_REGBASE,
1153 .end = TWI0_REGBASE + 0xFF,
1154 .flags = IORESOURCE_MEM,
1155 },
1156 [1] = {
1157 .start = IRQ_TWI0,
1158 .end = IRQ_TWI0,
1159 .flags = IORESOURCE_IRQ,
1160 },
1161};
1162
1163static struct platform_device i2c_bfin_twi0_device = {
1164 .name = "i2c-bfin-twi",
1165 .id = 0,
1166 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1167 .resource = bfin_twi0_resource,
1168};
1169
7160e950 1170#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
c6c4d7bb
BW		 1171static struct resource bfin_twi1_resource[] = {
1172 [0] = {
1173 .start = TWI1_REGBASE,
1174 .end = TWI1_REGBASE + 0xFF,
1175 .flags = IORESOURCE_MEM,
1176 },
1177 [1] = {
1178 .start = IRQ_TWI1,
1179 .end = IRQ_TWI1,
1180 .flags = IORESOURCE_IRQ,
1181 },
1182};
1183
1184static struct platform_device i2c_bfin_twi1_device = {
1185 .name = "i2c-bfin-twi",
1186 .id = 1,
1187 .num_resources = ARRAY_SIZE(bfin_twi1_resource),
1188 .resource = bfin_twi1_resource,
1189};
1190#endif
7160e950 1191#endif
c6c4d7bb 1192
81d9c7f2
BW		 1193static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
1194};
1195
1196#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
1197static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
ebd58333 1198#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
81d9c7f2
BW		 1199 {
1200 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
81d9c7f2
BW		 1201 },
1202#endif
204844eb 1203#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
81d9c7f2
BW		 1204 {
1205 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
81d9c7f2
BW		 1206 .irq = 212,
1207 },
1208#endif
ffc4d8bc
MH		 1209#if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
1210 {
1211 I2C_BOARD_INFO("adxl34x", 0x53),
1212 .irq = IRQ_PC5,
1213 .platform_data = (void *)&adxl34x_info,
1214 },
1215#endif
39d3c1ca 1216#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
1217 {
1218 I2C_BOARD_INFO("ad5252", 0x2f),
1219 },
1220#endif
81d9c7f2
BW		 1221};
1222#endif
81d9c7f2 1223
2463ef22
MH		 1224#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1225#include <linux/gpio_keys.h>
1226
1227static struct gpio_keys_button bfin_gpio_keys_table[] = {
1228 {BTN_0, GPIO_PB8, 1, "gpio-keys: BTN0"},
1229 {BTN_1, GPIO_PB9, 1, "gpio-keys: BTN1"},
1230 {BTN_2, GPIO_PB10, 1, "gpio-keys: BTN2"},
1231 {BTN_3, GPIO_PB11, 1, "gpio-keys: BTN3"},
1232};
1233
1234static struct gpio_keys_platform_data bfin_gpio_keys_data = {
1235 .buttons = bfin_gpio_keys_table,
1236 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
1237};
1238
1239static struct platform_device bfin_device_gpiokeys = {
1240 .name = "gpio-keys",
1241 .dev = {
1242 .platform_data = &bfin_gpio_keys_data,
1243 },
1244};
1245#endif
1246
14b03204
MH		 1247static const unsigned int cclk_vlev_datasheet[] =
1248{
1249/*
1250 * Internal VLEV BF54XSBBC1533
1251 ****temporarily using these values until data sheet is updated
1252 */
1253 VRPAIR(VLEV_085, 150000000),
1254 VRPAIR(VLEV_090, 250000000),
1255 VRPAIR(VLEV_110, 276000000),
1256 VRPAIR(VLEV_115, 301000000),
1257 VRPAIR(VLEV_120, 525000000),
1258 VRPAIR(VLEV_125, 550000000),
1259 VRPAIR(VLEV_130, 600000000),
1260};
1261
1262static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
1263 .tuple_tab = cclk_vlev_datasheet,
1264 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
1265 .vr_settling_time = 25 /* us */,
1266};
1267
1268static struct platform_device bfin_dpmc = {
1269 .name = "bfin dpmc",
1270 .dev = {
1271 .platform_data = &bfin_dmpc_vreg_data,
1272 },
1273};
1274
439b4867
BS		 1275#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
1276static struct platform_device bfin_i2s = {
1277 .name = "bfin-i2s",
1278 .id = CONFIG_SND_BF5XX_SPORT_NUM,
1279 /* TODO: add platform data here */
1280};
1281#endif
1282
1283#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
1284static struct platform_device bfin_tdm = {
1285 .name = "bfin-tdm",
1286 .id = CONFIG_SND_BF5XX_SPORT_NUM,
1287 /* TODO: add platform data here */
1288};
1289#endif
1290
1291#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
1292static struct platform_device bfin_ac97 = {
1293 .name = "bfin-ac97",
1294 .id = CONFIG_SND_BF5XX_SPORT_NUM,
1295 /* TODO: add platform data here */
1296};
1297#endif
1298
24a07a12 1299static struct platform_device *ezkit_devices[] __initdata = {
14b03204
MH		 1300
1301 &bfin_dpmc,
1302
24a07a12
RH		 1303#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
1304 &rtc_device,
1305#endif
1306
1307#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
6bd1fbea
SZ		 1308#ifdef CONFIG_SERIAL_BFIN_UART0
1309 &bfin_uart0_device,
1310#endif
1311#ifdef CONFIG_SERIAL_BFIN_UART1
1312 &bfin_uart1_device,
1313#endif
1314#ifdef CONFIG_SERIAL_BFIN_UART2
1315 &bfin_uart2_device,
1316#endif
1317#ifdef CONFIG_SERIAL_BFIN_UART3
1318 &bfin_uart3_device,
1319#endif
24a07a12 1320#endif
c6c4d7bb 1321
5be36d22 1322#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb
GY		 1323#ifdef CONFIG_BFIN_SIR0
1324 &bfin_sir0_device,
1325#endif
1326#ifdef CONFIG_BFIN_SIR1
1327 &bfin_sir1_device,
1328#endif
1329#ifdef CONFIG_BFIN_SIR2
1330 &bfin_sir2_device,
1331#endif
1332#ifdef CONFIG_BFIN_SIR3
1333 &bfin_sir3_device,
1334#endif
5be36d22
GY		 1335#endif
1336
c6c4d7bb
BW		 1337#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
1338 &bf54x_lq043_device,
1339#endif
1340
1341#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
1342 &smsc911x_device,
1343#endif
1344
c6c4d7bb
BW		 1345#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
1346 &musb_device,
1347#endif
1348
3f375690
MH		 1349#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
1350 &bfin_isp1760_device,
1351#endif
1352
df5de261
SZ		 1353#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
1354#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1355 &bfin_sport0_uart_device,
1356#endif
1357#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1358 &bfin_sport1_uart_device,
1359#endif
1360#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1361 &bfin_sport2_uart_device,
1362#endif
1363#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
1364 &bfin_sport3_uart_device,
1365#endif
1366#endif
1367
706a01b1
BS		 1368#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
1369 &bfin_can_device,
1370#endif
1371
c6c4d7bb
BW		 1372#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
1373 &bfin_atapi_device,
1374#endif
1375
1376#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
1377 &bf5xx_nand_device,
1378#endif
1379
3d7e6cf8 1380#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
c6c4d7bb
BW		 1381 &bf54x_sdh_device,
1382#endif
1383
1384#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
1385 &bf54x_spi_master0,
d4b1d273 1386 &bf54x_spi_master1,
c6c4d7bb
BW		 1387#endif
1388
1389#if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE)
1390 &bf54x_kpad_device,
1391#endif
1392
adfc0467 1393#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
aca5e4aa
MH		 1394 &bfin_rotary_device,
1395#endif
1396
c6c4d7bb
BW		 1397#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1398 &i2c_bfin_twi0_device,
7160e950 1399#if !defined(CONFIG_BF542)
c6c4d7bb
BW		 1400 &i2c_bfin_twi1_device,
1401#endif
7160e950 1402#endif
2463ef22
MH		 1403
1404#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1405 &bfin_device_gpiokeys,
1406#endif
cad2ab65 1407
793dc27b 1408#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2 1409 &ezkit_flash_device,
793dc27b 1410#endif
439b4867
BS		 1411
1412#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
1413 &bfin_i2s,
1414#endif
1415
1416#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
1417 &bfin_tdm,
1418#endif
1419
1420#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
1421 &bfin_ac97,
1422#endif
24a07a12
RH		 1423};
1424
a01d7a76 1425static int __init ezkit_init(void)
24a07a12 1426{
b85d858b 1427 printk(KERN_INFO "%s(): registering device resources\n", __func__);
81d9c7f2 1428
81d9c7f2
BW		 1429 i2c_register_board_info(0, bfin_i2c_board_info0,
1430 ARRAY_SIZE(bfin_i2c_board_info0));
1431#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
1432 i2c_register_board_info(1, bfin_i2c_board_info1,
1433 ARRAY_SIZE(bfin_i2c_board_info1));
81d9c7f2
BW		 1434#endif
1435
24a07a12 1436 platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
c6c4d7bb 1437
5bda2723 1438 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
c6c4d7bb 1439
24a07a12
RH		 1440 return 0;
1441}
1442
a01d7a76 1443arch_initcall(ezkit_init);
c13ce9fd
SZ		 1444
1445static struct platform_device *ezkit_early_devices[] __initdata = {
1446#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
1447#ifdef CONFIG_SERIAL_BFIN_UART0
1448 &bfin_uart0_device,
1449#endif
1450#ifdef CONFIG_SERIAL_BFIN_UART1
1451 &bfin_uart1_device,
1452#endif
1453#ifdef CONFIG_SERIAL_BFIN_UART2
1454 &bfin_uart2_device,
1455#endif
1456#ifdef CONFIG_SERIAL_BFIN_UART3
1457 &bfin_uart3_device,
1458#endif
1459#endif
1460
1461#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
1462#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1463 &bfin_sport0_uart_device,
1464#endif
1465#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1466 &bfin_sport1_uart_device,
1467#endif
1468#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1469 &bfin_sport2_uart_device,
1470#endif
1471#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
1472 &bfin_sport3_uart_device,
1473#endif
1474#endif
1475};
1476
1477void __init native_machine_early_platform_add_devices(void)
1478{
1479 printk(KERN_INFO "register early platform devices\n");
1480 early_platform_add_devices(ezkit_early_devices,
1481 ARRAY_SIZE(ezkit_early_devices));
1482}
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