[mirror_ubuntu-hirsute-kernel.git] / arch / blackfin / mach-bf548 / include / mach / anomaly.h

/*
 * DO NOT EDIT THIS FILE
 * This file is under version control at
 *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
 * and can be replaced with that version at any time
 * DO NOT EDIT THIS FILE
 *
 * Copyright 2004-2010 Analog Devices Inc.
 * Licensed under the ADI BSD license.
 *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
 */

/* This file should be up to date with:
 *  - Revision I, 07/23/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
 */

#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_

/* We do not support 0.0 or 0.1 silicon - sorry */
#if __SILICON_REVISION__ < 2
# error will not work on BF548 silicon version 0.0, or 0.1
#endif

/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
#define ANOMALY_05000220 (1)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (1)
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
#define ANOMALY_05000272 (1)
/* False Hardware Error Exception when ISR Context Is Not Restored */
#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1)
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
/* TWI Slave Boot Mode Is Not Functional */
#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
/* FIFO Boot Mode Not Functional */
#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
/* Incorrect Access of OTP_STATUS During otp_write() Function */
#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
/* Synchronous Burst Flash Boot Mode Is Not Functional */
#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
/* Host DMA Boot Modes Are Not Functional */
#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
/* Inadequate Rotary Debounce Logic Duration */
#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
/* USB Calibration Value Is Not Initialized */
#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
/* USB Calibration Value to use */
#define ANOMALY_05000346_value 0x5411
/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
/* Data Lost when Core Reads SDH Data FIFO */
#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
/* PLL Status Register Is Inaccurate */
#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
/*
 * Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing
 *       shows that the fix itself does not cover all cases.
 */
#define ANOMALY_05000353 (1)
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
#define ANOMALY_05000357 (1)
/* External Memory Read Access Hangs Core With PLL Bypass */
#define ANOMALY_05000360 (1)
/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
#define ANOMALY_05000365 (1)
/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
/* Addressing Conflict between Boot ROM and Asynchronous Memory */
#define ANOMALY_05000369 (1)
/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
#define ANOMALY_05000379 (1)
/* 8-Bit NAND Flash Boot Mode Not Functional */
#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
/* Some ATAPI Modes Are Not Functional */
#define ANOMALY_05000383 (1)
/* Boot from OTP Memory Not Functional */
#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
/* bfrom_SysControl() Firmware Routine Not Functional */
#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
/* Programmable Preboot Settings Not Functional */
#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
/* CRC32 Checksum Support Not Functional */
#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
/* Reset Vector Must Not Be in SDRAM Memory Space */
#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
/* Changed Meaning of BCODE Field in SYSCR Register */
#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
/* Log Buffer Not Functional */
#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
/* Hook Routine Not Functional */
#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
/* Header Indirect Bit Not Functional */
#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
/* Lockbox SESR Disallows Certain User Interrupts */
#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
#define ANOMALY_05000405 (1)
/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
#define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
#define ANOMALY_05000408 (1)
/* Lockbox firmware leaves MDMA0 channel enabled */
#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
#define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
#define ANOMALY_05000416 (1)
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
#define ANOMALY_05000425 (1)
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
#define ANOMALY_05000426 (1)
/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
#define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
/* Software System Reset Corrupts PLL_LOCKCNT Register */
#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
#define ANOMALY_05000434 (1)
/* OTP Write Accesses Not Supported */
#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
#define ANOMALY_05000446 (1)
/* UART IrDA Receiver Fails on Extended Bit Pulses */
#define ANOMALY_05000447 (1)
/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
/* USB DMA Mode 1 Short Packet Data Corruption */
#define ANOMALY_05000450 (1)
/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
#define ANOMALY_05000456 (1)
/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
#define ANOMALY_05000457 (1)
/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
#define ANOMALY_05000460 (1)
/* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1)
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
#define ANOMALY_05000462 (1)
/* USB DMA RX Data Corruption */
#define ANOMALY_05000463 (1)
/* USB TX DMA Hang */
#define ANOMALY_05000464 (1)
/* USB Rx DMA hang */
#define ANOMALY_05000465 (1)
/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
#define ANOMALY_05000466 (1)
/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
#define ANOMALY_05000467 (1)
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
#define ANOMALY_05000473 (1)
/* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */
#define ANOMALY_05000474 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
#define ANOMALY_05000483 (1)
/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2)
/* IFLUSH sucks at life */
#define ANOMALY_05000491 (1)

/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
#define ANOMALY_05000120 (0)
#define ANOMALY_05000125 (0)
#define ANOMALY_05000149 (0)
#define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0)
#define ANOMALY_05000179 (0)
#define ANOMALY_05000182 (0)
#define ANOMALY_05000183 (0)
#define ANOMALY_05000189 (0)
#define ANOMALY_05000198 (0)
#define ANOMALY_05000202 (0)
#define ANOMALY_05000215 (0)
#define ANOMALY_05000219 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0)
#define ANOMALY_05000233 (0)
#define ANOMALY_05000234 (0)
#define ANOMALY_05000242 (0)
#define ANOMALY_05000244 (0)
#define ANOMALY_05000248 (0)
#define ANOMALY_05000250 (0)
#define ANOMALY_05000254 (0)
#define ANOMALY_05000257 (0)
#define ANOMALY_05000261 (0)
#define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0)
#define ANOMALY_05000274 (0)
#define ANOMALY_05000278 (0)
#define ANOMALY_05000283 (0)
#define ANOMALY_05000287 (0)
#define ANOMALY_05000301 (0)
#define ANOMALY_05000305 (0)
#define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000315 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0)
#define ANOMALY_05000364 (0)
#define ANOMALY_05000380 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000402 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
#define ANOMALY_05000475 (0)

#endif
Commit	Line	Data
088eec11	1	/*
af5d7fc7 MF	2	* DO NOT EDIT THIS FILE
	3	* This file is under version control at
	4	* svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
	5	* and can be replaced with that version at any time
	6	* DO NOT EDIT THIS FILE
088eec11	7	*
dc7101bb	8	* Copyright 2004-2010 Analog Devices Inc.
af5d7fc7 MF	9	* Licensed under the ADI BSD license.
af5d7fc7 MF	10	* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
088eec11 RH	11	*/
088eec11 RH	12
a413647b	13	/* This file should be up to date with:
bd411b15	14	* - Revision I, 07/23/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
1aafd909 MF	15	*/
1aafd909 MF	16
088eec11 RH	17	#ifndef _MACH_ANOMALY_H_
088eec11 RH	18	#define _MACH_ANOMALY_H_
287050fe	19
a413647b MF	20	/* We do not support 0.0 or 0.1 silicon - sorry */
	21	#if __SILICON_REVISION__ < 2
	22	# error will not work on BF548 silicon version 0.0, or 0.1
	23	#endif
	24
a200ad22	25	/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
1aafd909 MF	26	#define ANOMALY_05000074 (1)
	27	/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
	28	#define ANOMALY_05000119 (1)
	29	/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
	30	#define ANOMALY_05000122 (1)
dc7101bb	31	/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
af5d7fc7	32	#define ANOMALY_05000220 (1)
a413647b	33	/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
1aafd909	34	#define ANOMALY_05000245 (1)
1aafd909 MF	35	/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
	36	#define ANOMALY_05000265 (1)
	37	/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
	38	#define ANOMALY_05000272 (1)
a200ad22	39	/* False Hardware Error Exception when ISR Context Is Not Restored */
7cc1c4b2	40	#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
bc8c84c9	41	/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
7cc1c4b2	42	#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
1aafd909 MF	43	/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
1aafd909 MF	44	#define ANOMALY_05000310 (1)
a200ad22	45	/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
7cc1c4b2	46	#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
1aafd909	47	/* TWI Slave Boot Mode Is Not Functional */
7cc1c4b2	48	#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
a200ad22	49	/* FIFO Boot Mode Not Functional */
4e8086d6	50	#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
1aafd909	51	/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
7cc1c4b2	52	#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
1aafd909	53	/* Incorrect Access of OTP_STATUS During otp_write() Function */
7cc1c4b2	54	#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
1aafd909	55	/* Synchronous Burst Flash Boot Mode Is Not Functional */
7cc1c4b2	56	#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
4e8086d6	57	/* Host DMA Boot Modes Are Not Functional */
7cc1c4b2	58	#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
1aafd909	59	/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
7cc1c4b2	60	#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
1aafd909	61	/* Inadequate Rotary Debounce Logic Duration */
7cc1c4b2	62	#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
1aafd909	63	/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
7cc1c4b2	64	#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
1aafd909	65	/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
7cc1c4b2	66	#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
1aafd909	67	/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
7cc1c4b2	68	#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
bc8c84c9	69	/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
7cc1c4b2	70	#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
bc8c84c9	71	/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
7cc1c4b2	72	#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
a413647b	73	/* USB Calibration Value Is Not Initialized */
7cc1c4b2	74	#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
202d7bd9 RG	75	/* USB Calibration Value to use */
202d7bd9 RG	76	#define ANOMALY_05000346_value 0x5411
4e8086d6	77	/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
7cc1c4b2	78	#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
bc8c84c9	79	/* Data Lost when Core Reads SDH Data FIFO */
7cc1c4b2	80	#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
bc8c84c9	81	/* PLL Status Register Is Inaccurate */
7cc1c4b2	82	#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
4e8086d6	83	/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
de55aa33 MF	84	/*
	85	* Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing
	86	* shows that the fix itself does not cover all cases.
	87	*/
	88	#define ANOMALY_05000353 (1)
4e8086d6 MF	89	/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
	90	#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
	91	/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
	92	#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
7cc1c4b2 MF	93	/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
	94	#define ANOMALY_05000357 (1)
	95	/* External Memory Read Access Hangs Core With PLL Bypass */
	96	#define ANOMALY_05000360 (1)
	97	/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
	98	#define ANOMALY_05000365 (1)
4e8086d6 MF	99	/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
4e8086d6 MF	100	#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
7cc1c4b2 MF	101	/* Addressing Conflict between Boot ROM and Asynchronous Memory */
7cc1c4b2 MF	102	#define ANOMALY_05000369 (1)
4e8086d6 MF	103	/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
4e8086d6 MF	104	#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
a70ce072	105	/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
4e8086d6 MF	106	#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
	107	/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
	108	#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
7cc1c4b2	109	/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
4e8086d6 MF	110	#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
	111	/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
	112	#define ANOMALY_05000379 (1)
	113	/* 8-Bit NAND Flash Boot Mode Not Functional */
	114	#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
	115	/* Some ATAPI Modes Are Not Functional */
	116	#define ANOMALY_05000383 (1)
	117	/* Boot from OTP Memory Not Functional */
	118	#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
	119	/* bfrom_SysControl() Firmware Routine Not Functional */
	120	#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
	121	/* Programmable Preboot Settings Not Functional */
	122	#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
	123	/* CRC32 Checksum Support Not Functional */
	124	#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
	125	/* Reset Vector Must Not Be in SDRAM Memory Space */
	126	#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
	127	/* Changed Meaning of BCODE Field in SYSCR Register */
	128	#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
	129	/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
	130	#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
	131	/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
	132	#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
	133	/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
	134	#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
	135	/* Log Buffer Not Functional */
	136	#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
	137	/* Hook Routine Not Functional */
	138	#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
	139	/* Header Indirect Bit Not Functional */
	140	#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
	141	/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
	142	#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
	143	/* Lockbox SESR Disallows Certain User Interrupts */
	144	#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
	145	/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
	146	#define ANOMALY_05000405 (1)
	147	/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
	148	#define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
	149	/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
	150	#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
	151	/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
	152	#define ANOMALY_05000408 (1)
	153	/* Lockbox firmware leaves MDMA0 channel enabled */
	154	#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
	155	/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
	156	#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
	157	/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
	158	#define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
	159	/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
	160	#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
	161	/* Speculative Fetches Can Cause Undesired External FIFO Operations */
	162	#define ANOMALY_05000416 (1)
	163	/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
	164	#define ANOMALY_05000425 (1)
a413647b	165	/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
4e8086d6 MF	166	#define ANOMALY_05000426 (1)
	167	/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
	168	#define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
a413647b	169	/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
4e8086d6 MF	170	#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
	171	/* Software System Reset Corrupts PLL_LOCKCNT Register */
	172	#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
c18e99cf MF	173	/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
c18e99cf MF	174	#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
bd411b15 YL	175	/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
bd411b15 YL	176	#define ANOMALY_05000434 (1)
c18e99cf MF	177	/* OTP Write Accesses Not Supported */
c18e99cf MF	178	#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
3529e041 MF	179	/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
3529e041 MF	180	#define ANOMALY_05000443 (1)
c18e99cf MF	181	/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
	182	#define ANOMALY_05000446 (1)
	183	/* UART IrDA Receiver Fails on Extended Bit Pulses */
	184	#define ANOMALY_05000447 (1)
	185	/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
	186	#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
	187	/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
	188	#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
	189	/* USB DMA Mode 1 Short Packet Data Corruption */
a413647b	190	#define ANOMALY_05000450 (1)
bd411b15 YL	191	/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
bd411b15 YL	192	#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
a413647b	193	/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
bd411b15 YL	194	#define ANOMALY_05000456 (1)
	195	/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
	196	#define ANOMALY_05000457 (1)
	197	/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
	198	#define ANOMALY_05000460 (1)
a200ad22	199	/* False Hardware Error when RETI Points to Invalid Memory */
a413647b	200	#define ANOMALY_05000461 (1)
bd411b15 YL	201	/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
	202	#define ANOMALY_05000462 (1)
	203	/* USB DMA RX Data Corruption */
	204	#define ANOMALY_05000463 (1)
	205	/* USB TX DMA Hang */
	206	#define ANOMALY_05000464 (1)
a200ad22 MF	207	/* USB Rx DMA hang */
a200ad22 MF	208	#define ANOMALY_05000465 (1)
bd411b15 YL	209	/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
bd411b15 YL	210	#define ANOMALY_05000466 (1)
a200ad22 MF	211	/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
a200ad22 MF	212	#define ANOMALY_05000467 (1)
af5d7fc7 MF	213	/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
	214	#define ANOMALY_05000473 (1)
	215	/* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */
	216	#define ANOMALY_05000474 (1)
af5d7fc7 MF	217	/* TESTSET Instruction Cannot Be Interrupted */
af5d7fc7 MF	218	#define ANOMALY_05000477 (1)
dc7101bb MF	219	/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
	220	#define ANOMALY_05000481 (1)
	221	/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
	222	#define ANOMALY_05000483 (1)
	223	/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
	224	#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2)
	225	/* IFLUSH sucks at life */
	226	#define ANOMALY_05000491 (1)
1aafd909 MF	227
1aafd909 MF	228	/* Anomalies that don't exist on this proc */
a413647b MF	229	#define ANOMALY_05000099 (0)
a413647b MF	230	#define ANOMALY_05000120 (0)
1aafd909	231	#define ANOMALY_05000125 (0)
a413647b	232	#define ANOMALY_05000149 (0)
2cbfe107	233	#define ANOMALY_05000158 (0)
a413647b MF	234	#define ANOMALY_05000171 (0)
a413647b MF	235	#define ANOMALY_05000179 (0)
a200ad22	236	#define ANOMALY_05000182 (0)
1aafd909	237	#define ANOMALY_05000183 (0)
976119bc	238	#define ANOMALY_05000189 (0)
1aafd909	239	#define ANOMALY_05000198 (0)
a200ad22	240	#define ANOMALY_05000202 (0)
a413647b	241	#define ANOMALY_05000215 (0)
dc7101bb	242	#define ANOMALY_05000219 (0)
a413647b	243	#define ANOMALY_05000227 (0)
0174dd59	244	#define ANOMALY_05000230 (0)
a413647b MF	245	#define ANOMALY_05000231 (0)
a413647b MF	246	#define ANOMALY_05000233 (0)
a200ad22	247	#define ANOMALY_05000234 (0)
a413647b	248	#define ANOMALY_05000242 (0)
1aafd909	249	#define ANOMALY_05000244 (0)
a413647b MF	250	#define ANOMALY_05000248 (0)
	251	#define ANOMALY_05000250 (0)
	252	#define ANOMALY_05000254 (0)
a200ad22	253	#define ANOMALY_05000257 (0)
60e9356d	254	#define ANOMALY_05000261 (0)
1aafd909 MF	255	#define ANOMALY_05000263 (0)
	256	#define ANOMALY_05000266 (0)
	257	#define ANOMALY_05000273 (0)
a413647b	258	#define ANOMALY_05000274 (0)
ee554be9	259	#define ANOMALY_05000278 (0)
a200ad22	260	#define ANOMALY_05000283 (0)
a413647b MF	261	#define ANOMALY_05000287 (0)
a413647b MF	262	#define ANOMALY_05000301 (0)
c18e99cf	263	#define ANOMALY_05000305 (0)
4e8086d6	264	#define ANOMALY_05000307 (0)
1aafd909	265	#define ANOMALY_05000311 (0)
a200ad22	266	#define ANOMALY_05000315 (0)
2b39331a	267	#define ANOMALY_05000323 (0)
a413647b	268	#define ANOMALY_05000362 (1)
4d555630	269	#define ANOMALY_05000363 (0)
976119bc	270	#define ANOMALY_05000364 (0)
1c302b6c	271	#define ANOMALY_05000380 (0)
a413647b	272	#define ANOMALY_05000400 (0)
bd411b15	273	#define ANOMALY_05000402 (0)
6651ece9 MF	274	#define ANOMALY_05000412 (0)
6651ece9 MF	275	#define ANOMALY_05000432 (0)
94b28211	276	#define ANOMALY_05000435 (0)
dc7101bb	277	#define ANOMALY_05000475 (0)
088eec11	278
1aafd909	279	#endif