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Commit | Line | Data |
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0b39db28 GY |
1 | /* |
2 | * Copyright 2007-2009 Analog Devices Inc. | |
3 | * Graff Yang <graf.yang@analog.com> | |
4 | * | |
5 | * Licensed under the GPL-2 or later. | |
6 | */ | |
7 | ||
6f546bc3 | 8 | #include <linux/smp.h> |
0b39db28 | 9 | #include <asm/blackfin.h> |
1e924e2f | 10 | #include <asm/cacheflush.h> |
6f546bc3 | 11 | #include <mach/pll.h> |
0b39db28 GY |
12 | |
13 | int hotplug_coreb; | |
14 | ||
15 | void platform_cpu_die(void) | |
16 | { | |
6f546bc3 | 17 | unsigned long iwr; |
1e924e2f | 18 | |
0b39db28 GY |
19 | hotplug_coreb = 1; |
20 | ||
1e924e2f GY |
21 | /* |
22 | * When CoreB wakes up, the code in _coreb_trampoline_start cannot | |
23 | * turn off the data cache. This causes the CoreB failed to boot. | |
24 | * As a workaround, we invalidate all the data cache before sleep. | |
25 | */ | |
26 | blackfin_invalidate_entire_dcache(); | |
27 | ||
0b39db28 GY |
28 | /* disable core timer */ |
29 | bfin_write_TCNTL(0); | |
30 | ||
6f546bc3 | 31 | /* clear ipi interrupt IRQ_SUPPLE_0 of CoreB */ |
0b39db28 GY |
32 | bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + 1))); |
33 | SSYNC(); | |
34 | ||
6f546bc3 GY |
35 | /* set CoreB wakeup by ipi0, iwr will be discarded */ |
36 | bfin_iwr_set_sup0(&iwr, &iwr, &iwr); | |
37 | SSYNC(); | |
38 | ||
39 | coreb_die(); | |
0b39db28 | 40 | } |