]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - arch/blackfin/mach-bf609/boards/ezkit.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
blackfin: serial: Add serial port_fer and port_mux early platform resources.
[mirror_ubuntu-jammy-kernel.git] / arch / blackfin / mach-bf609 / boards / ezkit.c
CommitLineData
22a82628
SZ		 1/*
2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2005 National ICT Australia (NICTA)
4 * Aidan Williams <aidan@nicta.com.au>
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <linux/device.h>
10#include <linux/platform_device.h>
11#include <linux/mtd/mtd.h>
12#include <linux/mtd/partitions.h>
13#include <linux/mtd/physmap.h>
14#include <linux/spi/spi.h>
15#include <linux/spi/flash.h>
16#include <linux/irq.h>
17#include <linux/i2c.h>
18#include <linux/interrupt.h>
19#include <linux/usb/musb.h>
54e4ff4d
SZ		 20#include <linux/pinctrl/machine.h>
21#include <linux/pinctrl/pinconf-generic.h>
22#include <linux/platform_data/pinctrl-adi2.h>
5e50175b 23#include <asm/bfin_spi3.h>
22a82628
SZ		 24#include <asm/dma.h>
25#include <asm/gpio.h>
26#include <asm/nand.h>
27#include <asm/dpmc.h>
28#include <asm/portmux.h>
29#include <asm/bfin_sdh.h>
30#include <linux/input.h>
31#include <linux/spi/ad7877.h>
32
33/*
34 * Name the Board for the /proc/cpuinfo
35 */
36const char bfin_board_name[] = "ADI BF609-EZKIT";
37
38/*
39 * Driver needs to know address, irq and flag pin.
40 */
41
42#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
43#include <linux/usb/isp1760.h>
44static struct resource bfin_isp1760_resources[] = {
45 [0] = {
46 .start = 0x2C0C0000,
47 .end = 0x2C0C0000 + 0xfffff,
48 .flags = IORESOURCE_MEM,
49 },
50 [1] = {
51 .start = IRQ_PG7,
52 .end = IRQ_PG7,
53 .flags = IORESOURCE_IRQ,
54 },
55};
56
57static struct isp1760_platform_data isp1760_priv = {
58 .is_isp1761 = 0,
59 .bus_width_16 = 1,
60 .port1_otg = 0,
61 .analog_oc = 0,
62 .dack_polarity_high = 0,
63 .dreq_polarity_high = 0,
64};
65
66static struct platform_device bfin_isp1760_device = {
67 .name = "isp1760",
68 .id = 0,
69 .dev = {
70 .platform_data = &isp1760_priv,
71 },
72 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
73 .resource = bfin_isp1760_resources,
74};
75#endif
76
77#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
78#include <asm/bfin_rotary.h>
79
80static struct bfin_rotary_platform_data bfin_rotary_data = {
81 /*.rotary_up_key = KEY_UP,*/
82 /*.rotary_down_key = KEY_DOWN,*/
83 .rotary_rel_code = REL_WHEEL,
84 .rotary_button_key = KEY_ENTER,
85 .debounce = 10, /* 0..17 */
86 .mode = ROT_QUAD_ENC | ROT_DEBE,
87};
88
89static struct resource bfin_rotary_resources[] = {
90 {
91 .start = IRQ_CNT,
92 .end = IRQ_CNT,
93 .flags = IORESOURCE_IRQ,
94 },
95};
96
97static struct platform_device bfin_rotary_device = {
98 .name = "bfin-rotary",
99 .id = -1,
100 .num_resources = ARRAY_SIZE(bfin_rotary_resources),
101 .resource = bfin_rotary_resources,
102 .dev = {
103 .platform_data = &bfin_rotary_data,
104 },
105};
106#endif
107
108#if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
109#include <linux/stmmac.h>
1d899fd6 110#include <linux/phy.h>
22a82628
SZ		 111
112static struct stmmac_mdio_bus_data phy_private_data = {
22a82628
SZ		 113 .phy_mask = 1,
114};
115
1d899fd6
SZ		 116static struct stmmac_dma_cfg eth_dma_cfg = {
117 .pbl = 2,
118};
119
120int stmmac_ptp_clk_init(struct platform_device *pdev)
121{
122 bfin_write32(PADS0_EMAC_PTP_CLKSEL, 0);
123 return 0;
124}
125
22a82628 126static struct plat_stmmacenet_data eth_private_data = {
1d899fd6 127 .has_gmac = 1,
22a82628
SZ		 128 .bus_id = 0,
129 .enh_desc = 1,
130 .phy_addr = 1,
131 .mdio_bus_data = &phy_private_data,
1d899fd6
SZ		 132 .dma_cfg = &eth_dma_cfg,
133 .force_thresh_dma_mode = 1,
134 .interface = PHY_INTERFACE_MODE_RMII,
135 .init = stmmac_ptp_clk_init,
22a82628
SZ		 136};
137
138static struct platform_device bfin_eth_device = {
139 .name = "stmmaceth",
140 .id = 0,
141 .num_resources = 2,
142 .resource = (struct resource[]) {
143 {
144 .start = EMAC0_MACCFG,
145 .end = EMAC0_MACCFG + 0x1274,
146 .flags = IORESOURCE_MEM,
147 },
148 {
149 .name = "macirq",
150 .start = IRQ_EMAC0_STAT,
151 .end = IRQ_EMAC0_STAT,
152 .flags = IORESOURCE_IRQ,
153 },
154 },
155 .dev = {
6e1953e1 156 .power.can_wakeup = 1,
22a82628
SZ		 157 .platform_data = &eth_private_data,
158 }
159};
160#endif
161
162#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
163#include <linux/input/adxl34x.h>
164static const struct adxl34x_platform_data adxl34x_info = {
165 .x_axis_offset = 0,
166 .y_axis_offset = 0,
167 .z_axis_offset = 0,
168 .tap_threshold = 0x31,
169 .tap_duration = 0x10,
170 .tap_latency = 0x60,
171 .tap_window = 0xF0,
172 .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
173 .act_axis_control = 0xFF,
174 .activity_threshold = 5,
175 .inactivity_threshold = 3,
176 .inactivity_time = 4,
177 .free_fall_threshold = 0x7,
178 .free_fall_time = 0x20,
179 .data_rate = 0x8,
180 .data_range = ADXL_FULL_RES,
181
182 .ev_type = EV_ABS,
183 .ev_code_x = ABS_X, /* EV_REL */
184 .ev_code_y = ABS_Y, /* EV_REL */
185 .ev_code_z = ABS_Z, /* EV_REL */
186
187 .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
188
189/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
190/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
191 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
192 .fifo_mode = ADXL_FIFO_STREAM,
193 .orientation_enable = ADXL_EN_ORIENTATION_3D,
194 .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
195 .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
196 /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
197 .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
198};
199#endif
200
201#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
202static struct platform_device rtc_device = {
203 .name = "rtc-bfin",
204 .id = -1,
205};
206#endif
207
208#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
209#ifdef CONFIG_SERIAL_BFIN_UART0
210static struct resource bfin_uart0_resources[] = {
211 {
212 .start = UART0_REVID,
213 .end = UART0_RXDIV+4,
214 .flags = IORESOURCE_MEM,
215 },
eb06c064
SZ		 216#ifdef CONFIG_EARLY_PRINTK
217 {
218 .start = PORTD_FER,
219 .end = PORTD_FER+2,
220 .flags = IORESOURCE_REG,
221 },
222 {
223 .start = PORTD_MUX,
224 .end = PORTD_MUX+3,
225 .flags = IORESOURCE_REG,
226 },
227#endif
22a82628
SZ		 228 {
229 .start = IRQ_UART0_TX,
230 .end = IRQ_UART0_TX,
231 .flags = IORESOURCE_IRQ,
232 },
233 {
234 .start = IRQ_UART0_RX,
235 .end = IRQ_UART0_RX,
236 .flags = IORESOURCE_IRQ,
237 },
238 {
239 .start = IRQ_UART0_STAT,
240 .end = IRQ_UART0_STAT,
241 .flags = IORESOURCE_IRQ,
242 },
243 {
244 .start = CH_UART0_TX,
245 .end = CH_UART0_TX,
246 .flags = IORESOURCE_DMA,
247 },
248 {
249 .start = CH_UART0_RX,
250 .end = CH_UART0_RX,
251 .flags = IORESOURCE_DMA,
252 },
253#ifdef CONFIG_BFIN_UART0_CTSRTS
254 { /* CTS pin -- 0 means not supported */
255 .start = GPIO_PD10,
256 .end = GPIO_PD10,
257 .flags = IORESOURCE_IO,
258 },
259 { /* RTS pin -- 0 means not supported */
260 .start = GPIO_PD9,
261 .end = GPIO_PD9,
262 .flags = IORESOURCE_IO,
263 },
264#endif
265};
266
267static unsigned short bfin_uart0_peripherals[] = {
268 P_UART0_TX, P_UART0_RX,
269#ifdef CONFIG_BFIN_UART0_CTSRTS
270 P_UART0_RTS, P_UART0_CTS,
271#endif
272 0
273};
274
275static struct platform_device bfin_uart0_device = {
276 .name = "bfin-uart",
277 .id = 0,
278 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
279 .resource = bfin_uart0_resources,
280 .dev = {
281 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
282 },
283};
284#endif
285#ifdef CONFIG_SERIAL_BFIN_UART1
286static struct resource bfin_uart1_resources[] = {
287 {
288 .start = UART1_REVID,
289 .end = UART1_RXDIV+4,
290 .flags = IORESOURCE_MEM,
291 },
eb06c064
SZ		 292#ifdef CONFIG_EARLY_PRINTK
293 {
294 .start = PORTG_FER_SET,
295 .end = PORTG_FER_SET+2,
296 .flags = IORESOURCE_REG,
297 },
298#endif
22a82628
SZ		 299 {
300 .start = IRQ_UART1_TX,
301 .end = IRQ_UART1_TX,
302 .flags = IORESOURCE_IRQ,
303 },
304 {
305 .start = IRQ_UART1_RX,
306 .end = IRQ_UART1_RX,
307 .flags = IORESOURCE_IRQ,
308 },
309 {
310 .start = IRQ_UART1_STAT,
311 .end = IRQ_UART1_STAT,
312 .flags = IORESOURCE_IRQ,
313 },
314 {
315 .start = CH_UART1_TX,
316 .end = CH_UART1_TX,
317 .flags = IORESOURCE_DMA,
318 },
319 {
320 .start = CH_UART1_RX,
321 .end = CH_UART1_RX,
322 .flags = IORESOURCE_DMA,
323 },
324#ifdef CONFIG_BFIN_UART1_CTSRTS
325 { /* CTS pin -- 0 means not supported */
326 .start = GPIO_PG13,
327 .end = GPIO_PG13,
328 .flags = IORESOURCE_IO,
329 },
330 { /* RTS pin -- 0 means not supported */
331 .start = GPIO_PG10,
332 .end = GPIO_PG10,
333 .flags = IORESOURCE_IO,
334 },
335#endif
336};
337
338static unsigned short bfin_uart1_peripherals[] = {
339 P_UART1_TX, P_UART1_RX,
340#ifdef CONFIG_BFIN_UART1_CTSRTS
341 P_UART1_RTS, P_UART1_CTS,
342#endif
343 0
344};
345
346static struct platform_device bfin_uart1_device = {
347 .name = "bfin-uart",
348 .id = 1,
349 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
350 .resource = bfin_uart1_resources,
351 .dev = {
352 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
353 },
354};
355#endif
356#endif
357
358#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
359#ifdef CONFIG_BFIN_SIR0
360static struct resource bfin_sir0_resources[] = {
361 {
362 .start = 0xFFC00400,
363 .end = 0xFFC004FF,
364 .flags = IORESOURCE_MEM,
365 },
366 {
367 .start = IRQ_UART0_TX,
368 .end = IRQ_UART0_TX+1,
369 .flags = IORESOURCE_IRQ,
370 },
371 {
372 .start = CH_UART0_TX,
373 .end = CH_UART0_TX+1,
374 .flags = IORESOURCE_DMA,
375 },
376};
377static struct platform_device bfin_sir0_device = {
378 .name = "bfin_sir",
379 .id = 0,
380 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
381 .resource = bfin_sir0_resources,
382};
383#endif
384#ifdef CONFIG_BFIN_SIR1
385static struct resource bfin_sir1_resources[] = {
386 {
387 .start = 0xFFC02000,
388 .end = 0xFFC020FF,
389 .flags = IORESOURCE_MEM,
390 },
391 {
392 .start = IRQ_UART1_TX,
393 .end = IRQ_UART1_TX+1,
394 .flags = IORESOURCE_IRQ,
395 },
396 {
397 .start = CH_UART1_TX,
398 .end = CH_UART1_TX+1,
399 .flags = IORESOURCE_DMA,
400 },
401};
402static struct platform_device bfin_sir1_device = {
403 .name = "bfin_sir",
404 .id = 1,
405 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
406 .resource = bfin_sir1_resources,
407};
408#endif
409#endif
410
411#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
412static struct resource musb_resources[] = {
413 [0] = {
414 .start = 0xFFCC1000,
415 .end = 0xFFCC1398,
416 .flags = IORESOURCE_MEM,
417 },
418 [1] = { /* general IRQ */
419 .start = IRQ_USB_STAT,
420 .end = IRQ_USB_STAT,
421 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
422 .name = "mc"
423 },
424 [2] = { /* DMA IRQ */
425 .start = IRQ_USB_DMA,
426 .end = IRQ_USB_DMA,
427 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
428 .name = "dma"
429 },
430};
431
432static struct musb_hdrc_config musb_config = {
433 .multipoint = 1,
434 .dyn_fifo = 0,
435 .dma = 1,
436 .num_eps = 16,
437 .dma_channels = 8,
438 .clkin = 48, /* musb CLKIN in MHZ */
439};
440
441static struct musb_hdrc_platform_data musb_plat = {
442#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
443 .mode = MUSB_OTG,
444#elif defined(CONFIG_USB_MUSB_HDRC)
445 .mode = MUSB_HOST,
446#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
447 .mode = MUSB_PERIPHERAL,
448#endif
449 .config = &musb_config,
450};
451
452static u64 musb_dmamask = ~(u32)0;
453
454static struct platform_device musb_device = {
455 .name = "musb-blackfin",
456 .id = 0,
457 .dev = {
458 .dma_mask = &musb_dmamask,
459 .coherent_dma_mask = 0xffffffff,
460 .platform_data = &musb_plat,
461 },
462 .num_resources = ARRAY_SIZE(musb_resources),
463 .resource = musb_resources,
464};
465#endif
466
467#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
468#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
469static struct resource bfin_sport0_uart_resources[] = {
470 {
471 .start = SPORT0_TCR1,
472 .end = SPORT0_MRCS3+4,
473 .flags = IORESOURCE_MEM,
474 },
475 {
476 .start = IRQ_SPORT0_RX,
477 .end = IRQ_SPORT0_RX+1,
478 .flags = IORESOURCE_IRQ,
479 },
480 {
481 .start = IRQ_SPORT0_ERROR,
482 .end = IRQ_SPORT0_ERROR,
483 .flags = IORESOURCE_IRQ,
484 },
485};
486
487static unsigned short bfin_sport0_peripherals[] = {
488 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
489 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
490};
491
492static struct platform_device bfin_sport0_uart_device = {
493 .name = "bfin-sport-uart",
494 .id = 0,
495 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
496 .resource = bfin_sport0_uart_resources,
497 .dev = {
498 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
499 },
500};
501#endif
502#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
503static struct resource bfin_sport1_uart_resources[] = {
504 {
505 .start = SPORT1_TCR1,
506 .end = SPORT1_MRCS3+4,
507 .flags = IORESOURCE_MEM,
508 },
509 {
510 .start = IRQ_SPORT1_RX,
511 .end = IRQ_SPORT1_RX+1,
512 .flags = IORESOURCE_IRQ,
513 },
514 {
515 .start = IRQ_SPORT1_ERROR,
516 .end = IRQ_SPORT1_ERROR,
517 .flags = IORESOURCE_IRQ,
518 },
519};
520
521static unsigned short bfin_sport1_peripherals[] = {
522 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
523 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
524};
525
526static struct platform_device bfin_sport1_uart_device = {
527 .name = "bfin-sport-uart",
528 .id = 1,
529 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
530 .resource = bfin_sport1_uart_resources,
531 .dev = {
532 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
533 },
534};
535#endif
536#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
537static struct resource bfin_sport2_uart_resources[] = {
538 {
539 .start = SPORT2_TCR1,
540 .end = SPORT2_MRCS3+4,
541 .flags = IORESOURCE_MEM,
542 },
543 {
544 .start = IRQ_SPORT2_RX,
545 .end = IRQ_SPORT2_RX+1,
546 .flags = IORESOURCE_IRQ,
547 },
548 {
549 .start = IRQ_SPORT2_ERROR,
550 .end = IRQ_SPORT2_ERROR,
551 .flags = IORESOURCE_IRQ,
552 },
553};
554
555static unsigned short bfin_sport2_peripherals[] = {
556 P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
557 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
558};
559
560static struct platform_device bfin_sport2_uart_device = {
561 .name = "bfin-sport-uart",
562 .id = 2,
563 .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
564 .resource = bfin_sport2_uart_resources,
565 .dev = {
566 .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
567 },
568};
569#endif
570#endif
571
572#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
573
574static unsigned short bfin_can0_peripherals[] = {
575 P_CAN0_RX, P_CAN0_TX, 0
576};
577
578static struct resource bfin_can0_resources[] = {
579 {
580 .start = 0xFFC00A00,
581 .end = 0xFFC00FFF,
582 .flags = IORESOURCE_MEM,
583 },
584 {
585 .start = IRQ_CAN0_RX,
586 .end = IRQ_CAN0_RX,
587 .flags = IORESOURCE_IRQ,
588 },
589 {
590 .start = IRQ_CAN0_TX,
591 .end = IRQ_CAN0_TX,
592 .flags = IORESOURCE_IRQ,
593 },
594 {
595 .start = IRQ_CAN0_STAT,
596 .end = IRQ_CAN0_STAT,
597 .flags = IORESOURCE_IRQ,
598 },
599};
600
601static struct platform_device bfin_can0_device = {
602 .name = "bfin_can",
603 .id = 0,
604 .num_resources = ARRAY_SIZE(bfin_can0_resources),
605 .resource = bfin_can0_resources,
606 .dev = {
607 .platform_data = &bfin_can0_peripherals, /* Passed to driver */
608 },
609};
610
611#endif
612
613#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
614static struct mtd_partition partition_info[] = {
615 {
616 .name = "bootloader(nand)",
617 .offset = 0,
618 .size = 0x80000,
619 }, {
620 .name = "linux kernel(nand)",
621 .offset = MTDPART_OFS_APPEND,
622 .size = 4 * 1024 * 1024,
623 },
624 {
625 .name = "file system(nand)",
626 .offset = MTDPART_OFS_APPEND,
627 .size = MTDPART_SIZ_FULL,
628 },
629};
630
631static struct bf5xx_nand_platform bfin_nand_platform = {
632 .data_width = NFC_NWIDTH_8,
633 .partitions = partition_info,
634 .nr_partitions = ARRAY_SIZE(partition_info),
635 .rd_dly = 3,
636 .wr_dly = 3,
637};
638
639static struct resource bfin_nand_resources[] = {
640 {
641 .start = 0xFFC03B00,
642 .end = 0xFFC03B4F,
643 .flags = IORESOURCE_MEM,
644 },
645 {
646 .start = CH_NFC,
647 .end = CH_NFC,
648 .flags = IORESOURCE_IRQ,
649 },
650};
651
652static struct platform_device bfin_nand_device = {
653 .name = "bfin-nand",
654 .id = 0,
655 .num_resources = ARRAY_SIZE(bfin_nand_resources),
656 .resource = bfin_nand_resources,
657 .dev = {
658 .platform_data = &bfin_nand_platform,
659 },
660};
661#endif
662
663#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
664
665static struct bfin_sd_host bfin_sdh_data = {
666 .dma_chan = CH_RSI,
667 .irq_int0 = IRQ_RSI_INT0,
668 .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
669};
670
671static struct platform_device bfin_sdh_device = {
672 .name = "bfin-sdh",
673 .id = 0,
674 .dev = {
675 .platform_data = &bfin_sdh_data,
676 },
677};
678#endif
679
1c400939 680#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
22a82628
SZ		 681static struct mtd_partition ezkit_partitions[] = {
682 {
683 .name = "bootloader(nor)",
684 .size = 0x80000,
685 .offset = 0,
686 }, {
687 .name = "linux kernel(nor)",
688 .size = 0x400000,
689 .offset = MTDPART_OFS_APPEND,
690 }, {
691 .name = "file system(nor)",
692 .size = 0x1000000 - 0x80000 - 0x400000,
693 .offset = MTDPART_OFS_APPEND,
694 },
695};
696
54e4ff4d 697int bf609_nor_flash_init(struct platform_device *pdev)
22a82628
SZ		 698{
699#define CONFIG_SMC_GCTL_VAL 0x00000010
22a82628 700
37035d62
SM		 701 if (!devm_pinctrl_get_select_default(&pdev->dev))
702 return -EBUSY;
22a82628 703 bfin_write32(SMC_GCTL, CONFIG_SMC_GCTL_VAL);
1c400939 704 bfin_write32(SMC_B0CTL, 0x01002011);
22a82628
SZ		 705 bfin_write32(SMC_B0TIM, 0x08170977);
706 bfin_write32(SMC_B0ETIM, 0x00092231);
707 return 0;
708}
709
37035d62 710void bf609_nor_flash_exit(struct platform_device *pdev)
0220874a 711{
37035d62 712 devm_pinctrl_put(pdev->dev.pins->p);
0220874a 713 bfin_write32(SMC_GCTL, 0);
0220874a
SM		 714}
715
22a82628
SZ		 716static struct physmap_flash_data ezkit_flash_data = {
717 .width = 2,
718 .parts = ezkit_partitions,
0220874a
SM		 719 .init = bf609_nor_flash_init,
720 .exit = bf609_nor_flash_exit,
22a82628 721 .nr_parts = ARRAY_SIZE(ezkit_partitions),
3fa8c4b0
BL		 722#ifdef CONFIG_ROMKERNEL
723 .probe_type = "map_rom",
724#endif
22a82628
SZ		 725};
726
727static struct resource ezkit_flash_resource = {
728 .start = 0xb0000000,
729 .end = 0xb0ffffff,
730 .flags = IORESOURCE_MEM,
731};
732
733static struct platform_device ezkit_flash_device = {
1c400939 734 .name = "physmap-flash",
22a82628
SZ		 735 .id = 0,
736 .dev = {
737 .platform_data = &ezkit_flash_data,
738 },
739 .num_resources = 1,
740 .resource = &ezkit_flash_resource,
741};
742#endif
743
744#if defined(CONFIG_MTD_M25P80) \
745 || defined(CONFIG_MTD_M25P80_MODULE)
746/* SPI flash chip (w25q32) */
747static struct mtd_partition bfin_spi_flash_partitions[] = {
748 {
749 .name = "bootloader(spi)",
750 .size = 0x00080000,
751 .offset = 0,
752 .mask_flags = MTD_CAP_ROM
753 }, {
754 .name = "linux kernel(spi)",
755 .size = 0x00180000,
756 .offset = MTDPART_OFS_APPEND,
757 }, {
758 .name = "file system(spi)",
759 .size = MTDPART_SIZ_FULL,
760 .offset = MTDPART_OFS_APPEND,
761 }
762};
763
764static struct flash_platform_data bfin_spi_flash_data = {
765 .name = "m25p80",
766 .parts = bfin_spi_flash_partitions,
767 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
768 .type = "w25q32",
769};
770
5e50175b 771static struct bfin_spi3_chip spi_flash_chip_info = {
22a82628
SZ		 772 .enable_dma = true, /* use dma transfer with this chip*/
773};
774#endif
775
776#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
5e50175b 777static struct bfin_spi3_chip spidev_chip_info = {
22a82628
SZ		 778 .enable_dma = true,
779};
780#endif
781
2984b52b 782#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
22a82628
SZ		 783static struct platform_device bfin_i2s_pcm = {
784 .name = "bfin-i2s-pcm-audio",
785 .id = -1,
786};
787#endif
788
789#if defined(CONFIG_SND_BF6XX_SOC_I2S) || \
790 defined(CONFIG_SND_BF6XX_SOC_I2S_MODULE)
791#include <asm/bfin_sport3.h>
792static struct resource bfin_snd_resources[] = {
793 {
794 .start = SPORT0_CTL_A,
795 .end = SPORT0_CTL_A,
796 .flags = IORESOURCE_MEM,
797 },
798 {
799 .start = SPORT0_CTL_B,
800 .end = SPORT0_CTL_B,
801 .flags = IORESOURCE_MEM,
802 },
803 {
804 .start = CH_SPORT0_TX,
805 .end = CH_SPORT0_TX,
806 .flags = IORESOURCE_DMA,
807 },
808 {
809 .start = CH_SPORT0_RX,
810 .end = CH_SPORT0_RX,
811 .flags = IORESOURCE_DMA,
812 },
813 {
814 .start = IRQ_SPORT0_TX_STAT,
815 .end = IRQ_SPORT0_TX_STAT,
816 .flags = IORESOURCE_IRQ,
817 },
818 {
819 .start = IRQ_SPORT0_RX_STAT,
820 .end = IRQ_SPORT0_RX_STAT,
821 .flags = IORESOURCE_IRQ,
822 },
823};
824
825static const unsigned short bfin_snd_pin[] = {
826 P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK,
827 P_SPORT0_BFS, P_SPORT0_BD0, 0,
828};
829
830static struct bfin_snd_platform_data bfin_snd_data = {
831 .pin_req = bfin_snd_pin,
832};
833
834static struct platform_device bfin_i2s = {
835 .name = "bfin-i2s",
836 .num_resources = ARRAY_SIZE(bfin_snd_resources),
837 .resource = bfin_snd_resources,
838 .dev = {
839 .platform_data = &bfin_snd_data,
840 },
841};
842#endif
843
63f49dce
SJ		 844#if defined(CONFIG_SND_BF5XX_SOC_AD1836) \
845 || defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
846static const char * const ad1836_link[] = {
34f40955 847 "bfin-i2s.0",
63f49dce
SJ		 848 "spi0.76",
849};
850static struct platform_device bfin_ad1836_machine = {
851 .name = "bfin-snd-ad1836",
852 .id = -1,
853 .dev = {
854 .platform_data = (void *)ad1836_link,
855 },
856};
857#endif
858
22a82628
SZ		 859#if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) || \
860 defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61_MODULE)
861static struct platform_device adau1761_device = {
862 .name = "bfin-eval-adau1x61",
863};
864#endif
865
866#if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
867#include <sound/adau17x1.h>
868static struct adau1761_platform_data adau1761_info = {
869 .lineout_mode = ADAU1761_OUTPUT_MODE_LINE,
870 .headphone_mode = ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS,
871};
872#endif
873
874#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
875 || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
876#include <linux/videodev2.h>
877#include <media/blackfin/bfin_capture.h>
878#include <media/blackfin/ppi.h>
879
880static const unsigned short ppi_req[] = {
881 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
882 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
338881a5
SJ		 883 P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
884 P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
00afdbbf 885#if !defined(CONFIG_VIDEO_VS6624) && !defined(CONFIG_VIDEO_VS6624_MODULE)
338881a5
SJ		 886 P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
887 P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
00afdbbf 888#endif
22a82628
SZ		 889 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
890 0,
891};
892
893static const struct ppi_info ppi_info = {
894 .type = PPI_TYPE_EPPI3,
895 .dma_ch = CH_EPPI0_CH0,
896 .irq_err = IRQ_EPPI0_STAT,
897 .base = (void __iomem *)EPPI0_STAT,
898 .pin_req = ppi_req,
899};
900
901#if defined(CONFIG_VIDEO_VS6624) \
902 || defined(CONFIG_VIDEO_VS6624_MODULE)
903static struct v4l2_input vs6624_inputs[] = {
904 {
905 .index = 0,
906 .name = "Camera",
907 .type = V4L2_INPUT_TYPE_CAMERA,
908 .std = V4L2_STD_UNKNOWN,
909 },
910};
911
912static struct bcap_route vs6624_routes[] = {
913 {
914 .input = 0,
915 .output = 0,
916 },
917};
918
00afdbbf 919static const unsigned vs6624_ce_pin = GPIO_PE4;
22a82628
SZ		 920
921static struct bfin_capture_config bfin_capture_data = {
922 .card_name = "BF609",
923 .inputs = vs6624_inputs,
924 .num_inputs = ARRAY_SIZE(vs6624_inputs),
925 .routes = vs6624_routes,
926 .i2c_adapter_id = 0,
927 .board_info = {
928 .type = "vs6624",
929 .addr = 0x10,
930 .platform_data = (void *)&vs6624_ce_pin,
931 },
932 .ppi_info = &ppi_info,
933 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI
934 | EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
ac5bb893 935 .blank_pixels = 4,
22a82628
SZ		 936};
937#endif
938
338881a5
SJ		 939#if defined(CONFIG_VIDEO_ADV7842) \
940 || defined(CONFIG_VIDEO_ADV7842_MODULE)
941#include <media/adv7842.h>
942
943static struct v4l2_input adv7842_inputs[] = {
944 {
945 .index = 0,
946 .name = "Composite",
947 .type = V4L2_INPUT_TYPE_CAMERA,
948 .std = V4L2_STD_ALL,
688da5e8 949 .capabilities = V4L2_IN_CAP_STD,
338881a5
SJ		 950 },
951 {
952 .index = 1,
953 .name = "S-Video",
954 .type = V4L2_INPUT_TYPE_CAMERA,
955 .std = V4L2_STD_ALL,
688da5e8 956 .capabilities = V4L2_IN_CAP_STD,
338881a5
SJ		 957 },
958 {
959 .index = 2,
960 .name = "Component",
961 .type = V4L2_INPUT_TYPE_CAMERA,
a8451ed2 962 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
338881a5
SJ		 963 },
964 {
965 .index = 3,
966 .name = "VGA",
967 .type = V4L2_INPUT_TYPE_CAMERA,
a8451ed2 968 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
338881a5
SJ		 969 },
970 {
971 .index = 4,
972 .name = "HDMI",
973 .type = V4L2_INPUT_TYPE_CAMERA,
a8451ed2 974 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
338881a5
SJ		 975 },
976};
977
978static struct bcap_route adv7842_routes[] = {
979 {
980 .input = 3,
b5c00ae7 981 .output = 0,
688da5e8
SJ		 982 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
983 | EPPI_CTL_ACTIVE656),
338881a5
SJ		 984 },
985 {
986 .input = 4,
b5c00ae7 987 .output = 0,
338881a5
SJ		 988 },
989 {
990 .input = 2,
b5c00ae7 991 .output = 0,
338881a5
SJ		 992 },
993 {
994 .input = 1,
b5c00ae7 995 .output = 0,
338881a5
SJ		 996 },
997 {
998 .input = 0,
688da5e8
SJ		 999 .output = 1,
1000 .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
1001 | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC2
1002 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
b5c00ae7
SJ		 1003 },
1004};
1005
1006static struct adv7842_output_format adv7842_opf[] = {
1007 {
1008 .op_ch_sel = ADV7842_OP_CH_SEL_BRG,
1009 .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_8,
1010 .op_656_range = 1,
1011 .blank_data = 1,
1012 .insert_av_codes = 1,
338881a5 1013 },
688da5e8
SJ		 1014 {
1015 .op_ch_sel = ADV7842_OP_CH_SEL_RGB,
1016 .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_16,
1017 .op_656_range = 1,
1018 .blank_data = 1,
1019 },
338881a5
SJ		 1020};
1021
1022static struct adv7842_platform_data adv7842_data = {
b5c00ae7
SJ		 1023 .opf = adv7842_opf,
1024 .num_opf = ARRAY_SIZE(adv7842_opf),
338881a5 1025 .ain_sel = ADV7842_AIN10_11_12_NC_SYNC_4_1,
338881a5
SJ		 1026 .prim_mode = ADV7842_PRIM_MODE_SDP,
1027 .vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1,
1028 .inp_color_space = ADV7842_INP_COLOR_SPACE_AUTO,
e942d619
SJ		 1029 .i2c_sdp_io = 0x40,
1030 .i2c_sdp = 0x41,
1031 .i2c_cp = 0x42,
1032 .i2c_vdp = 0x43,
1033 .i2c_afe = 0x44,
1034 .i2c_hdmi = 0x45,
1035 .i2c_repeater = 0x46,
1036 .i2c_edid = 0x47,
1037 .i2c_infoframe = 0x48,
1038 .i2c_cec = 0x49,
1039 .i2c_avlink = 0x4a,
b5c00ae7 1040 .i2c_ex = 0x26,
338881a5
SJ		 1041};
1042
1043static struct bfin_capture_config bfin_capture_data = {
1044 .card_name = "BF609",
1045 .inputs = adv7842_inputs,
1046 .num_inputs = ARRAY_SIZE(adv7842_inputs),
1047 .routes = adv7842_routes,
1048 .i2c_adapter_id = 0,
1049 .board_info = {
1050 .type = "adv7842",
1051 .addr = 0x20,
1052 .platform_data = (void *)&adv7842_data,
1053 },
1054 .ppi_info = &ppi_info,
1055 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
1056 | EPPI_CTL_ACTIVE656),
1057};
1058#endif
1059
22a82628
SZ		 1060static struct platform_device bfin_capture_device = {
1061 .name = "bfin_capture",
1062 .dev = {
1063 .platform_data = &bfin_capture_data,
1064 },
1065};
1066#endif
1067
e942d619
SJ		 1068#if defined(CONFIG_VIDEO_BLACKFIN_DISPLAY) \
1069 || defined(CONFIG_VIDEO_BLACKFIN_DISPLAY_MODULE)
1070#include <linux/videodev2.h>
1071#include <media/blackfin/bfin_display.h>
1072#include <media/blackfin/ppi.h>
1073
1074static const unsigned short ppi_req_disp[] = {
1075 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
1076 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
1077 P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
1078 P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
1079 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
1080 0,
1081};
1082
1083static const struct ppi_info ppi_info = {
1084 .type = PPI_TYPE_EPPI3,
1085 .dma_ch = CH_EPPI0_CH0,
1086 .irq_err = IRQ_EPPI0_STAT,
1087 .base = (void __iomem *)EPPI0_STAT,
1088 .pin_req = ppi_req_disp,
1089};
1090
1091#if defined(CONFIG_VIDEO_ADV7511) \
1092 || defined(CONFIG_VIDEO_ADV7511_MODULE)
1093#include <media/adv7511.h>
1094
1095static struct v4l2_output adv7511_outputs[] = {
1096 {
1097 .index = 0,
1098 .name = "HDMI",
1099 .type = V4L2_INPUT_TYPE_CAMERA,
a8451ed2 1100 .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
e942d619
SJ		 1101 },
1102};
1103
1104static struct disp_route adv7511_routes[] = {
1105 {
1106 .output = 0,
1107 },
1108};
1109
1110static struct adv7511_platform_data adv7511_data = {
1111 .edid_addr = 0x7e,
1112 .i2c_ex = 0x25,
1113};
1114
1115static struct bfin_display_config bfin_display_data = {
1116 .card_name = "BF609",
1117 .outputs = adv7511_outputs,
1118 .num_outputs = ARRAY_SIZE(adv7511_outputs),
1119 .routes = adv7511_routes,
1120 .i2c_adapter_id = 0,
1121 .board_info = {
1122 .type = "adv7511",
1123 .addr = 0x39,
1124 .platform_data = (void *)&adv7511_data,
1125 },
1126 .ppi_info = &ppi_info,
1127 .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
1128 | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC3
1129 | EPPI_CTL_IFSGEN | EPPI_CTL_SYNC2
1130 | EPPI_CTL_NON656 | EPPI_CTL_DIR),
1131};
1132#endif
1133
4940c53d
SJ		 1134#if IS_ENABLED(CONFIG_VIDEO_ADV7343)
1135#include <media/adv7343.h>
1136
1137static struct v4l2_output adv7343_outputs[] = {
1138 {
1139 .index = 0,
1140 .name = "Composite",
1141 .type = V4L2_OUTPUT_TYPE_ANALOG,
1142 .std = V4L2_STD_ALL,
1143 .capabilities = V4L2_OUT_CAP_STD,
1144 },
e5786092
SJ		 1145 {
1146 .index = 1,
1147 .name = "S-Video",
1148 .type = V4L2_OUTPUT_TYPE_ANALOG,
1149 .std = V4L2_STD_ALL,
1150 .capabilities = V4L2_OUT_CAP_STD,
1151 },
1152 {
1153 .index = 2,
1154 .name = "Component",
1155 .type = V4L2_OUTPUT_TYPE_ANALOG,
1156 .std = V4L2_STD_ALL,
1157 .capabilities = V4L2_OUT_CAP_STD,
1158 },
1159
4940c53d
SJ		 1160};
1161
1162static struct disp_route adv7343_routes[] = {
1163 {
e5786092
SJ		 1164 .output = ADV7343_COMPOSITE_ID,
1165 },
1166 {
1167 .output = ADV7343_SVIDEO_ID,
1168 },
1169 {
1170 .output = ADV7343_COMPONENT_ID,
4940c53d
SJ		 1171 },
1172};
1173
1174static struct adv7343_platform_data adv7343_data = {
1175 .mode_config = {
1176 .sleep_mode = false,
1177 .pll_control = false,
1178 .dac_1 = true,
1179 .dac_2 = true,
1180 .dac_3 = true,
1181 .dac_4 = true,
1182 .dac_5 = true,
1183 .dac_6 = true,
1184 },
1185 .sd_config = {
1186 .sd_dac_out1 = false,
1187 .sd_dac_out2 = false,
1188 },
1189};
1190
1191static struct bfin_display_config bfin_display_data = {
1192 .card_name = "BF609",
1193 .outputs = adv7343_outputs,
1194 .num_outputs = ARRAY_SIZE(adv7343_outputs),
1195 .routes = adv7343_routes,
1196 .i2c_adapter_id = 0,
1197 .board_info = {
1198 .type = "adv7343",
1199 .addr = 0x2b,
1200 .platform_data = (void *)&adv7343_data,
1201 },
1202 .ppi_info = &ppi_info_disp,
1203 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1LO_FS2LO
1204 | EPPI_CTL_POLC3 | EPPI_CTL_BLANKGEN | EPPI_CTL_SYNC2
1205 | EPPI_CTL_NON656 | EPPI_CTL_DIR),
1206};
1207#endif
1208
e942d619
SJ		 1209static struct platform_device bfin_display_device = {
1210 .name = "bfin_display",
1211 .dev = {
1212 .platform_data = &bfin_display_data,
1213 },
1214};
1215#endif
1216
22a82628
SZ		 1217#if defined(CONFIG_BFIN_CRC)
1218#define BFIN_CRC_NAME "bfin-crc"
1219
1220static struct resource bfin_crc0_resources[] = {
1221 {
1222 .start = REG_CRC0_CTL,
1223 .end = REG_CRC0_REVID+4,
1224 .flags = IORESOURCE_MEM,
1225 },
1226 {
1227 .start = IRQ_CRC0_DCNTEXP,
1228 .end = IRQ_CRC0_DCNTEXP,
1229 .flags = IORESOURCE_IRQ,
1230 },
1231 {
1232 .start = CH_MEM_STREAM0_SRC_CRC0,
1233 .end = CH_MEM_STREAM0_SRC_CRC0,
1234 .flags = IORESOURCE_DMA,
1235 },
1236 {
1237 .start = CH_MEM_STREAM0_DEST_CRC0,
1238 .end = CH_MEM_STREAM0_DEST_CRC0,
1239 .flags = IORESOURCE_DMA,
1240 },
1241};
1242
1243static struct platform_device bfin_crc0_device = {
1244 .name = BFIN_CRC_NAME,
1245 .id = 0,
1246 .num_resources = ARRAY_SIZE(bfin_crc0_resources),
1247 .resource = bfin_crc0_resources,
1248};
1249
1250static struct resource bfin_crc1_resources[] = {
1251 {
1252 .start = REG_CRC1_CTL,
1253 .end = REG_CRC1_REVID+4,
1254 .flags = IORESOURCE_MEM,
1255 },
1256 {
1257 .start = IRQ_CRC1_DCNTEXP,
1258 .end = IRQ_CRC1_DCNTEXP,
1259 .flags = IORESOURCE_IRQ,
1260 },
1261 {
1262 .start = CH_MEM_STREAM1_SRC_CRC1,
1263 .end = CH_MEM_STREAM1_SRC_CRC1,
1264 .flags = IORESOURCE_DMA,
1265 },
1266 {
1267 .start = CH_MEM_STREAM1_DEST_CRC1,
1268 .end = CH_MEM_STREAM1_DEST_CRC1,
1269 .flags = IORESOURCE_DMA,
1270 },
1271};
1272
1273static struct platform_device bfin_crc1_device = {
1274 .name = BFIN_CRC_NAME,
1275 .id = 1,
1276 .num_resources = ARRAY_SIZE(bfin_crc1_resources),
1277 .resource = bfin_crc1_resources,
1278};
1279#endif
1280
c21e783b
SZ		 1281#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
1282#define BFIN_CRYPTO_CRC_NAME "bfin-hmac-crc"
1283#define BFIN_CRYPTO_CRC_POLY_DATA 0x5c5c5c5c
1284
1285static struct resource bfin_crypto_crc_resources[] = {
1286 {
1287 .start = REG_CRC0_CTL,
1288 .end = REG_CRC0_REVID+4,
1289 .flags = IORESOURCE_MEM,
1290 },
1291 {
1292 .start = IRQ_CRC0_DCNTEXP,
1293 .end = IRQ_CRC0_DCNTEXP,
1294 .flags = IORESOURCE_IRQ,
1295 },
1296 {
1297 .start = CH_MEM_STREAM0_SRC_CRC0,
1298 .end = CH_MEM_STREAM0_SRC_CRC0,
1299 .flags = IORESOURCE_DMA,
1300 },
c21e783b
SZ		 1301};
1302
1303static struct platform_device bfin_crypto_crc_device = {
1304 .name = BFIN_CRYPTO_CRC_NAME,
1305 .id = 0,
1306 .num_resources = ARRAY_SIZE(bfin_crypto_crc_resources),
1307 .resource = bfin_crypto_crc_resources,
1308 .dev = {
1309 .platform_data = (void *)BFIN_CRYPTO_CRC_POLY_DATA,
1310 },
1311};
1312#endif
1313
22a82628
SZ		 1314#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
1315static const struct ad7877_platform_data bfin_ad7877_ts_info = {
1316 .model = 7877,
1317 .vref_delay_usecs = 50, /* internal, no capacitor */
1318 .x_plate_ohms = 419,
1319 .y_plate_ohms = 486,
1320 .pressure_max = 1000,
1321 .pressure_min = 0,
1322 .stopacq_polarity = 1,
1323 .first_conversion_delay = 3,
1324 .acquisition_time = 1,
1325 .averaging = 1,
1326 .pen_down_acc_interval = 1,
1327};
1328#endif
1329
54e4ff4d
SZ		 1330#ifdef CONFIG_PINCTRL_ADI2
1331
1332# define ADI_PINT_DEVNAME "adi-gpio-pint"
1333# define ADI_GPIO_DEVNAME "adi-gpio"
1334# define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
1335
1336static struct platform_device bfin_pinctrl_device = {
1337 .name = ADI_PINCTRL_DEVNAME,
1338 .id = 0,
1339};
1340
54e4ff4d
SZ		 1341static struct resource bfin_pint0_resources[] = {
1342 {
1343 .start = PINT0_MASK_SET,
1344 .end = PINT0_LATCH + 3,
1345 .flags = IORESOURCE_MEM,
1346 },
1347 {
1348 .start = IRQ_PINT0,
1349 .end = IRQ_PINT0,
1350 .flags = IORESOURCE_IRQ,
1351 },
1352};
1353
1354static struct platform_device bfin_pint0_device = {
1355 .name = ADI_PINT_DEVNAME,
1356 .id = 0,
1357 .num_resources = ARRAY_SIZE(bfin_pint0_resources),
1358 .resource = bfin_pint0_resources,
1359};
1360
1361static struct resource bfin_pint1_resources[] = {
1362 {
1363 .start = PINT1_MASK_SET,
1364 .end = PINT1_LATCH + 3,
1365 .flags = IORESOURCE_MEM,
1366 },
1367 {
1368 .start = IRQ_PINT1,
1369 .end = IRQ_PINT1,
1370 .flags = IORESOURCE_IRQ,
1371 },
1372};
1373
1374static struct platform_device bfin_pint1_device = {
1375 .name = ADI_PINT_DEVNAME,
1376 .id = 1,
1377 .num_resources = ARRAY_SIZE(bfin_pint1_resources),
1378 .resource = bfin_pint1_resources,
1379};
1380
1381static struct resource bfin_pint2_resources[] = {
1382 {
1383 .start = PINT2_MASK_SET,
1384 .end = PINT2_LATCH + 3,
1385 .flags = IORESOURCE_MEM,
1386 },
1387 {
1388 .start = IRQ_PINT2,
1389 .end = IRQ_PINT2,
1390 .flags = IORESOURCE_IRQ,
1391 },
1392};
1393
1394static struct platform_device bfin_pint2_device = {
1395 .name = ADI_PINT_DEVNAME,
1396 .id = 2,
1397 .num_resources = ARRAY_SIZE(bfin_pint2_resources),
1398 .resource = bfin_pint2_resources,
1399};
1400
1401static struct resource bfin_pint3_resources[] = {
1402 {
1403 .start = PINT3_MASK_SET,
1404 .end = PINT3_LATCH + 3,
1405 .flags = IORESOURCE_MEM,
1406 },
1407 {
1408 .start = IRQ_PINT3,
1409 .end = IRQ_PINT3,
1410 .flags = IORESOURCE_IRQ,
1411 },
1412};
1413
1414static struct platform_device bfin_pint3_device = {
1415 .name = ADI_PINT_DEVNAME,
1416 .id = 3,
1417 .num_resources = ARRAY_SIZE(bfin_pint3_resources),
1418 .resource = bfin_pint3_resources,
1419};
1420
1421static struct resource bfin_pint4_resources[] = {
1422 {
1423 .start = PINT4_MASK_SET,
1424 .end = PINT4_LATCH + 3,
1425 .flags = IORESOURCE_MEM,
1426 },
1427 {
1428 .start = IRQ_PINT4,
1429 .end = IRQ_PINT4,
1430 .flags = IORESOURCE_IRQ,
1431 },
1432};
1433
1434static struct platform_device bfin_pint4_device = {
1435 .name = ADI_PINT_DEVNAME,
1436 .id = 4,
1437 .num_resources = ARRAY_SIZE(bfin_pint4_resources),
1438 .resource = bfin_pint4_resources,
1439};
1440
1441static struct resource bfin_pint5_resources[] = {
1442 {
1443 .start = PINT5_MASK_SET,
1444 .end = PINT5_LATCH + 3,
1445 .flags = IORESOURCE_MEM,
1446 },
1447 {
1448 .start = IRQ_PINT5,
1449 .end = IRQ_PINT5,
1450 .flags = IORESOURCE_IRQ,
1451 },
1452};
1453
1454static struct platform_device bfin_pint5_device = {
1455 .name = ADI_PINT_DEVNAME,
1456 .id = 5,
1457 .num_resources = ARRAY_SIZE(bfin_pint5_resources),
1458 .resource = bfin_pint5_resources,
1459};
1460
1461static struct resource bfin_gpa_resources[] = {
1462 {
1463 .start = PORTA_FER,
1464 .end = PORTA_MUX + 3,
1465 .flags = IORESOURCE_MEM,
1466 },
1467 { /* optional */
1468 .start = IRQ_PA0,
1469 .end = IRQ_PA0,
1470 .flags = IORESOURCE_IRQ,
1471 },
1472};
1473
1474static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = {
1475 .port_pin_base = GPIO_PA0,
1476 .port_width = GPIO_BANKSIZE,
1477 .pint_id = 0, /* PINT0 */
1478 .pint_assign = true, /* PINT upper 16 bit */
1479 .pint_map = 0, /* mapping mask in PINT */
1480};
1481
1482static struct platform_device bfin_gpa_device = {
1483 .name = ADI_GPIO_DEVNAME,
1484 .id = 0,
1485 .num_resources = ARRAY_SIZE(bfin_gpa_resources),
1486 .resource = bfin_gpa_resources,
1487 .dev = {
1488 .platform_data = &bfin_gpa_pdata, /* Passed to driver */
1489 },
1490};
1491
1492static struct resource bfin_gpb_resources[] = {
1493 {
1494 .start = PORTB_FER,
1495 .end = PORTB_MUX + 3,
1496 .flags = IORESOURCE_MEM,
1497 },
1498 {
1499 .start = IRQ_PB0,
1500 .end = IRQ_PB0,
1501 .flags = IORESOURCE_IRQ,
1502 },
1503};
1504
1505static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = {
1506 .port_pin_base = GPIO_PB0,
1507 .port_width = GPIO_BANKSIZE,
1508 .pint_id = 0,
1509 .pint_assign = false,
1510 .pint_map = 1,
1511};
1512
1513static struct platform_device bfin_gpb_device = {
1514 .name = ADI_GPIO_DEVNAME,
1515 .id = 1,
1516 .num_resources = ARRAY_SIZE(bfin_gpb_resources),
1517 .resource = bfin_gpb_resources,
1518 .dev = {
1519 .platform_data = &bfin_gpb_pdata, /* Passed to driver */
1520 },
1521};
1522
1523static struct resource bfin_gpc_resources[] = {
1524 {
1525 .start = PORTC_FER,
1526 .end = PORTC_MUX + 3,
1527 .flags = IORESOURCE_MEM,
1528 },
1529 {
1530 .start = IRQ_PC0,
1531 .end = IRQ_PC0,
1532 .flags = IORESOURCE_IRQ,
1533 },
1534};
1535
1536static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = {
1537 .port_pin_base = GPIO_PC0,
1538 .port_width = GPIO_BANKSIZE,
1539 .pint_id = 1,
1540 .pint_assign = false,
1541 .pint_map = 1,
1542};
1543
1544static struct platform_device bfin_gpc_device = {
1545 .name = ADI_GPIO_DEVNAME,
1546 .id = 2,
1547 .num_resources = ARRAY_SIZE(bfin_gpc_resources),
1548 .resource = bfin_gpc_resources,
1549 .dev = {
1550 .platform_data = &bfin_gpc_pdata, /* Passed to driver */
1551 },
1552};
1553
1554static struct resource bfin_gpd_resources[] = {
1555 {
1556 .start = PORTD_FER,
1557 .end = PORTD_MUX + 3,
1558 .flags = IORESOURCE_MEM,
1559 },
1560 {
1561 .start = IRQ_PD0,
1562 .end = IRQ_PD0,
1563 .flags = IORESOURCE_IRQ,
1564 },
1565};
1566
1567static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = {
1568 .port_pin_base = GPIO_PD0,
1569 .port_width = GPIO_BANKSIZE,
1570 .pint_id = 2,
1571 .pint_assign = false,
1572 .pint_map = 1,
1573};
1574
1575static struct platform_device bfin_gpd_device = {
1576 .name = ADI_GPIO_DEVNAME,
1577 .id = 3,
1578 .num_resources = ARRAY_SIZE(bfin_gpd_resources),
1579 .resource = bfin_gpd_resources,
1580 .dev = {
1581 .platform_data = &bfin_gpd_pdata, /* Passed to driver */
1582 },
1583};
1584
1585static struct resource bfin_gpe_resources[] = {
1586 {
1587 .start = PORTE_FER,
1588 .end = PORTE_MUX + 3,
1589 .flags = IORESOURCE_MEM,
1590 },
1591 {
1592 .start = IRQ_PE0,
1593 .end = IRQ_PE0,
1594 .flags = IORESOURCE_IRQ,
1595 },
1596};
1597
1598static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = {
1599 .port_pin_base = GPIO_PE0,
1600 .port_width = GPIO_BANKSIZE,
1601 .pint_id = 3,
1602 .pint_assign = false,
1603 .pint_map = 1,
1604};
1605
1606static struct platform_device bfin_gpe_device = {
1607 .name = ADI_GPIO_DEVNAME,
1608 .id = 4,
1609 .num_resources = ARRAY_SIZE(bfin_gpe_resources),
1610 .resource = bfin_gpe_resources,
1611 .dev = {
1612 .platform_data = &bfin_gpe_pdata, /* Passed to driver */
1613 },
1614};
1615
1616static struct resource bfin_gpf_resources[] = {
1617 {
1618 .start = PORTF_FER,
1619 .end = PORTF_MUX + 3,
1620 .flags = IORESOURCE_MEM,
1621 },
1622 {
1623 .start = IRQ_PF0,
1624 .end = IRQ_PF0,
1625 .flags = IORESOURCE_IRQ,
1626 },
1627};
1628
1629static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = {
1630 .port_pin_base = GPIO_PF0,
1631 .port_width = GPIO_BANKSIZE,
1632 .pint_id = 4,
1633 .pint_assign = false,
1634 .pint_map = 1,
1635};
1636
1637static struct platform_device bfin_gpf_device = {
1638 .name = ADI_GPIO_DEVNAME,
1639 .id = 5,
1640 .num_resources = ARRAY_SIZE(bfin_gpf_resources),
1641 .resource = bfin_gpf_resources,
1642 .dev = {
1643 .platform_data = &bfin_gpf_pdata, /* Passed to driver */
1644 },
1645};
1646
1647static struct resource bfin_gpg_resources[] = {
1648 {
1649 .start = PORTG_FER,
1650 .end = PORTG_MUX + 3,
1651 .flags = IORESOURCE_MEM,
1652 },
1653 {
1654 .start = IRQ_PG0,
1655 .end = IRQ_PG0,
1656 .flags = IORESOURCE_IRQ,
1657 },
1658};
1659
1660static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = {
1661 .port_pin_base = GPIO_PG0,
1662 .port_width = GPIO_BANKSIZE,
1663 .pint_id = 5,
1664 .pint_assign = false,
1665 .pint_map = 1,
1666};
1667
1668static struct platform_device bfin_gpg_device = {
1669 .name = ADI_GPIO_DEVNAME,
1670 .id = 6,
1671 .num_resources = ARRAY_SIZE(bfin_gpg_resources),
1672 .resource = bfin_gpg_resources,
1673 .dev = {
1674 .platform_data = &bfin_gpg_pdata, /* Passed to driver */
1675 },
1676};
1677
1678#endif
1679
bbca5c6d
SM		 1680#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1681#include <linux/input.h>
1682#include <linux/gpio_keys.h>
1683
1684static struct gpio_keys_button bfin_gpio_keys_table[] = {
1685 {BTN_0, GPIO_PB10, 1, "gpio-keys: BTN0"},
1686 {BTN_1, GPIO_PE1, 1, "gpio-keys: BTN1"},
1687};
1688
1689static struct gpio_keys_platform_data bfin_gpio_keys_data = {
1690 .buttons = bfin_gpio_keys_table,
1691 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
1692};
1693
1694static struct platform_device bfin_device_gpiokeys = {
1695 .name = "gpio-keys",
1696 .dev = {
1697 .platform_data = &bfin_gpio_keys_data,
1698 },
1699};
1700#endif
1701
22a82628
SZ		 1702static struct spi_board_info bfin_spi_board_info[] __initdata = {
1703#if defined(CONFIG_MTD_M25P80) \
1704 || defined(CONFIG_MTD_M25P80_MODULE)
1705 {
1706 /* the modalias must be the same as spi device driver name */
1707 .modalias = "m25p80", /* Name of spi_driver for this device */
1708 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
1709 .bus_num = 0, /* Framework bus number */
54e4ff4d 1710 .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
22a82628
SZ		 1711 .platform_data = &bfin_spi_flash_data,
1712 .controller_data = &spi_flash_chip_info,
1713 .mode = SPI_MODE_3,
1714 },
1715#endif
1716#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
1717 {
1718 .modalias = "ad7877",
1719 .platform_data = &bfin_ad7877_ts_info,
2cdd7008 1720 .irq = IRQ_PD9,
22a82628
SZ		 1721 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
1722 .bus_num = 0,
54e4ff4d 1723 .chip_select = MAX_CTRL_CS + GPIO_PC15, /* SPI_SSEL4 */
22a82628
SZ		 1724 },
1725#endif
1726#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
1727 {
1728 .modalias = "spidev",
1729 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1730 .bus_num = 0,
54e4ff4d 1731 .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
22a82628
SZ		 1732 .controller_data = &spidev_chip_info,
1733 },
1734#endif
1735#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
1736 {
1737 .modalias = "adxl34x",
1738 .platform_data = &adxl34x_info,
1739 .irq = IRQ_PC5,
1740 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
1741 .bus_num = 1,
1742 .chip_select = 2,
1743 .mode = SPI_MODE_3,
1744 },
1745#endif
1746};
5e50175b 1747#if IS_ENABLED(CONFIG_SPI_BFIN_V3)
22a82628
SZ		 1748/* SPI (0) */
1749static struct resource bfin_spi0_resource[] = {
1750 {
1751 .start = SPI0_REGBASE,
1752 .end = SPI0_REGBASE + 0xFF,
1753 .flags = IORESOURCE_MEM,
1754 },
1755 {
1756 .start = CH_SPI0_TX,
1757 .end = CH_SPI0_TX,
1758 .flags = IORESOURCE_DMA,
1759 },
1760 {
1761 .start = CH_SPI0_RX,
1762 .end = CH_SPI0_RX,
1763 .flags = IORESOURCE_DMA,
1764 },
1765};
1766
1767/* SPI (1) */
1768static struct resource bfin_spi1_resource[] = {
1769 {
1770 .start = SPI1_REGBASE,
1771 .end = SPI1_REGBASE + 0xFF,
1772 .flags = IORESOURCE_MEM,
1773 },
1774 {
1775 .start = CH_SPI1_TX,
1776 .end = CH_SPI1_TX,
1777 .flags = IORESOURCE_DMA,
1778 },
1779 {
1780 .start = CH_SPI1_RX,
1781 .end = CH_SPI1_RX,
1782 .flags = IORESOURCE_DMA,
1783 },
1784
1785};
1786
1787/* SPI controller data */
5e50175b 1788static struct bfin_spi3_master bf60x_spi_master_info0 = {
2cdd7008 1789 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
22a82628
SZ		 1790 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1791};
1792
1793static struct platform_device bf60x_spi_master0 = {
5e50175b 1794 .name = "bfin-spi3",
22a82628
SZ		 1795 .id = 0, /* Bus number */
1796 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
1797 .resource = bfin_spi0_resource,
1798 .dev = {
1799 .platform_data = &bf60x_spi_master_info0, /* Passed to driver */
1800 },
1801};
1802
5e50175b 1803static struct bfin_spi3_master bf60x_spi_master_info1 = {
2cdd7008 1804 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
22a82628
SZ		 1805 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
1806};
1807
1808static struct platform_device bf60x_spi_master1 = {
5e50175b 1809 .name = "bfin-spi3",
22a82628
SZ		 1810 .id = 1, /* Bus number */
1811 .num_resources = ARRAY_SIZE(bfin_spi1_resource),
1812 .resource = bfin_spi1_resource,
1813 .dev = {
1814 .platform_data = &bf60x_spi_master_info1, /* Passed to driver */
1815 },
1816};
1817#endif /* spi master and devices */
1818
1819#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
cf93feb3
SZ		 1820static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
1821
22a82628
SZ		 1822static struct resource bfin_twi0_resource[] = {
1823 [0] = {
1824 .start = TWI0_CLKDIV,
1825 .end = TWI0_CLKDIV + 0xFF,
1826 .flags = IORESOURCE_MEM,
1827 },
1828 [1] = {
1829 .start = IRQ_TWI0,
1830 .end = IRQ_TWI0,
1831 .flags = IORESOURCE_IRQ,
1832 },
1833};
1834
1835static struct platform_device i2c_bfin_twi0_device = {
1836 .name = "i2c-bfin-twi",
1837 .id = 0,
1838 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1839 .resource = bfin_twi0_resource,
cf93feb3
SZ		 1840 .dev = {
1841 .platform_data = &bfin_twi0_pins,
1842 },
22a82628
SZ		 1843};
1844
cf93feb3
SZ		 1845static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
1846
22a82628
SZ		 1847static struct resource bfin_twi1_resource[] = {
1848 [0] = {
1849 .start = TWI1_CLKDIV,
1850 .end = TWI1_CLKDIV + 0xFF,
1851 .flags = IORESOURCE_MEM,
1852 },
1853 [1] = {
1854 .start = IRQ_TWI1,
1855 .end = IRQ_TWI1,
1856 .flags = IORESOURCE_IRQ,
1857 },
1858};
1859
1860static struct platform_device i2c_bfin_twi1_device = {
1861 .name = "i2c-bfin-twi",
1862 .id = 1,
1863 .num_resources = ARRAY_SIZE(bfin_twi1_resource),
1864 .resource = bfin_twi1_resource,
cf93feb3
SZ		 1865 .dev = {
1866 .platform_data = &bfin_twi1_pins,
1867 },
22a82628
SZ		 1868};
1869#endif
1870
1871static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
1872#if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
1873 {
1874 I2C_BOARD_INFO("adxl34x", 0x53),
1875 .irq = IRQ_PC5,
1876 .platform_data = (void *)&adxl34x_info,
1877 },
1878#endif
1879#if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
1880 {
1881 I2C_BOARD_INFO("adau1761", 0x38),
1882 .platform_data = (void *)&adau1761_info
1883 },
1884#endif
335dd559
SJ		 1885#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
1886 {
1887 I2C_BOARD_INFO("ssm2602", 0x1b),
1888 },
1889#endif
22a82628
SZ		 1890};
1891
1892static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
1893};
1894
1895static const unsigned int cclk_vlev_datasheet[] =
1896{
1897/*
1898 * Internal VLEV BF54XSBBC1533
1899 ****temporarily using these values until data sheet is updated
1900 */
1901 VRPAIR(VLEV_085, 150000000),
1902 VRPAIR(VLEV_090, 250000000),
1903 VRPAIR(VLEV_110, 276000000),
1904 VRPAIR(VLEV_115, 301000000),
1905 VRPAIR(VLEV_120, 525000000),
1906 VRPAIR(VLEV_125, 550000000),
1907 VRPAIR(VLEV_130, 600000000),
1908};
1909
1910static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
1911 .tuple_tab = cclk_vlev_datasheet,
1912 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
1913 .vr_settling_time = 25 /* us */,
1914};
1915
1916static struct platform_device bfin_dpmc = {
1917 .name = "bfin dpmc",
1918 .dev = {
1919 .platform_data = &bfin_dmpc_vreg_data,
1920 },
1921};
1922
1923static struct platform_device *ezkit_devices[] __initdata = {
1924
1925 &bfin_dpmc,
54e4ff4d
SZ		 1926#if defined(CONFIG_PINCTRL_ADI2)
1927 &bfin_pinctrl_device,
1928 &bfin_pint0_device,
1929 &bfin_pint1_device,
1930 &bfin_pint2_device,
1931 &bfin_pint3_device,
1932 &bfin_pint4_device,
1933 &bfin_pint5_device,
1934 &bfin_gpa_device,
1935 &bfin_gpb_device,
1936 &bfin_gpc_device,
1937 &bfin_gpd_device,
1938 &bfin_gpe_device,
1939 &bfin_gpf_device,
1940 &bfin_gpg_device,
1941#endif
22a82628
SZ		 1942
1943#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
1944 &rtc_device,
1945#endif
1946
1947#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
1948#ifdef CONFIG_SERIAL_BFIN_UART0
1949 &bfin_uart0_device,
1950#endif
1951#ifdef CONFIG_SERIAL_BFIN_UART1
1952 &bfin_uart1_device,
1953#endif
1954#endif
1955
1956#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
1957#ifdef CONFIG_BFIN_SIR0
1958 &bfin_sir0_device,
1959#endif
1960#ifdef CONFIG_BFIN_SIR1
1961 &bfin_sir1_device,
1962#endif
1963#endif
1964
1965#if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
1966 &bfin_eth_device,
1967#endif
1968
1969#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
1970 &musb_device,
1971#endif
1972
1973#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
1974 &bfin_isp1760_device,
1975#endif
1976
1977#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
1978#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1979 &bfin_sport0_uart_device,
1980#endif
1981#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1982 &bfin_sport1_uart_device,
1983#endif
1984#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1985 &bfin_sport2_uart_device,
1986#endif
1987#endif
1988
1989#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
1990 &bfin_can0_device,
1991#endif
1992
1993#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
1994 &bfin_nand_device,
1995#endif
1996
1997#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
1998 &bfin_sdh_device,
1999#endif
2000
5e50175b 2001#if IS_ENABLED(CONFIG_SPI_BFIN_V3)
22a82628
SZ		 2002 &bf60x_spi_master0,
2003 &bf60x_spi_master1,
2004#endif
2005
2006#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
2007 &bfin_rotary_device,
2008#endif
2009
2010#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
2011 &i2c_bfin_twi0_device,
2012#if !defined(CONFIG_BF542)
2013 &i2c_bfin_twi1_device,
2014#endif
2015#endif
2016
2017#if defined(CONFIG_BFIN_CRC)
2018 &bfin_crc0_device,
2019 &bfin_crc1_device,
2020#endif
c21e783b
SZ		 2021#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
2022 &bfin_crypto_crc_device,
2023#endif
22a82628
SZ		 2024
2025#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
2026 &bfin_device_gpiokeys,
2027#endif
2028
1c400939 2029#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
22a82628
SZ		 2030 &ezkit_flash_device,
2031#endif
2984b52b 2032#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
22a82628
SZ		 2033 &bfin_i2s_pcm,
2034#endif
2035#if defined(CONFIG_SND_BF6XX_SOC_I2S) || \
2036 defined(CONFIG_SND_BF6XX_SOC_I2S_MODULE)
2037 &bfin_i2s,
2038#endif
63f49dce
SJ		 2039#if defined(CONFIG_SND_BF5XX_SOC_AD1836) || \
2040 defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
2041 &bfin_ad1836_machine,
2042#endif
22a82628
SZ		 2043#if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) || \
2044 defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61_MODULE)
2045 &adau1761_device,
2046#endif
2047#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
2048 || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
2049 &bfin_capture_device,
2050#endif
e942d619
SJ		 2051#if defined(CONFIG_VIDEO_BLACKFIN_DISPLAY) \
2052 || defined(CONFIG_VIDEO_BLACKFIN_DISPLAY_MODULE)
2053 &bfin_display_device,
2054#endif
2055
22a82628
SZ		 2056};
2057
54e4ff4d
SZ		 2058/* Pin control settings */
2059static struct pinctrl_map __initdata bfin_pinmux_map[] = {
2060 /* per-device maps */
2061 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"),
2062 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"),
2063 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"),
2064 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
2065 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
2066 PIN_MAP_MUX_GROUP_DEFAULT("stmmaceth.0", "pinctrl-adi2.0", NULL, "eth0"),
2067 PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi3.0", "pinctrl-adi2.0", NULL, "spi0"),
2068 PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi3.1", "pinctrl-adi2.0", NULL, "spi1"),
2069 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
2070 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
2071 PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
2072 PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"),
2073 PIN_MAP_MUX_GROUP_DEFAULT("physmap-flash.0", "pinctrl-adi2.0", NULL, "smc0"),
2074 PIN_MAP_MUX_GROUP_DEFAULT("bf609_nl8048.2", "pinctrl-adi2.0", NULL, "ppi2_16b"),
2075 PIN_MAP_MUX_GROUP_DEFAULT("bfin_display.0", "pinctrl-adi2.0", NULL, "ppi0_16b"),
2076#if defined(CONFIG_VIDEO_MT9M114) || defined(CONFIG_VIDEO_MT9M114_MODULE)
2077 PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_8b"),
54e4ff4d
SZ		 2078#elif defined(CONFIG_VIDEO_VS6624) || defined(CONFIG_VIDEO_VS6624_MODULE)
2079 PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_16b"),
2080#else
2081 PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_24b"),
2082#endif
2083 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"),
2084 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"),
2085 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"),
2086 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"),
2087 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"),
2088 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"),
2089};
2090
22a82628
SZ		 2091static int __init ezkit_init(void)
2092{
2093 printk(KERN_INFO "%s(): registering device resources\n", __func__);
2094
54e4ff4d
SZ		 2095 /* Initialize pinmuxing */
2096 pinctrl_register_mappings(bfin_pinmux_map,
2097 ARRAY_SIZE(bfin_pinmux_map));
2098
22a82628
SZ		 2099 i2c_register_board_info(0, bfin_i2c_board_info0,
2100 ARRAY_SIZE(bfin_i2c_board_info0));
2101 i2c_register_board_info(1, bfin_i2c_board_info1,
2102 ARRAY_SIZE(bfin_i2c_board_info1));
2103
22a82628
SZ		 2104 platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
2105
2106 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
2107
2108 return 0;
2109}
2110
2111arch_initcall(ezkit_init);
2112
2113static struct platform_device *ezkit_early_devices[] __initdata = {
2114#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
2115#ifdef CONFIG_SERIAL_BFIN_UART0
2116 &bfin_uart0_device,
2117#endif
2118#ifdef CONFIG_SERIAL_BFIN_UART1
2119 &bfin_uart1_device,
2120#endif
2121#endif
22a82628
SZ		 2122};
2123
2124void __init native_machine_early_platform_add_devices(void)
2125{
2126 printk(KERN_INFO "register early platform devices\n");
2127 early_platform_add_devices(ezkit_early_devices,
2128 ARRAY_SIZE(ezkit_early_devices));
2129}
Ubuntu Jammy Linux kernel mirror