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Commit | Line | Data |
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e6c91b64 | 1 | /* |
96f1050d | 2 | * Blackfin core clock scaling |
e6c91b64 | 3 | * |
96f1050d | 4 | * Copyright 2008-2009 Analog Devices Inc. |
e6c91b64 | 5 | * |
96f1050d | 6 | * Licensed under the GPL-2 or later. |
e6c91b64 MH |
7 | */ |
8 | ||
9 | #include <linux/kernel.h> | |
10 | #include <linux/types.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/cpufreq.h> | |
13 | #include <linux/fs.h> | |
7998a878 | 14 | #include <linux/delay.h> |
e6c91b64 MH |
15 | #include <asm/blackfin.h> |
16 | #include <asm/time.h> | |
761ec44a | 17 | #include <asm/dpmc.h> |
e6c91b64 MH |
18 | |
19 | /* this is the table of CCLK frequencies, in Hz */ | |
20 | /* .index is the entry in the auxillary dpm_state_table[] */ | |
21 | static struct cpufreq_frequency_table bfin_freq_table[] = { | |
22 | { | |
23 | .frequency = CPUFREQ_TABLE_END, | |
24 | .index = 0, | |
25 | }, | |
26 | { | |
27 | .frequency = CPUFREQ_TABLE_END, | |
28 | .index = 1, | |
29 | }, | |
30 | { | |
31 | .frequency = CPUFREQ_TABLE_END, | |
32 | .index = 2, | |
33 | }, | |
34 | { | |
35 | .frequency = CPUFREQ_TABLE_END, | |
36 | .index = 0, | |
37 | }, | |
38 | }; | |
39 | ||
40 | static struct bfin_dpm_state { | |
41 | unsigned int csel; /* system clock divider */ | |
42 | unsigned int tscale; /* change the divider on the core timer interrupt */ | |
43 | } dpm_state_table[3]; | |
44 | ||
6c2b7072 | 45 | #if defined(CONFIG_CYCLES_CLOCKSOURCE) |
1bfb4b21 | 46 | /* |
6c2b7072 GY |
47 | * normalized to maximum frequncy offset for CYCLES, |
48 | * used in time-ts cycles clock source, but could be used | |
49 | * somewhere also. | |
1bfb4b21 VM |
50 | */ |
51 | unsigned long long __bfin_cycles_off; | |
52 | unsigned int __bfin_cycles_mod; | |
6c2b7072 | 53 | #endif |
1bfb4b21 | 54 | |
e6c91b64 | 55 | /**************************************************************************/ |
6c2b7072 GY |
56 | static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk) |
57 | { | |
e6c91b64 | 58 | |
6c2b7072 GY |
59 | unsigned long csel, min_cclk; |
60 | int index; | |
61 | ||
62 | /* Anomaly 273 seems to still exist on non-BF54x w/dcache turned on */ | |
63 | #if ANOMALY_05000273 || ANOMALY_05000274 || \ | |
64 | (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE)) | |
65 | min_cclk = sclk * 2; | |
66 | #else | |
67 | min_cclk = sclk; | |
68 | #endif | |
69 | csel = ((bfin_read_PLL_DIV() & CSEL) >> 4); | |
70 | ||
71 | for (index = 0; (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) { | |
72 | bfin_freq_table[index].frequency = cclk >> index; | |
73 | dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */ | |
74 | dpm_state_table[index].tscale = (TIME_SCALE / (1 << csel)) - 1; | |
75 | ||
76 | pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n", | |
77 | bfin_freq_table[index].frequency, | |
78 | dpm_state_table[index].csel, | |
79 | dpm_state_table[index].tscale); | |
80 | } | |
81 | return; | |
82 | } | |
83 | ||
84 | static void bfin_adjust_core_timer(void *info) | |
e6c91b64 | 85 | { |
6c2b7072 GY |
86 | unsigned int tscale; |
87 | unsigned int index = *(unsigned int *)info; | |
88 | ||
89 | /* we have to adjust the core timer, because it is using cclk */ | |
90 | tscale = dpm_state_table[index].tscale; | |
91 | bfin_write_TSCALE(tscale); | |
92 | return; | |
93 | } | |
e6c91b64 | 94 | |
6c2b7072 GY |
95 | static unsigned int bfin_getfreq_khz(unsigned int cpu) |
96 | { | |
97 | /* Both CoreA/B have the same core clock */ | |
a10101d5 | 98 | return get_cclk() / 1000; |
e6c91b64 MH |
99 | } |
100 | ||
6c2b7072 | 101 | static int bfin_target(struct cpufreq_policy *poli, |
e6c91b64 MH |
102 | unsigned int target_freq, unsigned int relation) |
103 | { | |
6c2b7072 | 104 | unsigned int index, plldiv, cpu; |
e6c91b64 MH |
105 | unsigned long flags, cclk_hz; |
106 | struct cpufreq_freqs freqs; | |
7998a878 GY |
107 | static unsigned long lpj_ref; |
108 | static unsigned int lpj_ref_freq; | |
109 | ||
6c2b7072 | 110 | #if defined(CONFIG_CYCLES_CLOCKSOURCE) |
1bfb4b21 | 111 | cycles_t cycles; |
6c2b7072 | 112 | #endif |
e6c91b64 | 113 | |
6c2b7072 GY |
114 | for_each_online_cpu(cpu) { |
115 | struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); | |
116 | ||
117 | if (!policy) | |
118 | continue; | |
119 | ||
120 | if (cpufreq_frequency_table_target(policy, bfin_freq_table, | |
121 | target_freq, relation, &index)) | |
122 | return -EINVAL; | |
123 | ||
124 | cclk_hz = bfin_freq_table[index].frequency; | |
125 | ||
126 | freqs.old = bfin_getfreq_khz(0); | |
127 | freqs.new = cclk_hz; | |
128 | freqs.cpu = cpu; | |
129 | ||
130 | pr_debug("cpufreq: changing cclk to %lu; target = %u, oldfreq = %u\n", | |
131 | cclk_hz, target_freq, freqs.old); | |
132 | ||
133 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | |
134 | if (cpu == CPUFREQ_CPU) { | |
3b139cdb | 135 | flags = hard_local_irq_save(); |
6c2b7072 GY |
136 | plldiv = (bfin_read_PLL_DIV() & SSEL) | |
137 | dpm_state_table[index].csel; | |
138 | bfin_write_PLL_DIV(plldiv); | |
139 | on_each_cpu(bfin_adjust_core_timer, &index, 1); | |
140 | #if defined(CONFIG_CYCLES_CLOCKSOURCE) | |
141 | cycles = get_cycles(); | |
142 | SSYNC(); | |
143 | cycles += 10; /* ~10 cycles we lose after get_cycles() */ | |
144 | __bfin_cycles_off += | |
145 | (cycles << __bfin_cycles_mod) - (cycles << index); | |
146 | __bfin_cycles_mod = index; | |
147 | #endif | |
7998a878 GY |
148 | if (!lpj_ref_freq) { |
149 | lpj_ref = loops_per_jiffy; | |
150 | lpj_ref_freq = freqs.old; | |
151 | } | |
152 | if (freqs.new != freqs.old) { | |
153 | loops_per_jiffy = cpufreq_scale(lpj_ref, | |
154 | lpj_ref_freq, freqs.new); | |
155 | } | |
3b139cdb | 156 | hard_local_irq_restore(flags); |
6c2b7072 GY |
157 | } |
158 | /* TODO: just test case for cycles clock source, remove later */ | |
159 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | |
160 | } | |
e6c91b64 | 161 | |
6c2b7072 | 162 | pr_debug("cpufreq: done\n"); |
e6c91b64 MH |
163 | return 0; |
164 | } | |
165 | ||
166 | static int bfin_verify_speed(struct cpufreq_policy *policy) | |
167 | { | |
168 | return cpufreq_frequency_table_verify(policy, bfin_freq_table); | |
169 | } | |
170 | ||
171 | static int __init __bfin_cpu_init(struct cpufreq_policy *policy) | |
172 | { | |
173 | ||
6c2b7072 | 174 | unsigned long cclk, sclk; |
e6c91b64 | 175 | |
a10101d5 MH |
176 | cclk = get_cclk() / 1000; |
177 | sclk = get_sclk() / 1000; | |
e6c91b64 | 178 | |
6c2b7072 GY |
179 | if (policy->cpu == CPUFREQ_CPU) |
180 | bfin_init_tables(cclk, sclk); | |
e6c91b64 | 181 | |
d887a1ce MH |
182 | policy->cpuinfo.transition_latency = 50000; /* 50us assumed */ |
183 | ||
e6c91b64 MH |
184 | policy->cur = cclk; |
185 | cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu); | |
186 | return cpufreq_frequency_table_cpuinfo(policy, bfin_freq_table); | |
187 | } | |
188 | ||
189 | static struct freq_attr *bfin_freq_attr[] = { | |
190 | &cpufreq_freq_attr_scaling_available_freqs, | |
191 | NULL, | |
192 | }; | |
193 | ||
194 | static struct cpufreq_driver bfin_driver = { | |
195 | .verify = bfin_verify_speed, | |
196 | .target = bfin_target, | |
a10101d5 | 197 | .get = bfin_getfreq_khz, |
e6c91b64 MH |
198 | .init = __bfin_cpu_init, |
199 | .name = "bfin cpufreq", | |
200 | .owner = THIS_MODULE, | |
201 | .attr = bfin_freq_attr, | |
202 | }; | |
203 | ||
204 | static int __init bfin_cpu_init(void) | |
205 | { | |
206 | return cpufreq_register_driver(&bfin_driver); | |
207 | } | |
208 | ||
209 | static void __exit bfin_cpu_exit(void) | |
210 | { | |
211 | cpufreq_unregister_driver(&bfin_driver); | |
212 | } | |
213 | ||
214 | MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>"); | |
215 | MODULE_DESCRIPTION("cpufreq driver for Blackfin"); | |
216 | MODULE_LICENSE("GPL"); | |
217 | ||
218 | module_init(bfin_cpu_init); | |
219 | module_exit(bfin_cpu_exit); |