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Commit | Line | Data |
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e6c91b64 | 1 | /* |
96f1050d | 2 | * Blackfin core clock scaling |
e6c91b64 | 3 | * |
8944b5a2 | 4 | * Copyright 2008-2011 Analog Devices Inc. |
e6c91b64 | 5 | * |
96f1050d | 6 | * Licensed under the GPL-2 or later. |
e6c91b64 MH |
7 | */ |
8 | ||
9 | #include <linux/kernel.h> | |
6a550b99 | 10 | #include <linux/module.h> |
e6c91b64 MH |
11 | #include <linux/types.h> |
12 | #include <linux/init.h> | |
96900315 | 13 | #include <linux/clk.h> |
e6c91b64 MH |
14 | #include <linux/cpufreq.h> |
15 | #include <linux/fs.h> | |
7998a878 | 16 | #include <linux/delay.h> |
e6c91b64 MH |
17 | #include <asm/blackfin.h> |
18 | #include <asm/time.h> | |
761ec44a | 19 | #include <asm/dpmc.h> |
e6c91b64 | 20 | |
96900315 | 21 | |
e6c91b64 | 22 | /* this is the table of CCLK frequencies, in Hz */ |
8944b5a2 | 23 | /* .index is the entry in the auxiliary dpm_state_table[] */ |
e6c91b64 MH |
24 | static struct cpufreq_frequency_table bfin_freq_table[] = { |
25 | { | |
26 | .frequency = CPUFREQ_TABLE_END, | |
27 | .index = 0, | |
28 | }, | |
29 | { | |
30 | .frequency = CPUFREQ_TABLE_END, | |
31 | .index = 1, | |
32 | }, | |
33 | { | |
34 | .frequency = CPUFREQ_TABLE_END, | |
35 | .index = 2, | |
36 | }, | |
37 | { | |
38 | .frequency = CPUFREQ_TABLE_END, | |
39 | .index = 0, | |
40 | }, | |
41 | }; | |
42 | ||
43 | static struct bfin_dpm_state { | |
44 | unsigned int csel; /* system clock divider */ | |
45 | unsigned int tscale; /* change the divider on the core timer interrupt */ | |
46 | } dpm_state_table[3]; | |
47 | ||
6c2b7072 | 48 | #if defined(CONFIG_CYCLES_CLOCKSOURCE) |
1bfb4b21 | 49 | /* |
8944b5a2 | 50 | * normalized to maximum frequency offset for CYCLES, |
6c2b7072 GY |
51 | * used in time-ts cycles clock source, but could be used |
52 | * somewhere also. | |
1bfb4b21 VM |
53 | */ |
54 | unsigned long long __bfin_cycles_off; | |
55 | unsigned int __bfin_cycles_mod; | |
6c2b7072 | 56 | #endif |
1bfb4b21 | 57 | |
e6c91b64 | 58 | /**************************************************************************/ |
6c2b7072 GY |
59 | static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk) |
60 | { | |
e6c91b64 | 61 | |
6c2b7072 GY |
62 | unsigned long csel, min_cclk; |
63 | int index; | |
64 | ||
65 | /* Anomaly 273 seems to still exist on non-BF54x w/dcache turned on */ | |
66 | #if ANOMALY_05000273 || ANOMALY_05000274 || \ | |
67 | (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE)) | |
68 | min_cclk = sclk * 2; | |
69 | #else | |
70 | min_cclk = sclk; | |
71 | #endif | |
96900315 SM |
72 | |
73 | #ifndef CONFIG_BF60x | |
6c2b7072 | 74 | csel = ((bfin_read_PLL_DIV() & CSEL) >> 4); |
96900315 SM |
75 | #else |
76 | csel = bfin_read32(CGU0_DIV) & 0x1F; | |
77 | #endif | |
6c2b7072 GY |
78 | |
79 | for (index = 0; (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) { | |
80 | bfin_freq_table[index].frequency = cclk >> index; | |
96900315 | 81 | #ifndef CONFIG_BF60x |
6c2b7072 GY |
82 | dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */ |
83 | dpm_state_table[index].tscale = (TIME_SCALE / (1 << csel)) - 1; | |
96900315 SM |
84 | #else |
85 | dpm_state_table[index].csel = csel; | |
86 | dpm_state_table[index].tscale = TIME_SCALE >> index; | |
87 | #endif | |
6c2b7072 GY |
88 | |
89 | pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n", | |
90 | bfin_freq_table[index].frequency, | |
91 | dpm_state_table[index].csel, | |
92 | dpm_state_table[index].tscale); | |
93 | } | |
94 | return; | |
95 | } | |
96 | ||
97 | static void bfin_adjust_core_timer(void *info) | |
e6c91b64 | 98 | { |
6c2b7072 GY |
99 | unsigned int tscale; |
100 | unsigned int index = *(unsigned int *)info; | |
101 | ||
102 | /* we have to adjust the core timer, because it is using cclk */ | |
103 | tscale = dpm_state_table[index].tscale; | |
104 | bfin_write_TSCALE(tscale); | |
105 | return; | |
106 | } | |
e6c91b64 | 107 | |
6c2b7072 GY |
108 | static unsigned int bfin_getfreq_khz(unsigned int cpu) |
109 | { | |
110 | /* Both CoreA/B have the same core clock */ | |
a10101d5 | 111 | return get_cclk() / 1000; |
e6c91b64 MH |
112 | } |
113 | ||
96900315 SM |
114 | unsigned long cpu_set_cclk(int cpu, unsigned long new) |
115 | { | |
116 | struct clk *clk; | |
117 | int ret; | |
118 | ||
119 | clk = clk_get(NULL, "CCLK"); | |
120 | if (IS_ERR(clk)) | |
121 | return -ENODEV; | |
122 | ||
123 | ret = clk_set_rate(clk, new); | |
124 | clk_put(clk); | |
125 | return ret; | |
126 | } | |
127 | ||
6c2b7072 | 128 | static int bfin_target(struct cpufreq_policy *poli, |
e6c91b64 MH |
129 | unsigned int target_freq, unsigned int relation) |
130 | { | |
6c2b7072 | 131 | unsigned int index, plldiv, cpu; |
e6c91b64 MH |
132 | unsigned long flags, cclk_hz; |
133 | struct cpufreq_freqs freqs; | |
7998a878 GY |
134 | static unsigned long lpj_ref; |
135 | static unsigned int lpj_ref_freq; | |
96900315 | 136 | int ret = 0; |
7998a878 | 137 | |
6c2b7072 | 138 | #if defined(CONFIG_CYCLES_CLOCKSOURCE) |
1bfb4b21 | 139 | cycles_t cycles; |
6c2b7072 | 140 | #endif |
e6c91b64 | 141 | |
6c2b7072 GY |
142 | for_each_online_cpu(cpu) { |
143 | struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); | |
144 | ||
145 | if (!policy) | |
146 | continue; | |
147 | ||
148 | if (cpufreq_frequency_table_target(policy, bfin_freq_table, | |
149 | target_freq, relation, &index)) | |
150 | return -EINVAL; | |
151 | ||
152 | cclk_hz = bfin_freq_table[index].frequency; | |
153 | ||
154 | freqs.old = bfin_getfreq_khz(0); | |
155 | freqs.new = cclk_hz; | |
156 | freqs.cpu = cpu; | |
157 | ||
158 | pr_debug("cpufreq: changing cclk to %lu; target = %u, oldfreq = %u\n", | |
159 | cclk_hz, target_freq, freqs.old); | |
160 | ||
161 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | |
162 | if (cpu == CPUFREQ_CPU) { | |
3b139cdb | 163 | flags = hard_local_irq_save(); |
96900315 | 164 | #ifndef CONFIG_BF60x |
6c2b7072 GY |
165 | plldiv = (bfin_read_PLL_DIV() & SSEL) | |
166 | dpm_state_table[index].csel; | |
167 | bfin_write_PLL_DIV(plldiv); | |
96900315 SM |
168 | #else |
169 | ret = cpu_set_cclk(cpu, freqs.new * 1000); | |
170 | if (ret != 0) { | |
171 | pr_debug("cpufreq set freq failed %d\n", ret); | |
172 | break; | |
173 | } | |
174 | #endif | |
6c2b7072 GY |
175 | on_each_cpu(bfin_adjust_core_timer, &index, 1); |
176 | #if defined(CONFIG_CYCLES_CLOCKSOURCE) | |
177 | cycles = get_cycles(); | |
178 | SSYNC(); | |
179 | cycles += 10; /* ~10 cycles we lose after get_cycles() */ | |
180 | __bfin_cycles_off += | |
181 | (cycles << __bfin_cycles_mod) - (cycles << index); | |
182 | __bfin_cycles_mod = index; | |
183 | #endif | |
7998a878 GY |
184 | if (!lpj_ref_freq) { |
185 | lpj_ref = loops_per_jiffy; | |
186 | lpj_ref_freq = freqs.old; | |
187 | } | |
188 | if (freqs.new != freqs.old) { | |
189 | loops_per_jiffy = cpufreq_scale(lpj_ref, | |
190 | lpj_ref_freq, freqs.new); | |
191 | } | |
3b139cdb | 192 | hard_local_irq_restore(flags); |
6c2b7072 GY |
193 | } |
194 | /* TODO: just test case for cycles clock source, remove later */ | |
195 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | |
196 | } | |
e6c91b64 | 197 | |
6c2b7072 | 198 | pr_debug("cpufreq: done\n"); |
96900315 | 199 | return ret; |
e6c91b64 MH |
200 | } |
201 | ||
202 | static int bfin_verify_speed(struct cpufreq_policy *policy) | |
203 | { | |
204 | return cpufreq_frequency_table_verify(policy, bfin_freq_table); | |
205 | } | |
206 | ||
96900315 | 207 | static int __bfin_cpu_init(struct cpufreq_policy *policy) |
e6c91b64 MH |
208 | { |
209 | ||
6c2b7072 | 210 | unsigned long cclk, sclk; |
e6c91b64 | 211 | |
a10101d5 MH |
212 | cclk = get_cclk() / 1000; |
213 | sclk = get_sclk() / 1000; | |
e6c91b64 | 214 | |
6c2b7072 GY |
215 | if (policy->cpu == CPUFREQ_CPU) |
216 | bfin_init_tables(cclk, sclk); | |
e6c91b64 | 217 | |
d887a1ce MH |
218 | policy->cpuinfo.transition_latency = 50000; /* 50us assumed */ |
219 | ||
e6c91b64 MH |
220 | policy->cur = cclk; |
221 | cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu); | |
222 | return cpufreq_frequency_table_cpuinfo(policy, bfin_freq_table); | |
223 | } | |
224 | ||
225 | static struct freq_attr *bfin_freq_attr[] = { | |
226 | &cpufreq_freq_attr_scaling_available_freqs, | |
227 | NULL, | |
228 | }; | |
229 | ||
230 | static struct cpufreq_driver bfin_driver = { | |
231 | .verify = bfin_verify_speed, | |
232 | .target = bfin_target, | |
a10101d5 | 233 | .get = bfin_getfreq_khz, |
e6c91b64 MH |
234 | .init = __bfin_cpu_init, |
235 | .name = "bfin cpufreq", | |
236 | .owner = THIS_MODULE, | |
237 | .attr = bfin_freq_attr, | |
238 | }; | |
239 | ||
240 | static int __init bfin_cpu_init(void) | |
241 | { | |
242 | return cpufreq_register_driver(&bfin_driver); | |
243 | } | |
244 | ||
245 | static void __exit bfin_cpu_exit(void) | |
246 | { | |
247 | cpufreq_unregister_driver(&bfin_driver); | |
248 | } | |
249 | ||
250 | MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>"); | |
251 | MODULE_DESCRIPTION("cpufreq driver for Blackfin"); | |
252 | MODULE_LICENSE("GPL"); | |
253 | ||
254 | module_init(bfin_cpu_init); | |
255 | module_exit(bfin_cpu_exit); |