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1394f032 | 1 | /* |
cfefe3c6 | 2 | * File: arch/blackfin/mach-common/ints-priority.c |
1394f032 | 3 | * |
d2d50aa9 | 4 | * Description: Set up the interrupt priorities |
1394f032 BW |
5 | * |
6 | * Modified: | |
7 | * 1996 Roman Zippel | |
8 | * 1999 D. Jeff Dionne <jeff@uclinux.org> | |
9 | * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca> | |
10 | * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca> | |
11 | * 2003 Metrowerks/Motorola | |
12 | * 2003 Bas Vermeulen <bas@buyways.nl> | |
cfefe3c6 | 13 | * Copyright 2004-2008 Analog Devices Inc. |
1394f032 BW |
14 | * |
15 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or modify | |
18 | * it under the terms of the GNU General Public License as published by | |
19 | * the Free Software Foundation; either version 2 of the License, or | |
20 | * (at your option) any later version. | |
21 | * | |
22 | * This program is distributed in the hope that it will be useful, | |
23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
25 | * GNU General Public License for more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License | |
28 | * along with this program; if not, see the file COPYING, or write | |
29 | * to the Free Software Foundation, Inc., | |
30 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
31 | */ | |
32 | ||
33 | #include <linux/module.h> | |
34 | #include <linux/kernel_stat.h> | |
35 | #include <linux/seq_file.h> | |
36 | #include <linux/irq.h> | |
6a01f230 YL |
37 | #ifdef CONFIG_IPIPE |
38 | #include <linux/ipipe.h> | |
39 | #endif | |
1394f032 BW |
40 | #ifdef CONFIG_KGDB |
41 | #include <linux/kgdb.h> | |
42 | #endif | |
43 | #include <asm/traps.h> | |
44 | #include <asm/blackfin.h> | |
45 | #include <asm/gpio.h> | |
46 | #include <asm/irq_handler.h> | |
47 | ||
7beb7439 MF |
48 | #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) |
49 | ||
1394f032 BW |
50 | #ifdef BF537_FAMILY |
51 | # define BF537_GENERIC_ERROR_INT_DEMUX | |
52 | #else | |
53 | # undef BF537_GENERIC_ERROR_INT_DEMUX | |
54 | #endif | |
55 | ||
56 | /* | |
57 | * NOTES: | |
58 | * - we have separated the physical Hardware interrupt from the | |
59 | * levels that the LINUX kernel sees (see the description in irq.h) | |
60 | * - | |
61 | */ | |
62 | ||
6b3087c6 | 63 | #ifndef CONFIG_SMP |
a99bbccd MF |
64 | /* Initialize this to an actual value to force it into the .data |
65 | * section so that we know it is properly initialized at entry into | |
66 | * the kernel but before bss is initialized to zero (which is where | |
67 | * it would live otherwise). The 0x1f magic represents the IRQs we | |
68 | * cannot actually mask out in hardware. | |
69 | */ | |
40059784 MF |
70 | unsigned long bfin_irq_flags = 0x1f; |
71 | EXPORT_SYMBOL(bfin_irq_flags); | |
6b3087c6 | 72 | #endif |
1394f032 BW |
73 | |
74 | /* The number of spurious interrupts */ | |
75 | atomic_t num_spurious; | |
76 | ||
cfefe3c6 MH |
77 | #ifdef CONFIG_PM |
78 | unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */ | |
4a88d0ce | 79 | unsigned vr_wakeup; |
cfefe3c6 MH |
80 | #endif |
81 | ||
1394f032 | 82 | struct ivgx { |
464abc5d | 83 | /* irq number for request_irq, available in mach-bf5xx/irq.h */ |
24a07a12 | 84 | unsigned int irqno; |
1394f032 | 85 | /* corresponding bit in the SIC_ISR register */ |
24a07a12 | 86 | unsigned int isrflag; |
1394f032 BW |
87 | } ivg_table[NR_PERI_INTS]; |
88 | ||
89 | struct ivg_slice { | |
90 | /* position of first irq in ivg_table for given ivg */ | |
91 | struct ivgx *ifirst; | |
92 | struct ivgx *istop; | |
93 | } ivg7_13[IVG13 - IVG7 + 1]; | |
94 | ||
1394f032 BW |
95 | |
96 | /* | |
97 | * Search SIC_IAR and fill tables with the irqvalues | |
98 | * and their positions in the SIC_ISR register. | |
99 | */ | |
100 | static void __init search_IAR(void) | |
101 | { | |
102 | unsigned ivg, irq_pos = 0; | |
103 | for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) { | |
104 | int irqn; | |
105 | ||
34e0fc89 | 106 | ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos]; |
1394f032 BW |
107 | |
108 | for (irqn = 0; irqn < NR_PERI_INTS; irqn++) { | |
109 | int iar_shift = (irqn & 7) * 4; | |
2c4f829b | 110 | if (ivg == (0xf & |
2f6f4bcd BW |
111 | #if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \ |
112 | || defined(CONFIG_BF539) || defined(CONFIG_BF51x) | |
34e0fc89 | 113 | bfin_read32((unsigned long *)SIC_IAR0 + |
dc26aec2 MH |
114 | ((irqn % 32) >> 3) + ((irqn / 32) * |
115 | ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) { | |
59003145 MH |
116 | #else |
117 | bfin_read32((unsigned long *)SIC_IAR0 + | |
dc26aec2 | 118 | (irqn >> 3)) >> iar_shift)) { |
59003145 | 119 | #endif |
1394f032 | 120 | ivg_table[irq_pos].irqno = IVG7 + irqn; |
24a07a12 | 121 | ivg_table[irq_pos].isrflag = 1 << (irqn % 32); |
1394f032 BW |
122 | ivg7_13[ivg].istop++; |
123 | irq_pos++; | |
124 | } | |
125 | } | |
126 | } | |
127 | } | |
128 | ||
129 | /* | |
464abc5d | 130 | * This is for core internal IRQs |
1394f032 BW |
131 | */ |
132 | ||
464abc5d | 133 | static void bfin_ack_noop(unsigned int irq) |
1394f032 BW |
134 | { |
135 | /* Dummy function. */ | |
136 | } | |
137 | ||
138 | static void bfin_core_mask_irq(unsigned int irq) | |
139 | { | |
40059784 | 140 | bfin_irq_flags &= ~(1 << irq); |
6a01f230 YL |
141 | if (!irqs_disabled_hw()) |
142 | local_irq_enable_hw(); | |
1394f032 BW |
143 | } |
144 | ||
145 | static void bfin_core_unmask_irq(unsigned int irq) | |
146 | { | |
40059784 | 147 | bfin_irq_flags |= 1 << irq; |
1394f032 BW |
148 | /* |
149 | * If interrupts are enabled, IMASK must contain the same value | |
40059784 | 150 | * as bfin_irq_flags. Make sure that invariant holds. If interrupts |
1394f032 BW |
151 | * are currently disabled we need not do anything; one of the |
152 | * callers will take care of setting IMASK to the proper value | |
153 | * when reenabling interrupts. | |
40059784 | 154 | * local_irq_enable just does "STI bfin_irq_flags", so it's exactly |
1394f032 BW |
155 | * what we need. |
156 | */ | |
6a01f230 YL |
157 | if (!irqs_disabled_hw()) |
158 | local_irq_enable_hw(); | |
1394f032 BW |
159 | return; |
160 | } | |
161 | ||
162 | static void bfin_internal_mask_irq(unsigned int irq) | |
163 | { | |
59003145 | 164 | #ifdef CONFIG_BF53x |
1394f032 | 165 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & |
464abc5d | 166 | ~(1 << SIC_SYSIRQ(irq))); |
24a07a12 RH |
167 | #else |
168 | unsigned mask_bank, mask_bit; | |
464abc5d MH |
169 | mask_bank = SIC_SYSIRQ(irq) / 32; |
170 | mask_bit = SIC_SYSIRQ(irq) % 32; | |
c04d66bb BW |
171 | bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & |
172 | ~(1 << mask_bit)); | |
6b3087c6 GY |
173 | #ifdef CONFIG_SMP |
174 | bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) & | |
175 | ~(1 << mask_bit)); | |
176 | #endif | |
24a07a12 | 177 | #endif |
1394f032 BW |
178 | } |
179 | ||
180 | static void bfin_internal_unmask_irq(unsigned int irq) | |
181 | { | |
59003145 | 182 | #ifdef CONFIG_BF53x |
1394f032 | 183 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | |
464abc5d | 184 | (1 << SIC_SYSIRQ(irq))); |
24a07a12 RH |
185 | #else |
186 | unsigned mask_bank, mask_bit; | |
464abc5d MH |
187 | mask_bank = SIC_SYSIRQ(irq) / 32; |
188 | mask_bit = SIC_SYSIRQ(irq) % 32; | |
c04d66bb BW |
189 | bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | |
190 | (1 << mask_bit)); | |
6b3087c6 GY |
191 | #ifdef CONFIG_SMP |
192 | bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) | | |
193 | (1 << mask_bit)); | |
194 | #endif | |
24a07a12 | 195 | #endif |
1394f032 BW |
196 | } |
197 | ||
cfefe3c6 MH |
198 | #ifdef CONFIG_PM |
199 | int bfin_internal_set_wake(unsigned int irq, unsigned int state) | |
200 | { | |
8d022374 | 201 | u32 bank, bit, wakeup = 0; |
cfefe3c6 | 202 | unsigned long flags; |
464abc5d MH |
203 | bank = SIC_SYSIRQ(irq) / 32; |
204 | bit = SIC_SYSIRQ(irq) % 32; | |
cfefe3c6 | 205 | |
4a88d0ce MH |
206 | switch (irq) { |
207 | #ifdef IRQ_RTC | |
208 | case IRQ_RTC: | |
209 | wakeup |= WAKE; | |
210 | break; | |
211 | #endif | |
212 | #ifdef IRQ_CAN0_RX | |
213 | case IRQ_CAN0_RX: | |
214 | wakeup |= CANWE; | |
215 | break; | |
216 | #endif | |
217 | #ifdef IRQ_CAN1_RX | |
218 | case IRQ_CAN1_RX: | |
219 | wakeup |= CANWE; | |
220 | break; | |
221 | #endif | |
222 | #ifdef IRQ_USB_INT0 | |
223 | case IRQ_USB_INT0: | |
224 | wakeup |= USBWE; | |
225 | break; | |
226 | #endif | |
227 | #ifdef IRQ_KEY | |
228 | case IRQ_KEY: | |
229 | wakeup |= KPADWE; | |
230 | break; | |
231 | #endif | |
d310fb4b | 232 | #ifdef CONFIG_BF54x |
4a88d0ce MH |
233 | case IRQ_CNT: |
234 | wakeup |= ROTWE; | |
235 | break; | |
236 | #endif | |
237 | default: | |
238 | break; | |
239 | } | |
240 | ||
6a01f230 | 241 | local_irq_save_hw(flags); |
cfefe3c6 | 242 | |
4a88d0ce | 243 | if (state) { |
cfefe3c6 | 244 | bfin_sic_iwr[bank] |= (1 << bit); |
4a88d0ce MH |
245 | vr_wakeup |= wakeup; |
246 | ||
247 | } else { | |
cfefe3c6 | 248 | bfin_sic_iwr[bank] &= ~(1 << bit); |
4a88d0ce MH |
249 | vr_wakeup &= ~wakeup; |
250 | } | |
cfefe3c6 | 251 | |
6a01f230 | 252 | local_irq_restore_hw(flags); |
cfefe3c6 MH |
253 | |
254 | return 0; | |
255 | } | |
256 | #endif | |
257 | ||
1394f032 | 258 | static struct irq_chip bfin_core_irqchip = { |
763e63c6 | 259 | .name = "CORE", |
464abc5d | 260 | .ack = bfin_ack_noop, |
1394f032 BW |
261 | .mask = bfin_core_mask_irq, |
262 | .unmask = bfin_core_unmask_irq, | |
263 | }; | |
264 | ||
265 | static struct irq_chip bfin_internal_irqchip = { | |
763e63c6 | 266 | .name = "INTN", |
464abc5d | 267 | .ack = bfin_ack_noop, |
1394f032 BW |
268 | .mask = bfin_internal_mask_irq, |
269 | .unmask = bfin_internal_unmask_irq, | |
ce3b7bb6 MH |
270 | .mask_ack = bfin_internal_mask_irq, |
271 | .disable = bfin_internal_mask_irq, | |
272 | .enable = bfin_internal_unmask_irq, | |
cfefe3c6 MH |
273 | #ifdef CONFIG_PM |
274 | .set_wake = bfin_internal_set_wake, | |
275 | #endif | |
1394f032 BW |
276 | }; |
277 | ||
6a01f230 YL |
278 | static void bfin_handle_irq(unsigned irq) |
279 | { | |
280 | #ifdef CONFIG_IPIPE | |
281 | struct pt_regs regs; /* Contents not used. */ | |
282 | ipipe_trace_irq_entry(irq); | |
283 | __ipipe_handle_irq(irq, ®s); | |
284 | ipipe_trace_irq_exit(irq); | |
285 | #else /* !CONFIG_IPIPE */ | |
286 | struct irq_desc *desc = irq_desc + irq; | |
287 | desc->handle_irq(irq, desc); | |
288 | #endif /* !CONFIG_IPIPE */ | |
289 | } | |
290 | ||
1394f032 BW |
291 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX |
292 | static int error_int_mask; | |
293 | ||
1394f032 BW |
294 | static void bfin_generic_error_mask_irq(unsigned int irq) |
295 | { | |
296 | error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR)); | |
297 | ||
464abc5d MH |
298 | if (!error_int_mask) |
299 | bfin_internal_mask_irq(IRQ_GENERIC_ERROR); | |
1394f032 BW |
300 | } |
301 | ||
302 | static void bfin_generic_error_unmask_irq(unsigned int irq) | |
303 | { | |
464abc5d | 304 | bfin_internal_unmask_irq(IRQ_GENERIC_ERROR); |
1394f032 BW |
305 | error_int_mask |= 1L << (irq - IRQ_PPI_ERROR); |
306 | } | |
307 | ||
308 | static struct irq_chip bfin_generic_error_irqchip = { | |
763e63c6 | 309 | .name = "ERROR", |
464abc5d MH |
310 | .ack = bfin_ack_noop, |
311 | .mask_ack = bfin_generic_error_mask_irq, | |
1394f032 BW |
312 | .mask = bfin_generic_error_mask_irq, |
313 | .unmask = bfin_generic_error_unmask_irq, | |
314 | }; | |
315 | ||
316 | static void bfin_demux_error_irq(unsigned int int_err_irq, | |
2c4f829b | 317 | struct irq_desc *inta_desc) |
1394f032 BW |
318 | { |
319 | int irq = 0; | |
320 | ||
1394f032 BW |
321 | #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) |
322 | if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK) | |
323 | irq = IRQ_MAC_ERROR; | |
324 | else | |
325 | #endif | |
326 | if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK) | |
327 | irq = IRQ_SPORT0_ERROR; | |
328 | else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK) | |
329 | irq = IRQ_SPORT1_ERROR; | |
330 | else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK) | |
331 | irq = IRQ_PPI_ERROR; | |
332 | else if (bfin_read_CAN_GIF() & CAN_ERR_MASK) | |
333 | irq = IRQ_CAN_ERROR; | |
334 | else if (bfin_read_SPI_STAT() & SPI_ERR_MASK) | |
335 | irq = IRQ_SPI_ERROR; | |
336 | else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) && | |
337 | (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0)) | |
338 | irq = IRQ_UART0_ERROR; | |
339 | else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) && | |
340 | (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0)) | |
341 | irq = IRQ_UART1_ERROR; | |
342 | ||
343 | if (irq) { | |
6a01f230 YL |
344 | if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) |
345 | bfin_handle_irq(irq); | |
346 | else { | |
1394f032 BW |
347 | |
348 | switch (irq) { | |
349 | case IRQ_PPI_ERROR: | |
350 | bfin_write_PPI_STATUS(PPI_ERR_MASK); | |
351 | break; | |
352 | #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) | |
353 | case IRQ_MAC_ERROR: | |
354 | bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK); | |
355 | break; | |
356 | #endif | |
357 | case IRQ_SPORT0_ERROR: | |
358 | bfin_write_SPORT0_STAT(SPORT_ERR_MASK); | |
359 | break; | |
360 | ||
361 | case IRQ_SPORT1_ERROR: | |
362 | bfin_write_SPORT1_STAT(SPORT_ERR_MASK); | |
363 | break; | |
364 | ||
365 | case IRQ_CAN_ERROR: | |
366 | bfin_write_CAN_GIS(CAN_ERR_MASK); | |
367 | break; | |
368 | ||
369 | case IRQ_SPI_ERROR: | |
370 | bfin_write_SPI_STAT(SPI_ERR_MASK); | |
371 | break; | |
372 | ||
373 | default: | |
374 | break; | |
375 | } | |
376 | ||
377 | pr_debug("IRQ %d:" | |
34e0fc89 MH |
378 | " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n", |
379 | irq); | |
1394f032 BW |
380 | } |
381 | } else | |
382 | printk(KERN_ERR | |
383 | "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR" | |
384 | " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n", | |
b85d858b | 385 | __func__, __FILE__, __LINE__); |
1394f032 | 386 | |
1394f032 BW |
387 | } |
388 | #endif /* BF537_GENERIC_ERROR_INT_DEMUX */ | |
389 | ||
bfd15117 GY |
390 | static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle) |
391 | { | |
6a01f230 YL |
392 | #ifdef CONFIG_IPIPE |
393 | _set_irq_handler(irq, handle_edge_irq); | |
394 | #else | |
bfd15117 GY |
395 | struct irq_desc *desc = irq_desc + irq; |
396 | /* May not call generic set_irq_handler() due to spinlock | |
397 | recursion. */ | |
398 | desc->handle_irq = handle; | |
6a01f230 | 399 | #endif |
bfd15117 GY |
400 | } |
401 | ||
8d022374 | 402 | static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS); |
affee2b2 | 403 | extern void bfin_gpio_irq_prepare(unsigned gpio); |
6fce6a8d | 404 | |
8d022374 MH |
405 | #if !defined(CONFIG_BF54x) |
406 | ||
1394f032 BW |
407 | static void bfin_gpio_ack_irq(unsigned int irq) |
408 | { | |
8d022374 MH |
409 | /* AFAIK ack_irq in case mask_ack is provided |
410 | * get's only called for edge sense irqs | |
411 | */ | |
412 | set_gpio_data(irq_to_gpio(irq), 0); | |
1394f032 BW |
413 | } |
414 | ||
415 | static void bfin_gpio_mask_ack_irq(unsigned int irq) | |
416 | { | |
8d022374 MH |
417 | struct irq_desc *desc = irq_desc + irq; |
418 | u32 gpionr = irq_to_gpio(irq); | |
1394f032 | 419 | |
8d022374 | 420 | if (desc->handle_irq == handle_edge_irq) |
1394f032 | 421 | set_gpio_data(gpionr, 0); |
1394f032 BW |
422 | |
423 | set_gpio_maska(gpionr, 0); | |
1394f032 BW |
424 | } |
425 | ||
426 | static void bfin_gpio_mask_irq(unsigned int irq) | |
427 | { | |
8d022374 | 428 | set_gpio_maska(irq_to_gpio(irq), 0); |
1394f032 BW |
429 | } |
430 | ||
431 | static void bfin_gpio_unmask_irq(unsigned int irq) | |
432 | { | |
8d022374 | 433 | set_gpio_maska(irq_to_gpio(irq), 1); |
1394f032 BW |
434 | } |
435 | ||
436 | static unsigned int bfin_gpio_irq_startup(unsigned int irq) | |
437 | { | |
8d022374 | 438 | u32 gpionr = irq_to_gpio(irq); |
1394f032 | 439 | |
8d022374 | 440 | if (__test_and_set_bit(gpionr, gpio_enabled)) |
affee2b2 | 441 | bfin_gpio_irq_prepare(gpionr); |
1394f032 | 442 | |
1394f032 BW |
443 | bfin_gpio_unmask_irq(irq); |
444 | ||
affee2b2 | 445 | return 0; |
1394f032 BW |
446 | } |
447 | ||
448 | static void bfin_gpio_irq_shutdown(unsigned int irq) | |
449 | { | |
30af6d49 GY |
450 | u32 gpionr = irq_to_gpio(irq); |
451 | ||
1394f032 | 452 | bfin_gpio_mask_irq(irq); |
30af6d49 | 453 | __clear_bit(gpionr, gpio_enabled); |
9570ff4a | 454 | bfin_gpio_irq_free(gpionr); |
1394f032 BW |
455 | } |
456 | ||
457 | static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) | |
458 | { | |
8eb3e3bf GY |
459 | int ret; |
460 | char buf[16]; | |
8d022374 | 461 | u32 gpionr = irq_to_gpio(irq); |
1394f032 BW |
462 | |
463 | if (type == IRQ_TYPE_PROBE) { | |
464 | /* only probe unenabled GPIO interrupt lines */ | |
8d022374 | 465 | if (__test_bit(gpionr, gpio_enabled)) |
1394f032 BW |
466 | return 0; |
467 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; | |
468 | } | |
469 | ||
470 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | | |
34e0fc89 | 471 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { |
8d022374 | 472 | |
9570ff4a GY |
473 | snprintf(buf, 16, "gpio-irq%d", irq); |
474 | ret = bfin_gpio_irq_request(gpionr, buf); | |
475 | if (ret) | |
476 | return ret; | |
477 | ||
8d022374 | 478 | if (__test_and_set_bit(gpionr, gpio_enabled)) |
affee2b2 | 479 | bfin_gpio_irq_prepare(gpionr); |
1394f032 | 480 | |
1394f032 | 481 | } else { |
8d022374 | 482 | __clear_bit(gpionr, gpio_enabled); |
1394f032 BW |
483 | return 0; |
484 | } | |
485 | ||
f1bceb47 | 486 | set_gpio_inen(gpionr, 0); |
1394f032 | 487 | set_gpio_dir(gpionr, 0); |
1394f032 BW |
488 | |
489 | if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) | |
490 | == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) | |
491 | set_gpio_both(gpionr, 1); | |
492 | else | |
493 | set_gpio_both(gpionr, 0); | |
494 | ||
495 | if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) | |
496 | set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */ | |
497 | else | |
498 | set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */ | |
499 | ||
f1bceb47 MH |
500 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { |
501 | set_gpio_edge(gpionr, 1); | |
502 | set_gpio_inen(gpionr, 1); | |
f1bceb47 MH |
503 | set_gpio_data(gpionr, 0); |
504 | ||
505 | } else { | |
506 | set_gpio_edge(gpionr, 0); | |
f1bceb47 MH |
507 | set_gpio_inen(gpionr, 1); |
508 | } | |
509 | ||
1394f032 | 510 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
bfd15117 | 511 | bfin_set_irq_handler(irq, handle_edge_irq); |
1394f032 | 512 | else |
bfd15117 | 513 | bfin_set_irq_handler(irq, handle_level_irq); |
1394f032 BW |
514 | |
515 | return 0; | |
516 | } | |
517 | ||
cfefe3c6 MH |
518 | #ifdef CONFIG_PM |
519 | int bfin_gpio_set_wake(unsigned int irq, unsigned int state) | |
520 | { | |
521 | unsigned gpio = irq_to_gpio(irq); | |
522 | ||
523 | if (state) | |
524 | gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE); | |
525 | else | |
526 | gpio_pm_wakeup_free(gpio); | |
527 | ||
528 | return 0; | |
529 | } | |
530 | #endif | |
531 | ||
2c4f829b MH |
532 | static void bfin_demux_gpio_irq(unsigned int inta_irq, |
533 | struct irq_desc *desc) | |
1394f032 | 534 | { |
2c4f829b MH |
535 | unsigned int i, gpio, mask, irq, search = 0; |
536 | ||
537 | switch (inta_irq) { | |
538 | #if defined(CONFIG_BF53x) | |
539 | case IRQ_PROG_INTA: | |
540 | irq = IRQ_PF0; | |
541 | search = 1; | |
542 | break; | |
543 | # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) | |
544 | case IRQ_MAC_RX: | |
545 | irq = IRQ_PH0; | |
546 | break; | |
547 | # endif | |
dc26aec2 MH |
548 | #elif defined(CONFIG_BF538) || defined(CONFIG_BF539) |
549 | case IRQ_PORTF_INTA: | |
550 | irq = IRQ_PF0; | |
551 | break; | |
2f6f4bcd | 552 | #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) |
2c4f829b MH |
553 | case IRQ_PORTF_INTA: |
554 | irq = IRQ_PF0; | |
555 | break; | |
556 | case IRQ_PORTG_INTA: | |
557 | irq = IRQ_PG0; | |
558 | break; | |
559 | case IRQ_PORTH_INTA: | |
560 | irq = IRQ_PH0; | |
561 | break; | |
562 | #elif defined(CONFIG_BF561) | |
563 | case IRQ_PROG0_INTA: | |
564 | irq = IRQ_PF0; | |
565 | break; | |
566 | case IRQ_PROG1_INTA: | |
567 | irq = IRQ_PF16; | |
568 | break; | |
569 | case IRQ_PROG2_INTA: | |
570 | irq = IRQ_PF32; | |
571 | break; | |
572 | #endif | |
573 | default: | |
574 | BUG(); | |
575 | return; | |
576 | } | |
577 | ||
578 | if (search) { | |
cfefe3c6 | 579 | for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { |
2c4f829b MH |
580 | irq += i; |
581 | ||
8d022374 | 582 | mask = get_gpiop_data(i) & get_gpiop_maska(i); |
2c4f829b MH |
583 | |
584 | while (mask) { | |
6a01f230 YL |
585 | if (mask & 1) |
586 | bfin_handle_irq(irq); | |
2c4f829b MH |
587 | irq++; |
588 | mask >>= 1; | |
1394f032 | 589 | } |
1394f032 | 590 | } |
2c4f829b MH |
591 | } else { |
592 | gpio = irq_to_gpio(irq); | |
8d022374 | 593 | mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio); |
2c4f829b MH |
594 | |
595 | do { | |
6a01f230 YL |
596 | if (mask & 1) |
597 | bfin_handle_irq(irq); | |
2c4f829b MH |
598 | irq++; |
599 | mask >>= 1; | |
600 | } while (mask); | |
1394f032 | 601 | } |
2c4f829b | 602 | |
1394f032 BW |
603 | } |
604 | ||
a055b2b4 | 605 | #else /* CONFIG_BF54x */ |
34e0fc89 MH |
606 | |
607 | #define NR_PINT_SYS_IRQS 4 | |
608 | #define NR_PINT_BITS 32 | |
609 | #define NR_PINTS 160 | |
610 | #define IRQ_NOT_AVAIL 0xFF | |
611 | ||
612 | #define PINT_2_BANK(x) ((x) >> 5) | |
613 | #define PINT_2_BIT(x) ((x) & 0x1F) | |
614 | #define PINT_BIT(x) (1 << (PINT_2_BIT(x))) | |
615 | ||
616 | static unsigned char irq2pint_lut[NR_PINTS]; | |
e3f23000 | 617 | static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS]; |
34e0fc89 MH |
618 | |
619 | struct pin_int_t { | |
620 | unsigned int mask_set; | |
621 | unsigned int mask_clear; | |
622 | unsigned int request; | |
623 | unsigned int assign; | |
624 | unsigned int edge_set; | |
625 | unsigned int edge_clear; | |
626 | unsigned int invert_set; | |
627 | unsigned int invert_clear; | |
628 | unsigned int pinstate; | |
629 | unsigned int latch; | |
630 | }; | |
631 | ||
632 | static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = { | |
633 | (struct pin_int_t *)PINT0_MASK_SET, | |
634 | (struct pin_int_t *)PINT1_MASK_SET, | |
635 | (struct pin_int_t *)PINT2_MASK_SET, | |
636 | (struct pin_int_t *)PINT3_MASK_SET, | |
637 | }; | |
638 | ||
8d022374 | 639 | inline unsigned int get_irq_base(u32 bank, u8 bmap) |
34e0fc89 | 640 | { |
8d022374 | 641 | unsigned int irq_base; |
34e0fc89 MH |
642 | |
643 | if (bank < 2) { /*PA-PB */ | |
644 | irq_base = IRQ_PA0 + bmap * 16; | |
645 | } else { /*PC-PJ */ | |
646 | irq_base = IRQ_PC0 + bmap * 16; | |
647 | } | |
648 | ||
649 | return irq_base; | |
34e0fc89 MH |
650 | } |
651 | ||
652 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ | |
653 | void init_pint_lut(void) | |
654 | { | |
655 | u16 bank, bit, irq_base, bit_pos; | |
656 | u32 pint_assign; | |
657 | u8 bmap; | |
658 | ||
659 | memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut)); | |
660 | ||
661 | for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) { | |
662 | ||
663 | pint_assign = pint[bank]->assign; | |
664 | ||
665 | for (bit = 0; bit < NR_PINT_BITS; bit++) { | |
666 | ||
667 | bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF; | |
668 | ||
669 | irq_base = get_irq_base(bank, bmap); | |
670 | ||
671 | irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0); | |
672 | bit_pos = bit + bank * NR_PINT_BITS; | |
673 | ||
e3f23000 | 674 | pint2irq_lut[bit_pos] = irq_base - SYS_IRQS; |
34e0fc89 | 675 | irq2pint_lut[irq_base - SYS_IRQS] = bit_pos; |
34e0fc89 | 676 | } |
34e0fc89 | 677 | } |
34e0fc89 MH |
678 | } |
679 | ||
34e0fc89 MH |
680 | static void bfin_gpio_ack_irq(unsigned int irq) |
681 | { | |
8d022374 MH |
682 | struct irq_desc *desc = irq_desc + irq; |
683 | u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; | |
8baf560b | 684 | u32 pintbit = PINT_BIT(pint_val); |
8d022374 | 685 | u32 bank = PINT_2_BANK(pint_val); |
8baf560b | 686 | |
8d022374 | 687 | if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { |
8baf560b MH |
688 | if (pint[bank]->invert_set & pintbit) |
689 | pint[bank]->invert_clear = pintbit; | |
690 | else | |
691 | pint[bank]->invert_set = pintbit; | |
692 | } | |
693 | pint[bank]->request = pintbit; | |
34e0fc89 | 694 | |
34e0fc89 MH |
695 | } |
696 | ||
697 | static void bfin_gpio_mask_ack_irq(unsigned int irq) | |
698 | { | |
8d022374 MH |
699 | struct irq_desc *desc = irq_desc + irq; |
700 | u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; | |
e3f23000 | 701 | u32 pintbit = PINT_BIT(pint_val); |
8d022374 | 702 | u32 bank = PINT_2_BANK(pint_val); |
34e0fc89 | 703 | |
8d022374 | 704 | if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { |
8baf560b MH |
705 | if (pint[bank]->invert_set & pintbit) |
706 | pint[bank]->invert_clear = pintbit; | |
707 | else | |
708 | pint[bank]->invert_set = pintbit; | |
709 | } | |
710 | ||
e3f23000 MH |
711 | pint[bank]->request = pintbit; |
712 | pint[bank]->mask_clear = pintbit; | |
34e0fc89 MH |
713 | } |
714 | ||
715 | static void bfin_gpio_mask_irq(unsigned int irq) | |
716 | { | |
8d022374 | 717 | u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
34e0fc89 MH |
718 | |
719 | pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val); | |
34e0fc89 MH |
720 | } |
721 | ||
722 | static void bfin_gpio_unmask_irq(unsigned int irq) | |
723 | { | |
8d022374 | 724 | u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
e3f23000 | 725 | u32 pintbit = PINT_BIT(pint_val); |
8d022374 | 726 | u32 bank = PINT_2_BANK(pint_val); |
34e0fc89 | 727 | |
e3f23000 MH |
728 | pint[bank]->request = pintbit; |
729 | pint[bank]->mask_set = pintbit; | |
34e0fc89 MH |
730 | } |
731 | ||
732 | static unsigned int bfin_gpio_irq_startup(unsigned int irq) | |
733 | { | |
8d022374 MH |
734 | u32 gpionr = irq_to_gpio(irq); |
735 | u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; | |
34e0fc89 | 736 | |
50e163ce MH |
737 | if (pint_val == IRQ_NOT_AVAIL) { |
738 | printk(KERN_ERR | |
739 | "GPIO IRQ %d :Not in PINT Assign table " | |
740 | "Reconfigure Interrupt to Port Assignemt\n", irq); | |
34e0fc89 | 741 | return -ENODEV; |
50e163ce | 742 | } |
34e0fc89 | 743 | |
8d022374 | 744 | if (__test_and_set_bit(gpionr, gpio_enabled)) |
affee2b2 | 745 | bfin_gpio_irq_prepare(gpionr); |
34e0fc89 | 746 | |
34e0fc89 MH |
747 | bfin_gpio_unmask_irq(irq); |
748 | ||
affee2b2 | 749 | return 0; |
34e0fc89 MH |
750 | } |
751 | ||
752 | static void bfin_gpio_irq_shutdown(unsigned int irq) | |
753 | { | |
8d022374 | 754 | u32 gpionr = irq_to_gpio(irq); |
8baf560b | 755 | |
34e0fc89 | 756 | bfin_gpio_mask_irq(irq); |
8d022374 | 757 | __clear_bit(gpionr, gpio_enabled); |
9570ff4a | 758 | bfin_gpio_irq_free(gpionr); |
34e0fc89 MH |
759 | } |
760 | ||
761 | static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) | |
762 | { | |
8eb3e3bf GY |
763 | int ret; |
764 | char buf[16]; | |
8d022374 MH |
765 | u32 gpionr = irq_to_gpio(irq); |
766 | u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; | |
e3f23000 | 767 | u32 pintbit = PINT_BIT(pint_val); |
8d022374 | 768 | u32 bank = PINT_2_BANK(pint_val); |
34e0fc89 MH |
769 | |
770 | if (pint_val == IRQ_NOT_AVAIL) | |
771 | return -ENODEV; | |
772 | ||
773 | if (type == IRQ_TYPE_PROBE) { | |
774 | /* only probe unenabled GPIO interrupt lines */ | |
8d022374 | 775 | if (__test_bit(gpionr, gpio_enabled)) |
34e0fc89 MH |
776 | return 0; |
777 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; | |
778 | } | |
779 | ||
780 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | | |
781 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { | |
9570ff4a GY |
782 | |
783 | snprintf(buf, 16, "gpio-irq%d", irq); | |
784 | ret = bfin_gpio_irq_request(gpionr, buf); | |
785 | if (ret) | |
786 | return ret; | |
787 | ||
8d022374 | 788 | if (__test_and_set_bit(gpionr, gpio_enabled)) |
affee2b2 | 789 | bfin_gpio_irq_prepare(gpionr); |
34e0fc89 | 790 | |
34e0fc89 | 791 | } else { |
8d022374 | 792 | __clear_bit(gpionr, gpio_enabled); |
34e0fc89 MH |
793 | return 0; |
794 | } | |
795 | ||
34e0fc89 | 796 | if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) |
e3f23000 | 797 | pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */ |
34e0fc89 | 798 | else |
8baf560b | 799 | pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */ |
34e0fc89 | 800 | |
8baf560b MH |
801 | if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
802 | == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { | |
8baf560b MH |
803 | if (gpio_get_value(gpionr)) |
804 | pint[bank]->invert_set = pintbit; | |
805 | else | |
806 | pint[bank]->invert_clear = pintbit; | |
8baf560b MH |
807 | } |
808 | ||
809 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { | |
810 | pint[bank]->edge_set = pintbit; | |
bfd15117 | 811 | bfin_set_irq_handler(irq, handle_edge_irq); |
8baf560b MH |
812 | } else { |
813 | pint[bank]->edge_clear = pintbit; | |
bfd15117 | 814 | bfin_set_irq_handler(irq, handle_level_irq); |
8baf560b MH |
815 | } |
816 | ||
34e0fc89 MH |
817 | return 0; |
818 | } | |
819 | ||
cfefe3c6 MH |
820 | #ifdef CONFIG_PM |
821 | u32 pint_saved_masks[NR_PINT_SYS_IRQS]; | |
822 | u32 pint_wakeup_masks[NR_PINT_SYS_IRQS]; | |
823 | ||
824 | int bfin_gpio_set_wake(unsigned int irq, unsigned int state) | |
825 | { | |
826 | u32 pint_irq; | |
8d022374 | 827 | u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
cfefe3c6 MH |
828 | u32 bank = PINT_2_BANK(pint_val); |
829 | u32 pintbit = PINT_BIT(pint_val); | |
830 | ||
831 | switch (bank) { | |
832 | case 0: | |
833 | pint_irq = IRQ_PINT0; | |
834 | break; | |
835 | case 2: | |
836 | pint_irq = IRQ_PINT2; | |
837 | break; | |
838 | case 3: | |
839 | pint_irq = IRQ_PINT3; | |
840 | break; | |
841 | case 1: | |
842 | pint_irq = IRQ_PINT1; | |
843 | break; | |
844 | default: | |
845 | return -EINVAL; | |
846 | } | |
847 | ||
848 | bfin_internal_set_wake(pint_irq, state); | |
849 | ||
850 | if (state) | |
851 | pint_wakeup_masks[bank] |= pintbit; | |
852 | else | |
853 | pint_wakeup_masks[bank] &= ~pintbit; | |
854 | ||
855 | return 0; | |
856 | } | |
857 | ||
858 | u32 bfin_pm_setup(void) | |
859 | { | |
860 | u32 val, i; | |
861 | ||
862 | for (i = 0; i < NR_PINT_SYS_IRQS; i++) { | |
863 | val = pint[i]->mask_clear; | |
864 | pint_saved_masks[i] = val; | |
865 | if (val ^ pint_wakeup_masks[i]) { | |
866 | pint[i]->mask_clear = val; | |
867 | pint[i]->mask_set = pint_wakeup_masks[i]; | |
868 | } | |
869 | } | |
870 | ||
871 | return 0; | |
872 | } | |
873 | ||
874 | void bfin_pm_restore(void) | |
875 | { | |
876 | u32 i, val; | |
877 | ||
878 | for (i = 0; i < NR_PINT_SYS_IRQS; i++) { | |
879 | val = pint_saved_masks[i]; | |
880 | if (val ^ pint_wakeup_masks[i]) { | |
881 | pint[i]->mask_clear = pint[i]->mask_clear; | |
882 | pint[i]->mask_set = val; | |
883 | } | |
884 | } | |
885 | } | |
886 | #endif | |
887 | ||
2c4f829b MH |
888 | static void bfin_demux_gpio_irq(unsigned int inta_irq, |
889 | struct irq_desc *desc) | |
34e0fc89 | 890 | { |
8d022374 | 891 | u32 bank, pint_val; |
34e0fc89 MH |
892 | u32 request, irq; |
893 | ||
2c4f829b | 894 | switch (inta_irq) { |
34e0fc89 MH |
895 | case IRQ_PINT0: |
896 | bank = 0; | |
897 | break; | |
898 | case IRQ_PINT2: | |
899 | bank = 2; | |
900 | break; | |
901 | case IRQ_PINT3: | |
902 | bank = 3; | |
903 | break; | |
904 | case IRQ_PINT1: | |
905 | bank = 1; | |
906 | break; | |
e3f23000 MH |
907 | default: |
908 | return; | |
34e0fc89 MH |
909 | } |
910 | ||
911 | pint_val = bank * NR_PINT_BITS; | |
912 | ||
913 | request = pint[bank]->request; | |
914 | ||
915 | while (request) { | |
916 | if (request & 1) { | |
e3f23000 | 917 | irq = pint2irq_lut[pint_val] + SYS_IRQS; |
6a01f230 | 918 | bfin_handle_irq(irq); |
34e0fc89 MH |
919 | } |
920 | pint_val++; | |
921 | request >>= 1; | |
922 | } | |
923 | ||
924 | } | |
a055b2b4 | 925 | #endif |
1394f032 | 926 | |
8d022374 MH |
927 | static struct irq_chip bfin_gpio_irqchip = { |
928 | .name = "GPIO", | |
929 | .ack = bfin_gpio_ack_irq, | |
930 | .mask = bfin_gpio_mask_irq, | |
931 | .mask_ack = bfin_gpio_mask_ack_irq, | |
932 | .unmask = bfin_gpio_unmask_irq, | |
933 | .disable = bfin_gpio_mask_irq, | |
934 | .enable = bfin_gpio_unmask_irq, | |
935 | .set_type = bfin_gpio_irq_type, | |
936 | .startup = bfin_gpio_irq_startup, | |
937 | .shutdown = bfin_gpio_irq_shutdown, | |
938 | #ifdef CONFIG_PM | |
939 | .set_wake = bfin_gpio_set_wake, | |
940 | #endif | |
941 | }; | |
942 | ||
6b3087c6 | 943 | void __cpuinit init_exception_vectors(void) |
8be80ed3 | 944 | { |
f0b5d12f MF |
945 | /* cannot program in software: |
946 | * evt0 - emulation (jtag) | |
947 | * evt1 - reset | |
948 | */ | |
949 | bfin_write_EVT2(evt_nmi); | |
8be80ed3 BS |
950 | bfin_write_EVT3(trap); |
951 | bfin_write_EVT5(evt_ivhw); | |
952 | bfin_write_EVT6(evt_timer); | |
953 | bfin_write_EVT7(evt_evt7); | |
954 | bfin_write_EVT8(evt_evt8); | |
955 | bfin_write_EVT9(evt_evt9); | |
956 | bfin_write_EVT10(evt_evt10); | |
957 | bfin_write_EVT11(evt_evt11); | |
958 | bfin_write_EVT12(evt_evt12); | |
959 | bfin_write_EVT13(evt_evt13); | |
960 | bfin_write_EVT14(evt14_softirq); | |
961 | bfin_write_EVT15(evt_system_call); | |
962 | CSYNC(); | |
963 | } | |
964 | ||
1394f032 BW |
965 | /* |
966 | * This function should be called during kernel startup to initialize | |
967 | * the BFin IRQ handling routines. | |
968 | */ | |
8d022374 | 969 | |
1394f032 BW |
970 | int __init init_arch_irq(void) |
971 | { | |
972 | int irq; | |
973 | unsigned long ilat = 0; | |
974 | /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ | |
2f6f4bcd BW |
975 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \ |
976 | || defined(BF538_FAMILY) || defined(CONFIG_BF51x) | |
24a07a12 RH |
977 | bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); |
978 | bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); | |
a055b2b4 | 979 | # ifdef CONFIG_BF54x |
59003145 | 980 | bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); |
a055b2b4 | 981 | # endif |
6b3087c6 GY |
982 | # ifdef CONFIG_SMP |
983 | bfin_write_SICB_IMASK0(SIC_UNMASK_ALL); | |
984 | bfin_write_SICB_IMASK1(SIC_UNMASK_ALL); | |
985 | # endif | |
24a07a12 | 986 | #else |
1394f032 | 987 | bfin_write_SIC_IMASK(SIC_UNMASK_ALL); |
24a07a12 | 988 | #endif |
1394f032 BW |
989 | |
990 | local_irq_disable(); | |
991 | ||
d70536ec | 992 | #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) |
95a86b5e MF |
993 | /* Clear EMAC Interrupt Status bits so we can demux it later */ |
994 | bfin_write_EMAC_SYSTAT(-1); | |
995 | #endif | |
996 | ||
a055b2b4 MF |
997 | #ifdef CONFIG_BF54x |
998 | # ifdef CONFIG_PINTx_REASSIGN | |
34e0fc89 MH |
999 | pint[0]->assign = CONFIG_PINT0_ASSIGN; |
1000 | pint[1]->assign = CONFIG_PINT1_ASSIGN; | |
1001 | pint[2]->assign = CONFIG_PINT2_ASSIGN; | |
1002 | pint[3]->assign = CONFIG_PINT3_ASSIGN; | |
a055b2b4 | 1003 | # endif |
34e0fc89 MH |
1004 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ |
1005 | init_pint_lut(); | |
1006 | #endif | |
1007 | ||
1008 | for (irq = 0; irq <= SYS_IRQS; irq++) { | |
1394f032 BW |
1009 | if (irq <= IRQ_CORETMR) |
1010 | set_irq_chip(irq, &bfin_core_irqchip); | |
1011 | else | |
1012 | set_irq_chip(irq, &bfin_internal_irqchip); | |
1394f032 | 1013 | |
464abc5d | 1014 | switch (irq) { |
59003145 | 1015 | #if defined(CONFIG_BF53x) |
464abc5d | 1016 | case IRQ_PROG_INTA: |
a055b2b4 | 1017 | # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) |
464abc5d | 1018 | case IRQ_MAC_RX: |
a055b2b4 | 1019 | # endif |
59003145 | 1020 | #elif defined(CONFIG_BF54x) |
464abc5d MH |
1021 | case IRQ_PINT0: |
1022 | case IRQ_PINT1: | |
1023 | case IRQ_PINT2: | |
1024 | case IRQ_PINT3: | |
2f6f4bcd | 1025 | #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) |
464abc5d MH |
1026 | case IRQ_PORTF_INTA: |
1027 | case IRQ_PORTG_INTA: | |
1028 | case IRQ_PORTH_INTA: | |
2c4f829b | 1029 | #elif defined(CONFIG_BF561) |
464abc5d MH |
1030 | case IRQ_PROG0_INTA: |
1031 | case IRQ_PROG1_INTA: | |
1032 | case IRQ_PROG2_INTA: | |
dc26aec2 MH |
1033 | #elif defined(CONFIG_BF538) || defined(CONFIG_BF539) |
1034 | case IRQ_PORTF_INTA: | |
1394f032 | 1035 | #endif |
dc26aec2 | 1036 | |
464abc5d MH |
1037 | set_irq_chained_handler(irq, |
1038 | bfin_demux_gpio_irq); | |
1039 | break; | |
1394f032 | 1040 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX |
464abc5d | 1041 | case IRQ_GENERIC_ERROR: |
6a01f230 | 1042 | set_irq_chained_handler(irq, bfin_demux_error_irq); |
464abc5d | 1043 | break; |
1394f032 | 1044 | #endif |
6a01f230 | 1045 | #if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE) |
6b3087c6 GY |
1046 | case IRQ_TIMER0: |
1047 | set_irq_handler(irq, handle_percpu_irq); | |
1048 | break; | |
1049 | #endif | |
1050 | #ifdef CONFIG_SMP | |
1051 | case IRQ_SUPPLE_0: | |
1052 | case IRQ_SUPPLE_1: | |
1053 | set_irq_handler(irq, handle_percpu_irq); | |
1054 | break; | |
1055 | #endif | |
464abc5d | 1056 | default: |
6a01f230 YL |
1057 | #ifdef CONFIG_IPIPE |
1058 | /* | |
1059 | * We want internal interrupt sources to be masked, because | |
1060 | * ISRs may trigger interrupts recursively (e.g. DMA), but | |
1061 | * interrupts are _not_ masked at CPU level. So let's handle | |
1062 | * them as level interrupts. | |
1063 | */ | |
1064 | set_irq_handler(irq, handle_level_irq); | |
1065 | #else /* !CONFIG_IPIPE */ | |
464abc5d | 1066 | set_irq_handler(irq, handle_simple_irq); |
6a01f230 | 1067 | #endif /* !CONFIG_IPIPE */ |
464abc5d MH |
1068 | break; |
1069 | } | |
1394f032 | 1070 | } |
464abc5d | 1071 | |
1394f032 | 1072 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX |
464abc5d MH |
1073 | for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) |
1074 | set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip, | |
1075 | handle_level_irq); | |
1394f032 BW |
1076 | #endif |
1077 | ||
464abc5d MH |
1078 | /* if configured as edge, then will be changed to do_edge_IRQ */ |
1079 | for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++) | |
1080 | set_irq_chip_and_handler(irq, &bfin_gpio_irqchip, | |
1081 | handle_level_irq); | |
2c4f829b | 1082 | |
a055b2b4 | 1083 | |
1394f032 BW |
1084 | bfin_write_IMASK(0); |
1085 | CSYNC(); | |
1086 | ilat = bfin_read_ILAT(); | |
1087 | CSYNC(); | |
1088 | bfin_write_ILAT(ilat); | |
1089 | CSYNC(); | |
1090 | ||
34e0fc89 | 1091 | printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n"); |
40059784 | 1092 | /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx, |
1394f032 BW |
1093 | * local_irq_enable() |
1094 | */ | |
1095 | program_IAR(); | |
1096 | /* Therefore it's better to setup IARs before interrupts enabled */ | |
1097 | search_IAR(); | |
1098 | ||
1099 | /* Enable interrupts IVG7-15 */ | |
40059784 | 1100 | bfin_irq_flags |= IMASK_IVG15 | |
1394f032 | 1101 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | |
34e0fc89 | 1102 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; |
1394f032 | 1103 | |
be1d8543 | 1104 | #ifdef SIC_IWR0 |
56f5f590 | 1105 | bfin_write_SIC_IWR0(IWR_DISABLE_ALL); |
be1d8543 | 1106 | # ifdef SIC_IWR1 |
2f6f4bcd | 1107 | /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which |
55546ac4 MH |
1108 | * will screw up the bootrom as it relies on MDMA0/1 waking it |
1109 | * up from IDLE instructions. See this report for more info: | |
1110 | * http://blackfin.uclinux.org/gf/tracker/4323 | |
1111 | */ | |
b7e11293 MF |
1112 | if (ANOMALY_05000435) |
1113 | bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); | |
1114 | else | |
1115 | bfin_write_SIC_IWR1(IWR_DISABLE_ALL); | |
be1d8543 MF |
1116 | # endif |
1117 | # ifdef SIC_IWR2 | |
56f5f590 | 1118 | bfin_write_SIC_IWR2(IWR_DISABLE_ALL); |
fe9ec9b9 MH |
1119 | # endif |
1120 | #else | |
56f5f590 | 1121 | bfin_write_SIC_IWR(IWR_DISABLE_ALL); |
fe9ec9b9 MH |
1122 | #endif |
1123 | ||
6a01f230 YL |
1124 | #ifdef CONFIG_IPIPE |
1125 | for (irq = 0; irq < NR_IRQS; irq++) { | |
1126 | struct irq_desc *desc = irq_desc + irq; | |
1127 | desc->ic_prio = __ipipe_get_irq_priority(irq); | |
1128 | desc->thr_prio = __ipipe_get_irqthread_priority(irq); | |
1129 | } | |
1130 | #endif /* CONFIG_IPIPE */ | |
1131 | ||
1394f032 BW |
1132 | return 0; |
1133 | } | |
1134 | ||
1135 | #ifdef CONFIG_DO_IRQ_L1 | |
a055b2b4 | 1136 | __attribute__((l1_text)) |
1394f032 | 1137 | #endif |
1394f032 BW |
1138 | void do_irq(int vec, struct pt_regs *fp) |
1139 | { | |
1140 | if (vec == EVT_IVTMR_P) { | |
1141 | vec = IRQ_CORETMR; | |
1142 | } else { | |
1143 | struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; | |
1144 | struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; | |
2f6f4bcd BW |
1145 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \ |
1146 | || defined(BF538_FAMILY) || defined(CONFIG_BF51x) | |
24a07a12 | 1147 | unsigned long sic_status[3]; |
1394f032 | 1148 | |
6b3087c6 GY |
1149 | if (smp_processor_id()) { |
1150 | #ifdef CONFIG_SMP | |
1151 | /* This will be optimized out in UP mode. */ | |
1152 | sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0(); | |
1153 | sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1(); | |
1154 | #endif | |
1155 | } else { | |
1156 | sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); | |
1157 | sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1(); | |
1158 | } | |
59003145 | 1159 | #ifdef CONFIG_BF54x |
4fb45241 | 1160 | sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2(); |
59003145 | 1161 | #endif |
1f83b8f1 | 1162 | for (;; ivg++) { |
24a07a12 RH |
1163 | if (ivg >= ivg_stop) { |
1164 | atomic_inc(&num_spurious); | |
1165 | return; | |
1166 | } | |
34e0fc89 | 1167 | if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag) |
24a07a12 RH |
1168 | break; |
1169 | } | |
1170 | #else | |
1171 | unsigned long sic_status; | |
464abc5d | 1172 | |
1394f032 BW |
1173 | sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); |
1174 | ||
1175 | for (;; ivg++) { | |
1176 | if (ivg >= ivg_stop) { | |
1177 | atomic_inc(&num_spurious); | |
1178 | return; | |
1179 | } else if (sic_status & ivg->isrflag) | |
1180 | break; | |
1181 | } | |
24a07a12 | 1182 | #endif |
1394f032 BW |
1183 | vec = ivg->irqno; |
1184 | } | |
1185 | asm_do_IRQ(vec, fp); | |
1394f032 | 1186 | } |
6a01f230 YL |
1187 | |
1188 | #ifdef CONFIG_IPIPE | |
1189 | ||
1190 | int __ipipe_get_irq_priority(unsigned irq) | |
1191 | { | |
1192 | int ient, prio; | |
1193 | ||
1194 | if (irq <= IRQ_CORETMR) | |
1195 | return irq; | |
1196 | ||
1197 | for (ient = 0; ient < NR_PERI_INTS; ient++) { | |
1198 | struct ivgx *ivg = ivg_table + ient; | |
1199 | if (ivg->irqno == irq) { | |
1200 | for (prio = 0; prio <= IVG13-IVG7; prio++) { | |
1201 | if (ivg7_13[prio].ifirst <= ivg && | |
1202 | ivg7_13[prio].istop > ivg) | |
1203 | return IVG7 + prio; | |
1204 | } | |
1205 | } | |
1206 | } | |
1207 | ||
1208 | return IVG15; | |
1209 | } | |
1210 | ||
1211 | int __ipipe_get_irqthread_priority(unsigned irq) | |
1212 | { | |
1213 | int ient, prio; | |
1214 | int demux_irq; | |
1215 | ||
1216 | /* The returned priority value is rescaled to [0..IVG13+1] | |
1217 | * with 0 being the lowest effective priority level. */ | |
1218 | ||
1219 | if (irq <= IRQ_CORETMR) | |
1220 | return IVG13 - irq + 1; | |
1221 | ||
1222 | /* GPIO IRQs are given the priority of the demux | |
1223 | * interrupt. */ | |
1224 | if (IS_GPIOIRQ(irq)) { | |
1225 | #if defined(CONFIG_BF54x) | |
1226 | u32 bank = PINT_2_BANK(irq2pint_lut[irq - SYS_IRQS]); | |
1227 | demux_irq = (bank == 0 ? IRQ_PINT0 : | |
1228 | bank == 1 ? IRQ_PINT1 : | |
1229 | bank == 2 ? IRQ_PINT2 : | |
1230 | IRQ_PINT3); | |
1231 | #elif defined(CONFIG_BF561) | |
1232 | demux_irq = (irq >= IRQ_PF32 ? IRQ_PROG2_INTA : | |
1233 | irq >= IRQ_PF16 ? IRQ_PROG1_INTA : | |
1234 | IRQ_PROG0_INTA); | |
1235 | #elif defined(CONFIG_BF52x) | |
1236 | demux_irq = (irq >= IRQ_PH0 ? IRQ_PORTH_INTA : | |
1237 | irq >= IRQ_PG0 ? IRQ_PORTG_INTA : | |
1238 | IRQ_PORTF_INTA); | |
1239 | #else | |
1240 | demux_irq = irq; | |
1241 | #endif | |
1242 | return IVG13 - PRIO_GPIODEMUX(demux_irq) + 1; | |
1243 | } | |
1244 | ||
1245 | /* The GPIO demux interrupt is given a lower priority | |
1246 | * than the GPIO IRQs, so that its threaded handler | |
1247 | * unmasks the interrupt line after the decoded IRQs | |
1248 | * have been processed. */ | |
1249 | prio = PRIO_GPIODEMUX(irq); | |
1250 | /* demux irq? */ | |
1251 | if (prio != -1) | |
1252 | return IVG13 - prio; | |
1253 | ||
1254 | for (ient = 0; ient < NR_PERI_INTS; ient++) { | |
1255 | struct ivgx *ivg = ivg_table + ient; | |
1256 | if (ivg->irqno == irq) { | |
1257 | for (prio = 0; prio <= IVG13-IVG7; prio++) { | |
1258 | if (ivg7_13[prio].ifirst <= ivg && | |
1259 | ivg7_13[prio].istop > ivg) | |
1260 | return IVG7 - prio; | |
1261 | } | |
1262 | } | |
1263 | } | |
1264 | ||
1265 | return 0; | |
1266 | } | |
1267 | ||
1268 | /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */ | |
1269 | #ifdef CONFIG_DO_IRQ_L1 | |
1270 | __attribute__((l1_text)) | |
1271 | #endif | |
1272 | asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) | |
1273 | { | |
1274 | struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop; | |
1275 | struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst; | |
1276 | int irq; | |
1277 | ||
1278 | if (likely(vec == EVT_IVTMR_P)) { | |
1279 | irq = IRQ_CORETMR; | |
1280 | goto handle_irq; | |
1281 | } | |
1282 | ||
1283 | SSYNC(); | |
1284 | ||
1285 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) | |
1286 | { | |
1287 | unsigned long sic_status[3]; | |
1288 | ||
1289 | sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); | |
1290 | sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1(); | |
1291 | #ifdef CONFIG_BF54x | |
1292 | sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2(); | |
1293 | #endif | |
1294 | for (;; ivg++) { | |
1295 | if (ivg >= ivg_stop) { | |
1296 | atomic_inc(&num_spurious); | |
1297 | return 0; | |
1298 | } | |
1299 | if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag) | |
1300 | break; | |
1301 | } | |
1302 | } | |
1303 | #else | |
1304 | { | |
1305 | unsigned long sic_status; | |
1306 | ||
1307 | sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); | |
1308 | ||
1309 | for (;; ivg++) { | |
1310 | if (ivg >= ivg_stop) { | |
1311 | atomic_inc(&num_spurious); | |
1312 | return 0; | |
1313 | } else if (sic_status & ivg->isrflag) | |
1314 | break; | |
1315 | } | |
1316 | } | |
1317 | #endif | |
1318 | ||
1319 | irq = ivg->irqno; | |
1320 | ||
1321 | if (irq == IRQ_SYSTMR) { | |
1322 | bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */ | |
1323 | /* This is basically what we need from the register frame. */ | |
1324 | __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend; | |
1325 | __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc; | |
1326 | if (!ipipe_root_domain_p) | |
1327 | __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10; | |
1328 | else | |
1329 | __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10; | |
1330 | } | |
1331 | ||
1332 | handle_irq: | |
1333 | ||
1334 | ipipe_trace_irq_entry(irq); | |
1335 | __ipipe_handle_irq(irq, regs); | |
1336 | ipipe_trace_irq_exit(irq); | |
1337 | ||
1338 | if (ipipe_root_domain_p) | |
1339 | return !test_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status)); | |
1340 | ||
1341 | return 0; | |
1342 | } | |
1343 | ||
1344 | #endif /* CONFIG_IPIPE */ |