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Commit | Line | Data |
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1394f032 | 1 | /* |
96f1050d | 2 | * Blackfin power management |
1394f032 | 3 | * |
96f1050d | 4 | * Copyright 2006-2009 Analog Devices Inc. |
1394f032 | 5 | * |
96f1050d RG |
6 | * Licensed under the GPL-2 |
7 | * based on arm/mach-omap/pm.c | |
8 | * Copyright 2001, Cliff Brake <cbrake@accelent.com> and others | |
1394f032 BW |
9 | */ |
10 | ||
95d9ffbe | 11 | #include <linux/suspend.h> |
1394f032 BW |
12 | #include <linux/sched.h> |
13 | #include <linux/proc_fs.h> | |
1f83b8f1 MF |
14 | #include <linux/io.h> |
15 | #include <linux/irq.h> | |
1394f032 | 16 | |
eb7bd9c4 | 17 | #include <asm/cplb.h> |
fd92348e | 18 | #include <asm/gpio.h> |
1efc80b5 MH |
19 | #include <asm/dma.h> |
20 | #include <asm/dpmc.h> | |
1394f032 BW |
21 | |
22 | #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_H | |
23 | #define WAKEUP_TYPE PM_WAKE_HIGH | |
24 | #endif | |
25 | ||
26 | #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_L | |
27 | #define WAKEUP_TYPE PM_WAKE_LOW | |
28 | #endif | |
29 | ||
30 | #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_F | |
31 | #define WAKEUP_TYPE PM_WAKE_FALLING | |
32 | #endif | |
33 | ||
34 | #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_R | |
35 | #define WAKEUP_TYPE PM_WAKE_RISING | |
36 | #endif | |
37 | ||
38 | #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_B | |
39 | #define WAKEUP_TYPE PM_WAKE_BOTH_EDGES | |
40 | #endif | |
41 | ||
1efc80b5 | 42 | |
1394f032 BW |
43 | void bfin_pm_suspend_standby_enter(void) |
44 | { | |
1efc80b5 MH |
45 | unsigned long flags; |
46 | ||
1394f032 BW |
47 | #ifdef CONFIG_PM_WAKEUP_BY_GPIO |
48 | gpio_pm_wakeup_request(CONFIG_PM_WAKEUP_GPIO_NUMBER, WAKEUP_TYPE); | |
49 | #endif | |
50 | ||
6a01f230 | 51 | local_irq_save_hw(flags); |
1efc80b5 | 52 | bfin_pm_standby_setup(); |
1394f032 | 53 | |
cfefe3c6 MH |
54 | #ifdef CONFIG_PM_BFIN_SLEEP_DEEPER |
55 | sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]); | |
fb5f0049 | 56 | #else |
cfefe3c6 | 57 | sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]); |
fb5f0049 | 58 | #endif |
1394f032 | 59 | |
1efc80b5 | 60 | bfin_pm_standby_restore(); |
1394f032 | 61 | |
be1d8543 | 62 | #ifdef SIC_IWR0 |
56f5f590 | 63 | bfin_write_SIC_IWR0(IWR_DISABLE_ALL); |
be1d8543 | 64 | # ifdef SIC_IWR1 |
55546ac4 MH |
65 | /* BF52x system reset does not properly reset SIC_IWR1 which |
66 | * will screw up the bootrom as it relies on MDMA0/1 waking it | |
67 | * up from IDLE instructions. See this report for more info: | |
68 | * http://blackfin.uclinux.org/gf/tracker/4323 | |
69 | */ | |
b7e11293 MF |
70 | if (ANOMALY_05000435) |
71 | bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); | |
72 | else | |
73 | bfin_write_SIC_IWR1(IWR_DISABLE_ALL); | |
be1d8543 MF |
74 | # endif |
75 | # ifdef SIC_IWR2 | |
56f5f590 | 76 | bfin_write_SIC_IWR2(IWR_DISABLE_ALL); |
fb5f0049 | 77 | # endif |
cfefe3c6 | 78 | #else |
56f5f590 | 79 | bfin_write_SIC_IWR(IWR_DISABLE_ALL); |
cfefe3c6 MH |
80 | #endif |
81 | ||
6a01f230 | 82 | local_irq_restore_hw(flags); |
1394f032 BW |
83 | } |
84 | ||
1efc80b5 MH |
85 | int bf53x_suspend_l1_mem(unsigned char *memptr) |
86 | { | |
87 | dma_memcpy(memptr, (const void *) L1_CODE_START, L1_CODE_LENGTH); | |
88 | dma_memcpy(memptr + L1_CODE_LENGTH, (const void *) L1_DATA_A_START, | |
89 | L1_DATA_A_LENGTH); | |
90 | dma_memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH, | |
91 | (const void *) L1_DATA_B_START, L1_DATA_B_LENGTH); | |
92 | memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH + | |
93 | L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START, | |
94 | L1_SCRATCH_LENGTH); | |
95 | ||
96 | return 0; | |
97 | } | |
98 | ||
99 | int bf53x_resume_l1_mem(unsigned char *memptr) | |
100 | { | |
101 | dma_memcpy((void *) L1_CODE_START, memptr, L1_CODE_LENGTH); | |
102 | dma_memcpy((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH, | |
103 | L1_DATA_A_LENGTH); | |
104 | dma_memcpy((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH + | |
105 | L1_DATA_A_LENGTH, L1_DATA_B_LENGTH); | |
106 | memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH + | |
107 | L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH); | |
108 | ||
109 | return 0; | |
110 | } | |
111 | ||
41ba653f | 112 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) |
1efc80b5 MH |
113 | static void flushinv_all_dcache(void) |
114 | { | |
115 | u32 way, bank, subbank, set; | |
116 | u32 status, addr; | |
117 | u32 dmem_ctl = bfin_read_DMEM_CONTROL(); | |
118 | ||
119 | for (bank = 0; bank < 2; ++bank) { | |
120 | if (!(dmem_ctl & (1 << (DMC1_P - bank)))) | |
121 | continue; | |
122 | ||
123 | for (way = 0; way < 2; ++way) | |
124 | for (subbank = 0; subbank < 4; ++subbank) | |
125 | for (set = 0; set < 64; ++set) { | |
126 | ||
127 | bfin_write_DTEST_COMMAND( | |
128 | way << 26 | | |
129 | bank << 23 | | |
130 | subbank << 16 | | |
131 | set << 5 | |
132 | ); | |
133 | CSYNC(); | |
134 | status = bfin_read_DTEST_DATA0(); | |
135 | ||
136 | /* only worry about valid/dirty entries */ | |
137 | if ((status & 0x3) != 0x3) | |
138 | continue; | |
139 | ||
140 | /* construct the address using the tag */ | |
141 | addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5); | |
142 | ||
143 | /* flush it */ | |
144 | __asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr)); | |
145 | } | |
146 | } | |
147 | } | |
148 | #endif | |
149 | ||
1efc80b5 MH |
150 | int bfin_pm_suspend_mem_enter(void) |
151 | { | |
152 | unsigned long flags; | |
153 | int wakeup, ret; | |
154 | ||
155 | unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH | |
156 | + L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH, | |
157 | GFP_KERNEL); | |
158 | ||
159 | if (memptr == NULL) { | |
160 | panic("bf53x_suspend_l1_mem malloc failed"); | |
161 | return -ENOMEM; | |
162 | } | |
163 | ||
164 | wakeup = bfin_read_VR_CTL() & ~FREQ; | |
165 | wakeup |= SCKELOW; | |
166 | ||
1efc80b5 MH |
167 | #ifdef CONFIG_PM_BFIN_WAKE_PH6 |
168 | wakeup |= PHYWE; | |
169 | #endif | |
1efc80b5 MH |
170 | #ifdef CONFIG_PM_BFIN_WAKE_GP |
171 | wakeup |= GPWE; | |
172 | #endif | |
1efc80b5 | 173 | |
6a01f230 | 174 | local_irq_save_hw(flags); |
1efc80b5 MH |
175 | |
176 | ret = blackfin_dma_suspend(); | |
177 | ||
178 | if (ret) { | |
6a01f230 | 179 | local_irq_restore_hw(flags); |
1efc80b5 MH |
180 | kfree(memptr); |
181 | return ret; | |
182 | } | |
183 | ||
184 | bfin_gpio_pm_hibernate_suspend(); | |
185 | ||
eb7bd9c4 YL |
186 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) |
187 | flushinv_all_dcache(); | |
188 | #endif | |
189 | _disable_dcplb(); | |
190 | _disable_icplb(); | |
1efc80b5 MH |
191 | bf53x_suspend_l1_mem(memptr); |
192 | ||
4a88d0ce | 193 | do_hibernate(wakeup | vr_wakeup); /* Goodbye */ |
1efc80b5 MH |
194 | |
195 | bf53x_resume_l1_mem(memptr); | |
196 | ||
eb7bd9c4 YL |
197 | _enable_icplb(); |
198 | _enable_dcplb(); | |
1efc80b5 MH |
199 | |
200 | bfin_gpio_pm_hibernate_restore(); | |
201 | blackfin_dma_resume(); | |
202 | ||
6a01f230 | 203 | local_irq_restore_hw(flags); |
1efc80b5 MH |
204 | kfree(memptr); |
205 | ||
206 | return 0; | |
207 | } | |
208 | ||
1394f032 | 209 | /* |
e6c5eb95 RW |
210 | * bfin_pm_valid - Tell the PM core that we only support the standby sleep |
211 | * state | |
212 | * @state: suspend state we're checking. | |
1394f032 BW |
213 | * |
214 | */ | |
e6c5eb95 | 215 | static int bfin_pm_valid(suspend_state_t state) |
1394f032 | 216 | { |
1efc80b5 | 217 | return (state == PM_SUSPEND_STANDBY |
b89df504 | 218 | #if !(defined(BF533_FAMILY) || defined(CONFIG_BF561)) |
1efc80b5 MH |
219 | /* |
220 | * On BF533/2/1: | |
221 | * If we enter Hibernate the SCKE Pin is driven Low, | |
222 | * so that the SDRAM enters Self Refresh Mode. | |
223 | * However when the reset sequence that follows hibernate | |
224 | * state is executed, SCKE is driven High, taking the | |
225 | * SDRAM out of Self Refresh. | |
226 | * | |
227 | * If you reconfigure and access the SDRAM "very quickly", | |
228 | * you are likely to avoid errors, otherwise the SDRAM | |
229 | * start losing its contents. | |
230 | * An external HW workaround is possible using logic gates. | |
231 | */ | |
232 | || state == PM_SUSPEND_MEM | |
233 | #endif | |
234 | ); | |
1394f032 BW |
235 | } |
236 | ||
237 | /* | |
238 | * bfin_pm_enter - Actually enter a sleep state. | |
239 | * @state: State we're entering. | |
240 | * | |
241 | */ | |
242 | static int bfin_pm_enter(suspend_state_t state) | |
243 | { | |
244 | switch (state) { | |
245 | case PM_SUSPEND_STANDBY: | |
246 | bfin_pm_suspend_standby_enter(); | |
247 | break; | |
9d7b6677 | 248 | case PM_SUSPEND_MEM: |
1efc80b5 MH |
249 | bfin_pm_suspend_mem_enter(); |
250 | break; | |
1394f032 BW |
251 | default: |
252 | return -EINVAL; | |
253 | } | |
254 | ||
255 | return 0; | |
256 | } | |
257 | ||
26398a70 | 258 | struct platform_suspend_ops bfin_pm_ops = { |
1394f032 | 259 | .enter = bfin_pm_enter, |
4bbd10fd | 260 | .valid = bfin_pm_valid, |
1394f032 BW |
261 | }; |
262 | ||
263 | static int __init bfin_pm_init(void) | |
264 | { | |
26398a70 | 265 | suspend_set_ops(&bfin_pm_ops); |
1394f032 BW |
266 | return 0; |
267 | } | |
268 | ||
269 | __initcall(bfin_pm_init); |